1 From 537082e01849ca85227c5b462b8ac9aceb11b77a Mon Sep 17 00:00:00 2001
2 From: Lars-Peter Clausen <lars@metafoo.de>
3 Date: Sat, 24 Apr 2010 12:18:46 +0200
4 Subject: [PATCH 02/21] Add jz4740 udc driver
8 - patch by Lars-Peter Clausen.
9 - updated to 3.1 by Maarten ter Huurne
11 drivers/usb/gadget/Kconfig | 8 +
12 drivers/usb/gadget/Makefile | 1 +
13 drivers/usb/gadget/gadget_chips.h | 3 +
14 drivers/usb/gadget/jz4740_udc.c | 2199 +++++++++++++++++++++++++++++++++++++
15 drivers/usb/gadget/jz4740_udc.h | 101 ++
16 5 files changed, 2312 insertions(+), 0 deletions(-)
17 create mode 100644 drivers/usb/gadget/jz4740_udc.c
18 create mode 100644 drivers/usb/gadget/jz4740_udc.h
20 --- a/drivers/usb/gadget/Kconfig
21 +++ b/drivers/usb/gadget/Kconfig
22 @@ -178,6 +178,14 @@ config USB_FUSB300
24 Faraday usb device controller FUSB300 driver
27 + tristate "JZ4740 UDC"
28 + depends on MACH_JZ4740
29 + select USB_GADGET_DUALSPEED
31 + Select this to support the Ingenic JZ4740 processor
32 + high speed USB device controller.
35 tristate "OMAP USB Device Controller"
37 --- a/drivers/usb/gadget/Makefile
38 +++ b/drivers/usb/gadget/Makefile
39 @@ -31,6 +31,7 @@ obj-$(CONFIG_USB_PXA_U2O) += mv_udc.o
40 mv_udc-y := mv_udc_core.o
41 obj-$(CONFIG_USB_CI13XXX_MSM) += ci13xxx_msm.o
42 obj-$(CONFIG_USB_FUSB300) += fusb300_udc.o
43 +obj-$(CONFIG_USB_JZ4740) += jz4740_udc.o
47 --- a/drivers/usb/gadget/gadget_chips.h
48 +++ b/drivers/usb/gadget/gadget_chips.h
50 #define gadget_is_fsl_usb2(g) (!strcmp("fsl-usb2-udc", (g)->name))
51 #define gadget_is_goku(g) (!strcmp("goku_udc", (g)->name))
52 #define gadget_is_imx(g) (!strcmp("imx_udc", (g)->name))
53 +#define gadget_is_jz4740(g) (!strcmp("ingenic_hsusb", (g)->name))
54 #define gadget_is_langwell(g) (!strcmp("langwell_udc", (g)->name))
55 #define gadget_is_m66592(g) (!strcmp("m66592_udc", (g)->name))
56 #define gadget_is_musbhdrc(g) (!strcmp("musb-hdrc", (g)->name))
57 @@ -118,6 +119,8 @@ static inline int usb_gadget_controller_
59 else if (gadget_is_dwc3(gadget))
61 + else if (gadget_is_jz4740(gadget))
67 +++ b/drivers/usb/gadget/jz4740_udc.c
70 + * linux/drivers/usb/gadget/jz4740_udc.c
72 + * Ingenic JZ4740 on-chip high speed USB device controller
74 + * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
75 + * Author: <jlwei@ingenic.cn>
77 + * This program is free software; you can redistribute it and/or modify
78 + * it under the terms of the GNU General Public License as published by
79 + * the Free Software Foundation; either version 2 of the License, or
80 + * (at your option) any later version.
84 + * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
86 + * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
87 + * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
90 +#include <linux/kernel.h>
91 +#include <linux/module.h>
92 +#include <linux/platform_device.h>
93 +#include <linux/delay.h>
94 +#include <linux/ioport.h>
95 +#include <linux/slab.h>
96 +#include <linux/errno.h>
97 +#include <linux/init.h>
98 +#include <linux/list.h>
99 +#include <linux/interrupt.h>
100 +#include <linux/proc_fs.h>
101 +#include <linux/usb.h>
102 +#include <linux/usb/gadget.h>
103 +#include <linux/clk.h>
105 +#include <asm/byteorder.h>
107 +#include <asm/irq.h>
108 +#include <asm/system.h>
109 +#include <asm/mach-jz4740/clock.h>
111 +#include "jz4740_udc.h"
113 +#define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */
114 +#define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */
115 +#define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */
116 +#define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */
117 +#define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */
118 +#define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */
119 +#define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */
120 +#define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
121 +#define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */
122 +#define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */
123 +#define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */
125 +#define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */
126 +#define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */
127 +#define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */
128 +#define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */
130 +#define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */
131 +#define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */
132 +#define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */
133 +#define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
135 +#define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20)
137 +#define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */
138 +#define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */
140 +#define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */
141 +#define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */
142 +#define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */
143 +#define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */
144 +#define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */
145 +#define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
146 +#define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
148 +/* Power register bit masks */
149 +#define USB_POWER_SUSPENDM 0x01
150 +#define USB_POWER_RESUME 0x04
151 +#define USB_POWER_HSMODE 0x10
152 +#define USB_POWER_HSENAB 0x20
153 +#define USB_POWER_SOFTCONN 0x40
155 +/* Interrupt register bit masks */
156 +#define USB_INTR_SUSPEND 0x01
157 +#define USB_INTR_RESUME 0x02
158 +#define USB_INTR_RESET 0x04
160 +#define USB_INTR_EP0 0x0001
161 +#define USB_INTR_INEP1 0x0002
162 +#define USB_INTR_INEP2 0x0004
163 +#define USB_INTR_OUTEP1 0x0002
165 +/* CSR0 bit masks */
166 +#define USB_CSR0_OUTPKTRDY 0x01
167 +#define USB_CSR0_INPKTRDY 0x02
168 +#define USB_CSR0_SENTSTALL 0x04
169 +#define USB_CSR0_DATAEND 0x08
170 +#define USB_CSR0_SETUPEND 0x10
171 +#define USB_CSR0_SENDSTALL 0x20
172 +#define USB_CSR0_SVDOUTPKTRDY 0x40
173 +#define USB_CSR0_SVDSETUPEND 0x80
175 +/* Endpoint CSR register bits */
176 +#define USB_INCSRH_AUTOSET 0x80
177 +#define USB_INCSRH_ISO 0x40
178 +#define USB_INCSRH_MODE 0x20
179 +#define USB_INCSRH_DMAREQENAB 0x10
180 +#define USB_INCSRH_DMAREQMODE 0x04
181 +#define USB_INCSR_CDT 0x40
182 +#define USB_INCSR_SENTSTALL 0x20
183 +#define USB_INCSR_SENDSTALL 0x10
184 +#define USB_INCSR_FF 0x08
185 +#define USB_INCSR_UNDERRUN 0x04
186 +#define USB_INCSR_FFNOTEMPT 0x02
187 +#define USB_INCSR_INPKTRDY 0x01
189 +#define USB_OUTCSRH_AUTOCLR 0x80
190 +#define USB_OUTCSRH_ISO 0x40
191 +#define USB_OUTCSRH_DMAREQENAB 0x20
192 +#define USB_OUTCSRH_DNYT 0x10
193 +#define USB_OUTCSRH_DMAREQMODE 0x08
194 +#define USB_OUTCSR_CDT 0x80
195 +#define USB_OUTCSR_SENTSTALL 0x40
196 +#define USB_OUTCSR_SENDSTALL 0x20
197 +#define USB_OUTCSR_FF 0x10
198 +#define USB_OUTCSR_DATAERR 0x08
199 +#define USB_OUTCSR_OVERRUN 0x04
200 +#define USB_OUTCSR_FFFULL 0x02
201 +#define USB_OUTCSR_OUTPKTRDY 0x01
203 +/* DMA control bits */
204 +#define USB_CNTL_ENA 0x01
205 +#define USB_CNTL_DIR_IN 0x02
206 +#define USB_CNTL_MODE_1 0x04
207 +#define USB_CNTL_INTR_EN 0x08
208 +#define USB_CNTL_EP(n) ((n) << 4)
209 +#define USB_CNTL_BURST_0 (0 << 9)
210 +#define USB_CNTL_BURST_4 (1 << 9)
211 +#define USB_CNTL_BURST_8 (2 << 9)
212 +#define USB_CNTL_BURST_16 (3 << 9)
216 +# define DEBUG(fmt,args...) do {} while(0)
220 +# define DEBUG_EP0(fmt,args...) do {} while(0)
223 +# define DEBUG_SETUP(fmt,args...) do {} while(0)
226 +static struct jz4740_udc jz4740_udc_controller;
229 + * Local declarations.
231 +static int jz4740_udc_start(struct usb_gadget_driver *driver,
232 + int (*bind)(struct usb_gadget *));
233 +static int jz4740_udc_stop(struct usb_gadget_driver *driver);
234 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
235 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
237 +static void done(struct jz4740_ep *ep, struct jz4740_request *req,
239 +static void pio_irq_enable(struct jz4740_ep *ep);
240 +static void pio_irq_disable(struct jz4740_ep *ep);
241 +static void stop_activity(struct jz4740_udc *dev,
242 + struct usb_gadget_driver *driver);
243 +static void nuke(struct jz4740_ep *ep, int status);
244 +static void flush(struct jz4740_ep *ep);
245 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
247 +/*-------------------------------------------------------------------------*/
249 +/* inline functions of register read/write/set/clear */
251 +static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
253 + return readb(udc->base + reg);
256 +static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
258 + return readw(udc->base + reg);
261 +static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
263 + return readl(udc->base + reg);
266 +static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
268 + writeb(val, udc->base + reg);
271 +static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
273 + writew(val, udc->base + reg);
276 +static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
278 + writel(val, udc->base + reg);
281 +static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
283 + usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
286 +static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
288 + usb_writew(udc, reg, usb_readw(udc, reg) | mask);
291 +static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
293 + usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
296 +static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
298 + usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
301 +/*-------------------------------------------------------------------------*/
303 +static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
305 + usb_writeb(udc, JZ_REG_UDC_INDEX, index);
308 +static inline void jz_udc_select_ep(struct jz4740_ep *ep)
310 + jz_udc_set_index(ep->dev, ep_index(ep));
313 +static inline int write_packet(struct jz4740_ep *ep,
314 + struct jz4740_request *req, unsigned int count)
317 + unsigned int length;
318 + void __iomem *fifo = ep->dev->base + ep->fifo;
320 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
322 + buf = req->req.buf + req->req.actual;
324 + length = req->req.length - req->req.actual;
325 + if (length > count)
327 + req->req.actual += length;
329 + DEBUG("Write %d (count %d), fifo %x\n", length, count, ep->fifo);
331 + writesl(fifo, buf, length >> 2);
332 + writesb(fifo, &buf[length - (length & 3)], length & 3);
337 +static int read_packet(struct jz4740_ep *ep,
338 + struct jz4740_request *req, unsigned int count)
341 + unsigned int length;
342 + void __iomem *fifo = ep->dev->base + ep->fifo;
343 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
345 + buf = req->req.buf + req->req.actual;
347 + length = req->req.length - req->req.actual;
348 + if (length > count)
350 + req->req.actual += length;
352 + DEBUG("Read %d, fifo %x\n", length, ep->fifo);
354 + readsl(fifo, buf, length >> 2);
355 + readsb(fifo, &buf[length - (length & 3)], length & 3);
360 +/*-------------------------------------------------------------------------*/
363 + * udc_disable - disable USB device controller
365 +static void udc_disable(struct jz4740_udc *dev)
367 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
369 + udc_set_address(dev, 0);
371 + /* Disable interrupts */
372 + usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
373 + usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
374 + usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
377 + usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
378 + usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
380 + /* Disconnect from usb */
381 + usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
383 + /* Disable the USB PHY */
384 + clk_disable(dev->clk);
386 + dev->ep0state = WAIT_FOR_SETUP;
387 + dev->gadget.speed = USB_SPEED_UNKNOWN;
393 + * udc_reinit - initialize software state
395 +static void udc_reinit(struct jz4740_udc *dev)
398 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
400 + /* device/ep0 records init */
401 + INIT_LIST_HEAD(&dev->gadget.ep_list);
402 + INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
403 + dev->ep0state = WAIT_FOR_SETUP;
405 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
406 + struct jz4740_ep *ep = &dev->ep[i];
409 + list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
411 + INIT_LIST_HEAD(&ep->queue);
417 +/* until it's enabled, this UDC should be completely invisible
420 +static void udc_enable(struct jz4740_udc *dev)
423 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
425 + /* UDC state is incorrect - Added by River */
426 + if (dev->state != UDC_STATE_ENABLE) {
430 + dev->gadget.speed = USB_SPEED_UNKNOWN;
432 + /* Flush FIFO for each */
433 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
434 + struct jz4740_ep *ep = &dev->ep[i];
436 + jz_udc_select_ep(ep);
440 + /* Set this bit to allow the UDC entering low-power mode when
441 + * there are no actions on the USB bus.
442 + * UDC still works during this bit was set.
444 + jz4740_clock_udc_enable_auto_suspend();
446 + /* Enable the USB PHY */
447 + clk_enable(dev->clk);
449 + /* Disable interrupts */
450 +/* usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
451 + usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
452 + usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
454 + /* Enable interrupts */
455 + usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
456 + usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
457 + /* Don't enable rest of the interrupts */
458 + /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
459 + usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
461 + /* Enable SUSPEND */
462 + /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
464 + /* Enable HS Mode */
465 + usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
467 + /* Let host detect UDC:
468 + * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
469 + * transistor on and pull the USBDP pin HIGH.
471 + usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
476 +/*-------------------------------------------------------------------------*/
478 +/* keeping it simple:
479 + * - one bus driver, initted first;
480 + * - one function driver, initted second
484 + * Register entry point for the peripheral controller driver.
487 +static int jz4740_udc_start(struct usb_gadget_driver *driver,
488 + int (*bind)(struct usb_gadget *))
490 + struct jz4740_udc *dev = &jz4740_udc_controller;
493 + if (!driver || !bind)
502 + /* hook up the driver */
503 + dev->driver = driver;
504 + dev->gadget.dev.driver = &driver->driver;
506 + retval = bind(&dev->gadget);
508 + DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name,
509 + driver->driver.name, retval);
514 + /* then enable host detection and ep0; and we're ready
515 + * for set_configuration as well as eventual disconnect.
519 + DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name,
520 + driver->driver.name);
525 +static void stop_activity(struct jz4740_udc *dev,
526 + struct usb_gadget_driver *driver)
530 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
532 + /* don't disconnect drivers more than once */
533 + if (dev->gadget.speed == USB_SPEED_UNKNOWN)
535 + dev->gadget.speed = USB_SPEED_UNKNOWN;
537 + /* prevent new request submissions, kill any outstanding requests */
538 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
539 + struct jz4740_ep *ep = &dev->ep[i];
543 + jz_udc_select_ep(ep);
544 + nuke(ep, -ESHUTDOWN);
547 + /* report disconnect; the driver is already quiesced */
549 + spin_unlock(&dev->lock);
550 + driver->disconnect(&dev->gadget);
551 + spin_lock(&dev->lock);
554 + /* re-init driver-visible data structures */
560 + * Unregister entry point for the peripheral controller driver.
562 +static int jz4740_udc_stop(struct usb_gadget_driver *driver)
564 + struct jz4740_udc *dev = &jz4740_udc_controller;
565 + unsigned long flags;
566 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
570 + if (!driver || driver != dev->driver)
572 + if (!driver->unbind)
575 + spin_lock_irqsave(&dev->lock, flags);
577 + stop_activity(dev, driver);
578 + spin_unlock_irqrestore(&dev->lock, flags);
580 + driver->unbind(&dev->gadget);
584 + DEBUG("unregistered driver '%s'\n", driver->driver.name);
589 +/*-------------------------------------------------------------------------*/
591 +/** Write request to FIFO (max write == maxp size)
592 + * Return: 0 = still running, 1 = completed, negative = errno
593 + * NOTE: INDEX register must be set for EP
595 +static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
597 + struct jz4740_udc *dev = ep->dev;
600 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
601 + max = le16_to_cpu(ep->desc->wMaxPacketSize);
603 + csr = usb_readb(dev, ep->csr);
605 + if (!(csr & USB_INCSR_FFNOTEMPT)) {
607 + int is_last, is_short;
609 + count = write_packet(ep, req, max);
610 + usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
612 + /* last packet is usually short (or a zlp) */
613 + if (unlikely(count != max))
614 + is_last = is_short = 1;
616 + if (likely(req->req.length != req->req.actual)
621 + /* interrupt/iso maxpacket may not fill the fifo */
622 + is_short = unlikely(max < ep_maxpacket(ep));
625 + DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
626 + ep->ep.name, count,
627 + is_last ? "/L" : "", is_short ? "/S" : "",
628 + req->req.length - req->req.actual, req);
630 + /* requests complete when all IN data is in the FIFO */
633 + if (list_empty(&ep->queue)) {
634 + pio_irq_disable(ep);
639 + DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
645 +/** Read to request from FIFO (max read == bytes in fifo)
646 + * Return: 0 = still running, 1 = completed, negative = errno
647 + * NOTE: INDEX register must be set for EP
649 +static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
651 + struct jz4740_udc *dev = ep->dev;
653 + unsigned count, is_short;
655 + /* make sure there's a packet in the FIFO. */
656 + csr = usb_readb(dev, ep->csr);
657 + if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
658 + DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
662 + /* read all bytes from this packet */
663 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
665 + is_short = (count < ep->ep.maxpacket);
667 + count = read_packet(ep, req, count);
669 + DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
670 + ep->ep.name, csr, count,
671 + is_short ? "/S" : "", req, req->req.actual, req->req.length);
673 + /* Clear OutPktRdy */
674 + usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
677 + if (is_short || req->req.actual == req->req.length) {
680 + if (list_empty(&ep->queue))
681 + pio_irq_disable(ep);
685 + /* finished that packet. the next one may be waiting... */
690 + * done - retire a request; caller blocked irqs
691 + * INDEX register is preserved to keep same
693 +static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
695 + unsigned int stopped = ep->stopped;
698 + DEBUG("%s, %p\n", __FUNCTION__, ep);
699 + list_del_init(&req->queue);
701 + if (likely(req->req.status == -EINPROGRESS))
702 + req->req.status = status;
704 + status = req->req.status;
706 + if (status && status != -ESHUTDOWN)
707 + DEBUG("complete %s req %p stat %d len %u/%u\n",
708 + ep->ep.name, &req->req, status,
709 + req->req.actual, req->req.length);
711 + /* don't modify queue heads during completion callback */
713 + /* Read current index (completion may modify it) */
714 + index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
715 + spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags);
717 + req->req.complete(&ep->ep, &req->req);
719 + spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags);
720 + /* Restore index */
721 + jz_udc_set_index(ep->dev, index);
722 + ep->stopped = stopped;
725 +static inline unsigned int jz4740_udc_ep_irq_enable_reg(struct jz4740_ep *ep)
728 + return JZ_REG_UDC_INTRINE;
730 + return JZ_REG_UDC_INTROUTE;
733 +/** Enable EP interrupt */
734 +static void pio_irq_enable(struct jz4740_ep *ep)
736 + DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
738 + usb_setw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
741 +/** Disable EP interrupt */
742 +static void pio_irq_disable(struct jz4740_ep *ep)
744 + DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
746 + usb_clearw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
750 + * nuke - dequeue ALL requests
752 +static void nuke(struct jz4740_ep *ep, int status)
754 + struct jz4740_request *req;
756 + DEBUG("%s, %p\n", __FUNCTION__, ep);
761 + /* called with irqs blocked */
762 + while (!list_empty(&ep->queue)) {
763 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
764 + done(ep, req, status);
767 + /* Disable IRQ if EP is enabled (has descriptor) */
769 + pio_irq_disable(ep);
773 + * NOTE: INDEX register must be set before this call
775 +static void flush(struct jz4740_ep *ep)
777 + DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
779 + switch (ep->type) {
782 + usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
785 + usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
793 + * jz4740_in_epn - handle IN interrupt
795 +static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
798 + struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
799 + struct jz4740_request *req;
800 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
802 + jz_udc_select_ep(ep);
804 + csr = usb_readb(dev, ep->csr);
805 + DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
807 + if (csr & USB_INCSR_SENTSTALL) {
808 + DEBUG("USB_INCSR_SENTSTALL\n");
809 + usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
814 + DEBUG("%s: NO EP DESC\n", __FUNCTION__);
818 + if (!list_empty(&ep->queue)) {
819 + req = list_first_entry(&ep->queue, struct jz4740_request, queue);
820 + write_fifo(ep, req);
827 +static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
829 + struct jz4740_ep *ep = &dev->ep[ep_idx];
830 + struct jz4740_request *req;
832 + DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
834 + jz_udc_select_ep(ep);
838 + while ((csr = usb_readb(dev, ep->csr)) &
839 + (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
840 + DEBUG("%s: %x\n", __FUNCTION__, csr);
842 + if (csr & USB_OUTCSR_SENTSTALL) {
843 + DEBUG("%s: stall sent, flush fifo\n",
845 + /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
847 + } else if (csr & USB_OUTCSR_OUTPKTRDY) {
848 + if (list_empty(&ep->queue))
852 + list_entry(ep->queue.next,
853 + struct jz4740_request,
857 + DEBUG("%s: NULL REQ %d\n",
858 + __FUNCTION__, ep_idx);
861 + read_fifo(ep, req);
866 + /* Throw packet away.. */
867 + DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
872 +/** Halt specific EP
873 + * Return 0 if success
874 + * NOTE: Sets INDEX register to EP !
876 +static int jz4740_set_halt(struct usb_ep *_ep, int value)
878 + struct jz4740_udc *dev;
879 + struct jz4740_ep *ep;
880 + unsigned long flags;
882 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
884 + ep = container_of(_ep, struct jz4740_ep, ep);
885 + if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
886 + DEBUG("%s, bad ep\n", __FUNCTION__);
892 + spin_lock_irqsave(&dev->lock, flags);
894 + jz_udc_select_ep(ep);
896 + DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
898 + if (ep_index(ep) == 0) {
900 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
901 + } else if (ep_is_in(ep)) {
902 + uint32_t csr = usb_readb(dev, ep->csr);
903 + if (value && ((csr & USB_INCSR_FFNOTEMPT)
904 + || !list_empty(&ep->queue))) {
906 + * Attempts to halt IN endpoints will fail (returning -EAGAIN)
907 + * if any transfer requests are still queued, or if the controller
908 + * FIFO still holds bytes that the host hasn
\92t collected.
910 + spin_unlock_irqrestore(&dev->lock, flags);
912 + ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
913 + (csr & USB_INCSR_FFNOTEMPT),
914 + !list_empty(&ep->queue));
919 + usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
921 + usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
922 + usb_setb(dev, ep->csr, USB_INCSR_CDT);
928 + usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
930 + usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
931 + usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
935 + ep->stopped = value;
937 + spin_unlock_irqrestore(&dev->lock, flags);
939 + DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
945 +static int jz4740_ep_enable(struct usb_ep *_ep,
946 + const struct usb_endpoint_descriptor *desc)
948 + struct jz4740_ep *ep;
949 + struct jz4740_udc *dev;
950 + unsigned long flags;
951 + uint32_t max, csrh = 0;
953 + DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
958 + ep = container_of(_ep, struct jz4740_ep, ep);
959 + if (ep->desc || ep->type == ep_control
960 + || desc->bDescriptorType != USB_DT_ENDPOINT
961 + || ep->bEndpointAddress != desc->bEndpointAddress) {
962 + DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
966 + /* xfer types must match, except that interrupt ~= bulk */
967 + if (ep->bmAttributes != desc->bmAttributes
968 + && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
969 + && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
970 + DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
975 + if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
976 + DEBUG("%s, bogus device state\n", __FUNCTION__);
980 + max = le16_to_cpu(desc->wMaxPacketSize);
982 + spin_lock_irqsave(&ep->dev->lock, flags);
984 + /* Configure the endpoint */
985 + jz_udc_select_ep(ep);
986 + if (ep_is_in(ep)) {
987 + usb_writew(dev, JZ_REG_UDC_INMAXP, max);
988 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
989 + case USB_ENDPOINT_XFER_BULK:
990 + case USB_ENDPOINT_XFER_INT:
991 + csrh &= ~USB_INCSRH_ISO;
993 + case USB_ENDPOINT_XFER_ISOC:
994 + csrh |= USB_INCSRH_ISO;
997 + usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
1000 + usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
1001 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
1002 + case USB_ENDPOINT_XFER_BULK:
1003 + csrh &= ~USB_OUTCSRH_ISO;
1005 + case USB_ENDPOINT_XFER_INT:
1006 + csrh &= ~USB_OUTCSRH_ISO;
1007 + csrh |= USB_OUTCSRH_DNYT;
1009 + case USB_ENDPOINT_XFER_ISOC:
1010 + csrh |= USB_OUTCSRH_ISO;
1013 + usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
1019 + ep->ep.maxpacket = max;
1021 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1023 + /* Reset halt state (does flush) */
1024 + jz4740_set_halt(_ep, 0);
1026 + DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
1032 + * NOTE: Sets INDEX register
1034 +static int jz4740_ep_disable(struct usb_ep *_ep)
1036 + struct jz4740_ep *ep;
1037 + unsigned long flags;
1039 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1041 + ep = container_of(_ep, struct jz4740_ep, ep);
1042 + if (!_ep || !ep->desc) {
1043 + DEBUG("%s, %s not enabled\n", __FUNCTION__,
1044 + _ep ? ep->ep.name : NULL);
1048 + spin_lock_irqsave(&ep->dev->lock, flags);
1050 + jz_udc_select_ep(ep);
1052 + /* Nuke all pending requests (does flush) */
1053 + nuke(ep, -ESHUTDOWN);
1055 + /* Disable ep IRQ */
1056 + pio_irq_disable(ep);
1061 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1063 + DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
1067 +static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1069 + struct jz4740_request *req;
1071 + req = kzalloc(sizeof(*req), gfp_flags);
1075 + INIT_LIST_HEAD(&req->queue);
1080 +static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1082 + struct jz4740_request *req;
1084 + req = container_of(_req, struct jz4740_request, req);
1085 + WARN_ON(!list_empty(&req->queue));
1090 +/*--------------------------------------------------------------------*/
1092 +/** Queue one request
1093 + * Kickstart transfer if needed
1094 + * NOTE: Sets INDEX register
1096 +static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1099 + struct jz4740_request *req;
1100 + struct jz4740_ep *ep;
1101 + struct jz4740_udc *dev;
1103 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1105 + req = container_of(_req, struct jz4740_request, req);
1107 + (!_req || !_req->complete || !_req->buf
1108 + || !list_empty(&req->queue))) {
1109 + DEBUG("%s, bad params\n", __FUNCTION__);
1113 + ep = container_of(_ep, struct jz4740_ep, ep);
1114 + if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1115 + DEBUG("%s, bad ep\n", __FUNCTION__);
1120 + if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1121 + DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1122 + return -ESHUTDOWN;
1125 + DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1128 + spin_lock_irqsave(&dev->lock, dev->lock_flags);
1130 + _req->status = -EINPROGRESS;
1133 + /* kickstart this i/o queue? */
1134 + DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1136 + if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1139 + if (unlikely(ep_index(ep) == 0)) {
1141 + list_add_tail(&req->queue, &ep->queue);
1142 + jz4740_ep0_kick(dev, ep);
1145 + else if (ep_is_in(ep)) {
1147 + jz_udc_select_ep(ep);
1148 + csr = usb_readb(dev, ep->csr);
1149 + pio_irq_enable(ep);
1150 + if (!(csr & USB_INCSR_FFNOTEMPT)) {
1151 + if (write_fifo(ep, req) == 1)
1156 + jz_udc_select_ep(ep);
1157 + csr = usb_readb(dev, ep->csr);
1158 + pio_irq_enable(ep);
1159 + if (csr & USB_OUTCSR_OUTPKTRDY) {
1160 + if (read_fifo(ep, req) == 1)
1166 + /* pio or dma irq handler advances the queue. */
1167 + if (likely(req != 0))
1168 + list_add_tail(&req->queue, &ep->queue);
1170 + spin_unlock_irqrestore(&dev->lock, dev->lock_flags);
1175 +/* dequeue JUST ONE request */
1176 +static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1178 + struct jz4740_ep *ep;
1179 + struct jz4740_request *req;
1180 + unsigned long flags;
1182 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1184 + ep = container_of(_ep, struct jz4740_ep, ep);
1185 + if (!_ep || ep->type == ep_control)
1188 + spin_lock_irqsave(&ep->dev->lock, flags);
1190 + /* make sure it's actually queued on this endpoint */
1191 + list_for_each_entry(req, &ep->queue, queue) {
1192 + if (&req->req == _req)
1195 + if (&req->req != _req) {
1196 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1199 + done(ep, req, -ECONNRESET);
1201 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1205 +/** Return bytes in EP FIFO
1206 + * NOTE: Sets INDEX register to EP
1208 +static int jz4740_fifo_status(struct usb_ep *_ep)
1212 + struct jz4740_ep *ep;
1213 + unsigned long flags;
1215 + ep = container_of(_ep, struct jz4740_ep, ep);
1217 + DEBUG("%s, bad ep\n", __FUNCTION__);
1221 + DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1223 + /* LPD can't report unclaimed bytes from IN fifos */
1225 + return -EOPNOTSUPP;
1227 + spin_lock_irqsave(&ep->dev->lock, flags);
1228 + jz_udc_select_ep(ep);
1230 + csr = usb_readb(ep->dev, ep->csr);
1231 + if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1233 + count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1236 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1242 + * NOTE: Sets INDEX register to EP
1244 +static void jz4740_fifo_flush(struct usb_ep *_ep)
1246 + struct jz4740_ep *ep;
1247 + unsigned long flags;
1249 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1251 + ep = container_of(_ep, struct jz4740_ep, ep);
1252 + if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1253 + DEBUG("%s, bad ep\n", __FUNCTION__);
1257 + spin_lock_irqsave(&ep->dev->lock, flags);
1259 + jz_udc_select_ep(ep);
1262 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1265 +/****************************************************************/
1266 +/* End Point 0 related functions */
1267 +/****************************************************************/
1269 +/* return: 0 = still running, 1 = completed, negative = errno */
1270 +static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1276 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1277 + max = ep_maxpacket(ep);
1279 + count = write_packet(ep, req, max);
1281 + /* last packet is usually short (or a zlp) */
1282 + if (unlikely(count != max))
1285 + if (likely(req->req.length != req->req.actual) || req->req.zero)
1291 + DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1292 + ep->ep.name, count,
1293 + is_last ? "/L" : "", req->req.length - req->req.actual, req);
1295 + /* requests complete when all IN data is in the FIFO */
1304 +static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1305 + unsigned char *cp, int max)
1308 + int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1314 + *cp++ = usb_readb(ep->dev, ep->fifo);
1319 +static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1320 + unsigned char *cp, int count)
1322 + DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1324 + usb_writeb(ep->dev, ep->fifo, *cp++);
1327 +static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1329 + struct jz4740_udc *dev = ep->dev;
1332 + unsigned bufferspace, count, is_short;
1334 + DEBUG_EP0("%s\n", __FUNCTION__);
1336 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1337 + if (!(csr & USB_CSR0_OUTPKTRDY))
1340 + buf = req->req.buf + req->req.actual;
1342 + bufferspace = req->req.length - req->req.actual;
1344 + /* read all bytes from this packet */
1345 + if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1346 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1347 + req->req.actual += min(count, bufferspace);
1351 + is_short = (count < ep->ep.maxpacket);
1352 + DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1353 + ep->ep.name, csr, count,
1354 + is_short ? "/S" : "", req, req->req.actual, req->req.length);
1356 + while (likely(count-- != 0)) {
1357 + uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1359 + if (unlikely(bufferspace == 0)) {
1360 + /* this happens when the driver's buffer
1361 + * is smaller than what the host sent.
1362 + * discard the extra data.
1364 + if (req->req.status != -EOVERFLOW)
1365 + DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1367 + req->req.status = -EOVERFLOW;
1375 + if (is_short || req->req.actual == req->req.length) {
1380 + /* finished that packet. the next one may be waiting... */
1385 + * udc_set_address - set the USB address for this device
1388 + * Called from control endpoint function after it decodes a set address setup packet.
1390 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1392 + DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1394 + usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1398 + * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1400 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1402 + * set USB_CSR0_SVDOUTPKTRDY bit
1403 + if last set USB_CSR0_DATAEND bit
1405 +static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1407 + struct jz4740_request *req;
1408 + struct jz4740_ep *ep = &dev->ep[0];
1411 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1413 + if (list_empty(&ep->queue))
1416 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1419 + if (req->req.length == 0) {
1420 + DEBUG_EP0("ZERO LENGTH OUT!\n");
1421 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1422 + dev->ep0state = WAIT_FOR_SETUP;
1424 + } else if (kickstart) {
1425 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1428 + ret = read_fifo_ep0(ep, req);
1431 + DEBUG_EP0("%s: finished, waiting for status\n",
1433 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1434 + dev->ep0state = WAIT_FOR_SETUP;
1436 + /* Not done yet.. */
1437 + DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1438 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1441 + DEBUG_EP0("NO REQ??!\n");
1448 +static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1450 + struct jz4740_request *req;
1451 + struct jz4740_ep *ep = &dev->ep[0];
1452 + int ret, need_zlp = 0;
1454 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1456 + if (list_empty(&ep->queue))
1459 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1462 + DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1466 + if (req->req.length == 0) {
1467 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1468 + dev->ep0state = WAIT_FOR_SETUP;
1472 + if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1473 + /* Next write will end with the packet size, */
1474 + /* so we need zero-length-packet */
1478 + ret = write_fifo_ep0(ep, req);
1480 + if (ret == 1 && !need_zlp) {
1482 + DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1484 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1485 + dev->ep0state = WAIT_FOR_SETUP;
1487 + DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1488 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1492 + DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1493 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1494 + dev->ep0state = DATA_STATE_NEED_ZLP;
1500 +static int jz4740_handle_get_status(struct jz4740_udc *dev,
1501 + struct usb_ctrlrequest *ctrl)
1503 + struct jz4740_ep *ep0 = &dev->ep[0];
1504 + struct jz4740_ep *qep;
1505 + int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1508 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1510 + if (reqtype == USB_RECIP_INTERFACE) {
1511 + /* This is not supported.
1512 + * And according to the USB spec, this one does nothing..
1515 + DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1516 + } else if (reqtype == USB_RECIP_DEVICE) {
1517 + DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1518 + val |= (1 << 0); /* Self powered */
1519 + /*val |= (1<<1); *//* Remote wakeup */
1520 + } else if (reqtype == USB_RECIP_ENDPOINT) {
1521 + int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1524 + ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1525 + ep_num, ctrl->wLength);
1527 + if (ctrl->wLength > 2 || ep_num > 3)
1528 + return -EOPNOTSUPP;
1530 + qep = &dev->ep[ep_num];
1531 + if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1532 + && ep_index(qep) != 0) {
1533 + return -EOPNOTSUPP;
1536 + jz_udc_select_ep(qep);
1538 + /* Return status on next IN token */
1539 + switch (qep->type) {
1542 + (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1543 + USB_CSR0_SENDSTALL;
1546 + case ep_interrupt:
1548 + (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1549 + USB_INCSR_SENDSTALL;
1553 + (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1554 + USB_OUTCSR_SENDSTALL;
1558 + /* Back to EP0 index */
1559 + jz_udc_set_index(dev, 0);
1561 + DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1562 + ctrl->wIndex, val);
1564 + DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1565 + return -EOPNOTSUPP;
1568 + /* Clear "out packet ready" */
1569 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1570 + /* Put status to FIFO */
1571 + jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1572 + /* Issue "In packet ready" */
1573 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1579 + * WAIT_FOR_SETUP (OUTPKTRDY)
1580 + * - read data packet from EP0 FIFO
1581 + * - decode command
1583 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1585 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1587 +static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1589 + struct jz4740_ep *ep = &dev->ep[0];
1590 + struct usb_ctrlrequest ctrl;
1593 + DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1595 + /* Nuke all previous transfers */
1596 + nuke(ep, -EPROTO);
1598 + /* read control req from fifo (8 bytes) */
1599 + jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1601 + DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1602 + ctrl.bRequestType, ctrl.bRequest,
1603 + ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1605 + /* Set direction of EP0 */
1606 + if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1607 + ep->bEndpointAddress |= USB_DIR_IN;
1609 + ep->bEndpointAddress &= ~USB_DIR_IN;
1612 + /* Handle some SETUP packets ourselves */
1613 + switch (ctrl.bRequest) {
1614 + case USB_REQ_SET_ADDRESS:
1615 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1618 + DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1619 + udc_set_address(dev, ctrl.wValue);
1620 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1623 + case USB_REQ_SET_CONFIGURATION:
1624 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1627 + DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1628 +/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1630 + /* Enable RESUME and SUSPEND interrupts */
1631 + usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1634 + case USB_REQ_SET_INTERFACE:
1635 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1638 + DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1639 +/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1642 + case USB_REQ_GET_STATUS:
1643 + if (jz4740_handle_get_status(dev, &ctrl) == 0)
1646 + case USB_REQ_CLEAR_FEATURE:
1647 + case USB_REQ_SET_FEATURE:
1648 + if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1649 + struct jz4740_ep *qep;
1650 + int ep_num = (ctrl.wIndex & 0x0f);
1652 + /* Support only HALT feature */
1653 + if (ctrl.wValue != 0 || ctrl.wLength != 0
1654 + || ep_num > 3 || ep_num < 1)
1657 + qep = &dev->ep[ep_num];
1658 + spin_unlock(&dev->lock);
1659 + if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1660 + DEBUG_SETUP("SET_FEATURE (%d)\n",
1662 + jz4740_set_halt(&qep->ep, 1);
1664 + DEBUG_SETUP("CLR_FEATURE (%d)\n",
1666 + jz4740_set_halt(&qep->ep, 0);
1668 + spin_lock(&dev->lock);
1670 + jz_udc_set_index(dev, 0);
1672 + /* Reply with a ZLP on next IN token */
1673 + usb_setb(dev, JZ_REG_UDC_CSR0,
1674 + (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1683 + /* gadget drivers see class/vendor specific requests,
1684 + * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1687 + if (dev->driver) {
1688 + /* device-2-host (IN) or no data setup command, process immediately */
1689 + spin_unlock(&dev->lock);
1691 + i = dev->driver->setup(&dev->gadget, &ctrl);
1692 + spin_lock(&dev->lock);
1694 + if (unlikely(i < 0)) {
1695 + /* setup processing failed, force stall */
1697 + (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1699 + jz_udc_set_index(dev, 0);
1700 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1702 + /* ep->stopped = 1; */
1703 + dev->ep0state = WAIT_FOR_SETUP;
1706 + DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1707 +/* if (!ctrl.wLength) {
1708 + usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1715 + * DATA_STATE_NEED_ZLP
1717 +static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1719 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1721 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1722 + dev->ep0state = WAIT_FOR_SETUP;
1726 + * handle ep0 interrupt
1728 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1730 + struct jz4740_ep *ep = &dev->ep[0];
1733 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1735 + jz_udc_set_index(dev, 0);
1736 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1738 + DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1741 + * if SENT_STALL is set
1742 + * - clear the SENT_STALL bit
1744 + if (csr & USB_CSR0_SENTSTALL) {
1745 + DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1746 + usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1747 + nuke(ep, -ECONNABORTED);
1748 + dev->ep0state = WAIT_FOR_SETUP;
1753 + * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
1755 + * - if last packet
1756 + * - set IN_PKT_RDY | DATA_END
1760 + if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
1761 + DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
1764 + switch (dev->ep0state) {
1765 + case DATA_STATE_XMIT:
1766 + DEBUG_EP0("continue with DATA_STATE_XMIT\n");
1767 + jz4740_ep0_in(dev, csr);
1769 + case DATA_STATE_NEED_ZLP:
1770 + DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
1771 + jz4740_ep0_in_zlp(dev, csr);
1775 +// DEBUG_EP0("Odd state!! state = %s\n",
1776 +// state_names[dev->ep0state]);
1777 + dev->ep0state = WAIT_FOR_SETUP;
1778 + /* nuke(ep, 0); */
1779 + /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
1786 + * if SETUPEND is set
1787 + * - abort the last transfer
1788 + * - set SERVICED_SETUP_END_BIT
1790 + if (csr & USB_CSR0_SETUPEND) {
1791 + DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
1793 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
1795 + dev->ep0state = WAIT_FOR_SETUP;
1799 + * if USB_CSR0_OUTPKTRDY is set
1800 + * - read data packet from EP0 FIFO
1801 + * - decode command
1803 + * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
1805 + * set SVDOUTPKTRDY | DATAEND bits
1807 + if (csr & USB_CSR0_OUTPKTRDY) {
1809 + DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
1812 + switch (dev->ep0state) {
1813 + case WAIT_FOR_SETUP:
1814 + DEBUG_EP0("WAIT_FOR_SETUP\n");
1815 + jz4740_ep0_setup(dev, csr);
1818 + case DATA_STATE_RECV:
1819 + DEBUG_EP0("DATA_STATE_RECV\n");
1820 + jz4740_ep0_out(dev, csr, 0);
1825 + DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
1832 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
1836 + jz_udc_set_index(dev, 0);
1838 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1840 + /* Clear "out packet ready" */
1842 + if (ep_is_in(ep)) {
1843 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1844 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1845 + dev->ep0state = DATA_STATE_XMIT;
1846 + jz4740_ep0_in(dev, csr);
1848 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1849 + dev->ep0state = DATA_STATE_RECV;
1850 + jz4740_ep0_out(dev, csr, 1);
1854 +/** Handle USB RESET interrupt
1856 +static void jz4740_reset_irq(struct jz4740_udc *dev)
1858 + dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
1859 + USB_SPEED_HIGH : USB_SPEED_FULL;
1861 + DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, 0,
1862 + (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
1866 + * jz4740 usb device interrupt handler.
1868 +static irqreturn_t jz4740_udc_irq(int irq, void *devid)
1870 + struct jz4740_udc *jz4740_udc = devid;
1873 + uint32_t intr_usb = usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
1874 + uint32_t intr_in = usb_readw(jz4740_udc, JZ_REG_UDC_INTRIN);
1875 + uint32_t intr_out = usb_readw(jz4740_udc, JZ_REG_UDC_INTROUT);
1876 + uint32_t intr_dma = usb_readb(jz4740_udc, JZ_REG_UDC_INTR);
1878 + if (!intr_usb && !intr_in && !intr_out && !intr_dma)
1879 + return IRQ_HANDLED;
1882 + DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
1883 + intr_out, intr_in, intr_usb);
1885 + spin_lock(&jz4740_udc->lock);
1886 + index = usb_readb(jz4740_udc, JZ_REG_UDC_INDEX);
1888 + /* Check for resume from suspend mode */
1889 + if ((intr_usb & USB_INTR_RESUME) &&
1890 + (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
1891 + DEBUG("USB resume\n");
1892 + jz4740_udc->driver->resume(&jz4740_udc->gadget); /* We have suspend(), so we must have resume() too. */
1895 + /* Check for system interrupts */
1896 + if (intr_usb & USB_INTR_RESET) {
1897 + DEBUG("USB reset\n");
1898 + jz4740_reset_irq(jz4740_udc);
1901 + /* Check for endpoint 0 interrupt */
1902 + if (intr_in & USB_INTR_EP0) {
1903 + DEBUG("USB_INTR_EP0 (control)\n");
1904 + jz4740_handle_ep0(jz4740_udc, intr_in);
1907 + /* Check for Bulk-IN DMA interrupt */
1908 + if (intr_dma & 0x1) {
1910 + struct jz4740_ep *ep;
1911 + ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
1912 + ep = &jz4740_udc->ep[ep_num + 1];
1913 + jz_udc_select_ep(ep);
1914 + usb_setb(jz4740_udc, ep->csr, USB_INCSR_INPKTRDY);
1915 +/* jz4740_in_epn(jz4740_udc, ep_num, intr_in);*/
1918 + /* Check for Bulk-OUT DMA interrupt */
1919 + if (intr_dma & 0x2) {
1921 + ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
1922 + jz4740_out_epn(jz4740_udc, ep_num, intr_out);
1925 + /* Check for each configured endpoint interrupt */
1926 + if (intr_in & USB_INTR_INEP1) {
1927 + DEBUG("USB_INTR_INEP1\n");
1928 + jz4740_in_epn(jz4740_udc, 1, intr_in);
1931 + if (intr_in & USB_INTR_INEP2) {
1932 + DEBUG("USB_INTR_INEP2\n");
1933 + jz4740_in_epn(jz4740_udc, 2, intr_in);
1936 + if (intr_out & USB_INTR_OUTEP1) {
1937 + DEBUG("USB_INTR_OUTEP1\n");
1938 + jz4740_out_epn(jz4740_udc, 1, intr_out);
1941 + /* Check for suspend mode */
1942 + if ((intr_usb & USB_INTR_SUSPEND) &&
1943 + (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
1944 + DEBUG("USB suspend\n");
1945 + jz4740_udc->driver->suspend(&jz4740_udc->gadget);
1946 + /* Host unloaded from us, can do something, such as flushing
1947 + the NAND block cache etc. */
1950 + jz_udc_set_index(jz4740_udc, index);
1952 + spin_unlock(&jz4740_udc->lock);
1954 + return IRQ_HANDLED;
1959 +/*-------------------------------------------------------------------------*/
1962 +static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
1964 + return container_of(gadget, struct jz4740_udc, gadget);
1967 +static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
1969 + DEBUG("%s, %p\n", __FUNCTION__, _gadget);
1970 + return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
1973 +static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
1975 + /* host may not have enabled remote wakeup */
1976 + /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
1977 + return -EHOSTUNREACH;
1978 + udc_set_mask_UDCCR(UDCCR_RSM); */
1982 +static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
1984 + struct jz4740_udc *udc = gadget_to_udc(_gadget);
1985 + unsigned long flags;
1987 + local_irq_save(flags);
1990 + udc->state = UDC_STATE_ENABLE;
1993 + udc->state = UDC_STATE_DISABLE;
1997 + local_irq_restore(flags);
2003 +static const struct usb_gadget_ops jz4740_udc_ops = {
2004 + .get_frame = jz4740_udc_get_frame,
2005 + .wakeup = jz4740_udc_wakeup,
2006 + .pullup = jz4740_udc_pullup,
2007 + .start = jz4740_udc_start,
2008 + .stop = jz4740_udc_stop,
2011 +static struct usb_ep_ops jz4740_ep_ops = {
2012 + .enable = jz4740_ep_enable,
2013 + .disable = jz4740_ep_disable,
2015 + .alloc_request = jz4740_alloc_request,
2016 + .free_request = jz4740_free_request,
2018 + .queue = jz4740_queue,
2019 + .dequeue = jz4740_dequeue,
2021 + .set_halt = jz4740_set_halt,
2022 + .fifo_status = jz4740_fifo_status,
2023 + .fifo_flush = jz4740_fifo_flush,
2027 +/*-------------------------------------------------------------------------*/
2029 +static struct jz4740_udc jz4740_udc_controller = {
2031 + .ops = &jz4740_udc_ops,
2032 + .ep0 = &jz4740_udc_controller.ep[0].ep,
2033 + .name = "jz4740-udc",
2035 + .init_name = "gadget",
2039 + /* control endpoint */
2043 + .ops = &jz4740_ep_ops,
2044 + .maxpacket = EP0_MAXPACKETSIZE,
2046 + .dev = &jz4740_udc_controller,
2048 + .bEndpointAddress = 0,
2049 + .bmAttributes = 0,
2051 + .type = ep_control,
2052 + .fifo = JZ_REG_UDC_EP_FIFO(0),
2053 + .csr = JZ_REG_UDC_CSR0,
2056 + /* bulk out endpoint */
2059 + .name = "ep1out-bulk",
2060 + .ops = &jz4740_ep_ops,
2061 + .maxpacket = EPBULK_MAXPACKETSIZE,
2063 + .dev = &jz4740_udc_controller,
2065 + .bEndpointAddress = 1,
2066 + .bmAttributes = USB_ENDPOINT_XFER_BULK,
2068 + .type = ep_bulk_out,
2069 + .fifo = JZ_REG_UDC_EP_FIFO(1),
2070 + .csr = JZ_REG_UDC_OUTCSR,
2073 + /* bulk in endpoint */
2076 + .name = "ep1in-bulk",
2077 + .ops = &jz4740_ep_ops,
2078 + .maxpacket = EPBULK_MAXPACKETSIZE,
2080 + .dev = &jz4740_udc_controller,
2082 + .bEndpointAddress = 1 | USB_DIR_IN,
2083 + .bmAttributes = USB_ENDPOINT_XFER_BULK,
2085 + .type = ep_bulk_in,
2086 + .fifo = JZ_REG_UDC_EP_FIFO(1),
2087 + .csr = JZ_REG_UDC_INCSR,
2090 + /* interrupt in endpoint */
2093 + .name = "ep2in-int",
2094 + .ops = &jz4740_ep_ops,
2095 + .maxpacket = EPINTR_MAXPACKETSIZE,
2097 + .dev = &jz4740_udc_controller,
2099 + .bEndpointAddress = 2 | USB_DIR_IN,
2100 + .bmAttributes = USB_ENDPOINT_XFER_INT,
2102 + .type = ep_interrupt,
2103 + .fifo = JZ_REG_UDC_EP_FIFO(2),
2104 + .csr = JZ_REG_UDC_INCSR,
2108 +static int __devinit jz4740_udc_probe(struct platform_device *pdev)
2110 + struct jz4740_udc *jz4740_udc = &jz4740_udc_controller;
2113 + spin_lock_init(&jz4740_udc->lock);
2115 + jz4740_udc->dev = &pdev->dev;
2116 + jz4740_udc->gadget.dev.parent = &pdev->dev;
2117 + jz4740_udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
2119 + ret = device_register(&jz4740_udc->gadget.dev);
2123 + jz4740_udc->clk = clk_get(&pdev->dev, "udc");
2124 + if (IS_ERR(jz4740_udc->clk)) {
2125 + ret = PTR_ERR(jz4740_udc->clk);
2126 + dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret);
2127 + goto err_device_unregister;
2130 + platform_set_drvdata(pdev, jz4740_udc);
2132 + jz4740_udc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2134 + if (!jz4740_udc->mem) {
2136 + dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2140 + jz4740_udc->mem = request_mem_region(jz4740_udc->mem->start,
2141 + resource_size(jz4740_udc->mem), pdev->name);
2143 + if (!jz4740_udc->mem) {
2145 + dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2146 + goto err_device_unregister;
2149 + jz4740_udc->base = ioremap(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2151 + if (!jz4740_udc->base) {
2153 + dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2154 + goto err_release_mem_region;
2157 + jz4740_udc->irq = platform_get_irq(pdev, 0);
2158 + ret = request_irq(jz4740_udc->irq, jz4740_udc_irq, 0, pdev->name,
2161 + dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2165 + ret = usb_add_gadget_udc(&pdev->dev, &jz4740_udc->gadget);
2167 + dev_err(&pdev->dev, "Failed to add gadget: %d\n", ret);
2168 + goto err_free_irq;
2171 + udc_disable(jz4740_udc);
2172 + udc_reinit(jz4740_udc);
2177 + free_irq(jz4740_udc->irq, pdev);
2179 + iounmap(jz4740_udc->base);
2180 +err_release_mem_region:
2181 + release_mem_region(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2183 + clk_put(jz4740_udc->clk);
2184 +err_device_unregister:
2185 + device_unregister(&jz4740_udc->gadget.dev);
2186 + platform_set_drvdata(pdev, NULL);
2191 +static int __devexit jz4740_udc_remove(struct platform_device *pdev)
2193 + struct jz4740_udc *dev = platform_get_drvdata(pdev);
2195 + usb_del_gadget_udc(&dev->gadget);
2201 + free_irq(dev->irq, dev);
2202 + iounmap(dev->base);
2203 + release_mem_region(dev->mem->start, resource_size(dev->mem));
2204 + clk_put(dev->clk);
2206 + platform_set_drvdata(pdev, NULL);
2207 + device_unregister(&dev->gadget.dev);
2214 +static int jz4740_udc_suspend(struct device *dev)
2216 + struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2218 + if (jz4740_udc->state == UDC_STATE_ENABLE)
2219 + udc_disable(jz4740_udc);
2224 +static int jz4740_udc_resume(struct device *dev)
2226 + struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2228 + if (jz4740_udc->state == UDC_STATE_ENABLE)
2229 + udc_enable(jz4740_udc);
2234 +static SIMPLE_DEV_PM_OPS(jz4740_udc_pm_ops, jz4740_udc_suspend, jz4740_udc_resume);
2235 +#define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops)
2238 +#define JZ4740_UDC_PM_OPS NULL
2241 +static struct platform_driver udc_driver = {
2242 + .probe = jz4740_udc_probe,
2243 + .remove = __devexit_p(jz4740_udc_remove),
2246 + .owner = THIS_MODULE,
2247 + .pm = JZ4740_UDC_PM_OPS,
2251 +/*-------------------------------------------------------------------------*/
2253 +static int __init udc_init (void)
2255 + return platform_driver_register(&udc_driver);
2257 +module_init(udc_init);
2259 +static void __exit udc_exit (void)
2261 + platform_driver_unregister(&udc_driver);
2263 +module_exit(udc_exit);
2265 +MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2266 +MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2267 +MODULE_LICENSE("GPL");
2269 +++ b/drivers/usb/gadget/jz4740_udc.h
2272 + * linux/drivers/usb/gadget/jz4740_udc.h
2274 + * Ingenic JZ4740 on-chip high speed USB device controller
2276 + * Copyright (C) 2006 Ingenic Semiconductor Inc.
2277 + * Author: <jlwei@ingenic.cn>
2279 + * This program is free software; you can redistribute it and/or modify
2280 + * it under the terms of the GNU General Public License as published by
2281 + * the Free Software Foundation; either version 2 of the License, or
2282 + * (at your option) any later version.
2285 +#ifndef __USB_GADGET_JZ4740_H__
2286 +#define __USB_GADGET_JZ4740_H__
2288 +/*-------------------------------------------------------------------------*/
2291 +#define EP0_MAXPACKETSIZE 64
2292 +#define EPBULK_MAXPACKETSIZE 512
2293 +#define EPINTR_MAXPACKETSIZE 64
2295 +#define UDC_MAX_ENDPOINTS 4
2297 +/*-------------------------------------------------------------------------*/
2300 + ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
2305 + struct jz4740_udc *dev;
2307 + const struct usb_endpoint_descriptor *desc;
2310 + uint8_t bEndpointAddress;
2311 + uint8_t bmAttributes;
2313 + enum ep_type type;
2317 + uint32_t reg_addr;
2318 + struct list_head queue;
2321 +struct jz4740_request {
2322 + struct usb_request req;
2323 + struct list_head queue;
2327 + WAIT_FOR_SETUP, /* between STATUS ack and SETUP report */
2328 + DATA_STATE_XMIT, /* data tx stage */
2329 + DATA_STATE_NEED_ZLP, /* data tx zlp stage */
2330 + WAIT_FOR_OUT_STATUS, /* status stages */
2331 + DATA_STATE_RECV, /* data rx stage */
2334 +/* For function binding with UDC Disable - Added by River */
2336 + UDC_STATE_ENABLE = 0,
2337 + UDC_STATE_DISABLE,
2340 +struct jz4740_udc {
2341 + struct usb_gadget gadget;
2342 + struct usb_gadget_driver *driver;
2343 + struct device *dev;
2345 + unsigned long lock_flags;
2347 + enum ep0state ep0state;
2348 + struct jz4740_ep ep[UDC_MAX_ENDPOINTS];
2350 + udc_state_t state;
2352 + struct resource *mem;
2353 + void __iomem *base;
2359 +#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
2361 +static inline bool ep_is_in(const struct jz4740_ep *ep)
2363 + return (ep->bEndpointAddress & USB_DIR_IN) == USB_DIR_IN;
2366 +static inline uint8_t ep_index(const struct jz4740_ep *ep)
2368 + return ep->bEndpointAddress & 0xf;
2371 +#endif /* __USB_GADGET_JZ4740_H__ */