4 # Add -D__USE_MINGW_ACCESS to enable the built compiler to work on Windows
5 # Vista (see PR33281 for details).
6 -BOOT_CFLAGS += -D__USE_MINGW_ACCESS -Wno-pedantic-ms-format
7 -CFLAGS += -D__USE_MINGW_ACCESS
8 +# Because we wrap access in libiberty/cygpath.c, we do not want to use
9 +# the MinGW wrappers for access.
10 +BOOT_CFLAGS += -Wno-pedantic-ms-format
11 +# CFLAGS += -D__USE_MINGW_ACCESS
12 # Increase stack limit to same as Linux default.
13 LDFLAGS += -Wl,--stack,8388608
14 --- a/config/stdint.m4
15 +++ b/config/stdint.m4
16 @@ -115,19 +115,19 @@ AC_MSG_RESULT($acx_cv_header_stdint $acx
18 # Lacking an uintptr_t? Test size of void *
19 case "$acx_cv_header_stdint:$ac_cv_type_uintptr_t" in
20 - stddef.h:* | *:no) AC_CHECK_SIZEOF(void *) ;;
21 + stddef.h:* | *:no) AC_CHECK_SIZEOF(void *,,/* no standard headers */) ;;
24 # Lacking an uint64_t? Test size of long
25 case "$acx_cv_header_stdint:$ac_cv_type_uint64_t:$ac_cv_type_u_int64_t" in
26 - stddef.h:*:* | *:no:no) AC_CHECK_SIZEOF(long) ;;
27 + stddef.h:*:* | *:no:no) AC_CHECK_SIZEOF(long,,/* no standard headers */) ;;
30 if test $acx_cv_header_stdint = stddef.h; then
31 # Lacking a good header? Test size of everything and deduce all types.
32 - AC_CHECK_SIZEOF(int)
33 - AC_CHECK_SIZEOF(short)
34 - AC_CHECK_SIZEOF(char)
35 + AC_CHECK_SIZEOF(int,,/* no standard headers */)
36 + AC_CHECK_SIZEOF(short,,/* no standard headers */)
37 + AC_CHECK_SIZEOF(char,,/* no standard headers */)
39 AC_MSG_CHECKING(for type equivalent to int8_t)
40 case "$ac_cv_sizeof_char" in
44 dnl Check whether the target supports TLS.
45 AC_DEFUN([GCC_CHECK_TLS], [
46 + AC_REQUIRE([AC_CANONICAL_HOST])
47 GCC_ENABLE(tls, yes, [], [Use thread-local storage])
48 AC_CACHE_CHECK([whether the target supports thread-local storage],
50 @@ -66,7 +67,24 @@ AC_DEFUN([GCC_CHECK_TLS], [
51 [dnl This is the cross-compiling case. Assume libc supports TLS if the
52 dnl binutils and the compiler do.
53 AC_LINK_IFELSE([__thread int a; int b; int main() { return a = b; }],
54 - [gcc_cv_have_tls=yes], [gcc_cv_have_tls=no])
55 + [chktls_save_LDFLAGS="$LDFLAGS"
56 + dnl Shared library options may depend on the host; this check
57 + dnl is only known to be needed for GNU/Linux.
60 + LDFLAGS="-shared -Wl,--no-undefined $LDFLAGS"
63 + chktls_save_CFLAGS="$CFLAGS"
64 + CFLAGS="-fPIC $CFLAGS"
65 + dnl If -shared works, test if TLS works in a shared library.
66 + AC_LINK_IFELSE([int f() { return 0; }],
67 + [AC_LINK_IFELSE([__thread int a; int b; int f() { return a = b; }],
68 + [gcc_cv_have_tls=yes],
69 + [gcc_cv_have_tls=no])],
70 + [gcc_cv_have_tls=yes])
71 + CFLAGS="$chktls_save_CFLAGS"
72 + LDFLAGS="$chktls_save_LDFLAGS"], [gcc_cv_have_tls=no])
75 if test "$enable_tls $gcc_cv_have_tls" = "yes yes"; then
78 @@ -2277,7 +2277,7 @@ case "${target}" in
79 noconfigdirs="$noconfigdirs target-newlib target-libgloss target-rda ${libgcj}"
82 - noconfigdirs="$noconfigdirs target-newlib target-libgloss target-libiberty target-libstdc++-v3 ${libgcj}"
83 + noconfigdirs="$noconfigdirs target-newlib target-libgloss target-libiberty ${libgcj}"
86 # ld works, but does not support shared libraries.
89 @@ -512,7 +512,7 @@ case "${target}" in
90 noconfigdirs="$noconfigdirs target-newlib target-libgloss target-rda ${libgcj}"
93 - noconfigdirs="$noconfigdirs target-newlib target-libgloss target-libiberty target-libstdc++-v3 ${libgcj}"
94 + noconfigdirs="$noconfigdirs target-newlib target-libgloss target-libiberty ${libgcj}"
97 # ld works, but does not support shared libraries.
98 --- a/fixincludes/fixincl.tpl
99 +++ b/fixincludes/fixincl.tpl
100 @@ -38,7 +38,7 @@ x=fixincl.x =]
102 #define SED_PROGRAM "/usr/bin/sed"
104 -static char const sed_cmd_z[] = SED_PROGRAM;
105 +static char const sed_cmd_z[] = "sed";
109 --- a/fixincludes/fixincl.x
110 +++ b/fixincludes/fixincl.x
113 * DO NOT EDIT THIS FILE (fixincl.x)
115 - * It has been AutoGen-ed Saturday February 28, 2009 at 10:11:41 AM PST
116 + * It has been AutoGen-ed Monday July 20, 2009 at 01:53:53 PM PDT
117 * From the definitions inclhack.def
118 * and the template file fixincl
120 -/* DO NOT SVN-MERGE THIS FILE, EITHER Sat Feb 28 10:11:41 PST 2009
121 +/* DO NOT SVN-MERGE THIS FILE, EITHER Mon Jul 20 13:53:53 PDT 2009
123 * You must regenerate it. Use the ./genfixes script.
126 * certain ANSI-incompatible system header files which are fixed to work
127 * correctly with ANSI C and placed in a directory that GNU C will search.
129 - * This file contains 180 fixup descriptions.
130 + * This file contains 181 fixup descriptions.
132 * See README for more information.
136 #define SED_PROGRAM "/usr/bin/sed"
138 -static char const sed_cmd_z[] = SED_PROGRAM;
139 +static char const sed_cmd_z[] = "sed";
141 /* * * * * * * * * * * * * * * * * * * * * * * * * *
143 @@ -2300,6 +2300,42 @@ s/{ { 0, } }/{ { 0, 0, 0, 0, 0, 0 } }/\n
145 /* * * * * * * * * * * * * * * * * * * * * * * * * *
147 + * Description of Glibc_String2_Memset fix
149 +tSCC zGlibc_String2_MemsetName[] =
150 + "glibc_string2_memset";
153 + * File name selection pattern
155 +tSCC zGlibc_String2_MemsetList[] =
156 + "bits/string2.h\0";
158 + * Machine/OS name selection pattern
160 +#define apzGlibc_String2_MemsetMachs (const char**)NULL
163 + * content selection pattern - do fix if pattern found
165 +tSCC zGlibc_String2_MemsetSelect0[] =
166 + "#ifndef _HAVE_STRING_ARCH_memset\n\
167 +# if _STRING_ARCH_unaligned";
169 +#define GLIBC_STRING2_MEMSET_TEST_CT 1
170 +static tTestDesc aGlibc_String2_MemsetTests[] = {
171 + { TT_EGREP, zGlibc_String2_MemsetSelect0, (regex_t*)NULL }, };
174 + * Fix Command Arguments for Glibc_String2_Memset
176 +static const char* apzGlibc_String2_MemsetPatch[] = {
181 +/* * * * * * * * * * * * * * * * * * * * * * * * * *
183 * Description of Gnu_Types fix
185 tSCC zGnu_TypesName[] =
186 @@ -5617,8 +5653,7 @@ tSCC zSolaris_Mutex_Init_2List[] =
187 * Machine/OS name selection pattern
189 tSCC* apzSolaris_Mutex_Init_2Machs[] = {
190 - "*-*-solaris2.[0-9]",
191 - "*-*-solaris2.[0-9][!0-9]*",
196 @@ -5627,8 +5662,15 @@ tSCC* apzSolaris_Mutex_Init_2Machs[] = {
197 tSCC zSolaris_Mutex_Init_2Select0[] =
198 "@\\(#\\)pthread.h[ \t]+1.[0-9]+[ \t]+[0-9/]+ SMI";
200 -#define SOLARIS_MUTEX_INIT_2_TEST_CT 1
202 + * perform the 'test' shell command - do fix on success
204 +tSCC zSolaris_Mutex_Init_2Test0[] =
205 + " -n \"`grep '#if __STDC__ - 0 == 0 && !defined(_NO_LONGLONG)' \\`dirname $file\\`/sys/types.h`\"";
207 +#define SOLARIS_MUTEX_INIT_2_TEST_CT 2
208 static tTestDesc aSolaris_Mutex_Init_2Tests[] = {
209 + { TT_TEST, zSolaris_Mutex_Init_2Test0, 0 /* unused */ },
210 { TT_EGREP, zSolaris_Mutex_Init_2Select0, (regex_t*)NULL }, };
213 @@ -5670,8 +5712,15 @@ tSCC* apzSolaris_Rwlock_Init_1Machs[] =
214 tSCC zSolaris_Rwlock_Init_1Select0[] =
215 "@\\(#\\)pthread.h[ \t]+1.[0-9]+[ \t]+[0-9/]+ SMI";
217 -#define SOLARIS_RWLOCK_INIT_1_TEST_CT 1
219 + * perform the 'test' shell command - do fix on success
221 +tSCC zSolaris_Rwlock_Init_1Test0[] =
222 + " -n \"`grep '#if __STDC__ - 0 == 0 && !defined(_NO_LONGLONG)' \\`dirname $file\\`/sys/types.h`\"";
224 +#define SOLARIS_RWLOCK_INIT_1_TEST_CT 2
225 static tTestDesc aSolaris_Rwlock_Init_1Tests[] = {
226 + { TT_TEST, zSolaris_Rwlock_Init_1Test0, 0 /* unused */ },
227 { TT_EGREP, zSolaris_Rwlock_Init_1Select0, (regex_t*)NULL }, };
230 @@ -5741,8 +5790,7 @@ tSCC zSolaris_Once_Init_2List[] =
231 * Machine/OS name selection pattern
233 tSCC* apzSolaris_Once_Init_2Machs[] = {
234 - "*-*-solaris2.[0-9]",
235 - "*-*-solaris2.[0-9][!0-9]*",
240 @@ -5751,8 +5799,15 @@ tSCC* apzSolaris_Once_Init_2Machs[] = {
241 tSCC zSolaris_Once_Init_2Select0[] =
242 "@\\(#\\)pthread.h[ \t]+1.[0-9]+[ \t]+[0-9/]+ SMI";
244 -#define SOLARIS_ONCE_INIT_2_TEST_CT 1
246 + * perform the 'test' shell command - do fix on success
248 +tSCC zSolaris_Once_Init_2Test0[] =
249 + " -n \"`grep '#if __STDC__ - 0 == 0 && !defined(_NO_LONGLONG)' \\`dirname $file\\`/sys/types.h`\"";
251 +#define SOLARIS_ONCE_INIT_2_TEST_CT 2
252 static tTestDesc aSolaris_Once_Init_2Tests[] = {
253 + { TT_TEST, zSolaris_Once_Init_2Test0, 0 /* unused */ },
254 { TT_EGREP, zSolaris_Once_Init_2Select0, (regex_t*)NULL }, };
257 @@ -7308,9 +7363,9 @@ static const char* apzX11_SprintfPatch[]
261 -#define REGEX_COUNT 226
262 -#define MACH_LIST_SIZE_LIMIT 181
263 -#define FIX_COUNT 180
264 +#define REGEX_COUNT 227
265 +#define MACH_LIST_SIZE_LIMIT 169
266 +#define FIX_COUNT 181
269 * Enumerate the fixes
270 @@ -7371,6 +7426,7 @@ typedef enum {
271 GLIBC_C99_INLINE_3_FIXIDX,
272 GLIBC_C99_INLINE_4_FIXIDX,
273 GLIBC_MUTEX_INIT_FIXIDX,
274 + GLIBC_STRING2_MEMSET_FIXIDX,
278 @@ -7774,6 +7830,11 @@ tFixDesc fixDescList[ FIX_COUNT ] = {
279 GLIBC_MUTEX_INIT_TEST_CT, FD_MACH_ONLY,
280 aGlibc_Mutex_InitTests, apzGlibc_Mutex_InitPatch, 0 },
282 + { zGlibc_String2_MemsetName, zGlibc_String2_MemsetList,
283 + apzGlibc_String2_MemsetMachs,
284 + GLIBC_STRING2_MEMSET_TEST_CT, FD_MACH_ONLY | FD_SUBROUTINE,
285 + aGlibc_String2_MemsetTests, apzGlibc_String2_MemsetPatch, 0 },
287 { zGnu_TypesName, zGnu_TypesList,
289 GNU_TYPES_TEST_CT, FD_MACH_IFNOT | FD_SUBROUTINE,
290 --- a/fixincludes/inclhack.def
291 +++ b/fixincludes/inclhack.def
292 @@ -1302,6 +1302,21 @@ fix = {
296 +/* glibc's bits/string2.h (before 2004-05-26) generates bogus
297 + -Wstrict-aliasing warnings from calls to memset. */
299 + hackname = glibc_string2_memset;
300 + files = "bits/string2.h";
301 + select = "#ifndef _HAVE_STRING_ARCH_memset\n# if _STRING_ARCH_unaligned";
303 + c_fix_arg = "%0 && 0";
304 + test_text = "#ifndef _HAVE_STRING_ARCH_memset\n"
305 + "# if _STRING_ARCH_unaligned\n"
312 * Fix these files to use the types we think they should for
313 * ptrdiff_t, size_t, and wchar_t.
314 @@ -2939,24 +2954,32 @@ fix = {
318 - * Sun Solaris defines PTHREAD_MUTEX_INITIALIZER with a trailing
319 - * "0" for the last field of the pthread_mutex_t structure, which is
320 - * of type upad64_t, which itself is typedef'd to int64_t, but with
321 - * __STDC__ defined (e.g. by -ansi) it is a union. So change the
322 - * initializer to "{0}" instead
323 + * Sun Solaris defines the last field of the pthread_mutex_t structure
324 + * to have type upad64_t. Whether upad64_t is an integer type or a
325 + * union depends on whether or not the headers believe that a 64-bit
326 + * integer type is available. But, PTHREAD_MUTEX_INITIALIZER is not
327 + * appropriately conditionalized; it always uses "0", and never "{0}".
328 + * In order to avoid warnings/errors from the compiler, we must make
329 + * the initializer use braces where appropriate.
331 + * Prior to Solaris 10, if __STDC__ is 1 (as when compiling with
332 + * -ansi), the definition would be a union. Beginning with Solaris
333 + * 10, the headers check for __GNUC__, and will never use a union with
334 + * GCC. We check /usr/include/sys/types.h to see if it checks for
337 + * A "mach" test for Solaris 10 is undesirable because we want to
338 + * allow a compiler built for Solaris <10 to be used on Solaris >=10,
339 + * but the installed version of fixincludes hard-wires the target
340 + * machine to the configure-time $target, rather than automatically
341 + * determining it at installation time.
344 hackname = solaris_mutex_init_2;
345 select = '@\(#\)pthread.h' "[ \t]+1.[0-9]+[ \t]+[0-9/]+ SMI";
348 - * On Solaris 10, this fix is unnecessary because upad64_t is
349 - * always defined correctly regardless of the definition of the
350 - * __STDC__ macro. The first "mach" pattern matches up to
351 - * solaris9. The second "mach" pattern will not match any two (or
352 - * more) digit solaris version, but it will match e.g. 2.5.1.
354 - mach = '*-*-solaris2.[0-9]', '*-*-solaris2.[0-9][!0-9]*';
355 + mach = '*-*-solaris*';
356 + test = " -n \"`grep '#if __STDC__ - 0 == 0 && !defined(_NO_LONGLONG)' \\`dirname $file\\`/sys/types.h`\"";
358 c_fix_arg = "#if __STDC__ - 0 == 0 && !defined(_NO_LONGLONG)\n"
360 @@ -2967,6 +2990,7 @@ fix = {
361 "(|/\*.*\*/[ \t]*\\\\\n[ \t]*)\\{.*)"
362 ",[ \t]*0\\}" "(|[ \t].*)$";
364 + "`mkdir -p sys; echo '#if __STDC__ - 0 == 0 && !defined(_NO_LONGLONG)' >> sys/types.h`"
365 '#ident "@(#)pthread.h 1.26 98/04/12 SMI"'"\n"
366 "#define PTHREAD_MUTEX_INITIALIZER\t{{{0},0}, {{{0}}}, 0}\n"
367 "#define PTHREAD_COND_INITIALIZER\t{{{0}, 0}, 0}\t/* DEFAULTCV */\n"
368 @@ -2978,17 +3002,14 @@ fix = {
372 - * Sun Solaris defines PTHREAD_RWLOCK_INITIALIZER with a "0" for some
373 - * fields of the pthread_rwlock_t structure, which are of type
374 - * upad64_t, which itself is typedef'd to int64_t, but with __STDC__
375 - * defined (e.g. by -ansi) it is a union. So change the initializer
376 - * to "{0}" instead.
377 + * See comments for solaris_mutex_init_2 re. upad64_t.
380 hackname = solaris_rwlock_init_1;
381 select = '@\(#\)pthread.h' "[ \t]+1.[0-9]+[ \t]+[0-9/]+ SMI";
383 mach = '*-*-solaris*';
384 + test = " -n \"`grep '#if __STDC__ - 0 == 0 && !defined(_NO_LONGLONG)' \\`dirname $file\\`/sys/types.h`\"";
386 c_fix_arg = "#if __STDC__ - 0 == 0 && !defined(_NO_LONGLONG)\n"
388 @@ -3024,24 +3045,14 @@ fix = {
392 - * Sun Solaris defines PTHREAD_ONCE_INIT with a "0" for some
393 - * fields of the pthread_once_t structure, which are of type
394 - * upad64_t, which itself is typedef'd to int64_t, but with __STDC__
395 - * defined (e.g. by -ansi) it is a union. So change the initializer
396 - * to "{0}" instead. This test relies on solaris_once_init_1.
397 + * See comments for solaris_mutex_init_2 re. upad64_t.
400 hackname = solaris_once_init_2;
401 select = '@\(#\)pthread.h' "[ \t]+1.[0-9]+[ \t]+[0-9/]+ SMI";
404 - * On Solaris 10, this fix is unnecessary because upad64_t is
405 - * always defined correctly regardless of the definition of the
406 - * __STDC__ macro. The first "mach" pattern matches up to
407 - * solaris9. The second "mach" pattern will not match any two (or
408 - * more) digit solaris version, but it will match e.g. 2.5.1.
410 - mach = '*-*-solaris2.[0-9]', '*-*-solaris2.[0-9][!0-9]*';
411 + mach = '*-*-solaris*';
412 + test = " -n \"`grep '#if __STDC__ - 0 == 0 && !defined(_NO_LONGLONG)' \\`dirname $file\\`/sys/types.h`\"";
414 c_fix_arg = "#if __STDC__ - 0 == 0 && !defined(_NO_LONGLONG)\n"
416 --- a/fixincludes/server.c
417 +++ b/fixincludes/server.c
418 @@ -266,7 +266,7 @@ run_shell (const char* pz_cmd)
419 /* Make sure the process will pay attention to us, send the
420 supplied command, and then have it output a special marker that
422 - fprintf (server_pair.pf_write, "cd %s\n%s\n\necho\necho %s\n",
423 + fprintf (server_pair.pf_write, "cd '%s'\n%s\n\necho\necho %s\n",
424 p_cur_dir, pz_cmd, z_done);
425 fflush (server_pair.pf_write);
427 --- a/fixincludes/tests/base/bits/string2.h
428 +++ b/fixincludes/tests/base/bits/string2.h
430 # define __STRING_INLINE extern __inline
432 #endif /* GLIBC_C99_INLINE_3_CHECK */
435 +#if defined( GLIBC_STRING2_MEMSET_CHECK )
436 +#ifndef _HAVE_STRING_ARCH_memset
437 +# if _STRING_ARCH_unaligned && 0
441 +#endif /* GLIBC_STRING2_MEMSET_CHECK */
442 --- a/fixincludes/tests/base/sys/types.h
443 +++ b/fixincludes/tests/base/sys/types.h
444 @@ -28,3 +28,4 @@ typedef __WCHAR_TYPE__ wchar_t;
446 #endif /* ushort_t */
447 #endif /* GNU_TYPES_CHECK */
448 +#if !defined(__STRICT_ANSI__) && !defined(_NO_LONGLONG)
449 --- a/gcc/Makefile.in
450 +++ b/gcc/Makefile.in
451 @@ -327,6 +327,8 @@ GCC_FOR_TARGET = $(STAGE_CC_WRAPPER) ./x
452 # It also specifies -isystem ./include to find, e.g., stddef.h.
453 GCC_CFLAGS=$(CFLAGS_FOR_TARGET) $(INTERNAL_CFLAGS) $(T_CFLAGS) $(LOOSE_WARN) -Wold-style-definition $($@-warn) -isystem ./include $(TCFLAGS)
455 +EGLIBC_CONFIGS = @EGLIBC_CONFIGS@
457 # ---------------------------------------------------
458 # Programs which produce files for the target machine
459 # ---------------------------------------------------
460 @@ -408,6 +410,9 @@ TARGET_SYSTEM_ROOT = @TARGET_SYSTEM_ROOT
462 xmake_file=@xmake_file@
463 tmake_file=@tmake_file@
464 +TM_ENDIAN_CONFIG=@TM_ENDIAN_CONFIG@
465 +TM_MULTILIB_CONFIG=@TM_MULTILIB_CONFIG@
466 +TM_MULTILIB_EXCEPTIONS_CONFIG=@TM_MULTILIB_EXCEPTIONS_CONFIG@
467 out_file=$(srcdir)/config/@out_file@
468 out_object_file=@out_object_file@
469 md_file=$(srcdir)/config/@md_file@
470 @@ -1249,6 +1254,7 @@ OBJS-common = \
471 tree-ssa-loop-manip.o \
472 tree-ssa-loop-niter.o \
473 tree-ssa-loop-prefetch.o \
474 + tree-ssa-loop-promote.o \
475 tree-ssa-loop-unswitch.o \
477 tree-ssa-math-opts.o \
478 @@ -1258,6 +1264,7 @@ OBJS-common = \
480 tree-ssa-propagate.o \
482 + tree-ssa-remove-local-statics.o \
485 tree-ssa-structalias.o \
486 @@ -1674,7 +1681,7 @@ libgcc-support: libgcc.mvars stmp-int-hd
487 $(MACHMODE_H) $(FPBIT) $(DPBIT) $(TPBIT) $(LIB2ADD) \
488 $(LIB2ADD_ST) $(LIB2ADDEH) $(srcdir)/emutls.c gcov-iov.h $(SFP_MACHINE)
490 -libgcc.mvars: config.status Makefile $(LIB2ADD) $(LIB2ADD_ST) specs \
491 +libgcc.mvars: config.status Makefile $(LIB2ADD) $(LIB2ADD_ST) specs $(tmake_file) \
494 echo LIB1ASMFUNCS = '$(LIB1ASMFUNCS)' >> tmp-libgcc.mvars
495 @@ -1728,7 +1735,7 @@ libgcc.mvars: config.status Makefile $(L
496 # driver program needs to select the library directory based on the
498 multilib.h: s-mlib; @true
499 -s-mlib: $(srcdir)/genmultilib Makefile
500 +s-mlib: $(srcdir)/genmultilib Makefile $(tmakefile)
501 if test @enable_multilib@ = yes \
502 || test -n "$(MULTILIB_OSDIRNAMES)"; then \
503 $(SHELL) $(srcdir)/genmultilib \
504 @@ -1739,10 +1746,11 @@ s-mlib: $(srcdir)/genmultilib Makefile
505 "$(MULTILIB_EXTRA_OPTS)" \
506 "$(MULTILIB_EXCLUSIONS)" \
507 "$(MULTILIB_OSDIRNAMES)" \
508 + "$(MULTILIB_ALIASES)" \
509 "@enable_multilib@" \
512 - $(SHELL) $(srcdir)/genmultilib '' '' '' '' '' '' '' no \
513 + $(SHELL) $(srcdir)/genmultilib '' '' '' '' '' '' '' '' no \
516 $(SHELL) $(srcdir)/../move-if-change tmp-mlib.h multilib.h
517 @@ -1816,7 +1824,7 @@ gcc.srcextra: gengtype-lex.c
519 incpath.o: incpath.c incpath.h $(CONFIG_H) $(SYSTEM_H) $(CPPLIB_H) \
520 intl.h prefix.h coretypes.h $(TM_H) cppdefault.h $(TARGET_H) \
522 + $(MACHMODE_H) $(FLAGS_H) toplev.h
524 c-decl.o : c-decl.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) \
525 $(RTL_H) $(C_TREE_H) $(GGC_H) $(TARGET_H) $(FLAGS_H) $(FUNCTION_H) output.h \
526 @@ -1900,7 +1908,7 @@ c-opts.o : c-opts.c $(CONFIG_H) $(SYSTEM
527 $(TREE_H) $(C_PRAGMA_H) $(FLAGS_H) $(TOPLEV_H) langhooks.h \
528 $(TREE_INLINE_H) $(DIAGNOSTIC_H) intl.h debug.h $(C_COMMON_H) \
529 opts.h options.h $(MKDEPS_H) incpath.h cppdefault.h $(TARGET_H) \
530 - $(TM_P_H) $(VARRAY_H)
531 + $(TM_P_H) $(VARRAY_H) $(C_TREE_H)
532 $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) \
533 $< $(OUTPUT_OPTION) @TARGET_SYSTEM_ROOT_DEFINE@
535 @@ -1953,7 +1961,8 @@ DRIVER_DEFINES = \
536 -DTOOLDIR_BASE_PREFIX=\"$(libsubdir_to_prefix)$(prefix_to_exec_prefix)\" \
537 @TARGET_SYSTEM_ROOT_DEFINE@ \
538 $(VALGRIND_DRIVER_DEFINES) \
539 - `test "X$${SHLIB_LINK}" = "X" || test "@enable_shared@" != "yes" || echo "-DENABLE_SHARED_LIBGCC"`
540 + `test "X$${SHLIB_LINK}" = "X" || test "@enable_shared@" != "yes" || echo "-DENABLE_SHARED_LIBGCC"` \
541 + -DCONFIGURE_SPECS="\"@CONFIGURE_SPECS@\""
543 gcc.o: gcc.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) intl.h multilib.h \
544 Makefile $(lang_specs_files) specs.h prefix.h $(GCC_H) $(FLAGS_H) \
545 @@ -2176,6 +2185,9 @@ tree-ssa-pre.o : tree-ssa-pre.c $(TREE_F
546 alloc-pool.h $(BASIC_BLOCK_H) $(BITMAP_H) $(HASHTAB_H) $(GIMPLE_H) \
547 $(TREE_INLINE_H) tree-iterator.h tree-ssa-sccvn.h $(PARAMS_H) \
549 +tree-ssa-remove-local-statics.o: tree-ssa-remove-local-statics.c \
550 + coretypes.h $(CONFIG_H) $(SYSTEM_H) $(BASIC_BLOCK_H) tree.h tree-pass.h \
551 + $(TM_H) $(HASHTAB_H) $(BASIC_BLOCK_H)
552 tree-ssa-sccvn.o : tree-ssa-sccvn.c $(TREE_FLOW_H) $(CONFIG_H) \
553 $(SYSTEM_H) $(TREE_H) $(GGC_H) $(DIAGNOSTIC_H) $(TIMEVAR_H) $(FIBHEAP_H) \
554 $(TM_H) coretypes.h $(TREE_DUMP_H) tree-pass.h $(FLAGS_H) $(CFGLOOP_H) \
555 @@ -2271,6 +2283,12 @@ tree-ssa-loop-prefetch.o: tree-ssa-loop-
556 $(CFGLOOP_H) $(PARAMS_H) langhooks.h $(BASIC_BLOCK_H) hard-reg-set.h \
557 tree-chrec.h $(TOPLEV_H) langhooks.h $(TREE_INLINE_H) $(TREE_DATA_REF_H) \
559 +tree-ssa-loop-promote.o: tree-ssa-loop-promote.c \
560 + coretypes.h $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TOPLEV_H) \
561 + $(RTL_H) $(TM_P_H) hard-reg-set.h $(OBSTACK_H) $(BASIC_BLOCK_H) \
562 + pointer-set.h intl.h $(TREE_H) $(GIMPLE_H) $(HASHTAB_H) $(DIAGNOSTIC_H) \
563 + $(TREE_FLOW_H) $(TREE_DUMP_H) $(CFGLOOP_H) $(FLAGS_H) $(TIMEVAR_H) \
564 + tree-pass.h $(TM_H)
565 tree-predcom.o: tree-predcom.c $(CONFIG_H) $(SYSTEM_H) $(TREE_H) $(TM_P_H) \
566 $(CFGLOOP_H) $(TREE_FLOW_H) $(GGC_H) $(TREE_DATA_REF_H) $(SCEV_H) \
567 $(PARAMS_H) $(DIAGNOSTIC_H) tree-pass.h $(TM_H) coretypes.h tree-affine.h \
568 @@ -2865,7 +2883,7 @@ postreload.o : postreload.c $(CONFIG_H)
569 $(RTL_H) $(REAL_H) $(FLAGS_H) $(EXPR_H) $(OPTABS_H) reload.h $(REGS_H) \
570 hard-reg-set.h insn-config.h $(BASIC_BLOCK_H) $(RECOG_H) output.h \
571 $(FUNCTION_H) $(TOPLEV_H) cselib.h $(TM_P_H) except.h $(TREE_H) $(MACHMODE_H) \
572 - $(OBSTACK_H) $(TIMEVAR_H) tree-pass.h $(DF_H) $(DBGCNT_H)
573 + $(OBSTACK_H) $(TIMEVAR_H) tree-pass.h addresses.h $(DF_H) $(DBGCNT_H)
574 postreload-gcse.o : postreload-gcse.c $(CONFIG_H) $(SYSTEM_H) coretypes.h \
575 $(TM_H) $(RTL_H) $(REGS_H) hard-reg-set.h $(FLAGS_H) insn-config.h \
576 $(RECOG_H) $(EXPR_H) $(BASIC_BLOCK_H) $(FUNCTION_H) output.h $(TOPLEV_H) \
577 @@ -3582,7 +3600,7 @@ gcov-dump$(exeext): $(GCOV_DUMP_OBJS) $(
580 # Build the include directories.
581 -stmp-int-hdrs: $(STMP_FIXINC) $(USER_H) $(UNWIND_H) fixinc_list
582 +stmp-int-hdrs: $(STMP_FIXINC) $(USER_H) $(UNWIND_H)
583 # Copy in the headers provided with gcc.
584 # The sed command gets just the last file name component;
585 # this is necessary because VPATH could add a dirname.
586 @@ -3601,21 +3619,23 @@ stmp-int-hdrs: $(STMP_FIXINC) $(USER_H)
588 rm -f include/unwind.h
589 cp $(UNWIND_H) include/unwind.h
590 - set -e; for ml in `cat fixinc_list`; do \
591 - sysroot_headers_suffix=`echo $${ml} | sed -e 's/;.*$$//'`; \
592 - multi_dir=`echo $${ml} | sed -e 's/^[^;]*;//'`; \
593 - fix_dir=include-fixed$${multi_dir}; \
594 - if $(LIMITS_H_TEST) ; then \
595 - cat $(srcdir)/limitx.h $(srcdir)/glimits.h $(srcdir)/limity.h > tmp-xlimits.h; \
597 - cat $(srcdir)/glimits.h > tmp-xlimits.h; \
599 - $(mkinstalldirs) $${fix_dir}; \
600 - chmod a+rx $${fix_dir} || true; \
601 - rm -f $${fix_dir}/limits.h; \
602 - mv tmp-xlimits.h $${fix_dir}/limits.h; \
603 - chmod a+r $${fix_dir}/limits.h; \
605 + set -e; if [ -f fixinc_list ] ; then \
606 + for ml in `cat fixinc_list`; do \
607 + sysroot_headers_suffix=`echo $${ml} | sed -e 's/;.*$$//'`; \
608 + multi_dir=`echo $${ml} | sed -e 's/^[^;]*;//'`; \
609 + fix_dir=include-fixed$${multi_dir}; \
610 + if $(LIMITS_H_TEST) ; then \
611 + cat $(srcdir)/limitx.h $(srcdir)/glimits.h $(srcdir)/limity.h > tmp-xlimits.h; \
613 + cat $(srcdir)/glimits.h > tmp-xlimits.h; \
615 + $(mkinstalldirs) $${fix_dir}; \
616 + chmod a+rx $${fix_dir} || true; \
617 + rm -f $${fix_dir}/limits.h; \
618 + mv tmp-xlimits.h $${fix_dir}/limits.h; \
619 + chmod a+r $${fix_dir}/limits.h; \
623 rm -f include-fixed/README
624 cp $(srcdir)/../fixincludes/README-fixinc include-fixed/README
625 @@ -4340,16 +4360,18 @@ real-install-headers-cp:
627 # Install supporting files for fixincludes to be run later.
628 install-mkheaders: stmp-int-hdrs $(STMP_FIXPROTO) install-itoolsdirs \
629 - macro_list fixinc_list
631 $(INSTALL_DATA) $(srcdir)/gsyslimits.h \
632 $(DESTDIR)$(itoolsdatadir)/gsyslimits.h
633 $(INSTALL_DATA) macro_list $(DESTDIR)$(itoolsdatadir)/macro_list
634 - $(INSTALL_DATA) fixinc_list $(DESTDIR)$(itoolsdatadir)/fixinc_list
635 - set -e; for ml in `cat fixinc_list`; do \
636 - multi_dir=`echo $${ml} | sed -e 's/^[^;]*;//'`; \
637 - $(mkinstalldirs) $(DESTDIR)$(itoolsdatadir)/include$${multi_dir}; \
638 - $(INSTALL_DATA) include-fixed$${multidir}/limits.h $(DESTDIR)$(itoolsdatadir)/include$${multi_dir}/limits.h; \
640 + set -e; if [ -f fixinc_list ] ; then \
641 + $(INSTALL_DATA) fixinc_list $(DESTDIR)$(itoolsdatadir)/fixinc_list; \
642 + for ml in `cat fixinc_list`; do \
643 + multi_dir=`echo $${ml} | sed -e 's/^[^;]*;//'`; \
644 + $(mkinstalldirs) $(DESTDIR)$(itoolsdatadir)/include$${multi_dir}; \
645 + $(INSTALL_DATA) include-fixed$${multidir}/limits.h $(DESTDIR)$(itoolsdatadir)/include$${multi_dir}/limits.h; \
648 $(INSTALL_SCRIPT) $(srcdir)/../mkinstalldirs \
649 $(DESTDIR)$(itoolsdir)/mkinstalldirs ; \
650 if [ x$(STMP_FIXPROTO) != x ] ; then \
651 --- a/gcc/addresses.h
652 +++ b/gcc/addresses.h
653 @@ -78,3 +78,42 @@ regno_ok_for_base_p (unsigned regno, enu
655 return ok_for_base_p_1 (regno, mode, outer_code, index_code);
658 +/* Wrapper function to unify target macros MODE_INDEX_REG_CLASS and
659 + INDEX_REG_CLASS. Arguments as for the MODE_INDEX_REG_CLASS macro. */
661 +static inline enum reg_class
662 +index_reg_class (enum machine_mode mode ATTRIBUTE_UNUSED)
664 +#ifdef MODE_INDEX_REG_CLASS
665 + return MODE_INDEX_REG_CLASS (mode);
667 + return INDEX_REG_CLASS;
671 +/* Wrapper function to unify target macros REGNO_MODE_OK_FOR_INDEX_P
672 + and REGNO_OK_FOR_INDEX_P. Arguments as for the
673 + REGNO_MODE_OK_FOR_INDEX_P macro. */
676 +ok_for_index_p_1 (unsigned regno, enum machine_mode mode ATTRIBUTE_UNUSED)
678 +#ifdef REGNO_MODE_OK_FOR_INDEX_P
679 + return REGNO_MODE_OK_FOR_INDEX_P (regno, mode);
681 + return REGNO_OK_FOR_INDEX_P (regno);
685 +/* Wrapper around ok_for_index_p_1, for use after register allocation is
686 + complete. Arguments as for the called function. */
689 +regno_ok_for_index_p (unsigned regno, enum machine_mode mode)
691 + if (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0)
692 + regno = reg_renumber[regno];
694 + return ok_for_index_p_1 (regno, mode);
698 @@ -33,7 +33,6 @@ along with GCC; see the file COPYING3.
701 #include "c-common.h"
702 -#include "diagnostic.h"
706 @@ -42,6 +41,7 @@ along with GCC; see the file COPYING3.
707 #include "tree-inline.h"
710 +#include "diagnostic.h"
711 #include "tree-iterator.h"
713 #include "tree-mudflap.h"
714 @@ -497,6 +497,10 @@ tree (*make_fname_decl) (tree, int);
715 This is a count, since unevaluated expressions can nest. */
718 +/* Whether lexing has been completed, so subsequent preprocessor
719 + errors should use the compiler's input_location. */
720 +bool done_lexing = false;
722 /* Information about how a function name is generated. */
725 @@ -7522,6 +7526,68 @@ c_parse_error (const char *gmsgid, enum
726 #undef catenate_messages
729 +/* Callback from cpp_error for PFILE to print diagnostics from the
730 + preprocessor. The diagnostic is of type LEVEL, at location
731 + LOCATION unless this is after lexing and the compiler's location
732 + should be used instead, with column number possibly overridden by
733 + COLUMN_OVERRIDE if not zero; MSG is the translated message and AP
734 + the arguments. Returns true if a diagnostic was emitted, false
738 +c_cpp_error (cpp_reader *pfile ATTRIBUTE_UNUSED, int level,
739 + location_t location, unsigned int column_override,
740 + const char *msg, va_list *ap)
742 + diagnostic_info diagnostic;
743 + diagnostic_t dlevel;
744 + int save_warn_system_headers = warn_system_headers;
749 + case CPP_DL_WARNING_SYSHDR:
750 + if (flag_no_output)
752 + warn_system_headers = 1;
753 + /* Fall through. */
754 + case CPP_DL_WARNING:
755 + if (flag_no_output)
757 + dlevel = DK_WARNING;
759 + case CPP_DL_PEDWARN:
760 + if (flag_no_output && !flag_pedantic_errors)
762 + dlevel = DK_PEDWARN;
777 + gcc_unreachable ();
780 + location = input_location;
781 + diagnostic_set_info_translated (&diagnostic, msg, ap,
783 + if (column_override)
784 + diagnostic_override_column (&diagnostic, column_override);
785 + ret = report_diagnostic (&diagnostic);
786 + if (level == CPP_DL_WARNING_SYSHDR)
787 + warn_system_headers = save_warn_system_headers;
791 /* Walk a gimplified function and warn for functions whose return value is
792 ignored and attribute((warn_unused_result)) is set. This is done before
793 inlining, so we don't have to worry about that. */
796 @@ -658,6 +658,11 @@ extern int max_tinst_depth;
798 extern int skip_evaluation;
800 +/* Whether lexing has been completed, so subsequent preprocessor
801 + errors should use the compiler's input_location. */
803 +extern bool done_lexing;
805 /* C types are partitioned into three subsets: object, function, and
807 #define C_TYPE_OBJECT_P(type) \
808 --- a/gcc/c-convert.c
809 +++ b/gcc/c-convert.c
810 @@ -70,6 +70,7 @@ convert (tree type, tree expr)
812 enum tree_code code = TREE_CODE (type);
813 const char *invalid_conv_diag;
816 if (type == error_mark_node
817 || expr == error_mark_node
818 @@ -85,6 +86,9 @@ convert (tree type, tree expr)
820 if (type == TREE_TYPE (expr))
822 + ret = targetm.convert_to_type (type, expr);
826 if (TYPE_MAIN_VARIANT (type) == TYPE_MAIN_VARIANT (TREE_TYPE (expr)))
827 return fold_convert (type, expr);
830 @@ -4001,6 +4001,7 @@ grokdeclarator (const struct c_declarato
831 bool bitfield = width != NULL;
833 struct c_arg_info *arg_info = 0;
834 + const char *errmsg;
836 if (decl_context == FUNCDEF)
837 funcdef_flag = true, decl_context = NORMAL;
838 @@ -4538,6 +4539,12 @@ grokdeclarator (const struct c_declarato
839 error ("%qs declared as function returning an array", name);
840 type = integer_type_node;
842 + errmsg = targetm.invalid_return_type (type);
846 + type = integer_type_node;
849 /* Construct the function type and go to the next
850 inner layer of declarator. */
851 @@ -5051,6 +5058,7 @@ grokparms (struct c_arg_info *arg_info,
853 tree parm, type, typelt;
855 + const char *errmsg;
857 /* If there is a parameter of incomplete type in a definition,
858 this is an error. In a declaration this is valid, and a
859 @@ -5094,6 +5102,14 @@ grokparms (struct c_arg_info *arg_info,
863 + errmsg = targetm.invalid_parameter_type (type);
867 + TREE_VALUE (typelt) = error_mark_node;
868 + TREE_TYPE (parm) = error_mark_node;
871 if (DECL_NAME (parm) && TREE_USED (parm))
872 warn_if_shadowing (parm);
874 @@ -8080,7 +8096,7 @@ c_write_global_declarations (void)
876 /* Don't waste time on further processing if -fsyntax-only or we've
877 encountered errors. */
878 - if (flag_syntax_only || errorcount || sorrycount || cpp_errors (parse_in))
879 + if (flag_syntax_only || errorcount || sorrycount)
882 /* Close the external scope. */
885 @@ -40,6 +40,7 @@ along with GCC; see the file COPYING3.
889 +#include "c-tree.h" /* For c_cpp_error. */
891 #ifndef DOLLARS_IN_IDENTIFIERS
892 # define DOLLARS_IN_IDENTIFIERS true
893 @@ -201,6 +202,7 @@ c_common_init_options (unsigned int argc
895 static const unsigned int lang_flags[] = {CL_C, CL_ObjC, CL_CXX, CL_ObjCXX};
896 unsigned int i, result;
897 + struct cpp_callbacks *cb;
899 /* This is conditionalized only because that is the way the front
900 ends used to do it. Maybe this should be unconditional? */
901 @@ -216,6 +218,8 @@ c_common_init_options (unsigned int argc
903 parse_in = cpp_create_reader (c_dialect_cxx () ? CLK_GNUCXX: CLK_GNUC89,
904 ident_hash, line_table);
905 + cb = cpp_get_callbacks (parse_in);
906 + cb->error = c_cpp_error;
908 cpp_opts = cpp_get_options (parse_in);
909 cpp_opts->dollars_in_ident = DOLLARS_IN_IDENTIFIERS;
910 @@ -333,12 +337,12 @@ c_common_handle_option (size_t scode, co
911 or environment var dependency generation is used. */
912 cpp_opts->deps.style = (code == OPT_M ? DEPS_SYSTEM: DEPS_USER);
914 - cpp_opts->inhibit_warnings = 1;
919 cpp_opts->deps.style = (code == OPT_MD ? DEPS_SYSTEM: DEPS_USER);
920 + cpp_opts->deps.need_preprocessor_output = true;
924 @@ -444,7 +448,6 @@ c_common_handle_option (size_t scode, co
928 - cpp_opts->warnings_are_errors = value;
929 global_dc->warning_as_error_requested = value;
932 @@ -503,10 +506,6 @@ c_common_handle_option (size_t scode, co
933 warn_strict_null_sentinel = value;
936 - case OPT_Wsystem_headers:
937 - cpp_opts->warn_system_headers = value;
940 case OPT_Wtraditional:
941 cpp_opts->warn_traditional = value;
943 @@ -895,8 +894,6 @@ c_common_handle_option (size_t scode, co
944 c_common_post_options, so that a subsequent -Wno-endif-labels
945 is not overridden. */
946 case OPT_pedantic_errors:
947 - cpp_opts->pedantic_errors = 1;
948 - /* Fall through. */
950 cpp_opts->pedantic = 1;
951 cpp_opts->warn_endif_labels = 1;
952 @@ -971,10 +968,6 @@ c_common_handle_option (size_t scode, co
957 - cpp_opts->inhibit_warnings = 1;
963 @@ -1159,10 +1152,6 @@ c_common_post_options (const char **pfil
965 input_location = UNKNOWN_LOCATION;
967 - /* If an error has occurred in cpplib, note it so we fail
969 - errorcount += cpp_errors (parse_in);
971 *pfilename = this_input_filename
972 = cpp_read_main_file (parse_in, in_fnames[0]);
973 /* Don't do any compilation or preprocessing if there is no input file. */
974 @@ -1274,7 +1263,8 @@ c_common_finish (void)
976 FILE *deps_stream = NULL;
978 - if (cpp_opts->deps.style != DEPS_NONE)
979 + /* Don't write the deps file if there are errors. */
980 + if (cpp_opts->deps.style != DEPS_NONE && errorcount == 0)
982 /* If -M or -MM was seen without -MF, default output to the
984 @@ -1290,7 +1280,7 @@ c_common_finish (void)
986 /* For performance, avoid tearing down cpplib's internal structures
987 with cpp_destroy (). */
988 - errorcount += cpp_finish (parse_in, deps_stream);
989 + cpp_finish (parse_in, deps_stream);
991 if (deps_stream && deps_stream != out_stream
992 && (ferror (deps_stream) || fclose (deps_stream)))
993 --- a/gcc/c-ppoutput.c
994 +++ b/gcc/c-ppoutput.c
995 @@ -521,6 +521,7 @@ pp_file_change (const struct line_map *m
999 + input_location = map->start_location;
1000 if (print.first_time)
1002 /* Avoid printing foo.i when the main file is foo.c. */
1005 @@ -647,4 +647,8 @@ extern void c_write_global_declarations
1006 extern void pedwarn_c90 (location_t, int opt, const char *, ...) ATTRIBUTE_GCC_CDIAG(3,4);
1007 extern void pedwarn_c99 (location_t, int opt, const char *, ...) ATTRIBUTE_GCC_CDIAG(3,4);
1009 +extern bool c_cpp_error (cpp_reader *, int, location_t, unsigned int,
1010 + const char *, va_list *)
1011 + ATTRIBUTE_GCC_CDIAG(5,0);
1013 #endif /* ! GCC_C_TREE_H */
1014 --- a/gcc/c-typeck.c
1015 +++ b/gcc/c-typeck.c
1016 @@ -1765,6 +1765,7 @@ default_conversion (tree exp)
1018 tree type = TREE_TYPE (exp);
1019 enum tree_code code = TREE_CODE (type);
1020 + tree promoted_type;
1022 /* Functions and arrays have been converted during parsing. */
1023 gcc_assert (code != FUNCTION_TYPE);
1024 @@ -1801,6 +1802,10 @@ default_conversion (tree exp)
1025 if (exp == error_mark_node)
1026 return error_mark_node;
1028 + promoted_type = targetm.promoted_type (type);
1029 + if (promoted_type)
1030 + return convert (promoted_type, exp);
1032 if (INTEGRAL_TYPE_P (type))
1033 return perform_integral_promotions (exp);
1037 @@ -720,6 +720,10 @@ fpreprocessed
1039 Treat the input file as already preprocessed
1041 +fremove-local-statics
1042 +C C++ Var(flag_remove_local_statics) Optimization
1043 +Convert function-local static variables to automatic variables when it is safe to do so
1045 freplace-objc-classes
1047 Used in Fix-and-Continue mode to indicate that object files may be swapped in at runtime
1050 @@ -3806,7 +3806,7 @@ emit_library_call_value_1 (int retval, r
1051 cse'ing of library calls could delete a call and leave the pop. */
1053 valreg = (mem_value == 0 && outmode != VOIDmode
1054 - ? hard_libcall_value (outmode) : NULL_RTX);
1055 + ? hard_libcall_value (outmode, orgfun) : NULL_RTX);
1057 /* Stack must be properly aligned now. */
1058 gcc_assert (!(stack_pointer_delta
1059 @@ -4051,8 +4051,17 @@ store_one_arg (struct arg_data *arg, rtx
1060 /* We need to make a save area. */
1061 unsigned int size = arg->locate.size.constant * BITS_PER_UNIT;
1062 enum machine_mode save_mode = mode_for_size (size, MODE_INT, 1);
1063 - rtx adr = memory_address (save_mode, XEXP (arg->stack_slot, 0));
1064 - rtx stack_area = gen_rtx_MEM (save_mode, adr);
1068 + /* We can only use save_mode if the arg is sufficiently
1070 + if (STRICT_ALIGNMENT
1071 + && GET_MODE_ALIGNMENT (save_mode) > arg->locate.boundary)
1072 + save_mode = BLKmode;
1074 + adr = memory_address (save_mode, XEXP (arg->stack_slot, 0));
1075 + stack_area = gen_rtx_MEM (save_mode, adr);
1077 if (save_mode == BLKmode)
1079 --- a/gcc/cfgexpand.c
1080 +++ b/gcc/cfgexpand.c
1081 @@ -488,7 +488,8 @@ get_decl_align_unit (tree decl)
1085 - align = LOCAL_DECL_ALIGNMENT (decl);
1086 + align = alignment_for_aligned_arrays (TREE_TYPE (decl),
1087 + LOCAL_DECL_ALIGNMENT (decl));
1089 if (align > MAX_SUPPORTED_STACK_ALIGNMENT)
1090 align = MAX_SUPPORTED_STACK_ALIGNMENT;
1093 @@ -475,9 +475,11 @@ cgraph_node (tree decl)
1094 if (DECL_CONTEXT (decl) && TREE_CODE (DECL_CONTEXT (decl)) == FUNCTION_DECL)
1096 node->origin = cgraph_node (DECL_CONTEXT (decl));
1097 + node->origin->ever_was_nested = 1;
1098 node->next_nested = node->origin->nested;
1099 node->origin->nested = node;
1100 node->master_clone = node;
1101 + node->ever_was_nested = 1;
1103 if (assembler_name_hash)
1107 @@ -185,6 +185,8 @@ struct cgraph_node GTY((chain_next ("%h.
1108 unsigned output : 1;
1109 /* Set for aliases once they got through assemble_alias. */
1111 + /* Set if the function is a nested function or has nested functions. */
1112 + unsigned ever_was_nested : 1;
1114 /* In non-unit-at-a-time mode the function body of inline candidates is saved
1115 into clone before compiling so the function in original form can be
1116 --- a/gcc/common.opt
1117 +++ b/gcc/common.opt
1118 @@ -153,6 +153,10 @@ Wpadded
1119 Common Var(warn_padded) Warning
1120 Warn when padding is required to align structure members
1122 +Wpoison-system-directories
1123 +Common Var(flag_poison_system_directories) Init(1)
1124 +Warn for -I and -L options using system directories if cross compiling
1127 Common Var(warn_shadow) Warning
1128 Warn when one local variable shadows another
1129 @@ -270,6 +274,12 @@ Common Separate
1131 Common Joined UInteger Var(flag_abi_version) Init(2)
1134 +Target Report Var(flag_align_arrays)
1135 +Set the minimum alignment for array variables to be the largest power
1136 +of two less than or equal to their total storage size, or the biggest
1137 +alignment used on the machine, whichever is smaller.
1140 Common Report Var(align_functions,0) Optimization UInteger
1141 Align the start of functions
1142 @@ -467,6 +477,10 @@ fearly-inlining
1143 Common Report Var(flag_early_inlining) Init(1) Optimization
1144 Perform early inlining
1147 +Common Report Joined Undocumented
1148 +EGLIBC configuration specifier, serves multilib purposes.
1150 feliminate-dwarf2-dups
1151 Common Report Var(flag_eliminate_dwarf2_dups)
1152 Perform DWARF2 duplicate elimination
1153 @@ -895,6 +909,10 @@ fprofile-values
1154 Common Report Var(flag_profile_values)
1155 Insert code to profile values of expressions
1157 +fpromote-loop-indices
1158 +Common Report Var(flag_promote_loop_indices) Optimization
1159 +Promote loop indices to word-sized indices when safe
1164 @@ -1227,6 +1245,15 @@ ftree-pre
1165 Common Report Var(flag_tree_pre) Optimization
1166 Enable SSA-PRE optimization on trees
1168 +ftree-pre-partial-partial
1169 +Common Report Var(flag_tree_pre_partial_partial) Optimization
1170 +In SSA-PRE optimization on trees, enable partial-partial redundancy elimination.
1172 +ftree-pre-partial-partial-obliviously
1173 +Common Report Var(flag_tree_pre_partial_partial_obliviously) Optimization
1174 +In SSA-PRE optimization on trees, enable partial-partial redundancy
1175 +elimination without regard for the cost of the inserted phi nodes.
1178 Common Report Var(flag_tree_reassoc) Init(1) Optimization
1179 Enable reassociation on tree level
1180 --- a/gcc/config.gcc
1181 +++ b/gcc/config.gcc
1182 @@ -1088,7 +1088,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfree
1183 tmake_file="${tmake_file} i386/t-linux64"
1184 need_64bit_hwint=yes
1185 case X"${with_cpu}" in
1186 - Xgeneric|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx)
1187 + Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx)
1190 if test x$with_cpu_64 = x; then
1191 @@ -1097,7 +1097,7 @@ i[34567]86-*-linux* | i[34567]86-*-kfree
1194 echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
1195 - echo "generic core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2
1196 + echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2
1200 @@ -1202,7 +1202,7 @@ i[34567]86-*-solaris2*)
1201 # libgcc/configure.ac instead.
1202 need_64bit_hwint=yes
1203 case X"${with_cpu}" in
1204 - Xgeneric|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx)
1205 + Xgeneric|Xatom|Xcore2|Xnocona|Xx86-64|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx)
1208 if test x$with_cpu_64 = x; then
1209 @@ -1211,7 +1211,7 @@ i[34567]86-*-solaris2*)
1212 echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2
1213 - echo "generic core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2
1214 + echo "generic atom core2 nocona x86-64 amdfam10 barcelona k8 opteron athlon64 athlon-fx" 1>&2
1218 @@ -1573,6 +1573,7 @@ mips64*-*-linux* | mipsisa64*-*-linux*)
1219 tm_defines="${tm_defines} MIPS_ISA_DEFAULT=65"
1222 + tmake_file="$tmake_file mips/t-crtfm"
1225 test x$with_llsc != x || with_llsc=yes
1226 @@ -1803,6 +1804,10 @@ powerpc-*-elf*)
1227 tm_file="${tm_file} dbxelf.h elfos.h usegas.h svr4.h freebsd-spec.h rs6000/sysv4.h"
1228 extra_options="${extra_options} rs6000/sysv4.opt"
1229 tmake_file="rs6000/t-fprules rs6000/t-fprules-fpbit rs6000/t-ppcgas rs6000/t-ppccomm"
1230 + if test x$enable_powerpc_e500mc_elf = xyes; then
1231 + tm_file="${tm_file} rs6000/e500mc.h"
1232 + tmake_file="${tmake_file} rs6000/t-ppc-e500mc"
1235 powerpc-*-eabialtivec*)
1236 tm_file="${tm_file} dbxelf.h elfos.h svr4.h freebsd-spec.h rs6000/sysv4.h rs6000/eabi.h rs6000/e500.h rs6000/eabialtivec.h"
1237 @@ -2016,9 +2021,14 @@ sh-*-symbianelf* | sh[12346l]*-*-symbian
1238 *) with_endian=big,little ;;
1241 + # TM_ENDIAN_CONFIG is used by t-sh to determine multilibs.
1242 + # First word : the default endian.
1243 + # Second word: the secondary endian (optional).
1244 case ${with_endian} in
1245 - big|little) tmake_file="${tmake_file} sh/t-1e" ;;
1246 - big,little|little,big) ;;
1247 + big) TM_ENDIAN_CONFIG=mb ;;
1248 + little) TM_ENDIAN_CONFIG=ml ;;
1249 + big,little) TM_ENDIAN_CONFIG="mb ml" ;;
1250 + little,big) TM_ENDIAN_CONFIG="ml mb" ;;
1251 *) echo "with_endian=${with_endian} not supported."; exit 1 ;;
1253 case ${with_endian} in
1254 @@ -2125,7 +2135,7 @@ sh-*-symbianelf* | sh[12346l]*-*-symbian
1255 *) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
1257 sh_multilibs=${with_multilib_list}
1258 - if test x${sh_multilibs} = x ; then
1259 + if test "$sh_multilibs" = "default" ; then
1261 sh64-superh-linux* | \
1262 sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
1263 @@ -2141,25 +2151,32 @@ sh-*-symbianelf* | sh[12346l]*-*-symbian
1265 target_cpu_default=SELECT_`echo ${sh_cpu_default}|tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_`
1266 tm_defines=${tm_defines}' SH_MULTILIB_CPU_DEFAULT=\"'`echo $sh_cpu_default|sed s/sh/m/`'\"'
1267 - sh_multilibs=`echo $sh_multilibs,$sh_cpu_default | sed -e 's/[ ,/][ ,]*/ /g' -e 's/ $//' -e 's/^m/sh/' -e 's/ m/ sh/g' | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ_ abcdefghijklmnopqrstuvwxyz-`
1268 + tm_defines="$tm_defines SUPPORT_`echo $sh_cpu_default | sed 's/^m/sh/' | tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_`=1"
1269 + sh_multilibs=`echo $sh_multilibs | sed -e 's/,/ /g' -e 's/^sh/m/i' -e 's/ sh/ m/gi' | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ_ abcdefghijklmnopqrstuvwxyz-`
1270 for sh_multilib in ${sh_multilibs}; do
1271 case ${sh_multilib} in
1272 - sh1 | sh2 | sh2e | sh3 | sh3e | \
1273 - sh4 | sh4-single | sh4-single-only | sh4-nofpu | sh4-300 |\
1274 - sh4a | sh4a-single | sh4a-single-only | sh4a-nofpu | sh4al | \
1275 - sh2a | sh2a-single | sh2a-single-only | sh2a-nofpu | \
1276 - sh5-64media | sh5-64media-nofpu | \
1277 - sh5-32media | sh5-32media-nofpu | \
1278 - sh5-compact | sh5-compact-nofpu)
1279 - tmake_file="${tmake_file} sh/t-mlib-${sh_multilib}"
1280 - tm_defines="$tm_defines SUPPORT_`echo $sh_multilib|tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_`=1"
1282 + m1 | m2 | m2e | m3 | m3e | \
1283 + m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\
1284 + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \
1285 + m2a | m2a-single | m2a-single-only | m2a-nofpu | \
1286 + m5-64media | m5-64media-nofpu | \
1287 + m5-32media | m5-32media-nofpu | \
1288 + m5-compact | m5-compact-nofpu)
1289 + # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
1290 + # It is passed to MULTIILIB_OPTIONS verbatim.
1291 + TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
1292 + tm_defines="$tm_defines SUPPORT_`echo $sh_multilib | sed 's/^m/sh/' | tr abcdefghijklmnopqrstuvwxyz- ABCDEFGHIJKLMNOPQRSTUVWXYZ_`=1"
1294 + \!*) # TM_MULTILIB_EXCEPTIONS_CONFIG is used by t-sh
1295 + # It is passed the MULTILIB_EXCEPTIONS verbatim.
1296 + TM_MULTILIB_EXCEPTIONS_CONFIG="${TM_MULTILIB_EXCEPTIONS_CONFIG} `echo $sh_multilib | sed 's/^!//'`" ;;
1298 echo "with_multilib_list=${sh_multilib} not supported."
1303 + TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
1304 if test x${enable_incomplete_targets} = xyes ; then
1305 tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1"
1307 @@ -2427,6 +2444,8 @@ i[34567]86-*-linux* | x86_64-*-linux*)
1308 i[34567]86-*-* | x86_64-*-*)
1309 tmake_file="${tmake_file} i386/t-gmm_malloc i386/t-i386"
1311 +powerpc*-*-* | rs6000-*-*)
1312 + tm_file="${tm_file} rs6000/option-defaults.h"
1315 # Support for --with-cpu and related options (and a few unrelated options,
1316 @@ -2653,8 +2672,8 @@ case "${target}" in
1317 | armv[23456] | armv2a | armv3m | armv4t | armv5t \
1318 | armv5te | armv6j |armv6k | armv6z | armv6zk | armv6-m \
1319 | armv7 | armv7-a | armv7-r | armv7-m \
1320 - | iwmmxt | ep9312)
1322 + | iwmmxt | ep9312 | marvell-f )
1326 echo "Unknown arch used in --with-arch=$with_arch" 1>&2
1327 @@ -2675,7 +2694,10 @@ case "${target}" in
1331 - | fpa | fpe2 | fpe3 | maverick | vfp | vfp3 | vfpv3 | vfpv3-d16 | neon )
1332 + | fpa | fpe2 | fpe3 | maverick \
1333 + | vfp | vfp3 | vfpv3 | vfpv3-fp16 | vfpv3-d16 \
1334 + | vfpv3-d16-fp16 | vfpv4 | vfpv4-d16 | fpv4-sp-d16 \
1335 + | neon | neon-fp16 | neon-vfpv4 )
1339 @@ -2812,7 +2834,7 @@ case "${target}" in
1343 - "" | amdfam10 | barcelona | k8 | opteron | athlon64 | athlon-fx | nocona | core2 | generic)
1344 + "" | amdfam10 | barcelona | k8 | opteron | athlon64 | athlon-fx | nocona | core2 | atom | generic)
1348 @@ -2824,7 +2846,7 @@ case "${target}" in
1352 - supported_defaults="abi arch float tune divide llsc mips-plt"
1353 + supported_defaults="abi arch arch_32 arch_64 float tune tune_32 tune_64 divide llsc mips-plt"
1355 case ${with_float} in
1357 @@ -2889,12 +2911,20 @@ case "${target}" in
1360 powerpc*-*-* | rs6000-*-*)
1361 - supported_defaults="cpu float tune"
1362 + supported_defaults="cpu cpu_32 cpu_64 float tune tune_32 tune_64"
1364 - for which in cpu tune; do
1365 + for which in cpu cpu_32 cpu_64 tune tune_32 tune_64; do
1366 eval "val=\$with_$which"
1368 default32 | default64)
1373 + echo "$val only valid for --with-cpu and --with-tune." 1>&2
1377 with_which="with_$which"
1382 @@ -108,6 +108,12 @@
1386 +/* Define to warn for use of native system header directories */
1387 +#ifndef USED_FOR_TARGET
1388 +#undef ENABLE_POISON_SYSTEM_DIRECTORIES
1392 /* Define if you want all operations on RTL (the basic data structure of the
1393 optimizer and back end) to be checked for dynamic type safety at runtime.
1394 This is quite expensive. */
1395 @@ -821,6 +827,13 @@
1399 +/* Define if your assembler supports specifying the alignment of objects
1400 + allocated using the GAS .comm command. */
1401 +#ifndef USED_FOR_TARGET
1402 +#undef HAVE_GAS_ALIGNED_COMM
1406 /* Define if your assembler supports .balign and .p2align. */
1407 #ifndef USED_FOR_TARGET
1408 #undef HAVE_GAS_BALIGN_AND_P2ALIGN
1409 --- a/gcc/config/arm/arm-cores.def
1410 +++ b/gcc/config/arm/arm-cores.def
1411 @@ -104,6 +104,7 @@ ARM_CORE("arm1022e", arm1022e, 5TE,
1412 ARM_CORE("xscale", xscale, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE, xscale)
1413 ARM_CORE("iwmmxt", iwmmxt, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale)
1414 ARM_CORE("iwmmxt2", iwmmxt2, 5TE, FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT, xscale)
1415 +ARM_CORE("marvell-f", marvell_f, 5TE, FL_LDSCHED | FL_VFPV2 | FL_MARVELL_F, 9e)
1417 /* V5TEJ Architecture Processors */
1418 ARM_CORE("arm926ej-s", arm926ejs, 5TEJ, FL_LDSCHED, 9e)
1419 @@ -117,9 +118,13 @@ ARM_CORE("arm1176jzf-s", arm1176jzfs, 6
1420 ARM_CORE("mpcorenovfp", mpcorenovfp, 6K, FL_LDSCHED, 9e)
1421 ARM_CORE("mpcore", mpcore, 6K, FL_LDSCHED | FL_VFPV2, 9e)
1422 ARM_CORE("arm1156t2-s", arm1156t2s, 6T2, FL_LDSCHED, 9e)
1424 +/* V7 Architecture Processors */
1425 +ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, 9e)
1426 ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, 9e)
1427 ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, 9e)
1428 ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, 9e)
1429 ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, 9e)
1430 ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, 9e)
1431 ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, 9e)
1432 +ARM_CORE("cortex-m0", cortexm0, 6M, FL_LDSCHED, 9e)
1433 --- a/gcc/config/arm/arm-modes.def
1434 +++ b/gcc/config/arm/arm-modes.def
1436 FIXME What format is this? */
1437 FLOAT_MODE (XF, 12, 0);
1439 +/* Half-precision floating point */
1440 +FLOAT_MODE (HF, 2, 0);
1441 +ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
1442 + ? &arm_half_format : &ieee_half_format));
1444 /* CCFPEmode should be used with floating inequalities,
1445 CCFPmode should be used with floating equalities.
1446 CC_NOOVmode should be used with SImode integer equalities.
1447 @@ -62,6 +67,4 @@ VECTOR_MODES (FLOAT, 16); /* V
1451 -/* ??? This should actually have 512 bits but the precision only has 9
1453 -FRACTIONAL_INT_MODE (XI, 511, 64);
1455 --- a/gcc/config/arm/arm-protos.h
1456 +++ b/gcc/config/arm/arm-protos.h
1457 @@ -88,7 +88,7 @@ extern bool arm_cannot_force_const_mem (
1459 extern int cirrus_memory_offset (rtx);
1460 extern int arm_coproc_mem_operand (rtx, bool);
1461 -extern int neon_vector_mem_operand (rtx, bool);
1462 +extern int neon_vector_mem_operand (rtx, int);
1463 extern int neon_struct_mem_operand (rtx);
1464 extern int arm_no_early_store_addr_dep (rtx, rtx);
1465 extern int arm_no_early_alu_shift_dep (rtx, rtx);
1466 @@ -144,6 +144,7 @@ extern void arm_final_prescan_insn (rtx)
1467 extern int arm_debugger_arg_offset (int, rtx);
1468 extern bool arm_is_long_call_p (tree);
1469 extern int arm_emit_vector_const (FILE *, rtx);
1470 +extern void arm_emit_fp16_const (rtx c);
1471 extern const char * arm_output_load_gr (rtx *);
1472 extern const char *vfp_output_fstmd (rtx *);
1473 extern void arm_set_return_address (rtx, rtx);
1474 @@ -154,13 +155,15 @@ extern bool arm_output_addr_const_extra
1476 #if defined TREE_CODE
1477 extern rtx arm_function_arg (CUMULATIVE_ARGS *, enum machine_mode, tree, int);
1478 +extern void arm_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
1480 extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree);
1481 extern bool arm_pad_arg_upward (enum machine_mode, const_tree);
1482 extern bool arm_pad_reg_upward (enum machine_mode, tree, int);
1483 extern bool arm_needs_doubleword_align (enum machine_mode, tree);
1484 -extern rtx arm_function_value(const_tree, const_tree);
1486 extern int arm_apply_result_size (void);
1487 +extern rtx aapcs_libcall_value (enum machine_mode);
1489 #endif /* RTX_CODE */
1491 --- a/gcc/config/arm/arm-tune.md
1492 +++ b/gcc/config/arm/arm-tune.md
1494 ;; -*- buffer-read-only: t -*-
1495 ;; Generated automatically by gentune.sh from arm-cores.def
1497 - "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm3,cortexm1"
1498 + "arm2,arm250,arm3,arm6,arm60,arm600,arm610,arm620,arm7,arm7d,arm7di,arm70,arm700,arm700i,arm710,arm720,arm710c,arm7100,arm7500,arm7500fe,arm7m,arm7dm,arm7dmi,arm8,arm810,strongarm,strongarm110,strongarm1100,strongarm1110,arm7tdmi,arm7tdmis,arm710t,arm720t,arm740t,arm9,arm9tdmi,arm920,arm920t,arm922t,arm940t,ep9312,arm10tdmi,arm1020t,arm9e,arm946es,arm966es,arm968es,arm10e,arm1020e,arm1022e,xscale,iwmmxt,iwmmxt2,marvell_f,arm926ejs,arm1026ejs,arm1136js,arm1136jfs,arm1176jzs,arm1176jzfs,mpcorenovfp,mpcore,arm1156t2s,cortexa5,cortexa8,cortexa9,cortexr4,cortexr4f,cortexm3,cortexm1,cortexm0"
1499 (const (symbol_ref "arm_tune")))
1500 --- a/gcc/config/arm/arm.c
1501 +++ b/gcc/config/arm/arm.c
1506 +#include "cgraph.h"
1509 #include "c-pragma.h"
1511 #include "langhooks.h"
1513 #include "libfuncs.h"
1515 +#include "params.h"
1517 /* Forward definitions of types. */
1518 typedef struct minipool_node Mnode;
1519 @@ -111,6 +114,7 @@ static unsigned long arm_compute_save_re
1520 static unsigned long arm_isr_value (tree);
1521 static unsigned long arm_compute_func_type (void);
1522 static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
1523 +static tree arm_handle_pcs_attribute (tree *, tree, tree, int, bool *);
1524 static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *);
1525 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
1526 static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *);
1527 @@ -124,6 +128,10 @@ static int arm_adjust_cost (rtx, rtx, rt
1528 static int count_insns_for_constant (HOST_WIDE_INT, int);
1529 static int arm_get_strip_length (int);
1530 static bool arm_function_ok_for_sibcall (tree, tree);
1531 +static bool arm_return_in_memory (const_tree, const_tree);
1532 +static rtx arm_function_value (const_tree, const_tree, bool);
1533 +static rtx arm_libcall_value (enum machine_mode, rtx);
1535 static void arm_internal_label (FILE *, const char *, unsigned long);
1536 static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
1538 @@ -149,6 +157,9 @@ static void emit_constant_insn (rtx cond
1539 static rtx emit_set_insn (rtx, rtx);
1540 static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
1542 +static rtx aapcs_allocate_return_reg (enum machine_mode, const_tree,
1544 +static int aapcs_select_return_coproc (const_tree, const_tree);
1546 #ifdef OBJECT_FORMAT_ELF
1547 static void arm_elf_asm_constructor (rtx, int) ATTRIBUTE_UNUSED;
1548 @@ -176,6 +187,7 @@ static void arm_unwind_emit (FILE *, rtx
1549 static bool arm_output_ttype (rtx);
1551 static void arm_dwarf_handle_frame_unspec (const char *, rtx, int);
1552 +static rtx arm_dwarf_register_span(rtx);
1554 static tree arm_cxx_guard_type (void);
1555 static bool arm_cxx_guard_mask_bit (void);
1556 @@ -198,6 +210,15 @@ static bool arm_tls_symbol_p (rtx x);
1557 static int arm_issue_rate (void);
1558 static void arm_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
1559 static bool arm_allocate_stack_slots_for_args (void);
1560 +static bool arm_warn_func_result (void);
1561 +static int arm_multipass_dfa_lookahead (void);
1562 +static const char *arm_invalid_parameter_type (const_tree t);
1563 +static const char *arm_invalid_return_type (const_tree t);
1564 +static tree arm_promoted_type (const_tree t);
1565 +static tree arm_convert_to_type (tree type, tree expr);
1566 +static bool arm_scalar_mode_supported_p (enum machine_mode);
1567 +static int arm_vector_min_alignment (const_tree type);
1568 +static bool arm_vector_always_misalign(const_tree);
1571 /* Initialize the GCC target structure. */
1572 @@ -257,6 +278,12 @@ static bool arm_allocate_stack_slots_for
1573 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1574 #define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall
1576 +#undef TARGET_FUNCTION_VALUE
1577 +#define TARGET_FUNCTION_VALUE arm_function_value
1579 +#undef TARGET_LIBCALL_VALUE
1580 +#define TARGET_LIBCALL_VALUE arm_libcall_value
1582 #undef TARGET_ASM_OUTPUT_MI_THUNK
1583 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
1584 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1585 @@ -300,6 +327,9 @@ static bool arm_allocate_stack_slots_for
1586 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
1587 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS arm_allocate_stack_slots_for_args
1589 +#undef TARGET_WARN_FUNC_RESULT
1590 +#define TARGET_WARN_FUNC_RESULT arm_warn_func_result
1592 #undef TARGET_DEFAULT_SHORT_ENUMS
1593 #define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums
1595 @@ -354,6 +384,9 @@ static bool arm_allocate_stack_slots_for
1596 #undef TARGET_ASM_TTYPE
1597 #define TARGET_ASM_TTYPE arm_output_ttype
1599 +#undef TARGET_CXX_TTYPE_REF_ENCODE
1600 +#define TARGET_CXX_TTYPE_REF_ENCODE hook_cxx_ttype_ref_in_bit0
1602 #undef TARGET_ARM_EABI_UNWINDER
1603 #define TARGET_ARM_EABI_UNWINDER true
1604 #endif /* TARGET_UNWIND_INFO */
1605 @@ -361,6 +394,9 @@ static bool arm_allocate_stack_slots_for
1606 #undef TARGET_DWARF_HANDLE_FRAME_UNSPEC
1607 #define TARGET_DWARF_HANDLE_FRAME_UNSPEC arm_dwarf_handle_frame_unspec
1609 +#undef TARGET_DWARF_REGISTER_SPAN
1610 +#define TARGET_DWARF_REGISTER_SPAN arm_dwarf_register_span
1612 #undef TARGET_CANNOT_COPY_INSN_P
1613 #define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p
1615 @@ -399,6 +435,30 @@ static bool arm_allocate_stack_slots_for
1616 #define TARGET_ASM_OUTPUT_DWARF_DTPREL arm_output_dwarf_dtprel
1619 +#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1620 +#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD arm_multipass_dfa_lookahead
1622 +#undef TARGET_INVALID_PARAMETER_TYPE
1623 +#define TARGET_INVALID_PARAMETER_TYPE arm_invalid_parameter_type
1625 +#undef TARGET_INVALID_RETURN_TYPE
1626 +#define TARGET_INVALID_RETURN_TYPE arm_invalid_return_type
1628 +#undef TARGET_PROMOTED_TYPE
1629 +#define TARGET_PROMOTED_TYPE arm_promoted_type
1631 +#undef TARGET_CONVERT_TO_TYPE
1632 +#define TARGET_CONVERT_TO_TYPE arm_convert_to_type
1634 +#undef TARGET_SCALAR_MODE_SUPPORTED_P
1635 +#define TARGET_SCALAR_MODE_SUPPORTED_P arm_scalar_mode_supported_p
1637 +#undef TARGET_VECTOR_MIN_ALIGNMENT
1638 +#define TARGET_VECTOR_MIN_ALIGNMENT arm_vector_min_alignment
1640 +#undef TARGET_VECTOR_ALWAYS_MISALIGN
1641 +#define TARGET_VECTOR_ALWAYS_MISALIGN arm_vector_always_misalign
1643 struct gcc_target targetm = TARGET_INITIALIZER;
1645 /* Obstack for minipool constant handling. */
1646 @@ -424,18 +484,18 @@ enum processor_type arm_tune = arm_none;
1647 /* The default processor used if not overridden by commandline. */
1648 static enum processor_type arm_default_cpu = arm_none;
1650 -/* Which floating point model to use. */
1651 -enum arm_fp_model arm_fp_model;
1653 -/* Which floating point hardware is available. */
1654 -enum fputype arm_fpu_arch;
1656 /* Which floating point hardware to schedule for. */
1657 -enum fputype arm_fpu_tune;
1660 +/* Which floating popint hardware to use. */
1661 +const struct arm_fpu_desc *arm_fpu_desc;
1663 /* Whether to use floating point hardware. */
1664 enum float_abi_type arm_float_abi;
1666 +/* Which __fp16 format to use. */
1667 +enum arm_fp16_format_type arm_fp16_format;
1669 /* Which ABI to use. */
1670 enum arm_abi_type arm_abi;
1672 @@ -474,9 +534,19 @@ static int thumb_call_reg_needed;
1673 #define FL_DIV (1 << 18) /* Hardware divide. */
1674 #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */
1675 #define FL_NEON (1 << 20) /* Neon instructions. */
1676 +#define FL_MARVELL_F (1 << 21) /* Marvell Feroceon. */
1677 +#define FL_ARCH7EM (1 << 22) /* Instructions present in ARMv7E-M. */
1679 #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */
1681 +/* Some flags are ignored when comparing -mcpu and -march:
1682 + FL_MARVELL_F so that -mcpu=marvell-f -march=v5te works.
1683 + FL_LDSCHED and FL_WBUF only effect tuning,
1684 + FL_CO_PROC, FL_VFPV2, FL_VFPV3 and FL_NEON because FP
1685 + coprocessors are handled separately. */
1686 +#define FL_COMPAT (FL_MARVELL_F | FL_LDSCHED | FL_WBUF | FL_CO_PROC | \
1687 + FL_VFPV2 | FL_VFPV3 | FL_NEON)
1689 #define FL_FOR_ARCH2 FL_NOTM
1690 #define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
1691 #define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
1692 @@ -498,6 +568,7 @@ static int thumb_call_reg_needed;
1693 #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM)
1694 #define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV)
1695 #define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV)
1696 +#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
1698 /* The bits in this mask specify which
1699 instructions we are allowed to generate. */
1700 @@ -534,6 +605,9 @@ int arm_arch6k = 0;
1701 /* Nonzero if instructions not present in the 'M' profile can be used. */
1702 int arm_arch_notm = 0;
1704 +/* Nonzero if instructions present in ARMv7E-M can be used. */
1705 +int arm_arch7em = 0;
1707 /* Nonzero if this chip can benefit from load scheduling. */
1708 int arm_ld_sched = 0;
1710 @@ -552,6 +626,9 @@ int arm_arch_xscale = 0;
1711 /* Nonzero if tuning for XScale */
1712 int arm_tune_xscale = 0;
1714 +/* Nonzero if tuning for Marvell Feroceon. */
1715 +int arm_tune_marvell_f = 0;
1717 /* Nonzero if we want to tune for stores that access the write-buffer.
1718 This typically means an ARM6 or ARM7 with MMU or MPU. */
1719 int arm_tune_wbuf = 0;
1720 @@ -562,6 +639,9 @@ int arm_tune_cortex_a9 = 0;
1721 /* Nonzero if generating Thumb instructions. */
1724 +/* Nonzero if generating code for Janus2. */
1725 +int janus2_code = 0;
1727 /* Nonzero if we should define __THUMB_INTERWORK__ in the
1729 XXX This is a bit of a hack, it's intended to help work around
1730 @@ -594,6 +674,8 @@ static int after_arm_reorg = 0;
1731 /* The maximum number of insns to be used when loading a constant. */
1732 static int arm_constant_limit = 3;
1734 +static enum arm_pcs arm_pcs_default;
1736 /* For an explanation of these variables, see final_prescan_insn below. */
1737 int arm_ccfsm_state;
1738 /* arm_current_cc is also used for Thumb-2 cond_exec blocks. */
1739 @@ -674,9 +756,11 @@ static const struct processors all_archi
1740 {"armv7-a", cortexa8, "7A", FL_CO_PROC | FL_FOR_ARCH7A, NULL},
1741 {"armv7-r", cortexr4, "7R", FL_CO_PROC | FL_FOR_ARCH7R, NULL},
1742 {"armv7-m", cortexm3, "7M", FL_CO_PROC | FL_FOR_ARCH7M, NULL},
1743 + {"armv7e-m", cortexm3, "7EM", FL_CO_PROC | FL_FOR_ARCH7EM, NULL},
1744 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL},
1745 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
1746 {"iwmmxt2", iwmmxt2, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL},
1747 + {"marvell-f", marvell_f, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE | FL_MARVELL_F, NULL},
1748 {NULL, arm_none, NULL, 0 , NULL}
1751 @@ -706,49 +790,34 @@ static struct arm_cpu_select arm_select[
1753 /* The name of the preprocessor macro to define for this architecture. */
1755 -char arm_arch_name[] = "__ARM_ARCH_0UNK__";
1759 - const char * name;
1763 +#define ARM_ARCH_NAME_SIZE 25
1764 +char arm_arch_name[ARM_ARCH_NAME_SIZE] = "__ARM_ARCH_0UNK__";
1766 /* Available values for -mfpu=. */
1768 -static const struct fpu_desc all_fpus[] =
1769 +static const struct arm_fpu_desc all_fpus[] =
1771 - {"fpa", FPUTYPE_FPA},
1772 - {"fpe2", FPUTYPE_FPA_EMU2},
1773 - {"fpe3", FPUTYPE_FPA_EMU2},
1774 - {"maverick", FPUTYPE_MAVERICK},
1775 - {"vfp", FPUTYPE_VFP},
1776 - {"vfp3", FPUTYPE_VFP3},
1777 - {"vfpv3", FPUTYPE_VFP3},
1778 - {"vfpv3-d16", FPUTYPE_VFP3D16},
1779 - {"neon", FPUTYPE_NEON}
1780 + {"fpa", ARM_FP_MODEL_FPA, 0, 0, false, false},
1781 + {"fpe2", ARM_FP_MODEL_FPA, 2, 0, false, false},
1782 + {"fpe3", ARM_FP_MODEL_FPA, 3, 0, false, false},
1783 + {"maverick", ARM_FP_MODEL_MAVERICK, 0, 0, false, false},
1784 + {"vfp", ARM_FP_MODEL_VFP, 2, VFP_REG_D16, false, false},
1785 + {"vfpv3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false},
1786 + {"vfpv3-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, true },
1787 + {"vfpv3-d16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, false},
1788 + {"vfpv3xd", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, false},
1789 + {"vfpv3xd-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_SINGLE, false, true },
1790 + {"vfpv3-d16-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D16, false, true },
1791 + {"neon", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true , false},
1792 + {"neon-fp16", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, true , true },
1793 + {"vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, false, true },
1794 + {"vfpv4-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_D16, false, true },
1795 + {"fpv4-sp-d16", ARM_FP_MODEL_VFP, 4, VFP_REG_SINGLE, false, true },
1796 + {"neon-vfpv4", ARM_FP_MODEL_VFP, 4, VFP_REG_D32, true , true },
1797 + /* Compatibility aliases. */
1798 + {"vfp3", ARM_FP_MODEL_VFP, 3, VFP_REG_D32, false, false},
1802 -/* Floating point models used by the different hardware.
1803 - See fputype in arm.h. */
1805 -static const enum fputype fp_model_for_fpu[] =
1807 - /* No FP hardware. */
1808 - ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */
1809 - ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */
1810 - ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */
1811 - ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */
1812 - ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */
1813 - ARM_FP_MODEL_VFP, /* FPUTYPE_VFP */
1814 - ARM_FP_MODEL_VFP, /* FPUTYPE_VFP3D16 */
1815 - ARM_FP_MODEL_VFP, /* FPUTYPE_VFP3 */
1816 - ARM_FP_MODEL_VFP /* FPUTYPE_NEON */
1823 @@ -766,6 +835,23 @@ static const struct float_abi all_float_
1830 + enum arm_fp16_format_type fp16_format_type;
1834 +/* Available values for -mfp16-format=. */
1836 +static const struct fp16_format all_fp16_formats[] =
1838 + {"none", ARM_FP16_FORMAT_NONE},
1839 + {"ieee", ARM_FP16_FORMAT_IEEE},
1840 + {"alternative", ARM_FP16_FORMAT_ALTERNATIVE}
1847 @@ -924,6 +1010,45 @@ arm_init_libfuncs (void)
1848 set_optab_libfunc (smod_optab, SImode, NULL);
1849 set_optab_libfunc (umod_optab, SImode, NULL);
1852 + /* Half-precision float operations. The compiler handles all operations
1853 + with NULL libfuncs by converting the SFmode. */
1854 + switch (arm_fp16_format)
1856 + case ARM_FP16_FORMAT_IEEE:
1857 + case ARM_FP16_FORMAT_ALTERNATIVE:
1859 + /* Conversions. */
1860 + set_conv_libfunc (trunc_optab, HFmode, SFmode,
1861 + (arm_fp16_format == ARM_FP16_FORMAT_IEEE
1862 + ? "__gnu_f2h_ieee"
1863 + : "__gnu_f2h_alternative"));
1864 + set_conv_libfunc (sext_optab, SFmode, HFmode,
1865 + (arm_fp16_format == ARM_FP16_FORMAT_IEEE
1866 + ? "__gnu_h2f_ieee"
1867 + : "__gnu_h2f_alternative"));
1870 + set_optab_libfunc (add_optab, HFmode, NULL);
1871 + set_optab_libfunc (sdiv_optab, HFmode, NULL);
1872 + set_optab_libfunc (smul_optab, HFmode, NULL);
1873 + set_optab_libfunc (neg_optab, HFmode, NULL);
1874 + set_optab_libfunc (sub_optab, HFmode, NULL);
1876 + /* Comparisons. */
1877 + set_optab_libfunc (eq_optab, HFmode, NULL);
1878 + set_optab_libfunc (ne_optab, HFmode, NULL);
1879 + set_optab_libfunc (lt_optab, HFmode, NULL);
1880 + set_optab_libfunc (le_optab, HFmode, NULL);
1881 + set_optab_libfunc (ge_optab, HFmode, NULL);
1882 + set_optab_libfunc (gt_optab, HFmode, NULL);
1883 + set_optab_libfunc (unord_optab, HFmode, NULL);
1890 if (TARGET_AAPCS_BASED)
1891 synchronize_libfunc = init_one_libfunc ("__sync_synchronize");
1893 @@ -1139,6 +1264,7 @@ void
1894 arm_override_options (void)
1898 enum processor_type target_arch_cpu = arm_none;
1899 enum processor_type selected_cpu = arm_none;
1901 @@ -1156,7 +1282,11 @@ arm_override_options (void)
1903 /* Set the architecture define. */
1904 if (i != ARM_OPT_SET_TUNE)
1905 - sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
1907 + len = snprintf (arm_arch_name, ARM_ARCH_NAME_SIZE,
1908 + "__ARM_ARCH_%s__", sel->arch);
1909 + gcc_assert (len < ARM_ARCH_NAME_SIZE);
1912 /* Determine the processor core for which we should
1913 tune code-generation. */
1914 @@ -1182,8 +1312,8 @@ arm_override_options (void)
1915 make sure that they are compatible. We only generate
1916 a warning though, and we prefer the CPU over the
1918 - if (insn_flags != 0 && (insn_flags ^ sel->flags))
1919 - warning (0, "switch -mcpu=%s conflicts with -march= switch",
1920 + if (insn_flags != 0 && ((insn_flags ^ sel->flags) & ~FL_COMPAT))
1921 + warning (0, "switch -mcpu=%s conflicts with -march= switch, assuming CPU feature set",
1924 insn_flags = sel->flags;
1925 @@ -1283,7 +1413,11 @@ arm_override_options (void)
1927 insn_flags = sel->flags;
1929 - sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch);
1931 + len = snprintf (arm_arch_name, ARM_ARCH_NAME_SIZE,
1932 + "__ARM_ARCH_%s__", sel->arch);
1933 + gcc_assert (len < ARM_ARCH_NAME_SIZE);
1935 arm_default_cpu = (enum processor_type) (sel - all_cores);
1936 if (arm_tune == arm_none)
1937 arm_tune = arm_default_cpu;
1938 @@ -1293,8 +1427,35 @@ arm_override_options (void)
1940 gcc_assert (arm_tune != arm_none);
1942 + if (arm_tune == cortexa8 && optimize >= 3)
1944 + /* These alignments were experimentally determined to improve SPECint
1945 + performance on SPECCPU 2000. */
1946 + if (align_functions <= 0)
1947 + align_functions = 16;
1948 + if (align_jumps <= 0)
1952 tune_flags = all_cores[(int)arm_tune].flags;
1954 + if (target_fp16_format_name)
1956 + for (i = 0; i < ARRAY_SIZE (all_fp16_formats); i++)
1958 + if (streq (all_fp16_formats[i].name, target_fp16_format_name))
1960 + arm_fp16_format = all_fp16_formats[i].fp16_format_type;
1964 + if (i == ARRAY_SIZE (all_fp16_formats))
1965 + error ("invalid __fp16 format option: -mfp16-format=%s",
1966 + target_fp16_format_name);
1969 + arm_fp16_format = ARM_FP16_FORMAT_NONE;
1971 if (target_abi_name)
1973 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++)
1974 @@ -1387,6 +1548,7 @@ arm_override_options (void)
1975 arm_arch6 = (insn_flags & FL_ARCH6) != 0;
1976 arm_arch6k = (insn_flags & FL_ARCH6K) != 0;
1977 arm_arch_notm = (insn_flags & FL_NOTM) != 0;
1978 + arm_arch7em = (insn_flags & FL_ARCH7EM) != 0;
1979 arm_arch_thumb2 = (insn_flags & FL_THUMB2) != 0;
1980 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0;
1981 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0;
1982 @@ -1394,12 +1556,25 @@ arm_override_options (void)
1983 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0;
1984 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0;
1985 thumb_code = (TARGET_ARM == 0);
1986 + janus2_code = (TARGET_FIX_JANUS != 0);
1987 + if (janus2_code && TARGET_THUMB2)
1988 + error ("janus2 fix is not applicable when targeting a thumb2 core");
1989 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0;
1990 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0;
1991 + arm_tune_marvell_f = (tune_flags & FL_MARVELL_F) != 0;
1992 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0;
1993 - arm_arch_hwdiv = (insn_flags & FL_DIV) != 0;
1994 arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0;
1996 + /* Hardware integer division is supported by some variants of the ARM
1997 + architecture in Thumb-2 mode. In addition some (but not all) Marvell
1998 + CPUs support their own hardware integer division instructions.
1999 + The assembler will pick the correct encoding. */
2000 + if (TARGET_MARVELL_DIV && (insn_flags & FL_MARVELL_F) == 0)
2001 + error ("-mmarvell-div is only supported when targeting a Marvell core");
2003 + arm_arch_hwdiv = (TARGET_ARM && TARGET_MARVELL_DIV)
2004 + || (TARGET_THUMB2 && (insn_flags & FL_DIV) != 0);
2006 /* If we are not using the default (ARM mode) section anchor offset
2007 ranges, then set the correct ranges now. */
2009 @@ -1438,7 +1613,6 @@ arm_override_options (void)
2010 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
2011 error ("iwmmxt abi requires an iwmmxt capable cpu");
2013 - arm_fp_model = ARM_FP_MODEL_UNKNOWN;
2014 if (target_fpu_name == NULL && target_fpe_name != NULL)
2016 if (streq (target_fpe_name, "2"))
2017 @@ -1449,46 +1623,52 @@ arm_override_options (void)
2018 error ("invalid floating point emulation option: -mfpe=%s",
2021 - if (target_fpu_name != NULL)
2023 - /* The user specified a FPU. */
2024 - for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
2026 - if (streq (all_fpus[i].name, target_fpu_name))
2028 - arm_fpu_arch = all_fpus[i].fpu;
2029 - arm_fpu_tune = arm_fpu_arch;
2030 - arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
2034 - if (arm_fp_model == ARM_FP_MODEL_UNKNOWN)
2035 - error ("invalid floating point option: -mfpu=%s", target_fpu_name);
2039 + if (target_fpu_name == NULL)
2041 #ifdef FPUTYPE_DEFAULT
2042 - /* Use the default if it is specified for this platform. */
2043 - arm_fpu_arch = FPUTYPE_DEFAULT;
2044 - arm_fpu_tune = FPUTYPE_DEFAULT;
2045 + target_fpu_name = FPUTYPE_DEFAULT;
2047 - /* Pick one based on CPU type. */
2048 - /* ??? Some targets assume FPA is the default.
2049 - if ((insn_flags & FL_VFP) != 0)
2050 - arm_fpu_arch = FPUTYPE_VFP;
2053 if (arm_arch_cirrus)
2054 - arm_fpu_arch = FPUTYPE_MAVERICK;
2055 + target_fpu_name = "maverick";
2057 - arm_fpu_arch = FPUTYPE_FPA_EMU2;
2058 + target_fpu_name = "fpe2";
2060 - if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2)
2061 - arm_fpu_tune = FPUTYPE_FPA;
2064 + arm_fpu_desc = NULL;
2065 + for (i = 0; i < ARRAY_SIZE (all_fpus); i++)
2067 + if (streq (all_fpus[i].name, target_fpu_name))
2069 + arm_fpu_desc = &all_fpus[i];
2073 + if (!arm_fpu_desc)
2074 + error ("invalid floating point option: -mfpu=%s", target_fpu_name);
2076 + switch (arm_fpu_desc->model)
2078 + case ARM_FP_MODEL_FPA:
2079 + if (arm_fpu_desc->rev == 2)
2080 + arm_fpu_attr = FPU_FPE2;
2081 + else if (arm_fpu_desc->rev == 3)
2082 + arm_fpu_attr = FPU_FPE3;
2084 - arm_fpu_tune = arm_fpu_arch;
2085 - arm_fp_model = fp_model_for_fpu[arm_fpu_arch];
2086 - gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN);
2087 + arm_fpu_attr = FPU_FPA;
2090 + case ARM_FP_MODEL_MAVERICK:
2091 + arm_fpu_attr = FPU_MAVERICK;
2094 + case ARM_FP_MODEL_VFP:
2095 + arm_fpu_attr = FPU_VFP;
2099 + gcc_unreachable();
2102 if (target_float_abi_name != NULL)
2103 @@ -1509,9 +1689,6 @@ arm_override_options (void)
2105 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI;
2107 - if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
2108 - sorry ("-mfloat-abi=hard and VFP");
2110 /* FPA and iWMMXt are incompatible because the insn encodings overlap.
2111 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon
2112 will ever exist. GCC makes no attempt to support this combination. */
2113 @@ -1522,15 +1699,40 @@ arm_override_options (void)
2114 if (TARGET_THUMB2 && TARGET_IWMMXT)
2115 sorry ("Thumb-2 iWMMXt");
2117 + /* __fp16 support currently assumes the core has ldrh. */
2118 + if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE)
2119 + sorry ("__fp16 and no ldrh");
2121 /* If soft-float is specified then don't use FPU. */
2122 if (TARGET_SOFT_FLOAT)
2123 - arm_fpu_arch = FPUTYPE_NONE;
2124 + arm_fpu_attr = FPU_NONE;
2126 + if (TARGET_AAPCS_BASED)
2128 + if (arm_abi == ARM_ABI_IWMMXT)
2129 + arm_pcs_default = ARM_PCS_AAPCS_IWMMXT;
2130 + else if (arm_float_abi == ARM_FLOAT_ABI_HARD
2131 + && TARGET_HARD_FLOAT
2133 + arm_pcs_default = ARM_PCS_AAPCS_VFP;
2135 + arm_pcs_default = ARM_PCS_AAPCS;
2139 + if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP)
2140 + sorry ("-mfloat-abi=hard and VFP");
2142 + if (arm_abi == ARM_ABI_APCS)
2143 + arm_pcs_default = ARM_PCS_APCS;
2145 + arm_pcs_default = ARM_PCS_ATPCS;
2148 /* For arm2/3 there is no need to do any scheduling if there is only
2149 a floating point emulator, or we are doing software floating-point. */
2150 if ((TARGET_SOFT_FLOAT
2151 - || arm_fpu_tune == FPUTYPE_FPA_EMU2
2152 - || arm_fpu_tune == FPUTYPE_FPA_EMU3)
2153 + || (TARGET_FPA && arm_fpu_desc->rev))
2154 && (tune_flags & FL_MODE32) == 0)
2155 flag_schedule_insns = flag_schedule_insns_after_reload = 0;
2157 @@ -1620,8 +1822,7 @@ arm_override_options (void)
2161 - /* ??? We might want scheduling for thumb2. */
2162 - if (TARGET_THUMB && flag_schedule_insns)
2163 + if (TARGET_THUMB1 && flag_schedule_insns)
2165 /* Don't warn since it's on by default in -O2. */
2166 flag_schedule_insns = 0;
2167 @@ -1664,6 +1865,36 @@ arm_override_options (void)
2169 /* Register global variables with the garbage collector. */
2170 arm_add_gc_roots ();
2172 + if (low_irq_latency && TARGET_THUMB)
2175 + "-low-irq-latency has no effect when compiling for the Thumb");
2176 + low_irq_latency = 0;
2180 + /* Loop unrolling can be a substantial win. At -O2, limit to 2x
2181 + unrolling by default to prevent excessive code growth; at -O3,
2182 + limit to 4x unrolling by default. We know we are not optimizing
2183 + for size if this is set (see arm_optimization_options). */
2184 + if (flag_unroll_loops == 2)
2186 + if (optimize == 2)
2188 + flag_unroll_loops = 1;
2189 + if (!PARAM_SET_P (PARAM_MAX_UNROLL_TIMES))
2190 + set_param_value ("max-unroll-times", 2);
2192 + else if (optimize > 2)
2194 + flag_unroll_loops = 1;
2195 + if (!PARAM_SET_P (PARAM_MAX_UNROLL_TIMES))
2196 + set_param_value ("max-unroll-times", 4);
2199 + flag_unroll_loops = 0;
2204 @@ -1793,6 +2024,14 @@ arm_allocate_stack_slots_for_args (void)
2205 return !IS_NAKED (arm_current_func_type ());
2209 +arm_warn_func_result (void)
2211 + /* Naked functions are implemented entirely in assembly, including the
2212 + return sequence, so suppress warnings about this. */
2213 + return !IS_NAKED (arm_current_func_type ());
2217 /* Return 1 if it is possible to return using a single instruction.
2218 If SIBLING is non-null, this is a test for a return before a sibling
2219 @@ -2884,14 +3123,19 @@ arm_canonicalize_comparison (enum rtx_co
2221 /* Define how to find the value returned by a function. */
2224 -arm_function_value(const_tree type, const_tree func ATTRIBUTE_UNUSED)
2226 +arm_function_value(const_tree type, const_tree func,
2227 + bool outgoing ATTRIBUTE_UNUSED)
2229 enum machine_mode mode;
2230 int unsignedp ATTRIBUTE_UNUSED;
2231 rtx r ATTRIBUTE_UNUSED;
2233 mode = TYPE_MODE (type);
2235 + if (TARGET_AAPCS_BASED)
2236 + return aapcs_allocate_return_reg (mode, type, func);
2238 /* Promote integer types. */
2239 if (INTEGRAL_TYPE_P (type))
2240 PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
2241 @@ -2908,7 +3152,36 @@ arm_function_value(const_tree type, cons
2245 - return LIBCALL_VALUE(mode);
2246 + return LIBCALL_VALUE (mode);
2250 +arm_libcall_value (enum machine_mode mode, rtx libcall)
2252 + if (TARGET_AAPCS_BASED && arm_pcs_default != ARM_PCS_AAPCS
2253 + && GET_MODE_CLASS (mode) == MODE_FLOAT)
2255 + /* The following libcalls return their result in integer registers,
2256 + even though they return a floating point value. */
2257 + if (rtx_equal_p (libcall,
2258 + convert_optab_libfunc (sfloat_optab, mode, SImode))
2259 + || rtx_equal_p (libcall,
2260 + convert_optab_libfunc (ufloat_optab, mode, SImode))
2261 + || rtx_equal_p (libcall,
2262 + convert_optab_libfunc (sfloat_optab, mode, DImode))
2263 + || rtx_equal_p (libcall,
2264 + convert_optab_libfunc (ufloat_optab, mode, DImode))
2265 + || rtx_equal_p (libcall,
2266 + convert_optab_libfunc (trunc_optab, HFmode, SFmode))
2267 + || rtx_equal_p (libcall,
2268 + convert_optab_libfunc (sext_optab, SFmode, HFmode)))
2269 + return gen_rtx_REG (mode, ARG_REGISTER(1));
2271 + /* XXX There are other libcalls that return in integer registers,
2272 + but I think they are all handled by hard insns. */
2275 + return LIBCALL_VALUE (mode);
2278 /* Determine the amount of memory needed to store the possible return
2279 @@ -2918,10 +3191,12 @@ arm_apply_result_size (void)
2286 if (TARGET_HARD_FLOAT_ABI)
2292 if (TARGET_MAVERICK)
2293 @@ -2934,27 +3209,56 @@ arm_apply_result_size (void)
2297 -/* Decide whether a type should be returned in memory (true)
2298 - or in a register (false). This is called as the target hook
2299 - TARGET_RETURN_IN_MEMORY. */
2300 +/* Decide whether TYPE should be returned in memory (true)
2301 + or in a register (false). FNTYPE is the type of the function making
2304 -arm_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
2305 +arm_return_in_memory (const_tree type, const_tree fntype)
2309 - size = int_size_in_bytes (type);
2310 + size = int_size_in_bytes (type); /* Negative if not fixed size. */
2312 + if (TARGET_AAPCS_BASED)
2314 + /* Simple, non-aggregate types (ie not including vectors and
2315 + complex) are always returned in a register (or registers).
2316 + We don't care about which register here, so we can short-cut
2317 + some of the detail. */
2318 + if (!AGGREGATE_TYPE_P (type)
2319 + && TREE_CODE (type) != VECTOR_TYPE
2320 + && TREE_CODE (type) != COMPLEX_TYPE)
2323 + /* Any return value that is no larger than one word can be
2324 + returned in r0. */
2325 + if (((unsigned HOST_WIDE_INT) size) <= UNITS_PER_WORD)
2328 + /* Check any available co-processors to see if they accept the
2329 + type as a register candidate (VFP, for example, can return
2330 + some aggregates in consecutive registers). These aren't
2331 + available if the call is variadic. */
2332 + if (aapcs_select_return_coproc (type, fntype) >= 0)
2335 + /* Vector values should be returned using ARM registers, not
2336 + memory (unless they're over 16 bytes, which will break since
2337 + we only have four call-clobbered registers to play with). */
2338 + if (TREE_CODE (type) == VECTOR_TYPE)
2339 + return (size < 0 || size > (4 * UNITS_PER_WORD));
2341 + /* The rest go in memory. */
2345 - /* Vector values should be returned using ARM registers, not memory (unless
2346 - they're over 16 bytes, which will break since we only have four
2347 - call-clobbered registers to play with). */
2348 if (TREE_CODE (type) == VECTOR_TYPE)
2349 return (size < 0 || size > (4 * UNITS_PER_WORD));
2351 if (!AGGREGATE_TYPE_P (type) &&
2352 - !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE))
2353 - /* All simple types are returned in registers.
2354 - For AAPCS, complex types are treated the same as aggregates. */
2356 + (TREE_CODE (type) != VECTOR_TYPE))
2357 + /* All simple types are returned in registers. */
2360 if (arm_abi != ARM_ABI_APCS)
2362 @@ -2971,7 +3275,7 @@ arm_return_in_memory (const_tree type, c
2363 the aggregate is either huge or of variable size, and in either case
2364 we will want to return it via memory and not in a register. */
2365 if (size < 0 || size > UNITS_PER_WORD)
2369 if (TREE_CODE (type) == RECORD_TYPE)
2371 @@ -2991,18 +3295,18 @@ arm_return_in_memory (const_tree type, c
2375 - return 0; /* An empty structure. Allowed by an extension to ANSI C. */
2376 + return false; /* An empty structure. Allowed by an extension to ANSI C. */
2378 /* Check that the first field is valid for returning in a register. */
2380 /* ... Floats are not allowed */
2381 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2385 /* ... Aggregates that are not themselves valid for returning in
2386 a register are not allowed. */
2387 if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE))
2391 /* Now check the remaining fields, if any. Only bitfields are allowed,
2392 since they are not addressable. */
2393 @@ -3014,10 +3318,10 @@ arm_return_in_memory (const_tree type, c
2396 if (!DECL_BIT_FIELD_TYPE (field))
2405 if (TREE_CODE (type) == UNION_TYPE)
2406 @@ -3034,18 +3338,18 @@ arm_return_in_memory (const_tree type, c
2409 if (FLOAT_TYPE_P (TREE_TYPE (field)))
2413 if (arm_return_in_memory (TREE_TYPE (field), NULL_TREE))
2421 #endif /* not ARM_WINCE */
2423 /* Return all other types in memory. */
2428 /* Indicate whether or not words of a double are in big-endian order. */
2429 @@ -3070,14 +3374,780 @@ arm_float_words_big_endian (void)
2433 +const struct pcs_attribute_arg
2436 + enum arm_pcs value;
2437 +} pcs_attribute_args[] =
2439 + {"aapcs", ARM_PCS_AAPCS},
2440 + {"aapcs-vfp", ARM_PCS_AAPCS_VFP},
2441 + {"aapcs-iwmmxt", ARM_PCS_AAPCS_IWMMXT},
2442 + {"atpcs", ARM_PCS_ATPCS},
2443 + {"apcs", ARM_PCS_APCS},
2444 + {NULL, ARM_PCS_UNKNOWN}
2447 +static enum arm_pcs
2448 +arm_pcs_from_attribute (tree attr)
2450 + const struct pcs_attribute_arg *ptr;
2453 + /* Get the value of the argument. */
2454 + if (TREE_VALUE (attr) == NULL_TREE
2455 + || TREE_CODE (TREE_VALUE (attr)) != STRING_CST)
2456 + return ARM_PCS_UNKNOWN;
2458 + arg = TREE_STRING_POINTER (TREE_VALUE (attr));
2460 + /* Check it against the list of known arguments. */
2461 + for (ptr = pcs_attribute_args; ptr->arg != NULL; ptr++)
2462 + if (streq (arg, ptr->arg))
2463 + return ptr->value;
2465 + /* An unrecognized interrupt type. */
2466 + return ARM_PCS_UNKNOWN;
2469 +/* Get the PCS variant to use for this call. TYPE is the function's type
2470 + specification, DECL is the specific declartion. DECL may be null if
2471 + the call could be indirect or if this is a library call. */
2472 +static enum arm_pcs
2473 +arm_get_pcs_model (const_tree type, const_tree decl)
2475 + bool user_convention = false;
2476 + enum arm_pcs user_pcs = arm_pcs_default;
2479 + gcc_assert (type);
2481 + attr = lookup_attribute ("pcs", TYPE_ATTRIBUTES (type));
2484 + user_pcs = arm_pcs_from_attribute (TREE_VALUE (attr));
2485 + user_convention = true;
2488 + if (TARGET_AAPCS_BASED)
2490 + /* Detect varargs functions. These always use the base rules
2491 + (no argument is ever a candidate for a co-processor
2493 + bool base_rules = (TYPE_ARG_TYPES (type) != 0
2494 + && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (type)))
2495 + != void_type_node));
2497 + if (user_convention)
2499 + if (user_pcs > ARM_PCS_AAPCS_LOCAL)
2500 + sorry ("Non-AAPCS derived PCS variant");
2501 + else if (base_rules && user_pcs != ARM_PCS_AAPCS)
2502 + error ("Variadic functions must use the base AAPCS variant");
2506 + return ARM_PCS_AAPCS;
2507 + else if (user_convention)
2509 + else if (decl && flag_unit_at_a_time)
2511 + /* Local functions never leak outside this compilation unit,
2512 + so we are free to use whatever conventions are
2514 + /* FIXME: remove CONST_CAST_TREE when cgraph is constified. */
2515 + struct cgraph_local_info *i = cgraph_local_info (CONST_CAST_TREE(decl));
2516 + if (i && i->local)
2517 + return ARM_PCS_AAPCS_LOCAL;
2520 + else if (user_convention && user_pcs != arm_pcs_default)
2521 + sorry ("PCS variant");
2523 + /* For everything else we use the target's default. */
2524 + return arm_pcs_default;
2529 +aapcs_vfp_cum_init (CUMULATIVE_ARGS *pcum ATTRIBUTE_UNUSED,
2530 + const_tree fntype ATTRIBUTE_UNUSED,
2531 + rtx libcall ATTRIBUTE_UNUSED,
2532 + const_tree fndecl ATTRIBUTE_UNUSED)
2534 + /* Record the unallocated VFP registers. */
2535 + pcum->aapcs_vfp_regs_free = (1 << NUM_VFP_ARG_REGS) - 1;
2536 + pcum->aapcs_vfp_reg_alloc = 0;
2539 +/* Walk down the type tree of TYPE counting consecutive base elements.
2540 + If *MODEP is VOIDmode, then set it to the first valid floating point
2541 + type. If a non-floating point type is found, or if a floating point
2542 + type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
2543 + otherwise return the count in the sub-tree. */
2545 +aapcs_vfp_sub_candidate (const_tree type, enum machine_mode *modep)
2547 + enum machine_mode mode;
2548 + HOST_WIDE_INT size;
2550 + switch (TREE_CODE (type))
2553 + mode = TYPE_MODE (type);
2554 + if (mode != DFmode && mode != SFmode)
2557 + if (*modep == VOIDmode)
2560 + if (*modep == mode)
2565 + case COMPLEX_TYPE:
2566 + mode = TYPE_MODE (TREE_TYPE (type));
2567 + if (mode != DFmode && mode != SFmode)
2570 + if (*modep == VOIDmode)
2573 + if (*modep == mode)
2579 + /* Use V2SImode and V4SImode as representatives of all 64-bit
2580 + and 128-bit vector types, whether or not those modes are
2581 + supported with the present options. */
2582 + size = int_size_in_bytes (type);
2595 + if (*modep == VOIDmode)
2598 + /* Vector modes are considered to be opaque: two vectors are
2599 + equivalent for the purposes of being homogeneous aggregates
2600 + if they are the same size. */
2601 + if (*modep == mode)
2609 + tree index = TYPE_DOMAIN (type);
2611 + /* Can't handle incomplete types. */
2612 + if (!COMPLETE_TYPE_P(type))
2615 + count = aapcs_vfp_sub_candidate (TREE_TYPE (type), modep);
2618 + || !TYPE_MAX_VALUE (index)
2619 + || !host_integerp (TYPE_MAX_VALUE (index), 1)
2620 + || !TYPE_MIN_VALUE (index)
2621 + || !host_integerp (TYPE_MIN_VALUE (index), 1)
2625 + count *= (1 + tree_low_cst (TYPE_MAX_VALUE (index), 1)
2626 + - tree_low_cst (TYPE_MIN_VALUE (index), 1));
2628 + /* There must be no padding. */
2629 + if (!host_integerp (TYPE_SIZE (type), 1)
2630 + || (tree_low_cst (TYPE_SIZE (type), 1)
2631 + != count * GET_MODE_BITSIZE (*modep)))
2643 + /* Can't handle incomplete types. */
2644 + if (!COMPLETE_TYPE_P(type))
2647 + for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
2649 + if (TREE_CODE (field) != FIELD_DECL)
2652 + sub_count = aapcs_vfp_sub_candidate (TREE_TYPE (field), modep);
2653 + if (sub_count < 0)
2655 + count += sub_count;
2658 + /* There must be no padding. */
2659 + if (!host_integerp (TYPE_SIZE (type), 1)
2660 + || (tree_low_cst (TYPE_SIZE (type), 1)
2661 + != count * GET_MODE_BITSIZE (*modep)))
2668 + case QUAL_UNION_TYPE:
2670 + /* These aren't very interesting except in a degenerate case. */
2675 + /* Can't handle incomplete types. */
2676 + if (!COMPLETE_TYPE_P(type))
2679 + for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
2681 + if (TREE_CODE (field) != FIELD_DECL)
2684 + sub_count = aapcs_vfp_sub_candidate (TREE_TYPE (field), modep);
2685 + if (sub_count < 0)
2687 + count = count > sub_count ? count : sub_count;
2690 + /* There must be no padding. */
2691 + if (!host_integerp (TYPE_SIZE (type), 1)
2692 + || (tree_low_cst (TYPE_SIZE (type), 1)
2693 + != count * GET_MODE_BITSIZE (*modep)))
2706 +/* Return true if PCS_VARIANT should use VFP registers. */
2708 +use_vfp_abi (enum arm_pcs pcs_variant, bool is_double)
2710 + if (pcs_variant == ARM_PCS_AAPCS_VFP)
2713 + if (pcs_variant != ARM_PCS_AAPCS_LOCAL)
2716 + return (TARGET_32BIT && TARGET_VFP && TARGET_HARD_FLOAT &&
2717 + (TARGET_VFP_DOUBLE || !is_double));
2721 +aapcs_vfp_is_call_or_return_candidate (enum arm_pcs pcs_variant,
2722 + enum machine_mode mode, const_tree type,
2723 + int *base_mode, int *count)
2725 + enum machine_mode new_mode = VOIDmode;
2727 + if (GET_MODE_CLASS (mode) == MODE_FLOAT
2728 + || GET_MODE_CLASS (mode) == MODE_VECTOR_INT
2729 + || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
2734 + else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
2737 + new_mode = (mode == DCmode ? DFmode : SFmode);
2739 + else if (type && (mode == BLKmode || TREE_CODE (type) == VECTOR_TYPE))
2741 + int ag_count = aapcs_vfp_sub_candidate (type, &new_mode);
2743 + if (ag_count > 0 && ag_count <= 4)
2744 + *count = ag_count;
2752 + if (!use_vfp_abi (pcs_variant, ARM_NUM_REGS (new_mode) > 1))
2755 + *base_mode = new_mode;
2760 +aapcs_vfp_is_return_candidate (enum arm_pcs pcs_variant,
2761 + enum machine_mode mode, const_tree type)
2763 + int count ATTRIBUTE_UNUSED;
2764 + int ag_mode ATTRIBUTE_UNUSED;
2766 + if (!use_vfp_abi (pcs_variant, false))
2768 + return aapcs_vfp_is_call_or_return_candidate (pcs_variant, mode, type,
2769 + &ag_mode, &count);
2773 +aapcs_vfp_is_call_candidate (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2776 + if (!use_vfp_abi (pcum->pcs_variant, false))
2779 + return aapcs_vfp_is_call_or_return_candidate (pcum->pcs_variant, mode, type,
2780 + &pcum->aapcs_vfp_rmode,
2781 + &pcum->aapcs_vfp_rcount);
2785 +aapcs_vfp_allocate (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2786 + const_tree type ATTRIBUTE_UNUSED)
2788 + int shift = GET_MODE_SIZE (pcum->aapcs_vfp_rmode) / GET_MODE_SIZE (SFmode);
2789 + unsigned mask = (1 << (shift * pcum->aapcs_vfp_rcount)) - 1;
2792 + for (regno = 0; regno < NUM_VFP_ARG_REGS; regno += shift)
2793 + if (((pcum->aapcs_vfp_regs_free >> regno) & mask) == mask)
2795 + pcum->aapcs_vfp_reg_alloc = mask << regno;
2796 + if (mode == BLKmode || (mode == TImode && !TARGET_NEON))
2799 + int rcount = pcum->aapcs_vfp_rcount;
2800 + int rshift = shift;
2801 + enum machine_mode rmode = pcum->aapcs_vfp_rmode;
2805 + /* Avoid using unsupported vector modes. */
2806 + if (rmode == V2SImode)
2808 + else if (rmode == V4SImode)
2815 + par = gen_rtx_PARALLEL (mode, rtvec_alloc (rcount));
2816 + for (i = 0; i < rcount; i++)
2818 + rtx tmp = gen_rtx_REG (rmode,
2819 + FIRST_VFP_REGNUM + regno + i * rshift);
2820 + tmp = gen_rtx_EXPR_LIST
2822 + GEN_INT (i * GET_MODE_SIZE (rmode)));
2823 + XVECEXP (par, 0, i) = tmp;
2826 + pcum->aapcs_reg = par;
2829 + pcum->aapcs_reg = gen_rtx_REG (mode, FIRST_VFP_REGNUM + regno);
2836 +aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED,
2837 + enum machine_mode mode,
2838 + const_tree type ATTRIBUTE_UNUSED)
2840 + if (!use_vfp_abi (pcs_variant, false))
2843 + if (mode == BLKmode || (mode == TImode && !TARGET_NEON))
2851 + aapcs_vfp_is_call_or_return_candidate (pcs_variant, mode, type,
2852 + &ag_mode, &count);
2856 + if (ag_mode == V2SImode)
2858 + else if (ag_mode == V4SImode)
2864 + shift = GET_MODE_SIZE(ag_mode) / GET_MODE_SIZE(SFmode);
2865 + par = gen_rtx_PARALLEL (mode, rtvec_alloc (count));
2866 + for (i = 0; i < count; i++)
2868 + rtx tmp = gen_rtx_REG (ag_mode, FIRST_VFP_REGNUM + i * shift);
2869 + tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp,
2870 + GEN_INT (i * GET_MODE_SIZE (ag_mode)));
2871 + XVECEXP (par, 0, i) = tmp;
2877 + return gen_rtx_REG (mode, FIRST_VFP_REGNUM);
2881 +aapcs_vfp_advance (CUMULATIVE_ARGS *pcum ATTRIBUTE_UNUSED,
2882 + enum machine_mode mode ATTRIBUTE_UNUSED,
2883 + const_tree type ATTRIBUTE_UNUSED)
2885 + pcum->aapcs_vfp_regs_free &= ~pcum->aapcs_vfp_reg_alloc;
2886 + pcum->aapcs_vfp_reg_alloc = 0;
2890 +#define AAPCS_CP(X) \
2892 + aapcs_ ## X ## _cum_init, \
2893 + aapcs_ ## X ## _is_call_candidate, \
2894 + aapcs_ ## X ## _allocate, \
2895 + aapcs_ ## X ## _is_return_candidate, \
2896 + aapcs_ ## X ## _allocate_return_reg, \
2897 + aapcs_ ## X ## _advance \
2900 +/* Table of co-processors that can be used to pass arguments in
2901 + registers. Idealy no arugment should be a candidate for more than
2902 + one co-processor table entry, but the table is processed in order
2903 + and stops after the first match. If that entry then fails to put
2904 + the argument into a co-processor register, the argument will go on
2908 + /* Initialize co-processor related state in CUMULATIVE_ARGS structure. */
2909 + void (*cum_init) (CUMULATIVE_ARGS *, const_tree, rtx, const_tree);
2911 + /* Return true if an argument of mode MODE (or type TYPE if MODE is
2912 + BLKmode) is a candidate for this co-processor's registers; this
2913 + function should ignore any position-dependent state in
2914 + CUMULATIVE_ARGS and only use call-type dependent information. */
2915 + bool (*is_call_candidate) (CUMULATIVE_ARGS *, enum machine_mode, const_tree);
2917 + /* Return true if the argument does get a co-processor register; it
2918 + should set aapcs_reg to an RTX of the register allocated as is
2919 + required for a return from FUNCTION_ARG. */
2920 + bool (*allocate) (CUMULATIVE_ARGS *, enum machine_mode, const_tree);
2922 + /* Return true if a result of mode MODE (or type TYPE if MODE is
2923 + BLKmode) is can be returned in this co-processor's registers. */
2924 + bool (*is_return_candidate) (enum arm_pcs, enum machine_mode, const_tree);
2926 + /* Allocate and return an RTX element to hold the return type of a
2927 + call, this routine must not fail and will only be called if
2928 + is_return_candidate returned true with the same parameters. */
2929 + rtx (*allocate_return_reg) (enum arm_pcs, enum machine_mode, const_tree);
2931 + /* Finish processing this argument and prepare to start processing
2933 + void (*advance) (CUMULATIVE_ARGS *, enum machine_mode, const_tree);
2934 +} aapcs_cp_arg_layout[ARM_NUM_COPROC_SLOTS] =
2942 +aapcs_select_call_coproc (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
2947 + for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++)
2948 + if (aapcs_cp_arg_layout[i].is_call_candidate (pcum, mode, type))
2955 +aapcs_select_return_coproc (const_tree type, const_tree fntype)
2957 + /* We aren't passed a decl, so we can't check that a call is local.
2958 + However, it isn't clear that that would be a win anyway, since it
2959 + might limit some tail-calling opportunities. */
2960 + enum arm_pcs pcs_variant;
2964 + const_tree fndecl = NULL_TREE;
2966 + if (TREE_CODE (fntype) == FUNCTION_DECL)
2969 + fntype = TREE_TYPE (fntype);
2972 + pcs_variant = arm_get_pcs_model (fntype, fndecl);
2975 + pcs_variant = arm_pcs_default;
2977 + if (pcs_variant != ARM_PCS_AAPCS)
2981 + for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++)
2982 + if (aapcs_cp_arg_layout[i].is_return_candidate (pcs_variant,
2991 +aapcs_allocate_return_reg (enum machine_mode mode, const_tree type,
2992 + const_tree fntype)
2994 + /* We aren't passed a decl, so we can't check that a call is local.
2995 + However, it isn't clear that that would be a win anyway, since it
2996 + might limit some tail-calling opportunities. */
2997 + enum arm_pcs pcs_variant;
3001 + const_tree fndecl = NULL_TREE;
3003 + if (TREE_CODE (fntype) == FUNCTION_DECL)
3006 + fntype = TREE_TYPE (fntype);
3009 + pcs_variant = arm_get_pcs_model (fntype, fndecl);
3012 + pcs_variant = arm_pcs_default;
3014 + /* Promote integer types. */
3015 + if (type && INTEGRAL_TYPE_P (type))
3016 + PROMOTE_FUNCTION_MODE (mode, unsignedp, type);
3018 + if (pcs_variant != ARM_PCS_AAPCS)
3022 + for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++)
3023 + if (aapcs_cp_arg_layout[i].is_return_candidate (pcs_variant, mode,
3025 + return aapcs_cp_arg_layout[i].allocate_return_reg (pcs_variant,
3029 + /* Promotes small structs returned in a register to full-word size
3030 + for big-endian AAPCS. */
3031 + if (type && arm_return_in_msb (type))
3033 + HOST_WIDE_INT size = int_size_in_bytes (type);
3034 + if (size % UNITS_PER_WORD != 0)
3036 + size += UNITS_PER_WORD - size % UNITS_PER_WORD;
3037 + mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0);
3041 + return gen_rtx_REG (mode, R0_REGNUM);
3045 +aapcs_libcall_value (enum machine_mode mode)
3047 + return aapcs_allocate_return_reg (mode, NULL_TREE, NULL_TREE);
3050 +/* Lay out a function argument using the AAPCS rules. The rule
3051 + numbers referred to here are those in the AAPCS. */
3053 +aapcs_layout_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
3054 + tree type, int named)
3056 + int nregs, nregs2;
3059 + /* We only need to do this once per argument. */
3060 + if (pcum->aapcs_arg_processed)
3063 + pcum->aapcs_arg_processed = true;
3065 + /* Special case: if named is false then we are handling an incoming
3066 + anonymous argument which is on the stack. */
3070 + /* Is this a potential co-processor register candidate? */
3071 + if (pcum->pcs_variant != ARM_PCS_AAPCS)
3073 + int slot = aapcs_select_call_coproc (pcum, mode, type);
3074 + pcum->aapcs_cprc_slot = slot;
3076 + /* We don't have to apply any of the rules from part B of the
3077 + preparation phase, these are handled elsewhere in the
3082 + /* A Co-processor register candidate goes either in its own
3083 + class of registers or on the stack. */
3084 + if (!pcum->aapcs_cprc_failed[slot])
3086 + /* C1.cp - Try to allocate the argument to co-processor
3088 + if (aapcs_cp_arg_layout[slot].allocate (pcum, mode, type))
3091 + /* C2.cp - Put the argument on the stack and note that we
3092 + can't assign any more candidates in this slot. We also
3093 + need to note that we have allocated stack space, so that
3094 + we won't later try to split a non-cprc candidate between
3095 + core registers and the stack. */
3096 + pcum->aapcs_cprc_failed[slot] = true;
3097 + pcum->can_split = false;
3100 + /* We didn't get a register, so this argument goes on the
3102 + gcc_assert (pcum->can_split == false);
3107 + /* C3 - For double-word aligned arguments, round the NCRN up to the
3108 + next even number. */
3109 + ncrn = pcum->aapcs_ncrn;
3110 + if ((ncrn & 1) && arm_needs_doubleword_align (mode, type))
3113 + nregs = ARM_NUM_REGS2(mode, type);
3115 + /* Sigh, this test should really assert that nregs > 0, but a GCC
3116 + extension allows empty structs and then gives them empty size; it
3117 + then allows such a structure to be passed by value. For some of
3118 + the code below we have to pretend that such an argument has
3119 + non-zero size so that we 'locate' it correctly either in
3120 + registers or on the stack. */
3121 + gcc_assert (nregs >= 0);
3123 + nregs2 = nregs ? nregs : 1;
3125 + /* C4 - Argument fits entirely in core registers. */
3126 + if (ncrn + nregs2 <= NUM_ARG_REGS)
3128 + pcum->aapcs_reg = gen_rtx_REG (mode, ncrn);
3129 + pcum->aapcs_next_ncrn = ncrn + nregs;
3133 + /* C5 - Some core registers left and there are no arguments already
3134 + on the stack: split this argument between the remaining core
3135 + registers and the stack. */
3136 + if (ncrn < NUM_ARG_REGS && pcum->can_split)
3138 + pcum->aapcs_reg = gen_rtx_REG (mode, ncrn);
3139 + pcum->aapcs_next_ncrn = NUM_ARG_REGS;
3140 + pcum->aapcs_partial = (NUM_ARG_REGS - ncrn) * UNITS_PER_WORD;
3144 + /* C6 - NCRN is set to 4. */
3145 + pcum->aapcs_next_ncrn = NUM_ARG_REGS;
3147 + /* C7,C8 - arugment goes on the stack. We have nothing to do here. */
3151 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3152 for a call to a function whose data type is FNTYPE.
3153 For a library call, FNTYPE is NULL. */
3155 arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype,
3156 - rtx libname ATTRIBUTE_UNUSED,
3158 tree fndecl ATTRIBUTE_UNUSED)
3160 + /* Long call handling. */
3162 + pcum->pcs_variant = arm_get_pcs_model (fntype, fndecl);
3164 + pcum->pcs_variant = arm_pcs_default;
3166 + if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL)
3168 + /* XXX We should also detect some library calls here and handle
3169 + them using the base rules too; for example the floating point
3170 + support functions always work this way. */
3172 + if (rtx_equal_p (libname,
3173 + convert_optab_libfunc (sfix_optab, DImode, DFmode))
3174 + || rtx_equal_p (libname,
3175 + convert_optab_libfunc (ufix_optab, DImode, DFmode))
3176 + || rtx_equal_p (libname,
3177 + convert_optab_libfunc (sfix_optab, DImode, SFmode))
3178 + || rtx_equal_p (libname,
3179 + convert_optab_libfunc (ufix_optab, DImode, SFmode))
3180 + || rtx_equal_p (libname,
3181 + convert_optab_libfunc (trunc_optab, HFmode, SFmode))
3182 + || rtx_equal_p (libname,
3183 + convert_optab_libfunc (sext_optab, SFmode, HFmode)))
3184 + pcum->pcs_variant = ARM_PCS_AAPCS;
3186 + pcum->aapcs_ncrn = pcum->aapcs_next_ncrn = 0;
3187 + pcum->aapcs_reg = NULL_RTX;
3188 + pcum->aapcs_partial = 0;
3189 + pcum->aapcs_arg_processed = false;
3190 + pcum->aapcs_cprc_slot = -1;
3191 + pcum->can_split = true;
3193 + if (pcum->pcs_variant != ARM_PCS_AAPCS)
3197 + for (i = 0; i < ARM_NUM_COPROC_SLOTS; i++)
3199 + pcum->aapcs_cprc_failed[i] = false;
3200 + aapcs_cp_arg_layout[i].cum_init (pcum, fntype, libname, fndecl);
3208 /* On the ARM, the offset starts at 0. */
3210 pcum->iwmmxt_nregs = 0;
3211 @@ -3131,6 +4201,17 @@ arm_function_arg (CUMULATIVE_ARGS *pcum,
3215 + /* Handle the special case quickly. Pick an arbitrary value for op2 of
3216 + a call insn (op3 of a call_value insn). */
3217 + if (mode == VOIDmode)
3218 + return const0_rtx;
3220 + if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL)
3222 + aapcs_layout_arg (pcum, mode, type, named);
3223 + return pcum->aapcs_reg;
3226 /* Varargs vectors are treated the same as long long.
3227 named_count avoids having to change the way arm handles 'named' */
3228 if (TARGET_IWMMXT_ABI
3229 @@ -3172,10 +4253,16 @@ arm_function_arg (CUMULATIVE_ARGS *pcum,
3232 arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
3233 - tree type, bool named ATTRIBUTE_UNUSED)
3234 + tree type, bool named)
3236 int nregs = pcum->nregs;
3238 + if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL)
3240 + aapcs_layout_arg (pcum, mode, type, named);
3241 + return pcum->aapcs_partial;
3244 if (TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (mode))
3247 @@ -3184,7 +4271,40 @@ arm_arg_partial_bytes (CUMULATIVE_ARGS *
3249 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
3256 +arm_function_arg_advance (CUMULATIVE_ARGS *pcum, enum machine_mode mode,
3257 + tree type, bool named)
3259 + if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL)
3261 + aapcs_layout_arg (pcum, mode, type, named);
3263 + if (pcum->aapcs_cprc_slot >= 0)
3265 + aapcs_cp_arg_layout[pcum->aapcs_cprc_slot].advance (pcum, mode,
3267 + pcum->aapcs_cprc_slot = -1;
3270 + /* Generic stuff. */
3271 + pcum->aapcs_arg_processed = false;
3272 + pcum->aapcs_ncrn = pcum->aapcs_next_ncrn;
3273 + pcum->aapcs_reg = NULL_RTX;
3274 + pcum->aapcs_partial = 0;
3279 + if (arm_vector_mode_supported_p (mode)
3280 + && pcum->named_count > pcum->nargs
3281 + && TARGET_IWMMXT_ABI)
3282 + pcum->iwmmxt_nregs += 1;
3284 + pcum->nregs += ARM_NUM_REGS2 (mode, type);
3288 /* Variable sized types are passed by reference. This is a GCC
3289 @@ -3237,6 +4357,8 @@ const struct attribute_spec arm_attribut
3290 /* Whereas these functions are always known to reside within the 26 bit
3291 addressing range. */
3292 { "short_call", 0, 0, false, true, true, NULL },
3293 + /* Specify the procedure call conventions for a function. */
3294 + { "pcs", 1, 1, false, true, true, arm_handle_pcs_attribute },
3295 /* Interrupt Service Routines have special prologue and epilogue requirements. */
3296 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute },
3297 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute },
3298 @@ -3339,6 +4461,21 @@ arm_handle_isr_attribute (tree *node, tr
3302 +/* Handle a "pcs" attribute; arguments as in struct
3303 + attribute_spec.handler. */
3305 +arm_handle_pcs_attribute (tree *node ATTRIBUTE_UNUSED, tree name, tree args,
3306 + int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
3308 + if (arm_pcs_from_attribute (args) == ARM_PCS_UNKNOWN)
3310 + warning (OPT_Wattributes, "%qs attribute ignored",
3311 + IDENTIFIER_POINTER (name));
3312 + *no_add_attrs = true;
3317 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
3318 /* Handle the "notshared" attribute. This attribute is another way of
3319 requesting hidden visibility. ARM's compiler supports
3320 @@ -3500,7 +4637,7 @@ arm_is_long_call_p (tree decl)
3322 /* Return nonzero if it is ok to make a tail-call to DECL. */
3324 -arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
3325 +arm_function_ok_for_sibcall (tree decl, tree exp)
3327 unsigned long func_type;
3329 @@ -3533,6 +4670,21 @@ arm_function_ok_for_sibcall (tree decl,
3330 if (IS_INTERRUPT (func_type))
3333 + if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
3335 + /* Check that the return value locations are the same. For
3336 + example that we aren't returning a value from the sibling in
3337 + a VFP register but then need to transfer it to a core
3341 + a = arm_function_value (TREE_TYPE (exp), decl, false);
3342 + b = arm_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)),
3343 + cfun->decl, false);
3344 + if (!rtx_equal_p (a, b))
3348 /* Never tailcall if function may be called with a misaligned SP. */
3349 if (IS_STACKALIGN (func_type))
3351 @@ -4131,6 +5283,7 @@ arm_legitimate_index_p (enum machine_mod
3352 if (GET_MODE_SIZE (mode) <= 4
3356 || (mode == QImode && outer == SIGN_EXTEND))))
3359 @@ -4159,13 +5312,15 @@ arm_legitimate_index_p (enum machine_mod
3363 - if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode))
3364 + if (mode == HImode
3366 + || (outer == SIGN_EXTEND && mode == QImode))
3372 - range = (mode == HImode) ? 4095 : 4096;
3373 + range = (mode == HImode || mode == HFmode) ? 4095 : 4096;
3375 return (code == CONST_INT
3376 && INTVAL (index) < range
3377 @@ -4336,7 +5491,8 @@ thumb1_legitimate_address_p (enum machin
3380 /* This is PC relative data after arm_reorg runs. */
3381 - else if (GET_MODE_SIZE (mode) >= 4 && reload_completed
3382 + else if ((GET_MODE_SIZE (mode) >= 4 || mode == HFmode)
3383 + && reload_completed
3384 && (GET_CODE (x) == LABEL_REF
3385 || (GET_CODE (x) == CONST
3386 && GET_CODE (XEXP (x, 0)) == PLUS
3387 @@ -5035,7 +6191,7 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou
3389 if (TARGET_HARD_FLOAT && mode == SFmode)
3390 *total = COSTS_N_INSNS (2);
3391 - else if (TARGET_HARD_FLOAT && mode == DFmode)
3392 + else if (TARGET_HARD_FLOAT && mode == DFmode && !TARGET_VFP_SINGLE)
3393 *total = COSTS_N_INSNS (4);
3395 *total = COSTS_N_INSNS (20);
3396 @@ -5074,23 +6230,6 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou
3400 - if (TARGET_THUMB2)
3402 - if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3404 - if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode))
3405 - *total = COSTS_N_INSNS (1);
3407 - *total = COSTS_N_INSNS (20);
3410 - *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
3411 - /* Thumb2 does not have RSB, so all arguments must be
3412 - registers (subtracting a constant is canonicalized as
3413 - addition of the negated constant). */
3419 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode));
3420 @@ -5113,7 +6252,9 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou
3422 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3424 - if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode))
3425 + if (TARGET_HARD_FLOAT
3426 + && (mode == SFmode
3427 + || (mode == DFmode && !TARGET_VFP_SINGLE)))
3429 *total = COSTS_N_INSNS (1);
3430 if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
3431 @@ -5154,6 +6295,17 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou
3435 + /* A shift as a part of RSB costs no more than RSB itself. */
3436 + if (GET_CODE (XEXP (x, 0)) == MULT
3437 + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3438 + && ((INTVAL (XEXP (XEXP (x, 0), 1))
3439 + & (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0))
3441 + *total += rtx_cost (XEXP (XEXP (x, 0), 0), code, speed);
3442 + *total += rtx_cost (XEXP (x, 1), code, speed);
3447 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3448 && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3449 @@ -5175,6 +6327,19 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou
3453 + /* MLS is just as expensive as its underlying multiplication.
3454 + Exclude a shift by a constant, which is expressed as a
3455 + multiplication. */
3456 + if (TARGET_32BIT && arm_arch_thumb2
3457 + && GET_CODE (XEXP (x, 1)) == MULT
3458 + && ! (GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3459 + && ((INTVAL (XEXP (XEXP (x, 1), 1)) &
3460 + (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0)))
3462 + /* The cost comes from the cost of the multiply. */
3469 @@ -5203,7 +6368,9 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou
3471 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3473 - if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode))
3474 + if (TARGET_HARD_FLOAT
3475 + && (mode == SFmode
3476 + || (mode == DFmode && !TARGET_VFP_SINGLE)))
3478 *total = COSTS_N_INSNS (1);
3479 if (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE
3480 @@ -5318,7 +6485,9 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou
3482 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3484 - if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode))
3485 + if (TARGET_HARD_FLOAT
3486 + && (mode == SFmode
3487 + || (mode == DFmode && !TARGET_VFP_SINGLE)))
3489 *total = COSTS_N_INSNS (1);
3491 @@ -5471,7 +6640,9 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou
3493 if (GET_MODE_CLASS (mode == MODE_FLOAT))
3495 - if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode))
3496 + if (TARGET_HARD_FLOAT
3497 + && (mode == SFmode
3498 + || (mode == DFmode && !TARGET_VFP_SINGLE)))
3500 *total = COSTS_N_INSNS (1);
3502 @@ -5574,7 +6745,8 @@ arm_rtx_costs_1 (rtx x, enum rtx_code ou
3506 - if (TARGET_HARD_FLOAT && vfp3_const_double_rtx (x))
3507 + if (TARGET_HARD_FLOAT && vfp3_const_double_rtx (x)
3508 + && (mode == SFmode || !TARGET_VFP_SINGLE))
3509 *total = COSTS_N_INSNS (1);
3511 *total = COSTS_N_INSNS (4);
3512 @@ -5649,7 +6821,8 @@ arm_size_rtx_costs (rtx x, enum rtx_code
3516 - if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
3517 + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
3518 + && (mode == SFmode || !TARGET_VFP_SINGLE))
3520 *total = COSTS_N_INSNS (1);
3522 @@ -5679,7 +6852,8 @@ arm_size_rtx_costs (rtx x, enum rtx_code
3526 - if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
3527 + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
3528 + && (mode == SFmode || !TARGET_VFP_SINGLE))
3530 *total = COSTS_N_INSNS (1);
3532 @@ -5709,7 +6883,8 @@ arm_size_rtx_costs (rtx x, enum rtx_code
3536 - if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
3537 + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
3538 + && (mode == SFmode || !TARGET_VFP_SINGLE))
3540 *total = COSTS_N_INSNS (1);
3542 @@ -5733,7 +6908,8 @@ arm_size_rtx_costs (rtx x, enum rtx_code
3546 - if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
3547 + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT
3548 + && (mode == SFmode || !TARGET_VFP_SINGLE))
3549 *total = COSTS_N_INSNS (1);
3551 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode));
3552 @@ -5950,7 +7126,9 @@ arm_fastmul_rtx_costs (rtx x, enum rtx_c
3554 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3556 - if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode))
3557 + if (TARGET_HARD_FLOAT
3558 + && (mode == SFmode
3559 + || (mode == DFmode && !TARGET_VFP_SINGLE)))
3561 *total = COSTS_N_INSNS (1);
3563 @@ -6107,7 +7285,9 @@ arm_9e_rtx_costs (rtx x, enum rtx_code c
3565 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
3567 - if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode))
3568 + if (TARGET_HARD_FLOAT
3569 + && (mode == SFmode
3570 + || (mode == DFmode && !TARGET_VFP_SINGLE)))
3572 *total = COSTS_N_INSNS (1);
3574 @@ -6930,10 +8110,13 @@ arm_coproc_mem_operand (rtx op, bool wb)
3577 /* Return TRUE if OP is a memory operand which we can load or store a vector
3578 - to/from. If CORE is true, we're moving from ARM registers not Neon
3580 + to/from. TYPE is one of the following values:
3581 + 0 - Vector load/stor (vldr)
3582 + 1 - Core registers (ldm)
3583 + 2 - Element/structure loads (vld1)
3586 -neon_vector_mem_operand (rtx op, bool core)
3587 +neon_vector_mem_operand (rtx op, int type)
3591 @@ -6966,23 +8149,16 @@ neon_vector_mem_operand (rtx op, bool co
3592 return arm_address_register_rtx_p (ind, 0);
3594 /* Allow post-increment with Neon registers. */
3595 - if (!core && GET_CODE (ind) == POST_INC)
3596 + if ((type != 1 && GET_CODE (ind) == POST_INC)
3597 + || (type == 0 && GET_CODE (ind) == PRE_DEC))
3598 return arm_address_register_rtx_p (XEXP (ind, 0), 0);
3601 - /* FIXME: We can support this too if we use VLD1/VST1. */
3603 - && GET_CODE (ind) == POST_MODIFY
3604 - && arm_address_register_rtx_p (XEXP (ind, 0), 0)
3605 - && GET_CODE (XEXP (ind, 1)) == PLUS
3606 - && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0)))
3607 - ind = XEXP (ind, 1);
3609 + /* FIXME: vld1 allows register post-modify. */
3616 && GET_CODE (ind) == PLUS
3617 && GET_CODE (XEXP (ind, 0)) == REG
3618 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
3619 @@ -7049,10 +8225,19 @@ arm_eliminable_register (rtx x)
3621 coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb)
3623 + if (mode == HFmode)
3625 + if (!TARGET_NEON_FP16)
3626 + return GENERAL_REGS;
3627 + if (s_register_operand (x, mode) || neon_vector_mem_operand (x, 2))
3629 + return GENERAL_REGS;
3633 && (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
3634 || GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
3635 - && neon_vector_mem_operand (x, FALSE))
3636 + && neon_vector_mem_operand (x, 0))
3639 if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode))
3640 @@ -7449,6 +8634,9 @@ load_multiple_sequence (rtx *operands, i
3644 + if (low_irq_latency)
3647 /* Can only handle 2, 3, or 4 insns at present,
3648 though could be easily extended if required. */
3649 gcc_assert (nops >= 2 && nops <= 4);
3650 @@ -7678,6 +8866,9 @@ store_multiple_sequence (rtx *operands,
3654 + if (low_irq_latency)
3657 /* Can only handle 2, 3, or 4 insns at present, though could be easily
3658 extended if required. */
3659 gcc_assert (nops >= 2 && nops <= 4);
3660 @@ -7885,7 +9076,7 @@ arm_gen_load_multiple (int base_regno, i
3662 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
3663 for counts of 3 or 4 regs. */
3664 - if (arm_tune_xscale && count <= 2 && ! optimize_size)
3665 + if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size))
3669 @@ -7948,7 +9139,7 @@ arm_gen_store_multiple (int base_regno,
3671 /* See arm_gen_load_multiple for discussion of
3672 the pros/cons of ldm/stm usage for XScale. */
3673 - if (arm_tune_xscale && count <= 2 && ! optimize_size)
3674 + if (low_irq_latency || (arm_tune_xscale && count <= 2 && ! optimize_size))
3678 @@ -9566,7 +10757,10 @@ create_fix_barrier (Mfix *fix, HOST_WIDE
3679 gcc_assert (GET_CODE (from) != BARRIER);
3681 /* Count the length of this insn. */
3682 - count += get_attr_length (from);
3683 + if (LABEL_P (from) && (align_jumps > 0 || align_loops > 0))
3684 + count += MAX (align_jumps, align_loops);
3686 + count += get_attr_length (from);
3688 /* If there is a jump table, add its length. */
3689 tmp = is_jump_table (from);
3690 @@ -9878,6 +11072,8 @@ arm_reorg (void)
3694 + else if (LABEL_P (insn) && (align_jumps > 0 || align_loops > 0))
3695 + address += MAX (align_jumps, align_loops);
3698 fix = minipool_fix_head;
3699 @@ -10083,6 +11279,21 @@ static void
3700 vfp_output_fldmd (FILE * stream, unsigned int base, int reg, int count)
3705 + if (low_irq_latency)
3707 + /* Output a sequence of FLDD instructions. */
3709 + for (i = reg; i < reg + count; ++i, offset += 8)
3711 + fputc ('\t', stream);
3712 + asm_fprintf (stream, "fldd\td%d, [%r,#%d]\n", i, base, offset);
3714 + asm_fprintf (stream, "\tadd\tsp, sp, #%d\n", count * 8);
3719 /* Workaround ARM10 VFPr1 bug. */
3720 if (count == 2 && !arm_arch6)
3721 @@ -10153,6 +11364,56 @@ vfp_emit_fstmd (int base_reg, int count)
3725 + if (low_irq_latency)
3733 + saved_size = count * GET_MODE_SIZE (DFmode);
3735 + /* Since fstd does not have postdecrement addressing mode,
3736 + we first decrement stack pointer and then use base+offset
3737 + stores for VFP registers. The ARM EABI unwind information
3738 + can't easily describe base+offset loads, so we attach
3739 + a note for the effects of the whole block in the first insn,
3740 + and avoid marking the subsequent instructions
3741 + with RTX_FRAME_RELATED_P. */
3742 + sp_insn = gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
3743 + GEN_INT (-saved_size));
3744 + sp_insn = emit_insn (sp_insn);
3745 + RTX_FRAME_RELATED_P (sp_insn) = 1;
3747 + dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1));
3748 + XVECEXP (dwarf, 0, 0) =
3749 + gen_rtx_SET (VOIDmode, stack_pointer_rtx,
3750 + plus_constant (stack_pointer_rtx, -saved_size));
3752 + /* push double VFP registers to stack */
3753 + for (i = 0; i < count; ++i )
3759 + reg = gen_rtx_REG (DFmode, base_reg + 2*i);
3760 + addr = (i == 0) ? stack_pointer_rtx
3761 + : gen_rtx_PLUS (SImode, stack_pointer_rtx,
3762 + GEN_INT (i * GET_MODE_SIZE (DFmode)));
3763 + mem = gen_frame_mem (DFmode, addr);
3764 + insn = emit_move_insn (mem, reg);
3765 + XVECEXP (dwarf, 0, i+1) =
3766 + gen_rtx_SET (VOIDmode, mem, reg);
3769 + REG_NOTES (sp_insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
3770 + REG_NOTES (sp_insn));
3772 + return saved_size;
3775 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two
3776 register pairs are stored by a store multiple insn. We avoid this
3777 by pushing an extra pair. */
3778 @@ -10769,7 +12030,7 @@ output_move_double (rtx *operands)
3781 /* Output a move, load or store for quad-word vectors in ARM registers. Only
3782 - handles MEMs accepted by neon_vector_mem_operand with CORE=true. */
3783 + handles MEMs accepted by neon_vector_mem_operand with TYPE=1. */
3786 output_move_quad (rtx *operands)
3787 @@ -10965,6 +12226,12 @@ output_move_neon (rtx *operands)
3792 + templ = "v%smdb%%?\t%%0!, %%h1";
3793 + ops[0] = XEXP (addr, 0);
3798 /* FIXME: Not currently enabled in neon_vector_mem_operand. */
3800 @@ -11568,7 +12835,7 @@ arm_get_vfp_saved_size (void)
3803 /* Workaround ARM10 VFPr1 bug. */
3804 - if (count == 2 && !arm_arch6)
3805 + if (count == 2 && !arm_arch6 && !low_irq_latency)
3809 @@ -11897,6 +13164,41 @@ arm_output_function_prologue (FILE *f, H
3810 return_used_this_function = 0;
3813 +/* Generate to STREAM a code sequence that pops registers identified
3814 + in REGS_MASK from SP. SP is incremented as the result.
3817 +print_pop_reg_by_ldr (FILE *stream, int regs_mask, int rfe)
3821 + gcc_assert (! (regs_mask & (1 << SP_REGNUM)));
3823 + for (reg = 0; reg < PC_REGNUM; ++reg)
3824 + if (regs_mask & (1 << reg))
3825 + asm_fprintf (stream, "\tldr\t%r, [%r], #4\n",
3828 + if (regs_mask & (1 << PC_REGNUM))
3831 + /* When returning from exception, we need to
3832 + copy SPSR to CPSR. There are two ways to do
3833 + that: the ldm instruction with "^" suffix,
3834 + and movs instruction. The latter would
3835 + require that we load from stack to some
3836 + scratch register, and then move to PC.
3837 + Therefore, we'd need extra instruction and
3838 + have to make sure we actually have a spare
3839 + register. Using ldm with a single register
3841 + asm_fprintf (stream, "\tldm\tsp!, {pc}^\n");
3843 + asm_fprintf (stream, "\tldr\t%r, [%r], #4\n",
3844 + PC_REGNUM, SP_REGNUM);
3849 arm_output_epilogue (rtx sibling)
3851 @@ -11957,7 +13259,7 @@ arm_output_epilogue (rtx sibling)
3852 /* This variable is for the Virtual Frame Pointer, not VFP regs. */
3853 int vfp_offset = offsets->frame;
3855 - if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
3856 + if (TARGET_FPA_EMU2)
3858 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
3859 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
3860 @@ -12180,7 +13482,7 @@ arm_output_epilogue (rtx sibling)
3861 SP_REGNUM, HARD_FRAME_POINTER_REGNUM);
3864 - if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
3865 + if (TARGET_FPA_EMU2)
3867 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++)
3868 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
3869 @@ -12264,22 +13566,19 @@ arm_output_epilogue (rtx sibling)
3870 to load use the LDR instruction - it is faster. For Thumb-2
3871 always use pop and the assembler will pick the best instruction.*/
3872 if (TARGET_ARM && saved_regs_mask == (1 << LR_REGNUM)
3873 - && !IS_INTERRUPT(func_type))
3874 + && !IS_INTERRUPT (func_type))
3876 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM);
3878 else if (saved_regs_mask)
3880 - if (saved_regs_mask & (1 << SP_REGNUM))
3881 - /* Note - write back to the stack register is not enabled
3882 - (i.e. "ldmfd sp!..."). We know that the stack pointer is
3883 - in the list of registers and if we add writeback the
3884 - instruction becomes UNPREDICTABLE. */
3885 - print_multi_reg (f, "ldmfd\t%r, ", SP_REGNUM, saved_regs_mask,
3887 - else if (TARGET_ARM)
3888 - print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask,
3890 + gcc_assert ( ! (saved_regs_mask & (1 << SP_REGNUM)));
3892 + if (low_irq_latency)
3893 + print_pop_reg_by_ldr (f, saved_regs_mask, rfe);
3895 + print_multi_reg (f, "ldmfd\t%r!, ", SP_REGNUM, saved_regs_mask,
3898 print_multi_reg (f, "pop\t", SP_REGNUM, saved_regs_mask, 0);
3900 @@ -12400,6 +13699,32 @@ emit_multi_reg_push (unsigned long mask)
3902 gcc_assert (num_regs && num_regs <= 16);
3904 + if (low_irq_latency)
3908 + /* Emit a series of ldr instructions rather rather than a single ldm. */
3909 + /* TODO: Use ldrd where possible. */
3910 + gcc_assert (! (mask & (1 << SP_REGNUM)));
3912 + for (i = LAST_ARM_REGNUM; i >= 0; --i)
3914 + if (mask & (1 << i))
3917 + rtx reg, where, mem;
3919 + reg = gen_rtx_REG (SImode, i);
3920 + where = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx);
3921 + mem = gen_rtx_MEM (SImode, where);
3922 + insn = emit_move_insn (mem, reg);
3923 + RTX_FRAME_RELATED_P (insn) = 1;
3930 /* We don't record the PC in the dwarf frame information. */
3931 num_dwarf_regs = num_regs;
3932 if (mask & (1 << PC_REGNUM))
3933 @@ -12748,22 +14073,23 @@ arm_get_frame_offsets (void)
3937 - for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++)
3939 - if ((offsets->saved_regs_mask & (1 << i)) == 0)
3946 - if (reg == -1 && arm_size_return_regs () <= 12
3947 - && !crtl->tail_call_emit)
3948 + /* If it is safe to use r3, then do so. This sometimes
3949 + generates better code on Thumb-2 by avoiding the need to
3950 + use 32-bit push/pop instructions. */
3951 + if (!crtl->tail_call_emit
3952 + && arm_size_return_regs () <= 12)
3954 - /* Push/pop an argument register (r3) if all callee saved
3955 - registers are already being pushed. */
3959 + for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++)
3961 + if ((offsets->saved_regs_mask & (1 << i)) == 0)
3970 @@ -12887,7 +14213,7 @@ arm_save_coproc_regs(void)
3972 /* Save any floating point call-saved registers used by this
3974 - if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
3975 + if (TARGET_FPA_EMU2)
3977 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--)
3978 if (df_regs_ever_live_p (reg) && !call_used_regs[reg])
3979 @@ -13494,7 +14820,11 @@ arm_print_operand (FILE *stream, rtx x,
3981 fprintf (stream, ", %s ", shift);
3983 - arm_print_operand (stream, XEXP (x, 1), 0);
3985 + arm_print_operand (stream, XEXP (x, 1), 0);
3987 + fprintf(stream, "\n\tnop");
3990 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val);
3992 @@ -13715,6 +15045,30 @@ arm_print_operand (FILE *stream, rtx x,
3996 + /* Print the high single-precision register of a VFP double-precision
4000 + int mode = GET_MODE (x);
4003 + if (GET_MODE_SIZE (mode) != 8 || GET_CODE (x) != REG)
4005 + output_operand_lossage ("invalid operand for code '%c'", code);
4009 + regno = REGNO (x);
4010 + if (!VFP_REGNO_OK_FOR_DOUBLE (regno))
4012 + output_operand_lossage ("invalid operand for code '%c'", code);
4016 + fprintf (stream, "s%d", regno - FIRST_VFP_REGNUM + 1);
4020 /* Print a VFP/Neon double precision or quad precision register name. */
4023 @@ -13832,6 +15186,57 @@ arm_print_operand (FILE *stream, rtx x,
4027 + /* Memory operand for vld1/vst1 instruction. */
4031 + bool postinc = FALSE;
4034 + gcc_assert (GET_CODE (x) == MEM);
4035 + addr = XEXP (x, 0);
4036 + if (GET_CODE (addr) == POST_INC)
4039 + addr = XEXP (addr, 0);
4041 + align = MEM_ALIGN (x) >> 3;
4042 + asm_fprintf (stream, "[%r", REGNO (addr));
4043 + if (align > GET_MODE_SIZE (GET_MODE (x)))
4044 + align = GET_MODE_SIZE (GET_MODE (x));
4046 + asm_fprintf (stream, ", :%d", align << 3);
4047 + asm_fprintf (stream, "]");
4049 + fputs("!", stream);
4053 + /* Register specifier for vld1.16/vst1.16. Translate the S register
4054 + number into a D register number and element index. */
4057 + int mode = GET_MODE (x);
4060 + if (GET_MODE_SIZE (mode) != 2 || GET_CODE (x) != REG)
4062 + output_operand_lossage ("invalid operand for code '%c'", code);
4066 + regno = REGNO (x);
4067 + if (!VFP_REGNO_OK_FOR_SINGLE (regno))
4069 + output_operand_lossage ("invalid operand for code '%c'", code);
4073 + regno = regno - FIRST_VFP_REGNUM;
4074 + fprintf (stream, "d%d[%d]", regno/2, ((regno % 2) ? 2 : 0));
4081 @@ -13865,6 +15270,12 @@ arm_print_operand (FILE *stream, rtx x,
4083 gcc_assert (GET_CODE (x) != NEG);
4084 fputc ('#', stream);
4085 + if (GET_CODE (x) == HIGH)
4087 + fputs (":lower16:", stream);
4091 output_addr_const (stream, x);
4094 @@ -14256,6 +15667,10 @@ arm_final_prescan_insn (rtx insn)
4095 first insn after the following code_label if REVERSE is true. */
4096 rtx start_insn = insn;
4098 + /* Don't do this if we're not considering conditional execution. */
4099 + if (TARGET_NO_SINGLE_COND_EXEC)
4102 /* If in state 4, check if the target branch is reached, in order to
4103 change back to state 0. */
4104 if (arm_ccfsm_state == 4)
4105 @@ -14629,6 +16044,11 @@ arm_hard_regno_mode_ok (unsigned int reg
4107 return VFP_REGNO_OK_FOR_DOUBLE (regno);
4109 + /* VFP registers can hold HFmode values, but there is no point in
4110 + putting them there unless we have hardware conversion insns. */
4111 + if (mode == HFmode)
4112 + return TARGET_FP16 && VFP_REGNO_OK_FOR_SINGLE (regno);
4115 return (VALID_NEON_DREG_MODE (mode) && VFP_REGNO_OK_FOR_DOUBLE (regno))
4116 || (VALID_NEON_QREG_MODE (mode)
4117 @@ -14648,16 +16068,16 @@ arm_hard_regno_mode_ok (unsigned int reg
4118 return mode == SImode;
4120 if (IS_IWMMXT_REGNUM (regno))
4121 - return VALID_IWMMXT_REG_MODE (mode);
4122 + return VALID_IWMMXT_REG_MODE (mode) && mode != SImode;
4125 - /* We allow any value to be stored in the general registers.
4126 + /* We allow almost any value to be stored in the general registers.
4127 Restrict doubleword quantities to even register pairs so that we can
4128 - use ldrd. Do not allow Neon structure opaque modes in general registers;
4129 - they would use too many. */
4130 + use ldrd. Do not allow very large Neon structure opaque modes in
4131 + general registers; they would use too many. */
4132 if (regno <= LAST_ARM_REGNUM)
4133 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0)
4134 - && !VALID_NEON_STRUCT_MODE (mode);
4135 + && ARM_NUM_REGS (mode) <= 4;
4137 if (regno == FRAME_POINTER_REGNUM
4138 || regno == ARG_POINTER_REGNUM)
4139 @@ -16114,6 +17534,15 @@ arm_init_neon_builtins (void)
4143 +arm_init_fp16_builtins (void)
4145 + tree fp16_type = make_node (REAL_TYPE);
4146 + TYPE_PRECISION (fp16_type) = 16;
4147 + layout_type (fp16_type);
4148 + (*lang_hooks.types.register_builtin_type) (fp16_type, "__fp16");
4152 arm_init_builtins (void)
4154 arm_init_tls_builtins ();
4155 @@ -16123,6 +17552,71 @@ arm_init_builtins (void)
4158 arm_init_neon_builtins ();
4160 + if (arm_fp16_format)
4161 + arm_init_fp16_builtins ();
4164 +/* Implement TARGET_INVALID_PARAMETER_TYPE. */
4166 +static const char *
4167 +arm_invalid_parameter_type (const_tree t)
4169 + if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16)
4170 + return N_("function parameters cannot have __fp16 type");
4174 +/* Implement TARGET_INVALID_PARAMETER_TYPE. */
4176 +static const char *
4177 +arm_invalid_return_type (const_tree t)
4179 + if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16)
4180 + return N_("functions cannot return __fp16 type");
4184 +/* Implement TARGET_PROMOTED_TYPE. */
4187 +arm_promoted_type (const_tree t)
4189 + if (SCALAR_FLOAT_TYPE_P (t) && TYPE_PRECISION (t) == 16)
4190 + return float_type_node;
4194 +/* Implement TARGET_CONVERT_TO_TYPE.
4195 + Specifically, this hook implements the peculiarity of the ARM
4196 + half-precision floating-point C semantics that requires conversions between
4197 + __fp16 to or from double to do an intermediate conversion to float. */
4200 +arm_convert_to_type (tree type, tree expr)
4202 + tree fromtype = TREE_TYPE (expr);
4203 + if (!SCALAR_FLOAT_TYPE_P (fromtype) || !SCALAR_FLOAT_TYPE_P (type))
4205 + if ((TYPE_PRECISION (fromtype) == 16 && TYPE_PRECISION (type) > 32)
4206 + || (TYPE_PRECISION (type) == 16 && TYPE_PRECISION (fromtype) > 32))
4207 + return convert (type, convert (float_type_node, expr));
4211 +/* Implement TARGET_SCALAR_MODE_SUPPORTED_P.
4212 + This simply adds HFmode as a supported mode; even though we don't
4213 + implement arithmetic on this type directly, it's supported by
4214 + optabs conversions, much the way the double-word arithmetic is
4215 + special-cased in the default hook. */
4218 +arm_scalar_mode_supported_p (enum machine_mode mode)
4220 + if (mode == HFmode)
4221 + return (arm_fp16_format != ARM_FP16_FORMAT_NONE);
4223 + return default_scalar_mode_supported_p (mode);
4226 /* Errors in the source file can cause expand_expr to return const0_rtx
4227 @@ -17202,6 +18696,7 @@ thumb_shiftable_const (unsigned HOST_WID
4228 unsigned HOST_WIDE_INT mask = 0xff;
4231 + val = val & (unsigned HOST_WIDE_INT)0xffffffffu;
4232 if (val == 0) /* XXX */
4235 @@ -18290,40 +19785,8 @@ arm_file_start (void)
4238 int set_float_abi_attributes = 0;
4239 - switch (arm_fpu_arch)
4244 - case FPUTYPE_FPA_EMU2:
4245 - fpu_name = "fpe2";
4247 - case FPUTYPE_FPA_EMU3:
4248 - fpu_name = "fpe3";
4250 - case FPUTYPE_MAVERICK:
4251 - fpu_name = "maverick";
4255 - set_float_abi_attributes = 1;
4257 - case FPUTYPE_VFP3D16:
4258 - fpu_name = "vfpv3-d16";
4259 - set_float_abi_attributes = 1;
4261 - case FPUTYPE_VFP3:
4262 - fpu_name = "vfpv3";
4263 - set_float_abi_attributes = 1;
4265 - case FPUTYPE_NEON:
4266 - fpu_name = "neon";
4267 - set_float_abi_attributes = 1;
4272 - if (set_float_abi_attributes)
4273 + fpu_name = arm_fpu_desc->name;
4274 + if (arm_fp_model == ARM_FP_MODEL_VFP)
4276 if (TARGET_HARD_FLOAT)
4277 asm_fprintf (asm_out_file, "\t.eabi_attribute 27, 3\n");
4278 @@ -18373,6 +19836,11 @@ arm_file_start (void)
4280 asm_fprintf (asm_out_file, "\t.eabi_attribute 30, %d\n", val);
4282 + /* Tag_ABI_FP_16bit_format. */
4283 + if (arm_fp16_format)
4284 + asm_fprintf (asm_out_file, "\t.eabi_attribute 38, %d\n",
4285 + (int)arm_fp16_format);
4287 if (arm_lang_output_object_attributes_hook)
4288 arm_lang_output_object_attributes_hook();
4290 @@ -18602,6 +20070,23 @@ arm_emit_vector_const (FILE *file, rtx x
4294 +/* Emit a fp16 constant appropriately padded to occupy a 4-byte word.
4295 + HFmode constant pool entries are actually loaded with ldr. */
4297 +arm_emit_fp16_const (rtx c)
4299 + REAL_VALUE_TYPE r;
4302 + REAL_VALUE_FROM_CONST_DOUBLE (r, c);
4303 + bits = real_to_target (NULL, &r, HFmode);
4304 + if (WORDS_BIG_ENDIAN)
4305 + assemble_zeros (2);
4306 + assemble_integer (GEN_INT (bits), 2, BITS_PER_WORD, 1);
4307 + if (!WORDS_BIG_ENDIAN)
4308 + assemble_zeros (2);
4312 arm_output_load_gr (rtx *operands)
4314 @@ -18639,19 +20124,24 @@ arm_output_load_gr (rtx *operands)
4318 -arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
4319 +arm_setup_incoming_varargs (CUMULATIVE_ARGS *pcum,
4320 enum machine_mode mode,
4323 int second_time ATTRIBUTE_UNUSED)
4325 - int nregs = cum->nregs;
4327 - && ARM_DOUBLEWORD_ALIGN
4328 - && arm_needs_doubleword_align (mode, type))
4333 cfun->machine->uses_anonymous_args = 1;
4334 + if (pcum->pcs_variant <= ARM_PCS_AAPCS_LOCAL)
4336 + nregs = pcum->aapcs_ncrn;
4337 + if ((nregs & 1) && arm_needs_doubleword_align (mode, type))
4341 + nregs = pcum->nregs;
4343 if (nregs < NUM_ARG_REGS)
4344 *pretend_size = (NUM_ARG_REGS - nregs) * UNITS_PER_WORD;
4346 @@ -19035,9 +20525,10 @@ arm_vector_mode_supported_p (enum machin
4347 || mode == V16QImode || mode == V4SFmode || mode == V2DImode))
4350 - if ((mode == V2SImode)
4351 - || (mode == V4HImode)
4352 - || (mode == V8QImode))
4353 + if ((TARGET_NEON || TARGET_IWMMXT)
4354 + && ((mode == V2SImode)
4355 + || (mode == V4HImode)
4356 + || (mode == V8QImode)))
4360 @@ -19068,9 +20559,14 @@ arm_dbx_register_number (unsigned int re
4361 if (IS_FPA_REGNUM (regno))
4362 return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM;
4364 - /* FIXME: VFPv3 register numbering. */
4365 if (IS_VFP_REGNUM (regno))
4366 - return 64 + regno - FIRST_VFP_REGNUM;
4368 + /* See comment in arm_dwarf_register_span. */
4369 + if (VFP_REGNO_OK_FOR_SINGLE (regno))
4370 + return 64 + regno - FIRST_VFP_REGNUM;
4372 + return 256 + (regno - FIRST_VFP_REGNUM) / 2;
4375 if (IS_IWMMXT_GR_REGNUM (regno))
4376 return 104 + regno - FIRST_IWMMXT_GR_REGNUM;
4377 @@ -19081,6 +20577,39 @@ arm_dbx_register_number (unsigned int re
4381 +/* Dwarf models VFPv3 registers as 32 64-bit registers.
4382 + GCC models tham as 64 32-bit registers, so we need to describe this to
4383 + the DWARF generation code. Other registers can use the default. */
4385 +arm_dwarf_register_span(rtx rtl)
4392 + regno = REGNO (rtl);
4393 + if (!IS_VFP_REGNUM (regno))
4396 + /* The EABI defines two VFP register ranges:
4397 + 64-95: Legacy VFPv2 numbering for S0-S31 (obsolescent)
4399 + The recommended encodings for s0-s31 is a DW_OP_bit_piece of the
4400 + corresponding D register. However gdb6.6 does not support this, so
4401 + we use the legacy encodings. We also use these encodings for D0-D15
4402 + for compatibility with older debuggers. */
4403 + if (VFP_REGNO_OK_FOR_SINGLE (regno))
4406 + nregs = GET_MODE_SIZE (GET_MODE (rtl)) / 8;
4407 + p = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc(nregs));
4408 + regno = (regno - FIRST_VFP_REGNUM) / 2;
4409 + for (i = 0; i < nregs; i++)
4410 + XVECEXP (p, 0, i) = gen_rtx_REG (DImode, 256 + regno + i);
4415 #ifdef TARGET_UNWIND_INFO
4416 /* Emit unwind directives for a store-multiple instruction or stack pointer
4417 @@ -19567,6 +21096,7 @@ arm_issue_rate (void)
4425 @@ -19631,6 +21161,10 @@ arm_mangle_type (const_tree type)
4426 return "St9__va_list";
4429 + /* Half-precision float. */
4430 + if (TREE_CODE (type) == REAL_TYPE && TYPE_PRECISION (type) == 16)
4433 if (TREE_CODE (type) != VECTOR_TYPE)
4436 @@ -19687,6 +21221,86 @@ arm_optimization_options (int level, int
4437 given on the command line. */
4439 flag_section_anchors = 2;
4443 + /* Select optimizations that are a win for code size.
4445 + The inlining options set below have two important
4446 + consequences for functions not explicitly marked
4448 + - Static functions used once are inlined if
4449 + sufficiently small. Static functions used twice
4451 + - Non-static functions are never inlined.
4452 + So in effect, inlining will never cause two copies
4453 + of function bodies to be created. */
4454 + /* Empirical results show that these options benefit code
4456 + /* FIXME: -fsee seems to be broken for Thumb-2. */
4457 + /* flag_see = 1; */
4458 + flag_move_loop_invariants = 0;
4459 + /* In Thumb mode the function call code size overhead is typically very
4460 + small, and narrow branch instructions have very limited range.
4461 + Inlining even medium sized functions tends to bloat the caller and
4462 + require the use of long branch instructions. On average the long
4463 + branches cost more than eliminating the function call overhead saves,
4464 + so we use extremely restrictive automatic inlining heuristics. In ARM
4465 + mode the results are fairly neutral, probably due to better constant
4466 + pool placement. */
4467 + set_param_value ("max-inline-insns-single", 1);
4468 + set_param_value ("max-inline-insns-auto", 1);
4473 + /* Set flag_unroll_loops to a default value, so that we can tell
4474 + if it was specified on the command line; see
4475 + arm_override_options. */
4476 + flag_unroll_loops = 2;
4477 + /* Promote loop indices to int where possible. Consider moving this
4479 + flag_promote_loop_indices = 1;
4483 +/* Return how many instructions to look ahead for better insn
4486 +arm_multipass_dfa_lookahead (void)
4488 + return (arm_tune == marvell_f) ? 4 : 0;
4491 +/* Return the minimum alignment required to load or store a
4492 + vector of the given type, which may be less than the
4493 + natural alignment of the type. */
4496 +arm_vector_min_alignment (const_tree type)
4500 + /* The NEON element load and store instructions only require the
4501 + alignment of the element type. They can benefit from higher
4502 + statically reported alignment, but we do not take advantage
4504 + gcc_assert (TREE_CODE (type) == VECTOR_TYPE);
4505 + return TYPE_ALIGN_UNIT (TREE_TYPE (type));
4508 + return default_vector_min_alignment (type);
4512 +arm_vector_always_misalign(const_tree type ATTRIBUTE_UNUSED)
4514 + /* On big-endian targets array loads (vld1) and vector loads (vldm)
4515 + use a different format. Always use the "misaligned" array variant.
4516 + FIXME: this still doesn't work for big-endian because of constant
4517 + loads and other operations using vldm ordering. See
4519 + return TARGET_NEON && !BYTES_BIG_ENDIAN;
4523 --- a/gcc/config/arm/arm.h
4524 +++ b/gcc/config/arm/arm.h
4525 @@ -85,6 +85,10 @@ extern char arm_arch_name[];
4526 builtin_define ("__IWMMXT__"); \
4527 if (TARGET_AAPCS_BASED) \
4528 builtin_define ("__ARM_EABI__"); \
4529 + if (arm_tune_marvell_f) \
4530 + builtin_define ("__ARM_TUNE_MARVELL_F__"); \
4531 + if (low_irq_latency) \
4532 + builtin_define ("__low_irq_latency__"); \
4535 /* The various ARM cores. */
4536 @@ -199,6 +203,13 @@ extern void (*arm_lang_output_object_att
4537 #define TARGET_AAPCS_BASED \
4538 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS)
4540 +/* True if we should avoid generating conditional execution instructions. */
4541 +#define TARGET_NO_COND_EXEC (arm_tune_marvell_f && !optimize_size)
4542 +/* Avoid most conditional instructions, but allow pairs with opposite
4543 + conditions and the same destination. */
4544 +#define TARGET_NO_SINGLE_COND_EXEC \
4545 + ((arm_tune_cortex_a9 || arm_tune_marvell_f) && !optimize_size)
4547 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15)
4548 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT)
4550 @@ -211,35 +222,43 @@ extern void (*arm_lang_output_object_att
4552 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm)
4554 +#define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2)
4555 /* The following two macros concern the ability to execute coprocessor
4556 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently
4557 only ever tested when we know we are generating for VFP hardware; we need
4558 to be more careful with TARGET_NEON as noted below. */
4560 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */
4561 -#define TARGET_VFPD32 (arm_fp_model == ARM_FP_MODEL_VFP \
4562 - && (arm_fpu_arch == FPUTYPE_VFP3 \
4563 - || arm_fpu_arch == FPUTYPE_NEON))
4564 +#define TARGET_VFPD32 (TARGET_VFP && arm_arch_vfp_regs == VFP_REG_D32)
4566 /* FPU supports VFPv3 instructions. */
4567 -#define TARGET_VFP3 (arm_fp_model == ARM_FP_MODEL_VFP \
4568 - && (arm_fpu_arch == FPUTYPE_VFP3D16 \
4569 - || TARGET_VFPD32))
4570 +#define TARGET_VFP3 (TARGET_VFP && arm_arch_vfp_rev >= 3)
4572 +/* FPU only supports VFP single-precision instructions. */
4573 +#define TARGET_VFP_SINGLE (TARGET_VFP && arm_arch_vfp_regs == VFP_REG_SINGLE)
4575 +/* FPU supports VFP double-precision instructions. */
4576 +#define TARGET_VFP_DOUBLE (TARGET_VFP && arm_arch_vfp_regs != VFP_REG_SINGLE)
4578 +/* FPU supports half-precision floating-point with NEON element load/store. */
4579 +#define TARGET_NEON_FP16 (TARGET_VFP && arm_arch_vfp_neon && arm_arch_vfp_fp16)
4581 +/* FPU supports VFP half-precision floating-point. */
4582 +#define TARGET_FP16 (TARGET_VFP && arm_arch_vfp_fp16)
4584 /* FPU supports Neon instructions. The setting of this macro gets
4585 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
4586 and TARGET_HARD_FLOAT to ensure that NEON instructions are
4588 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \
4589 - && arm_fp_model == ARM_FP_MODEL_VFP \
4590 - && arm_fpu_arch == FPUTYPE_NEON)
4591 + && TARGET_VFP && arm_arch_vfp_neon)
4593 /* "DSP" multiply instructions, eg. SMULxy. */
4594 #define TARGET_DSP_MULTIPLY \
4595 - (TARGET_32BIT && arm_arch5e && arm_arch_notm)
4596 + (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em))
4597 /* Integer SIMD instructions, and extend-accumulate instructions. */
4598 #define TARGET_INT_SIMD \
4599 - (TARGET_32BIT && arm_arch6 && arm_arch_notm)
4600 + (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em))
4602 /* Should MOVW/MOVT be used in preference to a constant pool. */
4603 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size)
4604 @@ -289,40 +308,30 @@ enum arm_fp_model
4608 -extern enum arm_fp_model arm_fp_model;
4610 -/* Which floating point hardware is available. Also update
4611 - fp_model_for_fpu in arm.c when adding entries to this list. */
4614 - /* No FP hardware. */
4616 - /* Full FPA support. */
4618 - /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */
4620 - /* Emulated FPA hardware, Issue 3 emulator. */
4622 - /* Cirrus Maverick floating point co-processor. */
4632 +enum vfp_reg_type {
4638 -/* Recast the floating point class to be the floating point attribute. */
4639 -#define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune)
4641 -/* What type of floating point to tune for */
4642 -extern enum fputype arm_fpu_tune;
4643 +extern const struct arm_fpu_desc
4646 + enum arm_fp_model model;
4648 + enum vfp_reg_type myregs;
4653 +#define arm_fp_model arm_fpu_desc->model
4654 +#define arm_arch_vfp_rev arm_fpu_desc->rev
4655 +#define arm_arch_vfp_regs arm_fpu_desc->myregs
4656 +#define arm_arch_vfp_neon arm_fpu_desc->neon
4657 +#define arm_arch_vfp_fp16 arm_fpu_desc->fp16
4659 -/* What type of floating point instructions are available */
4660 -extern enum fputype arm_fpu_arch;
4661 +/* Which floating point hardware to schedule for. */
4662 +extern int arm_fpu_attr;
4666 @@ -337,6 +346,21 @@ extern enum float_abi_type arm_float_abi
4667 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT
4670 +/* Which __fp16 format to use.
4671 + The enumeration values correspond to the numbering for the
4672 + Tag_ABI_FP_16bit_format attribute.
4674 +enum arm_fp16_format_type
4676 + ARM_FP16_FORMAT_NONE = 0,
4677 + ARM_FP16_FORMAT_IEEE = 1,
4678 + ARM_FP16_FORMAT_ALTERNATIVE = 2
4681 +extern enum arm_fp16_format_type arm_fp16_format;
4682 +#define LARGEST_EXPONENT_IS_NORMAL(bits) \
4683 + ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
4685 /* Which ABI to use. */
4688 @@ -383,12 +407,18 @@ extern int arm_arch6;
4689 /* Nonzero if instructions not present in the 'M' profile can be used. */
4690 extern int arm_arch_notm;
4692 +/* Nonzero if instructions present in ARMv7E-M can be used. */
4693 +extern int arm_arch7em;
4695 /* Nonzero if this chip can benefit from load scheduling. */
4696 extern int arm_ld_sched;
4698 /* Nonzero if generating thumb code. */
4699 extern int thumb_code;
4701 +/* Nonzero if generating Janus2 code. */
4702 +extern int janus2_code;
4704 /* Nonzero if this chip is a StrongARM. */
4705 extern int arm_tune_strongarm;
4707 @@ -404,6 +434,9 @@ extern int arm_arch_xscale;
4708 /* Nonzero if tuning for XScale. */
4709 extern int arm_tune_xscale;
4711 +/* Nonzero if tuning for Marvell Feroceon. */
4712 +extern int arm_tune_marvell_f;
4714 /* Nonzero if tuning for stores via the write buffer. */
4715 extern int arm_tune_wbuf;
4717 @@ -423,6 +456,10 @@ extern int arm_arch_thumb2;
4718 /* Nonzero if chip supports integer division instruction. */
4719 extern int arm_arch_hwdiv;
4721 +/* Nonzero if we should minimize interrupt latency of the
4722 + generated code. */
4723 +extern int low_irq_latency;
4725 #ifndef TARGET_DEFAULT
4726 #define TARGET_DEFAULT (MASK_APCS_FRAME)
4728 @@ -757,12 +794,11 @@ extern int arm_structure_size_boundary;
4729 fixed_regs[regno] = call_used_regs[regno] = 1; \
4732 - if (TARGET_THUMB && optimize_size) \
4734 - /* When optimizing for size, it's better not to use \
4735 - the HI regs, because of the overhead of stacking \
4737 - /* ??? Is this still true for thumb2? */ \
4738 + if (TARGET_THUMB1 && optimize_size) \
4740 + /* When optimizing for size on Thumb-1, it's better not \
4741 + to use the HI regs, because of the overhead of \
4742 + stacking them. */ \
4743 for (regno = FIRST_HI_REGNUM; \
4744 regno <= LAST_HI_REGNUM; ++regno) \
4745 fixed_regs[regno] = call_used_regs[regno] = 1; \
4746 @@ -881,6 +917,9 @@ extern int arm_structure_size_boundary;
4747 /* The number of (integer) argument register available. */
4748 #define NUM_ARG_REGS 4
4750 +/* And similarly for the VFP. */
4751 +#define NUM_VFP_ARG_REGS 16
4753 /* Return the register number of the N'th (integer) argument. */
4754 #define ARG_REGISTER(N) (N - 1)
4756 @@ -1059,7 +1098,7 @@ extern int arm_structure_size_boundary;
4757 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
4759 #define VALID_IWMMXT_REG_MODE(MODE) \
4760 - (arm_vector_mode_supported_p (MODE) || (MODE) == DImode)
4761 + (arm_vector_mode_supported_p (MODE) || (MODE) == DImode || (MODE) == SImode)
4763 /* Modes valid for Neon D registers. */
4764 #define VALID_NEON_DREG_MODE(MODE) \
4765 @@ -1230,11 +1269,14 @@ enum reg_class
4766 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \
4769 -/* We need to define this for LO_REGS on thumb. Otherwise we can end up
4770 - using r0-r4 for function arguments, r7 for the stack frame and don't
4771 - have enough left over to do doubleword arithmetic. */
4772 +/* We need to define this for LO_REGS on Thumb-1. Otherwise we can end up
4773 + using r0-r4 for function arguments, r7 for the stack frame and don't have
4774 + enough left over to do doubleword arithmetic. For Thumb-2 all the
4775 + potentially problematic instructions accept high registers so this is not
4776 + necessary. Care needs to be taken to avoid adding new Thumb-2 patterns
4777 + that require many low registers. */
4778 #define CLASS_LIKELY_SPILLED_P(CLASS) \
4779 - ((TARGET_THUMB && (CLASS) == LO_REGS) \
4780 + ((TARGET_THUMB1 && (CLASS) == LO_REGS) \
4781 || (CLASS) == CC_REG)
4783 /* The class value for index registers, and the one for base regs. */
4784 @@ -1245,7 +1287,7 @@ enum reg_class
4785 when addressing quantities in QI or HI mode; if we don't know the
4786 mode, then we must be conservative. */
4787 #define MODE_BASE_REG_CLASS(MODE) \
4788 - (TARGET_32BIT ? CORE_REGS : \
4789 + (TARGET_32BIT ? (TARGET_THUMB2 ? LO_REGS : CORE_REGS) : \
4790 (((MODE) == SImode) ? BASE_REGS : LO_REGS))
4792 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS
4793 @@ -1346,6 +1388,9 @@ enum reg_class
4794 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \
4795 /* Need to be careful, -256 is not a valid offset. */ \
4796 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
4797 + else if (TARGET_REALLY_IWMMXT && MODE == SImode) \
4798 + /* Need to be careful, -1024 is not a valid offset. */ \
4799 + low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
4800 else if (MODE == SImode \
4801 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
4802 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
4803 @@ -1416,13 +1461,17 @@ do { \
4804 /* If defined, gives a class of registers that cannot be used as the
4805 operand of a SUBREG that changes the mode of the object illegally. */
4807 -/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */
4808 +/* Moves between FPA_REGS and GENERAL_REGS are two memory insns.
4809 + Moves between VFP_REGS and GENERAL_REGS are a single insn, but
4810 + it is typically more expensive than a single memory access. We set
4811 + the cost to less than two memory accesses so that floating
4812 + point to integer conversion does not go through memory. */
4813 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
4815 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \
4816 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \
4817 - IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 10 : \
4818 - !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 10 : \
4819 + IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \
4820 + !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \
4821 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \
4822 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \
4823 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \
4824 @@ -1491,9 +1540,10 @@ do { \
4826 /* Define how to find the value returned by a library function
4827 assuming the value has mode MODE. */
4828 -#define LIBCALL_VALUE(MODE) \
4829 - (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
4830 - && GET_MODE_CLASS (MODE) == MODE_FLOAT \
4831 +#define LIBCALL_VALUE(MODE) \
4832 + (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \
4833 + : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \
4834 + && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
4835 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \
4836 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \
4837 && GET_MODE_CLASS (MODE) == MODE_FLOAT \
4838 @@ -1502,22 +1552,16 @@ do { \
4839 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \
4840 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
4842 -/* Define how to find the value returned by a function.
4843 - VALTYPE is the data type of the value (as a tree).
4844 - If the precise function being called is known, FUNC is its FUNCTION_DECL;
4845 - otherwise, FUNC is 0. */
4846 -#define FUNCTION_VALUE(VALTYPE, FUNC) \
4847 - arm_function_value (VALTYPE, FUNC);
4849 -/* 1 if N is a possible register number for a function value.
4850 - On the ARM, only r0 and f0 can return results. */
4851 -/* On a Cirrus chip, mvf0 can return results. */
4852 -#define FUNCTION_VALUE_REGNO_P(REGNO) \
4853 - ((REGNO) == ARG_REGISTER (1) \
4854 - || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
4855 - && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
4856 - || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
4857 - || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
4858 +/* 1 if REGNO is a possible register number for a function value. */
4859 +#define FUNCTION_VALUE_REGNO_P(REGNO) \
4860 + ((REGNO) == ARG_REGISTER (1) \
4861 + || (TARGET_AAPCS_BASED && TARGET_32BIT \
4862 + && TARGET_VFP && TARGET_HARD_FLOAT \
4863 + && (REGNO) == FIRST_VFP_REGNUM) \
4864 + || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \
4865 + && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \
4866 + || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \
4867 + || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \
4868 && TARGET_HARD_FLOAT_ABI && TARGET_FPA))
4870 /* Amount of memory needed for an untyped call to save all possible return
4871 @@ -1617,9 +1661,27 @@ machine_function;
4872 that is in text_section. */
4873 extern GTY(()) rtx thumb_call_via_label[14];
4875 +/* The number of potential ways of assigning to a co-processor. */
4876 +#define ARM_NUM_COPROC_SLOTS 1
4878 +/* Enumeration of procedure calling standard variants. We don't really
4879 + support all of these yet. */
4882 + ARM_PCS_AAPCS, /* Base standard AAPCS. */
4883 + ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */
4884 + ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */
4885 + /* This must be the last AAPCS variant. */
4886 + ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */
4887 + ARM_PCS_ATPCS, /* ATPCS. */
4888 + ARM_PCS_APCS, /* APCS (legacy Linux etc). */
4892 +/* We can't define this inside a generator file because it needs enum
4894 /* A C type for declaring a variable that is used as the first argument of
4895 - `FUNCTION_ARG' and other related values. For some target machines, the
4896 - type `int' suffices and can hold the number of bytes of argument so far. */
4897 + `FUNCTION_ARG' and other related values. */
4900 /* This is the number of registers of arguments scanned so far. */
4901 @@ -1628,9 +1690,33 @@ typedef struct
4906 + /* Which procedure call variant to use for this call. */
4907 + enum arm_pcs pcs_variant;
4909 + /* AAPCS related state tracking. */
4910 + int aapcs_arg_processed; /* No need to lay out this argument again. */
4911 + int aapcs_cprc_slot; /* Index of co-processor rules to handle
4912 + this argument, or -1 if using core
4915 + int aapcs_next_ncrn;
4916 + rtx aapcs_reg; /* Register assigned to this argument. */
4917 + int aapcs_partial; /* How many bytes are passed in regs (if
4918 + split between core regs and stack.
4919 + Zero otherwise. */
4920 + int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS];
4921 + int can_split; /* Argument can be split between core regs
4923 + /* Private data for tracking VFP register allocation */
4924 + unsigned aapcs_vfp_regs_free;
4925 + unsigned aapcs_vfp_reg_alloc;
4926 + int aapcs_vfp_rcount;
4927 + /* Can't include insn-modes.h because this header is needed before we
4929 + int /* enum machine_mode */ aapcs_vfp_rmode;
4933 /* Define where to put the arguments to a function.
4934 Value is zero to push the argument on the stack,
4935 or a hard register in which to store the argument.
4936 @@ -1674,13 +1760,7 @@ typedef struct
4937 of mode MODE and data type TYPE.
4938 (TYPE is null for libcalls where that information may not be available.) */
4939 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
4940 - (CUM).nargs += 1; \
4941 - if (arm_vector_mode_supported_p (MODE) \
4942 - && (CUM).named_count > (CUM).nargs \
4943 - && TARGET_IWMMXT_ABI) \
4944 - (CUM).iwmmxt_nregs += 1; \
4946 - (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE)
4947 + arm_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED))
4949 /* If defined, a C expression that gives the alignment boundary, in bits, of an
4950 argument with the specified mode and type. If it is not defined,
4951 @@ -1692,9 +1772,11 @@ typedef struct
4953 /* 1 if N is a possible register number for function argument passing.
4954 On the ARM, r0-r3 are used to pass args. */
4955 -#define FUNCTION_ARG_REGNO_P(REGNO) \
4956 - (IN_RANGE ((REGNO), 0, 3) \
4957 - || (TARGET_IWMMXT_ABI \
4958 +#define FUNCTION_ARG_REGNO_P(REGNO) \
4959 + (IN_RANGE ((REGNO), 0, 3) \
4960 + || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \
4961 + && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \
4962 + || (TARGET_IWMMXT_ABI \
4963 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9)))
4966 @@ -2324,7 +2406,8 @@ do { \
4967 /* Try to generate sequences that don't involve branches, we can then use
4968 conditional instructions */
4969 #define BRANCH_COST(speed_p, predictable_p) \
4970 - (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0))
4971 + (TARGET_32BIT ? (TARGET_THUMB2 && optimize_size ? 1 : 4) \
4972 + : (optimize > 0 ? 2 : 0))
4974 /* Position Independent Code. */
4975 /* We decide which register to use based on the compilation options and
4976 @@ -2392,6 +2475,7 @@ extern int making_const_table;
4978 /* The arm5 clz instruction returns 32. */
4979 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
4980 +#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
4983 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \
4984 @@ -2404,6 +2488,19 @@ extern int making_const_table;
4986 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
4987 STACK_POINTER_REGNUM, REGNO); \
4988 + else if (TARGET_THUMB1 \
4989 + && (REGNO) == STATIC_CHAIN_REGNUM) \
4991 + /* We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1.
4992 + We know that ASM_OUTPUT_REG_PUSH will be matched with
4993 + ASM_OUTPUT_REG_POP, and that r7 isn't used by the function
4994 + profiler, so we can use it as a scratch reg. WARNING: This isn't
4995 + safe in the general case! It may be sensitive to future changes
4996 + in final.c:profile_function. */ \
4997 + asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
4998 + asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\
4999 + asm_fprintf (STREAM, "\tpush\t{r7}\n"); \
5002 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \
5004 @@ -2415,6 +2512,14 @@ extern int making_const_table;
5006 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
5007 STACK_POINTER_REGNUM, REGNO); \
5008 + else if (TARGET_THUMB1 \
5009 + && (REGNO) == STATIC_CHAIN_REGNUM) \
5011 + /* See comment in ASM_OUTPUT_REG_PUSH. */ \
5012 + asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
5013 + asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\
5014 + asm_fprintf (STREAM, "\tpop\t{r7}\n"); \
5017 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \
5019 --- a/gcc/config/arm/arm.md
5020 +++ b/gcc/config/arm/arm.md
5022 ; correctly for PIC usage.
5023 (UNSPEC_GOTSYM_OFF 24) ; The offset of the start of the the GOT from a
5024 ; a given symbolic address.
5025 + (UNSPEC_RBIT 25) ; rbit operation.
5030 (VUNSPEC_WCMP_EQ 12) ; Used by the iWMMXt WCMPEQ instructions
5031 (VUNSPEC_WCMP_GTU 13) ; Used by the iWMMXt WCMPGTU instructions
5032 (VUNSPEC_WCMP_GT 14) ; Used by the iwMMXT WCMPGT instructions
5033 + (VUNSPEC_ALIGN16 15) ; Used to force 16-byte alignment.
5034 + (VUNSPEC_ALIGN32 16) ; Used to force 32-byte alignment.
5035 (VUNSPEC_EH_RETURN 20); Use to override the return address for exception
5038 @@ -144,6 +147,10 @@
5039 ; patterns that share the same RTL in both ARM and Thumb code.
5040 (define_attr "is_thumb" "no,yes" (const (symbol_ref "thumb_code")))
5042 +; FIX_JANUS is set to 'yes' when compiling for Janus2, it causes to
5043 +; add a nop after shifts, in order to work around a Janus2 bug
5044 +(define_attr "fix_janus" "no,yes" (const (symbol_ref "janus2_code")))
5046 ; IS_STRONGARM is set to 'yes' when compiling for StrongARM, it affects
5047 ; scheduling decisions for the load unit and the multiplier.
5048 (define_attr "is_strongarm" "no,yes" (const (symbol_ref "arm_tune_strongarm")))
5050 ; Floating Point Unit. If we only have floating point emulation, then there
5051 ; is no point in scheduling the floating point insns. (Well, for best
5052 ; performance we should try and group them together).
5053 -(define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp,vfpv3d16,vfpv3,neon"
5054 +(define_attr "fpu" "none,fpa,fpe2,fpe3,maverick,vfp"
5055 (const (symbol_ref "arm_fpu_attr")))
5057 ; LENGTH of an instruction (in bytes)
5059 ;; scheduling information.
5062 - "mov,mvn,smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,umaal,smlald,smlsld,clz,mrs,msr,xtab,sdiv,udiv,other"
5063 + "mov,mvn,and,orr,eor,smulxy,smlaxy,smlalxy,smulwy,smlawx,mul,muls,mla,mlas,umull,umulls,umlal,umlals,smull,smulls,smlal,smlals,smlawy,smuad,smuadx,smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,umaal,smlald,smlsld,clz,mrs,msr,xtab,sdiv,udiv,other"
5064 (const_string "other"))
5066 ; TYPE attribute is used to detect floating point instructions which, if
5068 (define_attr "ldsched" "no,yes" (const (symbol_ref "arm_ld_sched")))
5070 ;; Classification of NEON instructions for scheduling purposes.
5071 -;; Do not set this attribute and the "type" attribute together in
5072 -;; any one instruction pattern.
5073 (define_attr "neon_type"
5078 (define_attr "generic_sched" "yes,no"
5079 (const (if_then_else
5080 - (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9")
5081 + (ior (eq_attr "tune" "arm926ejs,arm1020e,arm1026ejs,arm1136js,arm1136jfs,cortexa8,cortexa9,marvell_f")
5082 (eq_attr "tune_cortexr4" "yes"))
5084 (const_string "yes"))))
5086 (define_attr "generic_vfp" "yes,no"
5087 (const (if_then_else
5088 (and (eq_attr "fpu" "vfp")
5089 - (eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9")
5090 + (eq_attr "tune" "!arm1020e,arm1022e,cortexa8,cortexa9,marvell_f")
5091 (eq_attr "tune_cortexr4" "no"))
5092 (const_string "yes")
5093 (const_string "no"))))
5095 (include "cortex-a9.md")
5096 (include "cortex-r4.md")
5097 (include "cortex-r4f.md")
5098 +(include "marvell-f.md")
5099 +(include "marvell-f-vfp.md")
5100 (include "vfp11.md")
5103 @@ -620,10 +627,11 @@
5104 sub%?\\t%0, %1, #%n2
5105 sub%?\\t%0, %1, #%n2
5108 - GET_CODE (operands[2]) == CONST_INT
5110 + && GET_CODE (operands[2]) == CONST_INT
5111 && !(const_ok_for_arm (INTVAL (operands[2]))
5112 - || const_ok_for_arm (-INTVAL (operands[2])))"
5113 + || const_ok_for_arm (-INTVAL (operands[2])))
5114 + && (reload_completed || !arm_eliminable_register (operands[1]))"
5115 [(clobber (const_int 0))]
5117 arm_split_constant (PLUS, SImode, curr_insn,
5118 @@ -639,10 +647,10 @@
5119 ;; register. Trying to reload it will always fail catastrophically,
5120 ;; so never allow those alternatives to match if reloading is needed.
5122 -(define_insn "*thumb1_addsi3"
5123 - [(set (match_operand:SI 0 "register_operand" "=l,l,l,*rk,*hk,l,!k")
5124 - (plus:SI (match_operand:SI 1 "register_operand" "%0,0,l,*0,*0,!k,!k")
5125 - (match_operand:SI 2 "nonmemory_operand" "I,J,lL,*hk,*rk,!M,!O")))]
5126 +(define_insn_and_split "*thumb1_addsi3"
5127 + [(set (match_operand:SI 0 "register_operand" "=l,l,l,*rk,*hk,l,!k,l,l")
5128 + (plus:SI (match_operand:SI 1 "register_operand" "%0,0,l,*0,*0,!k,!k,0,l")
5129 + (match_operand:SI 2 "nonmemory_operand" "I,J,lL,*hk,*rk,!M,!O,Pa,Pb")))]
5132 static const char * const asms[] =
5134 \"add\\t%0, %0, %2\",
5135 \"add\\t%0, %0, %2\",
5136 \"add\\t%0, %1, %2\",
5137 - \"add\\t%0, %1, %2\"
5138 + \"add\\t%0, %1, %2\",
5142 if ((which_alternative == 2 || which_alternative == 6)
5143 && GET_CODE (operands[2]) == CONST_INT
5144 @@ -661,7 +671,22 @@
5145 return \"sub\\t%0, %1, #%n2\";
5146 return asms[which_alternative];
5148 - [(set_attr "length" "2")]
5149 + "&& reload_completed && CONST_INT_P (operands[2])
5150 + && operands[1] != stack_pointer_rtx
5151 + && (INTVAL (operands[2]) > 255 || INTVAL (operands[2]) < -255)"
5152 + [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
5153 + (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
5155 + HOST_WIDE_INT offset = INTVAL (operands[2]);
5158 + else if (offset < -255)
5161 + operands[3] = GEN_INT (offset);
5162 + operands[2] = GEN_INT (INTVAL (operands[2]) - offset);
5164 + [(set_attr "length" "2,2,2,2,2,2,2,4,4")]
5167 ;; Reloading and elimination of the frame pointer can
5168 @@ -854,7 +879,11 @@
5169 [(set_attr "conds" "use")
5170 (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
5171 (const_string "alu_shift")
5172 - (const_string "alu_shift_reg")))]
5173 + (const_string "alu_shift_reg")))
5174 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
5175 + (eq_attr "fix_janus" "yes"))
5180 (define_insn "*addsi3_carryin_alt1"
5182 [(set (match_operand:DF 0 "s_register_operand" "")
5183 (plus:DF (match_operand:DF 1 "s_register_operand" "")
5184 (match_operand:DF 2 "arm_float_add_operand" "")))]
5185 - "TARGET_32BIT && TARGET_HARD_FLOAT"
5186 + "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
5189 && !cirrus_fp_register (operands[2], DFmode))
5190 @@ -1176,7 +1205,7 @@
5191 [(set (match_operand:DF 0 "s_register_operand" "")
5192 (minus:DF (match_operand:DF 1 "arm_float_rhs_operand" "")
5193 (match_operand:DF 2 "arm_float_rhs_operand" "")))]
5194 - "TARGET_32BIT && TARGET_HARD_FLOAT"
5195 + "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
5197 if (TARGET_MAVERICK)
5199 @@ -1332,6 +1361,49 @@
5200 (set_attr "predicable" "yes")]
5203 +; The combiner cannot combine the first and last insns in the
5204 +; following sequence because of the intervening insn, so help the
5205 +; combiner with this splitter. The combiner does attempt to split
5206 +; this particular combination but does not know this exact split.
5207 +; Note that the combiner puts the constant at the outermost operation
5208 +; as a part of canonicalization.
5211 +; <add/sub> r3, r3, <constant>
5215 + [(set (match_operand:SI 0 "s_register_operand" "")
5216 + (match_operator:SI 1 "plusminus_operator"
5217 + [(plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "")
5218 + (match_operand:SI 3 "s_register_operand" ""))
5219 + (match_operand:SI 4 "s_register_operand" ""))
5220 + (match_operand:SI 5 "arm_immediate_operand" "")]))]
5222 + [(set (match_dup 0)
5223 + (plus:SI (mult:SI (match_dup 2) (match_dup 3))
5225 + (set (match_dup 0)
5226 + (match_op_dup:SI 1 [(match_dup 0) (match_dup 5)]))]
5229 +; Likewise for MLS. MLS is available only on select architectures.
5232 + [(set (match_operand:SI 0 "s_register_operand" "")
5233 + (match_operator:SI 1 "plusminus_operator"
5234 + [(minus:SI (match_operand:SI 2 "s_register_operand" "")
5235 + (mult:SI (match_operand:SI 3 "s_register_operand" "")
5236 + (match_operand:SI 4 "s_register_operand" "")))
5237 + (match_operand:SI 5 "arm_immediate_operand" "")]))]
5238 + "TARGET_32BIT && arm_arch_thumb2"
5239 + [(set (match_dup 0)
5240 + (minus:SI (match_dup 2)
5241 + (mult:SI (match_dup 3) (match_dup 4))))
5242 + (set (match_dup 0)
5243 + (match_op_dup:SI 1 [(match_dup 0) (match_dup 5)]))]
5246 (define_insn "*mulsi3addsi_compare0"
5247 [(set (reg:CC_NOOV CC_REGNUM)
5249 @@ -1713,7 +1785,7 @@
5250 [(set (match_operand:DF 0 "s_register_operand" "")
5251 (mult:DF (match_operand:DF 1 "s_register_operand" "")
5252 (match_operand:DF 2 "arm_float_rhs_operand" "")))]
5253 - "TARGET_32BIT && TARGET_HARD_FLOAT"
5254 + "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
5257 && !cirrus_fp_register (operands[2], DFmode))
5258 @@ -1733,7 +1805,7 @@
5259 [(set (match_operand:DF 0 "s_register_operand" "")
5260 (div:DF (match_operand:DF 1 "arm_float_rhs_operand" "")
5261 (match_operand:DF 2 "arm_float_rhs_operand" "")))]
5262 - "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
5263 + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
5267 @@ -1960,6 +2032,7 @@
5270 [(set_attr "length" "4,4,16")
5271 + (set_attr "insn" "and")
5272 (set_attr "predicable" "yes")]
5275 @@ -1969,7 +2042,8 @@
5276 (match_operand:SI 2 "register_operand" "l")))]
5279 - [(set_attr "length" "2")]
5280 + [(set_attr "length" "2")
5281 + (set_attr "insn" "and")]
5284 (define_insn "*andsi3_compare0"
5285 @@ -1984,7 +2058,8 @@
5288 bic%.\\t%0, %1, #%B2"
5289 - [(set_attr "conds" "set")]
5290 + [(set_attr "conds" "set")
5291 + (set_attr "insn" "and,*")]
5294 (define_insn "*andsi3_compare0_scratch"
5295 @@ -2280,7 +2355,7 @@
5299 - target = operands[0];
5300 + target = copy_rtx (operands[0]);
5301 /* Avoid using a subreg as a subtarget, and avoid writing a paradoxical
5302 subreg as the final target. */
5303 if (GET_CODE (target) == SUBREG)
5304 @@ -2528,7 +2603,11 @@
5305 (set_attr "shift" "2")
5306 (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
5307 (const_string "alu_shift")
5308 - (const_string "alu_shift_reg")))]
5309 + (const_string "alu_shift_reg")))
5310 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
5311 + (eq_attr "fix_janus" "yes"))
5316 (define_insn "*andsi_notsi_si_compare0"
5317 @@ -2576,6 +2655,7 @@
5318 orr%?\\t%Q0, %Q1, %2
5320 [(set_attr "length" "4,8")
5321 + (set_attr "insn" "orr")
5322 (set_attr "predicable" "yes")]
5325 @@ -2638,7 +2718,8 @@
5326 (match_operand:SI 2 "register_operand" "l")))]
5329 - [(set_attr "length" "2")]
5330 + [(set_attr "length" "2")
5331 + (set_attr "insn" "orr")]
5335 @@ -2663,7 +2744,8 @@
5336 (ior:SI (match_dup 1) (match_dup 2)))]
5338 "orr%.\\t%0, %1, %2"
5339 - [(set_attr "conds" "set")]
5340 + [(set_attr "conds" "set")
5341 + (set_attr "insn" "orr")]
5344 (define_insn "*iorsi3_compare0_scratch"
5345 @@ -2674,7 +2756,8 @@
5346 (clobber (match_scratch:SI 0 "=r"))]
5348 "orr%.\\t%0, %1, %2"
5349 - [(set_attr "conds" "set")]
5350 + [(set_attr "conds" "set")
5351 + (set_attr "insn" "orr")]
5354 (define_insn "xordi3"
5355 @@ -2697,7 +2780,8 @@
5356 eor%?\\t%Q0, %Q1, %2
5358 [(set_attr "length" "4,8")
5359 - (set_attr "predicable" "yes")]
5360 + (set_attr "predicable" "yes")
5361 + (set_attr "insn" "eor")]
5364 (define_insn "*xordi_sesidi_di"
5365 @@ -2728,7 +2812,8 @@
5366 (match_operand:SI 2 "arm_rhs_operand" "rI")))]
5368 "eor%?\\t%0, %1, %2"
5369 - [(set_attr "predicable" "yes")]
5370 + [(set_attr "predicable" "yes")
5371 + (set_attr "insn" "eor")]
5374 (define_insn "*thumb1_xorsi3"
5375 @@ -2737,7 +2822,8 @@
5376 (match_operand:SI 2 "register_operand" "l")))]
5379 - [(set_attr "length" "2")]
5380 + [(set_attr "length" "2")
5381 + (set_attr "insn" "eor")]
5384 (define_insn "*xorsi3_compare0"
5385 @@ -2749,7 +2835,8 @@
5386 (xor:SI (match_dup 1) (match_dup 2)))]
5388 "eor%.\\t%0, %1, %2"
5389 - [(set_attr "conds" "set")]
5390 + [(set_attr "conds" "set")
5391 + (set_attr "insn" "eor")]
5394 (define_insn "*xorsi3_compare0_scratch"
5395 @@ -2906,7 +2993,7 @@
5396 (smax:SI (match_operand:SI 1 "s_register_operand" "")
5397 (match_operand:SI 2 "arm_rhs_operand" "")))
5398 (clobber (reg:CC CC_REGNUM))])]
5400 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
5402 if (operands[2] == const0_rtx || operands[2] == constm1_rtx)
5404 @@ -2933,7 +3020,8 @@
5407 "orr%?\\t%0, %1, %1, asr #31"
5408 - [(set_attr "predicable" "yes")]
5409 + [(set_attr "predicable" "yes")
5410 + (set_attr "insn" "orr")]
5413 (define_insn "*arm_smax_insn"
5414 @@ -2941,7 +3029,7 @@
5415 (smax:SI (match_operand:SI 1 "s_register_operand" "%0,?r")
5416 (match_operand:SI 2 "arm_rhs_operand" "rI,rI")))
5417 (clobber (reg:CC CC_REGNUM))]
5419 + "TARGET_ARM && !TARGET_NO_COND_EXEC"
5421 cmp\\t%1, %2\;movlt\\t%0, %2
5422 cmp\\t%1, %2\;movge\\t%0, %1\;movlt\\t%0, %2"
5423 @@ -2955,7 +3043,7 @@
5424 (smin:SI (match_operand:SI 1 "s_register_operand" "")
5425 (match_operand:SI 2 "arm_rhs_operand" "")))
5426 (clobber (reg:CC CC_REGNUM))])]
5428 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
5430 if (operands[2] == const0_rtx)
5432 @@ -2973,7 +3061,8 @@
5435 "and%?\\t%0, %1, %1, asr #31"
5436 - [(set_attr "predicable" "yes")]
5437 + [(set_attr "predicable" "yes")
5438 + (set_attr "insn" "and")]
5441 (define_insn "*arm_smin_insn"
5442 @@ -2981,7 +3070,7 @@
5443 (smin:SI (match_operand:SI 1 "s_register_operand" "%0,?r")
5444 (match_operand:SI 2 "arm_rhs_operand" "rI,rI")))
5445 (clobber (reg:CC CC_REGNUM))]
5447 + "TARGET_ARM && !TARGET_NO_COND_EXEC"
5449 cmp\\t%1, %2\;movge\\t%0, %2
5450 cmp\\t%1, %2\;movlt\\t%0, %1\;movge\\t%0, %2"
5451 @@ -2995,7 +3084,7 @@
5452 (umax:SI (match_operand:SI 1 "s_register_operand" "")
5453 (match_operand:SI 2 "arm_rhs_operand" "")))
5454 (clobber (reg:CC CC_REGNUM))])]
5456 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
5460 @@ -3004,7 +3093,7 @@
5461 (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
5462 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
5463 (clobber (reg:CC CC_REGNUM))]
5465 + "TARGET_ARM && !TARGET_NO_COND_EXEC"
5467 cmp\\t%1, %2\;movcc\\t%0, %2
5468 cmp\\t%1, %2\;movcs\\t%0, %1
5469 @@ -3019,7 +3108,7 @@
5470 (umin:SI (match_operand:SI 1 "s_register_operand" "")
5471 (match_operand:SI 2 "arm_rhs_operand" "")))
5472 (clobber (reg:CC CC_REGNUM))])]
5474 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
5478 @@ -3028,7 +3117,7 @@
5479 (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r")
5480 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
5481 (clobber (reg:CC CC_REGNUM))]
5483 + "TARGET_ARM && !TARGET_NO_COND_EXEC"
5485 cmp\\t%1, %2\;movcs\\t%0, %2
5486 cmp\\t%1, %2\;movcc\\t%0, %1
5487 @@ -3043,7 +3132,7 @@
5488 [(match_operand:SI 1 "s_register_operand" "r")
5489 (match_operand:SI 2 "s_register_operand" "r")]))
5490 (clobber (reg:CC CC_REGNUM))]
5492 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
5494 operands[3] = gen_rtx_fmt_ee (minmax_code (operands[3]), SImode,
5495 operands[1], operands[2]);
5496 @@ -3163,11 +3252,23 @@
5497 [(set (match_operand:SI 0 "register_operand" "=l,l")
5498 (ashift:SI (match_operand:SI 1 "register_operand" "l,0")
5499 (match_operand:SI 2 "nonmemory_operand" "N,l")))]
5501 + "TARGET_THUMB1 && !janus2_code"
5503 [(set_attr "length" "2")]
5506 +(define_insn "*thumb1_ashlsi3_janus2"
5507 + [(set (match_operand:SI 0 "register_operand" "=l,l")
5508 + (ashift:SI (match_operand:SI 1 "register_operand" "l,0")
5509 + (match_operand:SI 2 "nonmemory_operand" "N,l")))]
5510 + "TARGET_THUMB1 && janus2_code"
5513 + lsl\\t%0, %1, %2\;nop"
5514 + [(set_attr "length" "2,4")]
5518 (define_expand "ashrdi3"
5519 [(set (match_operand:DI 0 "s_register_operand" "")
5520 (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "")
5521 @@ -3200,6 +3301,7 @@
5523 "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx"
5524 [(set_attr "conds" "clob")
5525 + (set_attr "insn" "mov")
5526 (set_attr "length" "8")]
5529 @@ -3219,11 +3321,22 @@
5530 [(set (match_operand:SI 0 "register_operand" "=l,l")
5531 (ashiftrt:SI (match_operand:SI 1 "register_operand" "l,0")
5532 (match_operand:SI 2 "nonmemory_operand" "N,l")))]
5534 + "TARGET_THUMB1 && !janus2_code"
5536 [(set_attr "length" "2")]
5539 +(define_insn "*thumb1_ashrsi3_janus2"
5540 + [(set (match_operand:SI 0 "register_operand" "=l,l")
5541 + (ashiftrt:SI (match_operand:SI 1 "register_operand" "l,0")
5542 + (match_operand:SI 2 "nonmemory_operand" "N,l")))]
5543 + "TARGET_THUMB1 && janus2_code"
5546 + asr\\t%0, %1, %2\;nop"
5547 + [(set_attr "length" "2,4")]
5550 (define_expand "lshrdi3"
5551 [(set (match_operand:DI 0 "s_register_operand" "")
5552 (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "")
5553 @@ -3256,6 +3369,7 @@
5555 "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx"
5556 [(set_attr "conds" "clob")
5557 + (set_attr "insn" "mov")
5558 (set_attr "length" "8")]
5561 @@ -3278,11 +3392,22 @@
5562 [(set (match_operand:SI 0 "register_operand" "=l,l")
5563 (lshiftrt:SI (match_operand:SI 1 "register_operand" "l,0")
5564 (match_operand:SI 2 "nonmemory_operand" "N,l")))]
5566 + "TARGET_THUMB1 && !janus2_code"
5568 [(set_attr "length" "2")]
5571 +(define_insn "*thumb1_lshrsi3_janus2"
5572 + [(set (match_operand:SI 0 "register_operand" "=l,l")
5573 + (lshiftrt:SI (match_operand:SI 1 "register_operand" "l,0")
5574 + (match_operand:SI 2 "nonmemory_operand" "N,l")))]
5575 + "TARGET_THUMB1 && janus2_code"
5578 + lsr\\t%0, %1, %2; nop"
5579 + [(set_attr "length" "2,4")]
5582 (define_expand "rotlsi3"
5583 [(set (match_operand:SI 0 "s_register_operand" "")
5584 (rotatert:SI (match_operand:SI 1 "s_register_operand" "")
5585 @@ -3324,11 +3449,20 @@
5586 [(set (match_operand:SI 0 "register_operand" "=l")
5587 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5588 (match_operand:SI 2 "register_operand" "l")))]
5590 + "TARGET_THUMB1 && !janus2_code"
5592 [(set_attr "length" "2")]
5595 +(define_insn "*thumb1_rotrsi3_janus2"
5596 + [(set (match_operand:SI 0 "register_operand" "=l")
5597 + (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5598 + (match_operand:SI 2 "register_operand" "l")))]
5599 + "TARGET_THUMB1 && janus2_code"
5600 + "ror\\t%0, %0, %2; nop"
5601 + [(set_attr "length" "4")]
5604 (define_insn "*arm_shiftsi3"
5605 [(set (match_operand:SI 0 "s_register_operand" "=r")
5606 (match_operator:SI 3 "shift_operator"
5607 @@ -3340,7 +3474,11 @@
5608 (set_attr "shift" "1")
5609 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
5610 (const_string "alu_shift")
5611 - (const_string "alu_shift_reg")))]
5612 + (const_string "alu_shift_reg")))
5613 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
5614 + (eq_attr "fix_janus" "yes"))
5619 (define_insn "*shiftsi3_compare0"
5620 @@ -3357,7 +3495,11 @@
5621 (set_attr "shift" "1")
5622 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
5623 (const_string "alu_shift")
5624 - (const_string "alu_shift_reg")))]
5625 + (const_string "alu_shift_reg")))
5626 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
5627 + (eq_attr "fix_janus" "yes"))
5632 (define_insn "*shiftsi3_compare0_scratch"
5633 @@ -3370,7 +3512,11 @@
5635 "* return arm_output_shift(operands, 1);"
5636 [(set_attr "conds" "set")
5637 - (set_attr "shift" "1")]
5638 + (set_attr "shift" "1")
5639 + (set (attr "length") (if_then_else (and (match_operand 2 "s_register_operand" "")
5640 + (eq_attr "fix_janus" "yes"))
5645 (define_insn "*arm_notsi_shiftsi"
5646 @@ -3382,9 +3528,14 @@
5648 [(set_attr "predicable" "yes")
5649 (set_attr "shift" "1")
5650 + (set_attr "insn" "mvn")
5651 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
5652 (const_string "alu_shift")
5653 - (const_string "alu_shift_reg")))]
5654 + (const_string "alu_shift_reg")))
5655 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
5656 + (eq_attr "fix_janus" "yes"))
5661 (define_insn "*arm_notsi_shiftsi_compare0"
5662 @@ -3399,9 +3550,14 @@
5664 [(set_attr "conds" "set")
5665 (set_attr "shift" "1")
5666 + (set_attr "insn" "mvn")
5667 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
5668 (const_string "alu_shift")
5669 - (const_string "alu_shift_reg")))]
5670 + (const_string "alu_shift_reg")))
5671 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
5672 + (eq_attr "fix_janus" "yes"))
5677 (define_insn "*arm_not_shiftsi_compare0_scratch"
5678 @@ -3415,9 +3571,14 @@
5680 [(set_attr "conds" "set")
5681 (set_attr "shift" "1")
5682 + (set_attr "insn" "mvn")
5683 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
5684 (const_string "alu_shift")
5685 - (const_string "alu_shift_reg")))]
5686 + (const_string "alu_shift_reg")))
5687 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
5688 + (eq_attr "fix_janus" "yes"))
5693 ;; We don't really have extzv, but defining this using shifts helps
5694 @@ -3550,12 +3711,12 @@
5695 (define_expand "negdf2"
5696 [(set (match_operand:DF 0 "s_register_operand" "")
5697 (neg:DF (match_operand:DF 1 "s_register_operand" "")))]
5698 - "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
5699 + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
5702 ;; abssi2 doesn't really clobber the condition codes if a different register
5703 ;; is being set. To keep things simple, assume during rtl manipulations that
5704 -;; it does, but tell the final scan operator the truth. Similarly for
5705 +;; it does, and the splitter will eliminate it. Similarly for
5708 (define_expand "abssi2"
5709 @@ -3567,22 +3728,28 @@
5712 operands[2] = gen_rtx_SCRATCH (SImode);
5713 + else if (TARGET_NO_SINGLE_COND_EXEC)
5715 + emit_insn(gen_rtx_SET(VOIDmode, operands[0],
5716 + gen_rtx_ABS(SImode, operands[1])));
5720 operands[2] = gen_rtx_REG (CCmode, CC_REGNUM);
5723 (define_insn "*arm_abssi2"
5724 - [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
5725 - (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
5726 + [(set (match_operand:SI 0 "s_register_operand" "=r")
5727 + (abs:SI (match_operand:SI 1 "s_register_operand" "r")))
5728 (clobber (reg:CC CC_REGNUM))]
5731 - cmp\\t%0, #0\;rsblt\\t%0, %0, #0
5732 - eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31"
5733 - [(set_attr "conds" "clob,*")
5734 - (set_attr "shift" "1")
5735 + "TARGET_32BIT && !TARGET_NO_SINGLE_COND_EXEC"
5737 + [(set_attr "shift" "1")
5738 ;; predicable can't be set based on the variant, so left as no
5739 - (set_attr "length" "8")]
5740 + (set (attr "length")
5741 + (if_then_else (eq_attr "is_thumb" "yes")
5746 (define_insn_and_split "*thumb1_abssi2"
5747 @@ -3600,17 +3767,17 @@
5750 (define_insn "*arm_neg_abssi2"
5751 - [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
5752 - (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
5753 + [(set (match_operand:SI 0 "s_register_operand" "=r")
5754 + (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "r"))))
5755 (clobber (reg:CC CC_REGNUM))]
5758 - cmp\\t%0, #0\;rsbgt\\t%0, %0, #0
5759 - eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31"
5760 - [(set_attr "conds" "clob,*")
5761 - (set_attr "shift" "1")
5762 + "TARGET_32BIT && !TARGET_NO_SINGLE_COND_EXEC"
5764 + [(set_attr "shift" "1")
5765 ;; predicable can't be set based on the variant, so left as no
5766 - (set_attr "length" "8")]
5767 + (set (attr "length")
5768 + (if_then_else (eq_attr "is_thumb" "yes")
5773 (define_insn_and_split "*thumb1_neg_abssi2"
5774 @@ -3627,6 +3794,93 @@
5775 [(set_attr "length" "6")]
5778 +;; Simplified version for when avoiding conditional execution
5779 +(define_insn "*arm_nocond_abssi2"
5780 + [(set (match_operand:SI 0 "s_register_operand" "=&r")
5781 + (abs:SI (match_operand:SI 1 "s_register_operand" "r")))]
5782 + "TARGET_32BIT && TARGET_NO_SINGLE_COND_EXEC"
5784 + [(set_attr "shift" "1")
5785 + (set_attr "length" "8")
5786 + (set_attr "predicable" "yes")]
5789 +(define_insn "*arm_nocond_neg_abssi2"
5790 + [(set (match_operand:SI 0 "s_register_operand" "=&r")
5791 + (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "r"))))]
5792 + "TARGET_32BIT && TARGET_NO_SINGLE_COND_EXEC"
5794 + [(set_attr "shift" "1")
5795 + (set_attr "length" "8")
5796 + (set_attr "predicable" "yes")]
5799 +;; Splitters for ABS patterns.
5802 + [(set (match_operand:SI 0 "s_register_operand" "")
5803 + (abs:SI (match_operand:SI 1 "s_register_operand" "")))
5804 + (clobber (reg:CC CC_REGNUM))]
5805 + "TARGET_32BIT && reload_completed && rtx_equal_p(operands[0], operands[1])"
5806 + [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0)))
5807 + (cond_exec (lt (reg:CC CC_REGNUM) (const_int 0))
5808 + (set (match_dup 0) (neg:SI (match_dup 1))))]
5812 + [(set (match_operand:SI 0 "s_register_operand" "")
5813 + (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" ""))))
5814 + (clobber (reg:CC CC_REGNUM))]
5815 + "TARGET_32BIT && reload_completed && rtx_equal_p(operands[0], operands[1])"
5816 + [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0)))
5817 + (cond_exec (gt (reg:CC CC_REGNUM) (const_int 0))
5818 + (set (match_dup 0) (neg:SI (match_dup 1))))]
5821 +;; GCC does not add/remove clobbers when matching splitters, so we need
5822 +;; variants with and without the CC clobber.
5824 + [(set (match_operand:SI 0 "s_register_operand" "")
5825 + (abs:SI (match_operand:SI 1 "s_register_operand" "")))]
5826 + "TARGET_32BIT && reload_completed && !rtx_equal_p(operands[0], operands[1])"
5827 + [(set (match_dup 0) (xor:SI (ashiftrt:SI (match_dup 1) (const_int 31))
5829 + (set (match_dup 0) (minus:SI (match_dup 0)
5830 + (ashiftrt:SI (match_dup 1) (const_int 31))))]
5834 + [(set (match_operand:SI 0 "s_register_operand" "")
5835 + (abs:SI (match_operand:SI 1 "s_register_operand" "")))
5836 + (clobber (reg:CC CC_REGNUM))]
5837 + "TARGET_32BIT && reload_completed && !rtx_equal_p(operands[0], operands[1])"
5838 + [(set (match_dup 0) (xor:SI (ashiftrt:SI (match_dup 1) (const_int 31))
5840 + (set (match_dup 0) (minus:SI (match_dup 0)
5841 + (ashiftrt:SI (match_dup 1) (const_int 31))))]
5845 + [(set (match_operand:SI 0 "s_register_operand" "")
5846 + (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" ""))))]
5847 + "TARGET_32BIT && reload_completed && !rtx_equal_p(operands[0], operands[1])"
5848 + [(set (match_dup 0) (xor:SI (ashiftrt:SI (match_dup 1) (const_int 31))
5850 + (set (match_dup 0) (minus:SI (ashiftrt:SI (match_dup 1) (const_int 31))
5855 + [(set (match_operand:SI 0 "s_register_operand" "")
5856 + (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" ""))))
5857 + (clobber (reg:CC CC_REGNUM))]
5858 + "TARGET_32BIT && reload_completed && !rtx_equal_p(operands[0], operands[1])"
5859 + [(set (match_dup 0) (xor:SI (ashiftrt:SI (match_dup 1) (const_int 31))
5861 + (set (match_dup 0) (minus:SI (ashiftrt:SI (match_dup 1) (const_int 31))
5865 (define_expand "abssf2"
5866 [(set (match_operand:SF 0 "s_register_operand" "")
5867 (abs:SF (match_operand:SF 1 "s_register_operand" "")))]
5868 @@ -3636,7 +3890,7 @@
5869 (define_expand "absdf2"
5870 [(set (match_operand:DF 0 "s_register_operand" "")
5871 (abs:DF (match_operand:DF 1 "s_register_operand" "")))]
5872 - "TARGET_32BIT && TARGET_HARD_FLOAT"
5873 + "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
5876 (define_expand "sqrtsf2"
5877 @@ -3648,7 +3902,7 @@
5878 (define_expand "sqrtdf2"
5879 [(set (match_operand:DF 0 "s_register_operand" "")
5880 (sqrt:DF (match_operand:DF 1 "s_register_operand" "")))]
5881 - "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
5882 + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
5885 (define_insn_and_split "one_cmpldi2"
5886 @@ -3682,7 +3936,8 @@
5887 (not:SI (match_operand:SI 1 "s_register_operand" "r")))]
5890 - [(set_attr "predicable" "yes")]
5891 + [(set_attr "predicable" "yes")
5892 + (set_attr "insn" "mvn")]
5895 (define_insn "*thumb1_one_cmplsi2"
5896 @@ -3690,7 +3945,8 @@
5897 (not:SI (match_operand:SI 1 "register_operand" "l")))]
5900 - [(set_attr "length" "2")]
5901 + [(set_attr "length" "2")
5902 + (set_attr "insn" "mvn")]
5905 (define_insn "*notsi_compare0"
5906 @@ -3701,7 +3957,8 @@
5907 (not:SI (match_dup 1)))]
5910 - [(set_attr "conds" "set")]
5911 + [(set_attr "conds" "set")
5912 + (set_attr "insn" "mvn")]
5915 (define_insn "*notsi_compare0_scratch"
5916 @@ -3711,11 +3968,40 @@
5917 (clobber (match_scratch:SI 0 "=r"))]
5920 - [(set_attr "conds" "set")]
5921 + [(set_attr "conds" "set")
5922 + (set_attr "insn" "mvn")]
5925 ;; Fixed <--> Floating conversion insns
5927 +(define_expand "floatsihf2"
5928 + [(set (match_operand:HF 0 "general_operand" "")
5929 + (float:HF (match_operand:SI 1 "general_operand" "")))]
5933 + rtx op1 = gen_reg_rtx (SFmode);
5934 + expand_float (op1, operands[1], 0);
5935 + op1 = convert_to_mode (HFmode, op1, 0);
5936 + emit_move_insn (operands[0], op1);
5941 +(define_expand "floatdihf2"
5942 + [(set (match_operand:HF 0 "general_operand" "")
5943 + (float:HF (match_operand:DI 1 "general_operand" "")))]
5947 + rtx op1 = gen_reg_rtx (SFmode);
5948 + expand_float (op1, operands[1], 0);
5949 + op1 = convert_to_mode (HFmode, op1, 0);
5950 + emit_move_insn (operands[0], op1);
5955 (define_expand "floatsisf2"
5956 [(set (match_operand:SF 0 "s_register_operand" "")
5957 (float:SF (match_operand:SI 1 "s_register_operand" "")))]
5958 @@ -3731,7 +4017,7 @@
5959 (define_expand "floatsidf2"
5960 [(set (match_operand:DF 0 "s_register_operand" "")
5961 (float:DF (match_operand:SI 1 "s_register_operand" "")))]
5962 - "TARGET_32BIT && TARGET_HARD_FLOAT"
5963 + "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
5965 if (TARGET_MAVERICK)
5967 @@ -3740,6 +4026,30 @@
5971 +(define_expand "fix_trunchfsi2"
5972 + [(set (match_operand:SI 0 "general_operand" "")
5973 + (fix:SI (fix:HF (match_operand:HF 1 "general_operand" ""))))]
5977 + rtx op1 = convert_to_mode (SFmode, operands[1], 0);
5978 + expand_fix (operands[0], op1, 0);
5983 +(define_expand "fix_trunchfdi2"
5984 + [(set (match_operand:DI 0 "general_operand" "")
5985 + (fix:DI (fix:HF (match_operand:HF 1 "general_operand" ""))))]
5989 + rtx op1 = convert_to_mode (SFmode, operands[1], 0);
5990 + expand_fix (operands[0], op1, 0);
5995 (define_expand "fix_truncsfsi2"
5996 [(set (match_operand:SI 0 "s_register_operand" "")
5997 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))]
5998 @@ -3759,7 +4069,7 @@
5999 (define_expand "fix_truncdfsi2"
6000 [(set (match_operand:SI 0 "s_register_operand" "")
6001 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))]
6002 - "TARGET_32BIT && TARGET_HARD_FLOAT"
6003 + "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
6005 if (TARGET_MAVERICK)
6007 @@ -3776,9 +4086,25 @@
6008 [(set (match_operand:SF 0 "s_register_operand" "")
6010 (match_operand:DF 1 "s_register_operand" "")))]
6011 - "TARGET_32BIT && TARGET_HARD_FLOAT"
6012 + "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
6016 +/* DFmode -> HFmode conversions have to go through SFmode. */
6017 +(define_expand "truncdfhf2"
6018 + [(set (match_operand:HF 0 "general_operand" "")
6019 + (float_truncate:HF
6020 + (match_operand:DF 1 "general_operand" "")))]
6025 + op1 = convert_to_mode (SFmode, operands[1], 0);
6026 + op1 = convert_to_mode (HFmode, op1, 0);
6027 + emit_move_insn (operands[0], op1);
6032 ;; Zero and sign extension instructions.
6034 @@ -3800,6 +4126,7 @@
6035 return \"mov%?\\t%R0, #0\";
6037 [(set_attr "length" "8")
6038 + (set_attr "insn" "mov")
6039 (set_attr "predicable" "yes")]
6042 @@ -3843,6 +4170,7 @@
6044 [(set_attr "length" "8")
6045 (set_attr "shift" "1")
6046 + (set_attr "insn" "mov")
6047 (set_attr "predicable" "yes")]
6050 @@ -4123,6 +4451,28 @@
6054 +(define_code_iterator ior_xor [ior xor])
6057 + [(set (match_operand:SI 0 "s_register_operand" "")
6058 + (ior_xor:SI (and:SI (ashift:SI
6059 + (match_operand:SI 1 "s_register_operand" "")
6060 + (match_operand:SI 2 "const_int_operand" ""))
6061 + (match_operand:SI 3 "const_int_operand" ""))
6063 + (match_operator 5 "subreg_lowpart_operator"
6064 + [(match_operand:SI 4 "s_register_operand" "")]))))]
6066 + && (INTVAL (operands[3])
6067 + == (GET_MODE_MASK (GET_MODE (operands[5]))
6068 + & (GET_MODE_MASK (GET_MODE (operands[5]))
6069 + << (INTVAL (operands[2])))))"
6070 + [(set (match_dup 0) (ior_xor:SI (ashift:SI (match_dup 1) (match_dup 2))
6072 + (set (match_dup 0) (zero_extend:SI (match_dup 5)))]
6073 + "operands[5] = gen_lowpart (GET_MODE (operands[5]), operands[0]);"
6076 (define_insn "*compareqi_eq0"
6077 [(set (reg:CC_Z CC_REGNUM)
6078 (compare:CC_Z (match_operand:QI 0 "s_register_operand" "r")
6079 @@ -4639,9 +4989,24 @@
6080 (define_expand "extendsfdf2"
6081 [(set (match_operand:DF 0 "s_register_operand" "")
6082 (float_extend:DF (match_operand:SF 1 "s_register_operand" "")))]
6083 - "TARGET_32BIT && TARGET_HARD_FLOAT"
6084 + "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
6088 +/* HFmode -> DFmode conversions have to go through SFmode. */
6089 +(define_expand "extendhfdf2"
6090 + [(set (match_operand:DF 0 "general_operand" "")
6091 + (float_extend:DF (match_operand:HF 1 "general_operand" "")))]
6096 + op1 = convert_to_mode (SFmode, operands[1], 0);
6097 + op1 = convert_to_mode (DFmode, op1, 0);
6098 + emit_insn (gen_movdf (operands[0], op1));
6103 ;; Move insns (including loads and stores)
6105 @@ -4877,6 +5242,7 @@
6107 [(set_attr "length" "4,4,6,2,2,6,4,4")
6108 (set_attr "type" "*,*,*,load2,store2,load2,store2,*")
6109 + (set_attr "insn" "*,mov,*,*,*,*,*,mov")
6110 (set_attr "pool_range" "*,*,*,*,*,1020,*,*")]
6113 @@ -4903,14 +5269,6 @@
6114 optimize && can_create_pseudo_p ());
6118 - if (TARGET_USE_MOVT && !target_word_relocations
6119 - && GET_CODE (operands[1]) == SYMBOL_REF
6120 - && !flag_pic && !arm_tls_referenced_p (operands[1]))
6122 - arm_emit_movpair (operands[0], operands[1]);
6126 else /* TARGET_THUMB1... */
6128 @@ -4984,18 +5342,9 @@
6129 (set_attr "length" "4")]
6132 -(define_insn "*arm_movw"
6133 - [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
6134 - (high:SI (match_operand:SI 1 "general_operand" "i")))]
6136 - "movw%?\t%0, #:lower16:%c1"
6137 - [(set_attr "predicable" "yes")
6138 - (set_attr "length" "4")]
6141 (define_insn "*arm_movsi_insn"
6142 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m")
6143 - (match_operand:SI 1 "general_operand" "rk, I,K,N,mi,rk"))]
6144 + (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk"))]
6145 "TARGET_ARM && ! TARGET_IWMMXT
6146 && !(TARGET_HARD_FLOAT && TARGET_VFP)
6147 && ( register_operand (operands[0], SImode)
6148 @@ -5008,6 +5357,7 @@
6151 [(set_attr "type" "*,*,*,*,load1,store1")
6152 + (set_attr "insn" "mov,mov,mvn,mov,*,*")
6153 (set_attr "predicable" "yes")
6154 (set_attr "pool_range" "*,*,*,*,4096,*")
6155 (set_attr "neg_pool_range" "*,*,*,*,4084,*")]
6156 @@ -5027,6 +5377,19 @@
6161 + [(set (match_operand:SI 0 "arm_general_register_operand" "")
6162 + (match_operand:SI 1 "general_operand" ""))]
6164 + && TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF
6165 + && !flag_pic && !target_word_relocations
6166 + && !arm_tls_referenced_p (operands[1])"
6167 + [(clobber (const_int 0))]
6169 + arm_emit_movpair (operands[0], operands[1]);
6173 (define_insn "*thumb1_movsi_insn"
6174 [(set (match_operand:SI 0 "nonimmediate_operand" "=l,l,l,l,l,>,l, m,*lhk")
6175 (match_operand:SI 1 "general_operand" "l, I,J,K,>,l,mi,l,*lhk"))]
6176 @@ -5065,7 +5428,7 @@
6177 (set (match_dup 0) (ashift:SI (match_dup 0) (match_dup 2)))]
6180 - unsigned HOST_WIDE_INT val = INTVAL (operands[1]);
6181 + unsigned HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffffffffu;
6182 unsigned HOST_WIDE_INT mask = 0xff;
6185 @@ -5627,6 +5990,7 @@
6186 ldr%(h%)\\t%0, %1\\t%@ movhi"
6187 [(set_attr "type" "*,*,store1,load1")
6188 (set_attr "predicable" "yes")
6189 + (set_attr "insn" "mov,mvn,*,*")
6190 (set_attr "pool_range" "*,*,*,256")
6191 (set_attr "neg_pool_range" "*,*,*,244")]
6193 @@ -5638,7 +6002,8 @@
6195 mov%?\\t%0, %1\\t%@ movhi
6196 mvn%?\\t%0, #%B1\\t%@ movhi"
6197 - [(set_attr "predicable" "yes")]
6198 + [(set_attr "predicable" "yes")
6199 + (set_attr "insn" "mov,mvn")]
6202 (define_expand "thumb_movhi_clobber"
6203 @@ -5769,6 +6134,7 @@
6206 [(set_attr "type" "*,*,load1,store1")
6207 + (set_attr "insn" "mov,mvn,*,*")
6208 (set_attr "predicable" "yes")]
6211 @@ -5787,9 +6153,111 @@
6213 [(set_attr "length" "2")
6214 (set_attr "type" "*,load1,store1,*,*,*")
6215 + (set_attr "insn" "*,*,*,mov,mov,mov")
6216 (set_attr "pool_range" "*,32,*,*,*,*")]
6220 +(define_expand "movhf"
6221 + [(set (match_operand:HF 0 "general_operand" "")
6222 + (match_operand:HF 1 "general_operand" ""))]
6227 + if (GET_CODE (operands[0]) == MEM)
6228 + operands[1] = force_reg (HFmode, operands[1]);
6230 + else /* TARGET_THUMB1 */
6232 + if (can_create_pseudo_p ())
6234 + if (GET_CODE (operands[0]) != REG)
6235 + operands[1] = force_reg (HFmode, operands[1]);
6241 +(define_insn "*arm32_movhf"
6242 + [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,r,r")
6243 + (match_operand:HF 1 "general_operand" " m,r,r,F"))]
6244 + "TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_FP16)
6245 + && ( s_register_operand (operands[0], HFmode)
6246 + || s_register_operand (operands[1], HFmode))"
6248 + switch (which_alternative)
6250 + case 0: /* ARM register from memory */
6251 + return \"ldr%(h%)\\t%0, %1\\t%@ __fp16\";
6252 + case 1: /* memory from ARM register */
6253 + return \"str%(h%)\\t%1, %0\\t%@ __fp16\";
6254 + case 2: /* ARM register from ARM register */
6255 + return \"mov%?\\t%0, %1\\t%@ __fp16\";
6256 + case 3: /* ARM register from constant */
6258 + REAL_VALUE_TYPE r;
6262 + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
6263 + bits = real_to_target (NULL, &r, HFmode);
6264 + ops[0] = operands[0];
6265 + ops[1] = GEN_INT (bits);
6266 + ops[2] = GEN_INT (bits & 0xff00);
6267 + ops[3] = GEN_INT (bits & 0x00ff);
6269 + if (arm_arch_thumb2)
6270 + output_asm_insn (\"movw%?\\t%0, %1\", ops);
6272 + output_asm_insn (\"mov%?\\t%0, %2\;orr%?\\t%0, %0, %3\", ops);
6276 + gcc_unreachable ();
6279 + [(set_attr "conds" "unconditional")
6280 + (set_attr "type" "load1,store1,*,*")
6281 + (set_attr "length" "4,4,4,8")
6282 + (set_attr "predicable" "yes")
6286 +(define_insn "*thumb1_movhf"
6287 + [(set (match_operand:HF 0 "nonimmediate_operand" "=l,l,m,*r,*h")
6288 + (match_operand:HF 1 "general_operand" "l,mF,l,*h,*r"))]
6290 + && ( s_register_operand (operands[0], HFmode)
6291 + || s_register_operand (operands[1], HFmode))"
6293 + switch (which_alternative)
6298 + gcc_assert (GET_CODE(operands[1]) == MEM);
6299 + addr = XEXP (operands[1], 0);
6300 + if (GET_CODE (addr) == LABEL_REF
6301 + || (GET_CODE (addr) == CONST
6302 + && GET_CODE (XEXP (addr, 0)) == PLUS
6303 + && GET_CODE (XEXP (XEXP (addr, 0), 0)) == LABEL_REF
6304 + && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT))
6306 + /* Constant pool entry. */
6307 + return \"ldr\\t%0, %1\";
6309 + return \"ldrh\\t%0, %1\";
6311 + case 2: return \"strh\\t%1, %0\";
6312 + default: return \"mov\\t%0, %1\";
6315 + [(set_attr "length" "2")
6316 + (set_attr "type" "*,load1,store1,*,*")
6317 + (set_attr "pool_range" "*,1020,*,*,*")]
6320 (define_expand "movsf"
6321 [(set (match_operand:SF 0 "general_operand" "")
6322 (match_operand:SF 1 "general_operand" ""))]
6323 @@ -5842,6 +6310,7 @@
6324 [(set_attr "length" "4,4,4")
6325 (set_attr "predicable" "yes")
6326 (set_attr "type" "*,load1,store1")
6327 + (set_attr "insn" "mov,*,*")
6328 (set_attr "pool_range" "*,4096,*")
6329 (set_attr "neg_pool_range" "*,4084,*")]
6331 @@ -6297,7 +6766,7 @@
6332 (match_operand:BLK 1 "general_operand" "")
6333 (match_operand:SI 2 "const_int_operand" "")
6334 (match_operand:SI 3 "const_int_operand" "")]
6336 + "TARGET_EITHER && !low_irq_latency"
6340 @@ -7476,7 +7945,7 @@
6341 (define_expand "cmpdf"
6342 [(match_operand:DF 0 "s_register_operand" "")
6343 (match_operand:DF 1 "arm_float_compare_operand" "")]
6344 - "TARGET_32BIT && TARGET_HARD_FLOAT"
6345 + "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
6347 arm_compare_op0 = operands[0];
6348 arm_compare_op1 = operands[1];
6349 @@ -7507,7 +7976,11 @@
6350 (set_attr "shift" "1")
6351 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
6352 (const_string "alu_shift")
6353 - (const_string "alu_shift_reg")))]
6354 + (const_string "alu_shift_reg")))
6355 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
6356 + (eq_attr "fix_janus" "yes"))
6361 (define_insn "*arm_cmpsi_shiftsi_swp"
6362 @@ -7522,7 +7995,11 @@
6363 (set_attr "shift" "1")
6364 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
6365 (const_string "alu_shift")
6366 - (const_string "alu_shift_reg")))]
6367 + (const_string "alu_shift_reg")))
6368 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
6369 + (eq_attr "fix_janus" "yes"))
6374 (define_insn "*arm_cmpsi_negshiftsi_si"
6375 @@ -7537,7 +8014,11 @@
6376 [(set_attr "conds" "set")
6377 (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
6378 (const_string "alu_shift")
6379 - (const_string "alu_shift_reg")))]
6380 + (const_string "alu_shift_reg")))
6381 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
6382 + (eq_attr "fix_janus" "yes"))
6387 ;; Cirrus SF compare instruction
6388 @@ -7879,77 +8360,77 @@
6389 (define_expand "seq"
6390 [(set (match_operand:SI 0 "s_register_operand" "")
6391 (eq:SI (match_dup 1) (const_int 0)))]
6393 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
6394 "operands[1] = arm_gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1);"
6397 (define_expand "sne"
6398 [(set (match_operand:SI 0 "s_register_operand" "")
6399 (ne:SI (match_dup 1) (const_int 0)))]
6401 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
6402 "operands[1] = arm_gen_compare_reg (NE, arm_compare_op0, arm_compare_op1);"
6405 (define_expand "sgt"
6406 [(set (match_operand:SI 0 "s_register_operand" "")
6407 (gt:SI (match_dup 1) (const_int 0)))]
6409 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
6410 "operands[1] = arm_gen_compare_reg (GT, arm_compare_op0, arm_compare_op1);"
6413 (define_expand "sle"
6414 [(set (match_operand:SI 0 "s_register_operand" "")
6415 (le:SI (match_dup 1) (const_int 0)))]
6417 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
6418 "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);"
6421 (define_expand "sge"
6422 [(set (match_operand:SI 0 "s_register_operand" "")
6423 (ge:SI (match_dup 1) (const_int 0)))]
6425 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
6426 "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);"
6429 (define_expand "slt"
6430 [(set (match_operand:SI 0 "s_register_operand" "")
6431 (lt:SI (match_dup 1) (const_int 0)))]
6433 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
6434 "operands[1] = arm_gen_compare_reg (LT, arm_compare_op0, arm_compare_op1);"
6437 (define_expand "sgtu"
6438 [(set (match_operand:SI 0 "s_register_operand" "")
6439 (gtu:SI (match_dup 1) (const_int 0)))]
6441 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
6442 "operands[1] = arm_gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1);"
6445 (define_expand "sleu"
6446 [(set (match_operand:SI 0 "s_register_operand" "")
6447 (leu:SI (match_dup 1) (const_int 0)))]
6449 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
6450 "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);"
6453 (define_expand "sgeu"
6454 [(set (match_operand:SI 0 "s_register_operand" "")
6455 (geu:SI (match_dup 1) (const_int 0)))]
6457 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
6458 "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);"
6461 (define_expand "sltu"
6462 [(set (match_operand:SI 0 "s_register_operand" "")
6463 (ltu:SI (match_dup 1) (const_int 0)))]
6465 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
6466 "operands[1] = arm_gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1);"
6469 (define_expand "sunordered"
6470 [(set (match_operand:SI 0 "s_register_operand" "")
6471 (unordered:SI (match_dup 1) (const_int 0)))]
6472 - "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
6473 + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP) && !TARGET_NO_COND_EXEC"
6474 "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0,
6477 @@ -7957,7 +8438,7 @@
6478 (define_expand "sordered"
6479 [(set (match_operand:SI 0 "s_register_operand" "")
6480 (ordered:SI (match_dup 1) (const_int 0)))]
6481 - "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
6482 + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP) && !TARGET_NO_COND_EXEC"
6483 "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0,
6486 @@ -7965,7 +8446,7 @@
6487 (define_expand "sungt"
6488 [(set (match_operand:SI 0 "s_register_operand" "")
6489 (ungt:SI (match_dup 1) (const_int 0)))]
6490 - "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
6491 + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP) && !TARGET_NO_COND_EXEC"
6492 "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0,
6495 @@ -7973,7 +8454,7 @@
6496 (define_expand "sunge"
6497 [(set (match_operand:SI 0 "s_register_operand" "")
6498 (unge:SI (match_dup 1) (const_int 0)))]
6499 - "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
6500 + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP) && !TARGET_NO_COND_EXEC"
6501 "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0,
6504 @@ -7981,7 +8462,7 @@
6505 (define_expand "sunlt"
6506 [(set (match_operand:SI 0 "s_register_operand" "")
6507 (unlt:SI (match_dup 1) (const_int 0)))]
6508 - "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
6509 + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP) && !TARGET_NO_COND_EXEC"
6510 "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0,
6513 @@ -7989,7 +8470,7 @@
6514 (define_expand "sunle"
6515 [(set (match_operand:SI 0 "s_register_operand" "")
6516 (unle:SI (match_dup 1) (const_int 0)))]
6517 - "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
6518 + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP) && !TARGET_NO_COND_EXEC"
6519 "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0,
6522 @@ -8018,6 +8499,7 @@
6524 "mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
6525 [(set_attr "conds" "use")
6526 + (set_attr "insn" "mov")
6527 (set_attr "length" "8")]
6530 @@ -8028,6 +8510,7 @@
6532 "mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
6533 [(set_attr "conds" "use")
6534 + (set_attr "insn" "mov")
6535 (set_attr "length" "8")]
6538 @@ -8038,6 +8521,7 @@
6540 "mov%D1\\t%0, #0\;mvn%d1\\t%0, #1"
6541 [(set_attr "conds" "use")
6542 + (set_attr "insn" "mov")
6543 (set_attr "length" "8")]
6546 @@ -8241,7 +8725,7 @@
6547 (if_then_else:SI (match_operand 1 "arm_comparison_operator" "")
6548 (match_operand:SI 2 "arm_not_operand" "")
6549 (match_operand:SI 3 "arm_not_operand" "")))]
6551 + "TARGET_32BIT && !TARGET_NO_COND_EXEC"
6554 enum rtx_code code = GET_CODE (operands[1]);
6555 @@ -8260,7 +8744,7 @@
6556 (if_then_else:SF (match_operand 1 "arm_comparison_operator" "")
6557 (match_operand:SF 2 "s_register_operand" "")
6558 (match_operand:SF 3 "nonmemory_operand" "")))]
6559 - "TARGET_32BIT && TARGET_HARD_FLOAT"
6560 + "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_NO_COND_EXEC"
6563 enum rtx_code code = GET_CODE (operands[1]);
6564 @@ -8285,7 +8769,7 @@
6565 (if_then_else:DF (match_operand 1 "arm_comparison_operator" "")
6566 (match_operand:DF 2 "s_register_operand" "")
6567 (match_operand:DF 3 "arm_float_add_operand" "")))]
6568 - "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP)"
6569 + "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE) && !TARGET_NO_COND_EXEC"
6572 enum rtx_code code = GET_CODE (operands[1]);
6573 @@ -8317,7 +8801,8 @@
6574 mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
6575 mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2"
6576 [(set_attr "length" "4,4,4,4,8,8,8,8")
6577 - (set_attr "conds" "use")]
6578 + (set_attr "conds" "use")
6579 + (set_attr "insn" "mov,mvn,mov,mvn,mov,mov,mvn,mvn")]
6582 (define_insn "*movsfcc_soft_insn"
6583 @@ -8330,7 +8815,8 @@
6587 - [(set_attr "conds" "use")]
6588 + [(set_attr "conds" "use")
6589 + (set_attr "insn" "mov")]
6593 @@ -8733,7 +9219,7 @@
6594 [(match_operand 1 "cc_register" "") (const_int 0)])
6597 - "TARGET_ARM && USE_RETURN_INSN (TRUE)"
6598 + "TARGET_ARM && USE_RETURN_INSN (TRUE) && !TARGET_NO_COND_EXEC"
6601 if (arm_ccfsm_state == 2)
6602 @@ -8754,7 +9240,7 @@
6603 [(match_operand 1 "cc_register" "") (const_int 0)])
6606 - "TARGET_ARM && USE_RETURN_INSN (TRUE)"
6607 + "TARGET_ARM && USE_RETURN_INSN (TRUE) && !TARGET_NO_COND_EXEC"
6610 if (arm_ccfsm_state == 2)
6611 @@ -9072,7 +9558,11 @@
6612 (set_attr "shift" "4")
6613 (set (attr "type") (if_then_else (match_operand 5 "const_int_operand" "")
6614 (const_string "alu_shift")
6615 - (const_string "alu_shift_reg")))]
6616 + (const_string "alu_shift_reg")))
6617 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
6618 + (eq_attr "fix_janus" "yes"))
6624 @@ -9110,7 +9600,11 @@
6625 (set_attr "shift" "4")
6626 (set (attr "type") (if_then_else (match_operand 5 "const_int_operand" "")
6627 (const_string "alu_shift")
6628 - (const_string "alu_shift_reg")))]
6629 + (const_string "alu_shift_reg")))
6630 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
6631 + (eq_attr "fix_janus" "yes"))
6636 (define_insn "*arith_shiftsi_compare0_scratch"
6637 @@ -9128,7 +9622,11 @@
6638 (set_attr "shift" "4")
6639 (set (attr "type") (if_then_else (match_operand 5 "const_int_operand" "")
6640 (const_string "alu_shift")
6641 - (const_string "alu_shift_reg")))]
6642 + (const_string "alu_shift_reg")))
6643 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
6644 + (eq_attr "fix_janus" "yes"))
6649 (define_insn "*sub_shiftsi"
6650 @@ -9143,7 +9641,11 @@
6651 (set_attr "shift" "3")
6652 (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
6653 (const_string "alu_shift")
6654 - (const_string "alu_shift_reg")))]
6655 + (const_string "alu_shift_reg")))
6656 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
6657 + (eq_attr "fix_janus" "yes"))
6662 (define_insn "*sub_shiftsi_compare0"
6663 @@ -9163,7 +9665,11 @@
6664 (set_attr "shift" "3")
6665 (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
6666 (const_string "alu_shift")
6667 - (const_string "alu_shift_reg")))]
6668 + (const_string "alu_shift_reg")))
6669 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
6670 + (eq_attr "fix_janus" "yes"))
6675 (define_insn "*sub_shiftsi_compare0_scratch"
6676 @@ -9181,7 +9687,11 @@
6677 (set_attr "shift" "3")
6678 (set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
6679 (const_string "alu_shift")
6680 - (const_string "alu_shift_reg")))]
6681 + (const_string "alu_shift_reg")))
6682 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
6683 + (eq_attr "fix_janus" "yes"))
6689 @@ -9194,6 +9704,7 @@
6691 "mov%D1\\t%0, #0\;and%d1\\t%0, %2, #1"
6692 [(set_attr "conds" "use")
6693 + (set_attr "insn" "mov")
6694 (set_attr "length" "8")]
6697 @@ -9207,6 +9718,7 @@
6699 mov%D2\\t%0, %1\;orr%d2\\t%0, %1, #1"
6700 [(set_attr "conds" "use")
6701 + (set_attr "insn" "orr")
6702 (set_attr "length" "4,8")]
6705 @@ -9216,7 +9728,7 @@
6706 [(match_operand:SI 2 "s_register_operand" "r,r")
6707 (match_operand:SI 3 "arm_add_operand" "rI,L")]))
6708 (clobber (reg:CC CC_REGNUM))]
6710 + "TARGET_ARM && !TARGET_NO_COND_EXEC"
6712 if (operands[3] == const0_rtx)
6714 @@ -9271,6 +9783,7 @@
6717 [(set_attr "conds" "use")
6718 + (set_attr "insn" "mov")
6719 (set_attr "length" "4,4,8")]
6722 @@ -9282,7 +9795,7 @@
6723 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
6724 (match_operand:SI 1 "s_register_operand" "0,?r")]))
6725 (clobber (reg:CC CC_REGNUM))]
6727 + "TARGET_ARM && !TARGET_NO_SINGLE_COND_EXEC"
6729 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
6730 return \"%i5\\t%0, %1, %2, lsr #31\";
6731 @@ -9678,7 +10191,7 @@
6732 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
6733 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))
6734 (clobber (reg:CC CC_REGNUM))]
6736 + "TARGET_ARM && !TARGET_NO_COND_EXEC"
6738 if (GET_CODE (operands[5]) == LT
6739 && (operands[4] == const0_rtx))
6740 @@ -9744,7 +10257,7 @@
6741 (match_operand:SI 3 "arm_add_operand" "rIL,rIL"))
6742 (match_operand:SI 1 "arm_rhs_operand" "0,?rI")))
6743 (clobber (reg:CC CC_REGNUM))]
6745 + "TARGET_ARM && !TARGET_NO_SINGLE_COND_EXEC"
6747 [(set_attr "conds" "clob")
6748 (set_attr "length" "8,12")]
6749 @@ -9780,7 +10293,7 @@
6750 (match_operand:SI 2 "s_register_operand" "r,r")
6751 (match_operand:SI 3 "arm_add_operand" "rIL,rIL"))))
6752 (clobber (reg:CC CC_REGNUM))]
6754 + "TARGET_ARM && !TARGET_NO_SINGLE_COND_EXEC"
6756 [(set_attr "conds" "clob")
6757 (set_attr "length" "8,12")]
6758 @@ -9818,7 +10331,7 @@
6759 [(match_operand:SI 3 "s_register_operand" "r")
6760 (match_operand:SI 4 "arm_rhs_operand" "rI")])))
6761 (clobber (reg:CC CC_REGNUM))]
6763 + "TARGET_ARM && !TARGET_NO_SINGLE_COND_EXEC"
6765 [(set_attr "conds" "clob")
6766 (set_attr "length" "12")]
6767 @@ -9968,7 +10481,7 @@
6769 (match_operand:SI 2 "s_register_operand" "r,r"))))
6770 (clobber (reg:CC CC_REGNUM))]
6772 + "TARGET_ARM && !TARGET_NO_SINGLE_COND_EXEC"
6774 [(set_attr "conds" "clob")
6775 (set_attr "length" "8,12")]
6776 @@ -9987,6 +10500,7 @@
6777 mov%d4\\t%0, %1\;mvn%D4\\t%0, %2
6778 mvn%d4\\t%0, #%B1\;mvn%D4\\t%0, %2"
6779 [(set_attr "conds" "use")
6780 + (set_attr "insn" "mvn")
6781 (set_attr "length" "4,8,8")]
6784 @@ -10000,7 +10514,7 @@
6785 (match_operand:SI 2 "s_register_operand" "r,r"))
6786 (match_operand:SI 1 "arm_not_operand" "0,?rIK")))
6787 (clobber (reg:CC CC_REGNUM))]
6789 + "TARGET_ARM && !TARGET_NO_SINGLE_COND_EXEC"
6791 [(set_attr "conds" "clob")
6792 (set_attr "length" "8,12")]
6793 @@ -10019,6 +10533,7 @@
6794 mov%D4\\t%0, %1\;mvn%d4\\t%0, %2
6795 mvn%D4\\t%0, #%B1\;mvn%d4\\t%0, %2"
6796 [(set_attr "conds" "use")
6797 + (set_attr "insn" "mvn")
6798 (set_attr "length" "4,8,8")]
6801 @@ -10033,7 +10548,7 @@
6802 (match_operand:SI 3 "arm_rhs_operand" "rM,rM")])
6803 (match_operand:SI 1 "arm_not_operand" "0,?rIK")))
6804 (clobber (reg:CC CC_REGNUM))]
6806 + "TARGET_ARM && !TARGET_NO_SINGLE_COND_EXEC"
6808 [(set_attr "conds" "clob")
6809 (set_attr "length" "8,12")]
6810 @@ -10055,10 +10570,23 @@
6811 mvn%D5\\t%0, #%B1\;mov%d5\\t%0, %2%S4"
6812 [(set_attr "conds" "use")
6813 (set_attr "shift" "2")
6814 - (set_attr "length" "4,8,8")
6815 + (set_attr "insn" "mov")
6816 (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
6817 (const_string "alu_shift")
6818 - (const_string "alu_shift_reg")))]
6819 + (const_string "alu_shift_reg")))
6820 + (set_attr_alternative "length"
6821 + [(if_then_else (and (eq_attr "type" "alu_shift_reg")
6822 + (eq_attr "fix_janus" "yes"))
6825 + (if_then_else (and (eq_attr "type" "alu_shift_reg")
6826 + (eq_attr "fix_janus" "yes"))
6829 + (if_then_else (and (eq_attr "type" "alu_shift_reg")
6830 + (eq_attr "fix_janus" "yes"))
6835 (define_insn "*ifcompare_move_shift"
6836 @@ -10072,7 +10600,7 @@
6837 [(match_operand:SI 2 "s_register_operand" "r,r")
6838 (match_operand:SI 3 "arm_rhs_operand" "rM,rM")])))
6839 (clobber (reg:CC CC_REGNUM))]
6841 + "TARGET_ARM && !TARGET_NO_SINGLE_COND_EXEC"
6843 [(set_attr "conds" "clob")
6844 (set_attr "length" "8,12")]
6845 @@ -10094,10 +10622,24 @@
6846 mvn%d5\\t%0, #%B1\;mov%D5\\t%0, %2%S4"
6847 [(set_attr "conds" "use")
6848 (set_attr "shift" "2")
6849 - (set_attr "length" "4,8,8")
6850 + (set_attr "insn" "mov")
6851 (set (attr "type") (if_then_else (match_operand 3 "const_int_operand" "")
6852 (const_string "alu_shift")
6853 - (const_string "alu_shift_reg")))]
6854 + (const_string "alu_shift_reg")))
6855 + (set_attr_alternative "length"
6856 + [(if_then_else (and (eq_attr "type" "alu_shift_reg")
6857 + (eq_attr "fix_janus" "yes"))
6860 + (if_then_else (and (eq_attr "type" "alu_shift_reg")
6861 + (eq_attr "fix_janus" "yes"))
6864 + (if_then_else (and (eq_attr "type" "alu_shift_reg")
6865 + (eq_attr "fix_janus" "yes"))
6868 + (set_attr "insn" "mov")]
6871 (define_insn "*ifcompare_shift_shift"
6872 @@ -10113,7 +10655,7 @@
6873 [(match_operand:SI 3 "s_register_operand" "r")
6874 (match_operand:SI 4 "arm_rhs_operand" "rM")])))
6875 (clobber (reg:CC CC_REGNUM))]
6877 + "TARGET_ARM && !TARGET_NO_SINGLE_COND_EXEC"
6879 [(set_attr "conds" "clob")
6880 (set_attr "length" "12")]
6881 @@ -10134,12 +10676,16 @@
6882 "mov%d5\\t%0, %1%S6\;mov%D5\\t%0, %3%S7"
6883 [(set_attr "conds" "use")
6884 (set_attr "shift" "1")
6885 - (set_attr "length" "8")
6886 + (set_attr "insn" "mov")
6887 (set (attr "type") (if_then_else
6888 (and (match_operand 2 "const_int_operand" "")
6889 (match_operand 4 "const_int_operand" ""))
6890 (const_string "alu_shift")
6891 - (const_string "alu_shift_reg")))]
6892 + (const_string "alu_shift_reg")))
6893 + (set (attr "length") (if_then_else (and (eq_attr "type" "alu_shift_reg")
6894 + (eq_attr "fix_janus" "yes"))
6899 (define_insn "*ifcompare_not_arith"
6900 @@ -10153,7 +10699,7 @@
6901 [(match_operand:SI 2 "s_register_operand" "r")
6902 (match_operand:SI 3 "arm_rhs_operand" "rI")])))
6903 (clobber (reg:CC CC_REGNUM))]
6905 + "TARGET_ARM && !TARGET_NO_SINGLE_COND_EXEC"
6907 [(set_attr "conds" "clob")
6908 (set_attr "length" "12")]
6909 @@ -10171,6 +10717,7 @@
6911 "mvn%d5\\t%0, %1\;%I6%D5\\t%0, %2, %3"
6912 [(set_attr "conds" "use")
6913 + (set_attr "insn" "mvn")
6914 (set_attr "length" "8")]
6917 @@ -10185,7 +10732,7 @@
6918 (match_operand:SI 3 "arm_rhs_operand" "rI")])
6919 (not:SI (match_operand:SI 1 "s_register_operand" "r"))))
6920 (clobber (reg:CC CC_REGNUM))]
6922 + "TARGET_ARM && !TARGET_NO_SINGLE_COND_EXEC"
6924 [(set_attr "conds" "clob")
6925 (set_attr "length" "12")]
6926 @@ -10203,6 +10750,7 @@
6928 "mvn%D5\\t%0, %1\;%I6%d5\\t%0, %2, %3"
6929 [(set_attr "conds" "use")
6930 + (set_attr "insn" "mvn")
6931 (set_attr "length" "8")]
6934 @@ -10215,7 +10763,7 @@
6935 (neg:SI (match_operand:SI 2 "s_register_operand" "r,r"))
6936 (match_operand:SI 1 "arm_not_operand" "0,?rIK")))
6937 (clobber (reg:CC CC_REGNUM))]
6939 + "TARGET_ARM && !TARGET_NO_SINGLE_COND_EXEC"
6941 [(set_attr "conds" "clob")
6942 (set_attr "length" "8,12")]
6943 @@ -10246,7 +10794,7 @@
6944 (match_operand:SI 1 "arm_not_operand" "0,?rIK")
6945 (neg:SI (match_operand:SI 2 "s_register_operand" "r,r"))))
6946 (clobber (reg:CC CC_REGNUM))]
6948 + "TARGET_ARM && !TARGET_NO_SINGLE_COND_EXEC"
6950 [(set_attr "conds" "clob")
6951 (set_attr "length" "8,12")]
6952 @@ -10614,7 +11162,7 @@
6954 (match_operand 4 "" "")))
6955 (clobber (reg:CC CC_REGNUM))]
6956 - "TARGET_ARM && reload_completed"
6957 + "TARGET_ARM && reload_completed && !TARGET_NO_SINGLE_COND_EXEC"
6958 [(set (match_dup 5) (match_dup 6))
6959 (cond_exec (match_dup 7)
6960 (set (match_dup 0) (match_dup 4)))]
6961 @@ -10642,7 +11190,7 @@
6962 (match_operand 4 "" "")
6964 (clobber (reg:CC CC_REGNUM))]
6965 - "TARGET_ARM && reload_completed"
6966 + "TARGET_ARM && reload_completed && !TARGET_NO_SINGLE_COND_EXEC"
6967 [(set (match_dup 5) (match_dup 6))
6968 (cond_exec (match_op_dup 1 [(match_dup 5) (const_int 0)])
6969 (set (match_dup 0) (match_dup 4)))]
6970 @@ -10663,7 +11211,7 @@
6971 (match_operand 4 "" "")
6972 (match_operand 5 "" "")))
6973 (clobber (reg:CC CC_REGNUM))]
6974 - "TARGET_ARM && reload_completed"
6975 + "TARGET_ARM && reload_completed && !TARGET_NO_SINGLE_COND_EXEC"
6976 [(set (match_dup 6) (match_dup 7))
6977 (cond_exec (match_op_dup 1 [(match_dup 6) (const_int 0)])
6978 (set (match_dup 0) (match_dup 4)))
6979 @@ -10695,7 +11243,7 @@
6981 (match_operand:SI 5 "s_register_operand" ""))))
6982 (clobber (reg:CC CC_REGNUM))]
6983 - "TARGET_ARM && reload_completed"
6984 + "TARGET_ARM && reload_completed && !TARGET_NO_SINGLE_COND_EXEC"
6985 [(set (match_dup 6) (match_dup 7))
6986 (cond_exec (match_op_dup 1 [(match_dup 6) (const_int 0)])
6987 (set (match_dup 0) (match_dup 4)))
6988 @@ -10730,6 +11278,7 @@
6990 mov%d4\\t%0, %1\;mvn%D4\\t%0, %2"
6991 [(set_attr "conds" "use")
6992 + (set_attr "insn" "mvn")
6993 (set_attr "length" "4,8")]
6996 @@ -10864,6 +11413,24 @@
7000 +(define_insn "align_16"
7001 + [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN16)]
7004 + assemble_align (128);
7009 +(define_insn "align_32"
7010 + [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN32)]
7013 + assemble_align (256);
7018 (define_insn "consttable_end"
7019 [(unspec_volatile [(const_int 0)] VUNSPEC_POOL_END)]
7021 @@ -10890,6 +11457,7 @@
7024 making_const_table = TRUE;
7025 + gcc_assert (GET_MODE_CLASS (GET_MODE (operands[0])) != MODE_FLOAT);
7026 assemble_integer (operands[0], 2, BITS_PER_WORD, 1);
7029 @@ -10902,19 +11470,30 @@
7033 + rtx x = operands[0];
7034 making_const_table = TRUE;
7035 - switch (GET_MODE_CLASS (GET_MODE (operands[0])))
7036 + switch (GET_MODE_CLASS (GET_MODE (x)))
7040 - REAL_VALUE_TYPE r;
7041 - REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
7042 - assemble_real (r, GET_MODE (operands[0]), BITS_PER_WORD);
7045 + if (GET_MODE (x) == HFmode)
7046 + arm_emit_fp16_const (x);
7049 + REAL_VALUE_TYPE r;
7050 + REAL_VALUE_FROM_CONST_DOUBLE (r, x);
7051 + assemble_real (r, GET_MODE (x), BITS_PER_WORD);
7055 - assemble_integer (operands[0], 4, BITS_PER_WORD, 1);
7056 - mark_symbol_refs_as_used (operands[0]);
7057 + /* XXX: Sometimes gcc does something really dumb and ends up with
7058 + a HIGH in a constant pool entry, usually because it's trying to
7059 + load into a VFP register. We know this will always be used in
7060 + combination with a LO_SUM which ignores the high bits, so just
7061 + strip off the HIGH. */
7062 + if (GET_CODE (x) == HIGH)
7064 + assemble_integer (x, 4, BITS_PER_WORD, 1);
7065 + mark_symbol_refs_as_used (x);
7069 @@ -11008,6 +11587,28 @@
7070 [(set_attr "predicable" "yes")
7071 (set_attr "insn" "clz")])
7073 +(define_insn "rbitsi2"
7074 + [(set (match_operand:SI 0 "s_register_operand" "=r")
7075 + (unspec:SI [(match_operand:SI 1 "s_register_operand" "r")] UNSPEC_RBIT))]
7076 + "TARGET_32BIT && arm_arch_thumb2"
7078 + [(set_attr "predicable" "yes")
7079 + (set_attr "insn" "clz")])
7081 +(define_expand "ctzsi2"
7082 + [(set (match_operand:SI 0 "s_register_operand" "")
7083 + (ctz:SI (match_operand:SI 1 "s_register_operand" "")))]
7084 + "TARGET_32BIT && arm_arch_thumb2"
7087 + rtx tmp = gen_reg_rtx (SImode);
7088 + emit_insn (gen_rbitsi2 (tmp, operands[1]));
7089 + emit_insn (gen_clzsi2 (operands[0], tmp));
7095 ;; V5E instructions.
7097 (define_insn "prefetch"
7098 @@ -11017,13 +11618,15 @@
7099 "TARGET_32BIT && arm_arch5e"
7102 -;; General predication pattern
7103 +;; General predication pattern.
7104 +;; Conditional branches are available as both arm_cond_branch and
7105 +;; predicated arm_jump, so it doesn't matter if we disable the latter.
7108 [(match_operator 0 "arm_comparison_operator"
7109 [(match_operand 1 "cc_register" "")
7112 + "TARGET_32BIT && !TARGET_NO_SINGLE_COND_EXEC"
7116 --- a/gcc/config/arm/arm.opt
7117 +++ b/gcc/config/arm/arm.opt
7118 @@ -78,6 +78,10 @@ Specify if floating point hardware shoul
7120 Target RejectNegative Joined Undocumented Var(target_fpe_name)
7123 +Target RejectNegative Joined Var(target_fp16_format_name)
7124 +Specify the __fp16 floating-point format
7128 Target RejectNegative Mask(FPE) Undocumented
7129 @@ -93,6 +97,10 @@ mhard-float
7130 Target RejectNegative
7131 Alias for -mfloat-abi=hard
7134 +Target Report Mask(FIX_JANUS)
7135 +Work around hardware errata for Avalent Janus 2CC cores.
7138 Target Report RejectNegative InverseMask(BIG_END)
7139 Assume target CPU is configured as little endian
7140 @@ -101,6 +109,10 @@ mlong-calls
7141 Target Report Mask(LONG_CALLS)
7142 Generate call insns as indirect calls, if necessary
7145 +Target Report Mask(MARVELL_DIV)
7146 +Generate hardware integer division instructions supported by some Marvell cores.
7149 Target RejectNegative Joined Var(arm_pic_register_string)
7150 Specify the register to be used for PIC addressing
7151 @@ -157,6 +169,10 @@ mvectorize-with-neon-quad
7152 Target Report Mask(NEON_VECTORIZE_QUAD)
7153 Use Neon quad-word (rather than double-word) registers for vectorization
7156 +Target Report Var(low_irq_latency)
7157 +Try to reduce interrupt latency of the generated code
7160 Target Report Var(target_word_relocations) Init(TARGET_DEFAULT_WORD_RELOCATIONS)
7161 Only generate absolute relocations on word sized values.
7162 --- a/gcc/config/arm/arm_neon.h
7163 +++ b/gcc/config/arm/arm_neon.h
7168 +#if defined (__vxworks) && defined (_WRS_KERNEL)
7169 +#include <vxWorks.h>
7174 typedef __builtin_neon_qi int8x8_t __attribute__ ((__vector_size__ (8)));
7175 typedef __builtin_neon_hi int16x4_t __attribute__ ((__vector_size__ (8)));
7176 @@ -61,7 +65,7 @@ typedef __builtin_neon_uhi uint16x8_t __
7177 typedef __builtin_neon_usi uint32x4_t __attribute__ ((__vector_size__ (16)));
7178 typedef __builtin_neon_udi uint64x2_t __attribute__ ((__vector_size__ (16)));
7180 -typedef __builtin_neon_sf float32_t;
7181 +typedef float float32_t;
7182 typedef __builtin_neon_poly8 poly8_t;
7183 typedef __builtin_neon_poly16 poly16_t;
7185 @@ -5085,7 +5089,7 @@ vset_lane_s32 (int32_t __a, int32x2_t __
7186 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
7187 vset_lane_f32 (float32_t __a, float32x2_t __b, const int __c)
7189 - return (float32x2_t)__builtin_neon_vset_lanev2sf (__a, __b, __c);
7190 + return (float32x2_t)__builtin_neon_vset_lanev2sf ((__builtin_neon_sf) __a, __b, __c);
7193 __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
7194 @@ -5151,7 +5155,7 @@ vsetq_lane_s32 (int32_t __a, int32x4_t _
7195 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
7196 vsetq_lane_f32 (float32_t __a, float32x4_t __b, const int __c)
7198 - return (float32x4_t)__builtin_neon_vset_lanev4sf (__a, __b, __c);
7199 + return (float32x4_t)__builtin_neon_vset_lanev4sf ((__builtin_neon_sf) __a, __b, __c);
7202 __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
7203 @@ -5283,7 +5287,7 @@ vdup_n_s32 (int32_t __a)
7204 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
7205 vdup_n_f32 (float32_t __a)
7207 - return (float32x2_t)__builtin_neon_vdup_nv2sf (__a);
7208 + return (float32x2_t)__builtin_neon_vdup_nv2sf ((__builtin_neon_sf) __a);
7211 __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
7212 @@ -5349,7 +5353,7 @@ vdupq_n_s32 (int32_t __a)
7213 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
7214 vdupq_n_f32 (float32_t __a)
7216 - return (float32x4_t)__builtin_neon_vdup_nv4sf (__a);
7217 + return (float32x4_t)__builtin_neon_vdup_nv4sf ((__builtin_neon_sf) __a);
7220 __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
7221 @@ -5415,7 +5419,7 @@ vmov_n_s32 (int32_t __a)
7222 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
7223 vmov_n_f32 (float32_t __a)
7225 - return (float32x2_t)__builtin_neon_vdup_nv2sf (__a);
7226 + return (float32x2_t)__builtin_neon_vdup_nv2sf ((__builtin_neon_sf) __a);
7229 __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
7230 @@ -5481,7 +5485,7 @@ vmovq_n_s32 (int32_t __a)
7231 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
7232 vmovq_n_f32 (float32_t __a)
7234 - return (float32x4_t)__builtin_neon_vdup_nv4sf (__a);
7235 + return (float32x4_t)__builtin_neon_vdup_nv4sf ((__builtin_neon_sf) __a);
7238 __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
7239 @@ -6591,7 +6595,7 @@ vmul_n_s32 (int32x2_t __a, int32_t __b)
7240 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
7241 vmul_n_f32 (float32x2_t __a, float32_t __b)
7243 - return (float32x2_t)__builtin_neon_vmul_nv2sf (__a, __b, 3);
7244 + return (float32x2_t)__builtin_neon_vmul_nv2sf (__a, (__builtin_neon_sf) __b, 3);
7247 __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
7248 @@ -6621,7 +6625,7 @@ vmulq_n_s32 (int32x4_t __a, int32_t __b)
7249 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
7250 vmulq_n_f32 (float32x4_t __a, float32_t __b)
7252 - return (float32x4_t)__builtin_neon_vmul_nv4sf (__a, __b, 3);
7253 + return (float32x4_t)__builtin_neon_vmul_nv4sf (__a, (__builtin_neon_sf) __b, 3);
7256 __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
7257 @@ -6735,7 +6739,7 @@ vmla_n_s32 (int32x2_t __a, int32x2_t __b
7258 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
7259 vmla_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
7261 - return (float32x2_t)__builtin_neon_vmla_nv2sf (__a, __b, __c, 3);
7262 + return (float32x2_t)__builtin_neon_vmla_nv2sf (__a, __b, (__builtin_neon_sf) __c, 3);
7265 __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
7266 @@ -6765,7 +6769,7 @@ vmlaq_n_s32 (int32x4_t __a, int32x4_t __
7267 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
7268 vmlaq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
7270 - return (float32x4_t)__builtin_neon_vmla_nv4sf (__a, __b, __c, 3);
7271 + return (float32x4_t)__builtin_neon_vmla_nv4sf (__a, __b, (__builtin_neon_sf) __c, 3);
7274 __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
7275 @@ -6831,7 +6835,7 @@ vmls_n_s32 (int32x2_t __a, int32x2_t __b
7276 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
7277 vmls_n_f32 (float32x2_t __a, float32x2_t __b, float32_t __c)
7279 - return (float32x2_t)__builtin_neon_vmls_nv2sf (__a, __b, __c, 3);
7280 + return (float32x2_t)__builtin_neon_vmls_nv2sf (__a, __b, (__builtin_neon_sf) __c, 3);
7283 __extension__ static __inline uint16x4_t __attribute__ ((__always_inline__))
7284 @@ -6861,7 +6865,7 @@ vmlsq_n_s32 (int32x4_t __a, int32x4_t __
7285 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
7286 vmlsq_n_f32 (float32x4_t __a, float32x4_t __b, float32_t __c)
7288 - return (float32x4_t)__builtin_neon_vmls_nv4sf (__a, __b, __c, 3);
7289 + return (float32x4_t)__builtin_neon_vmls_nv4sf (__a, __b, (__builtin_neon_sf) __c, 3);
7292 __extension__ static __inline uint16x8_t __attribute__ ((__always_inline__))
7293 @@ -7851,7 +7855,7 @@ vld1_s64 (const int64_t * __a)
7294 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
7295 vld1_f32 (const float32_t * __a)
7297 - return (float32x2_t)__builtin_neon_vld1v2sf (__a);
7298 + return (float32x2_t)__builtin_neon_vld1v2sf ((const __builtin_neon_sf *) __a);
7301 __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
7302 @@ -7917,7 +7921,7 @@ vld1q_s64 (const int64_t * __a)
7303 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
7304 vld1q_f32 (const float32_t * __a)
7306 - return (float32x4_t)__builtin_neon_vld1v4sf (__a);
7307 + return (float32x4_t)__builtin_neon_vld1v4sf ((const __builtin_neon_sf *) __a);
7310 __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
7311 @@ -7977,7 +7981,7 @@ vld1_lane_s32 (const int32_t * __a, int3
7312 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
7313 vld1_lane_f32 (const float32_t * __a, float32x2_t __b, const int __c)
7315 - return (float32x2_t)__builtin_neon_vld1_lanev2sf (__a, __b, __c);
7316 + return (float32x2_t)__builtin_neon_vld1_lanev2sf ((const __builtin_neon_sf *) __a, __b, __c);
7319 __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
7320 @@ -8043,7 +8047,7 @@ vld1q_lane_s32 (const int32_t * __a, int
7321 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
7322 vld1q_lane_f32 (const float32_t * __a, float32x4_t __b, const int __c)
7324 - return (float32x4_t)__builtin_neon_vld1_lanev4sf (__a, __b, __c);
7325 + return (float32x4_t)__builtin_neon_vld1_lanev4sf ((const __builtin_neon_sf *) __a, __b, __c);
7328 __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
7329 @@ -8109,7 +8113,7 @@ vld1_dup_s32 (const int32_t * __a)
7330 __extension__ static __inline float32x2_t __attribute__ ((__always_inline__))
7331 vld1_dup_f32 (const float32_t * __a)
7333 - return (float32x2_t)__builtin_neon_vld1_dupv2sf (__a);
7334 + return (float32x2_t)__builtin_neon_vld1_dupv2sf ((const __builtin_neon_sf *) __a);
7337 __extension__ static __inline uint8x8_t __attribute__ ((__always_inline__))
7338 @@ -8175,7 +8179,7 @@ vld1q_dup_s32 (const int32_t * __a)
7339 __extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
7340 vld1q_dup_f32 (const float32_t * __a)
7342 - return (float32x4_t)__builtin_neon_vld1_dupv4sf (__a);
7343 + return (float32x4_t)__builtin_neon_vld1_dupv4sf ((const __builtin_neon_sf *) __a);
7346 __extension__ static __inline uint8x16_t __attribute__ ((__always_inline__))
7347 @@ -8247,7 +8251,7 @@ vst1_s64 (int64_t * __a, int64x1_t __b)
7348 __extension__ static __inline void __attribute__ ((__always_inline__))
7349 vst1_f32 (float32_t * __a, float32x2_t __b)
7351 - __builtin_neon_vst1v2sf (__a, __b);
7352 + __builtin_neon_vst1v2sf ((__builtin_neon_sf *) __a, __b);
7355 __extension__ static __inline void __attribute__ ((__always_inline__))
7356 @@ -8313,7 +8317,7 @@ vst1q_s64 (int64_t * __a, int64x2_t __b)
7357 __extension__ static __inline void __attribute__ ((__always_inline__))
7358 vst1q_f32 (float32_t * __a, float32x4_t __b)
7360 - __builtin_neon_vst1v4sf (__a, __b);
7361 + __builtin_neon_vst1v4sf ((__builtin_neon_sf *) __a, __b);
7364 __extension__ static __inline void __attribute__ ((__always_inline__))
7365 @@ -8373,7 +8377,7 @@ vst1_lane_s32 (int32_t * __a, int32x2_t
7366 __extension__ static __inline void __attribute__ ((__always_inline__))
7367 vst1_lane_f32 (float32_t * __a, float32x2_t __b, const int __c)
7369 - __builtin_neon_vst1_lanev2sf (__a, __b, __c);
7370 + __builtin_neon_vst1_lanev2sf ((__builtin_neon_sf *) __a, __b, __c);
7373 __extension__ static __inline void __attribute__ ((__always_inline__))
7374 @@ -8439,7 +8443,7 @@ vst1q_lane_s32 (int32_t * __a, int32x4_t
7375 __extension__ static __inline void __attribute__ ((__always_inline__))
7376 vst1q_lane_f32 (float32_t * __a, float32x4_t __b, const int __c)
7378 - __builtin_neon_vst1_lanev4sf (__a, __b, __c);
7379 + __builtin_neon_vst1_lanev4sf ((__builtin_neon_sf *) __a, __b, __c);
7382 __extension__ static __inline void __attribute__ ((__always_inline__))
7383 @@ -8512,7 +8516,7 @@ __extension__ static __inline float32x2x
7384 vld2_f32 (const float32_t * __a)
7386 union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv;
7387 - __rv.__o = __builtin_neon_vld2v2sf (__a);
7388 + __rv.__o = __builtin_neon_vld2v2sf ((const __builtin_neon_sf *) __a);
7392 @@ -8600,7 +8604,7 @@ __extension__ static __inline float32x4x
7393 vld2q_f32 (const float32_t * __a)
7395 union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv;
7396 - __rv.__o = __builtin_neon_vld2v4sf (__a);
7397 + __rv.__o = __builtin_neon_vld2v4sf ((const __builtin_neon_sf *) __a);
7401 @@ -8676,7 +8680,7 @@ vld2_lane_f32 (const float32_t * __a, fl
7403 union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
7404 union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv;
7405 - __rv.__o = __builtin_neon_vld2_lanev2sf (__a, __bu.__o, __c);
7406 + __rv.__o = __builtin_neon_vld2_lanev2sf ((const __builtin_neon_sf *) __a, __bu.__o, __c);
7410 @@ -8748,7 +8752,7 @@ vld2q_lane_f32 (const float32_t * __a, f
7412 union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
7413 union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv;
7414 - __rv.__o = __builtin_neon_vld2_lanev4sf (__a, __bu.__o, __c);
7415 + __rv.__o = __builtin_neon_vld2_lanev4sf ((const __builtin_neon_sf *) __a, __bu.__o, __c);
7419 @@ -8807,7 +8811,7 @@ __extension__ static __inline float32x2x
7420 vld2_dup_f32 (const float32_t * __a)
7422 union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv;
7423 - __rv.__o = __builtin_neon_vld2_dupv2sf (__a);
7424 + __rv.__o = __builtin_neon_vld2_dupv2sf ((const __builtin_neon_sf *) __a);
7428 @@ -8892,7 +8896,7 @@ __extension__ static __inline void __att
7429 vst2_f32 (float32_t * __a, float32x2x2_t __b)
7431 union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
7432 - __builtin_neon_vst2v2sf (__a, __bu.__o);
7433 + __builtin_neon_vst2v2sf ((__builtin_neon_sf *) __a, __bu.__o);
7436 __extension__ static __inline void __attribute__ ((__always_inline__))
7437 @@ -8969,7 +8973,7 @@ __extension__ static __inline void __att
7438 vst2q_f32 (float32_t * __a, float32x4x2_t __b)
7440 union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
7441 - __builtin_neon_vst2v4sf (__a, __bu.__o);
7442 + __builtin_neon_vst2v4sf ((__builtin_neon_sf *) __a, __bu.__o);
7445 __extension__ static __inline void __attribute__ ((__always_inline__))
7446 @@ -9032,7 +9036,7 @@ __extension__ static __inline void __att
7447 vst2_lane_f32 (float32_t * __a, float32x2x2_t __b, const int __c)
7449 union { float32x2x2_t __i; __builtin_neon_ti __o; } __bu = { __b };
7450 - __builtin_neon_vst2_lanev2sf (__a, __bu.__o, __c);
7451 + __builtin_neon_vst2_lanev2sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
7454 __extension__ static __inline void __attribute__ ((__always_inline__))
7455 @@ -9088,7 +9092,7 @@ __extension__ static __inline void __att
7456 vst2q_lane_f32 (float32_t * __a, float32x4x2_t __b, const int __c)
7458 union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
7459 - __builtin_neon_vst2_lanev4sf (__a, __bu.__o, __c);
7460 + __builtin_neon_vst2_lanev4sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
7463 __extension__ static __inline void __attribute__ ((__always_inline__))
7464 @@ -9140,7 +9144,7 @@ __extension__ static __inline float32x2x
7465 vld3_f32 (const float32_t * __a)
7467 union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv;
7468 - __rv.__o = __builtin_neon_vld3v2sf (__a);
7469 + __rv.__o = __builtin_neon_vld3v2sf ((const __builtin_neon_sf *) __a);
7473 @@ -9228,7 +9232,7 @@ __extension__ static __inline float32x4x
7474 vld3q_f32 (const float32_t * __a)
7476 union { float32x4x3_t __i; __builtin_neon_ci __o; } __rv;
7477 - __rv.__o = __builtin_neon_vld3v4sf (__a);
7478 + __rv.__o = __builtin_neon_vld3v4sf ((const __builtin_neon_sf *) __a);
7482 @@ -9304,7 +9308,7 @@ vld3_lane_f32 (const float32_t * __a, fl
7484 union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
7485 union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv;
7486 - __rv.__o = __builtin_neon_vld3_lanev2sf (__a, __bu.__o, __c);
7487 + __rv.__o = __builtin_neon_vld3_lanev2sf ((const __builtin_neon_sf *) __a, __bu.__o, __c);
7491 @@ -9376,7 +9380,7 @@ vld3q_lane_f32 (const float32_t * __a, f
7493 union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
7494 union { float32x4x3_t __i; __builtin_neon_ci __o; } __rv;
7495 - __rv.__o = __builtin_neon_vld3_lanev4sf (__a, __bu.__o, __c);
7496 + __rv.__o = __builtin_neon_vld3_lanev4sf ((const __builtin_neon_sf *) __a, __bu.__o, __c);
7500 @@ -9435,7 +9439,7 @@ __extension__ static __inline float32x2x
7501 vld3_dup_f32 (const float32_t * __a)
7503 union { float32x2x3_t __i; __builtin_neon_ei __o; } __rv;
7504 - __rv.__o = __builtin_neon_vld3_dupv2sf (__a);
7505 + __rv.__o = __builtin_neon_vld3_dupv2sf ((const __builtin_neon_sf *) __a);
7509 @@ -9520,7 +9524,7 @@ __extension__ static __inline void __att
7510 vst3_f32 (float32_t * __a, float32x2x3_t __b)
7512 union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
7513 - __builtin_neon_vst3v2sf (__a, __bu.__o);
7514 + __builtin_neon_vst3v2sf ((__builtin_neon_sf *) __a, __bu.__o);
7517 __extension__ static __inline void __attribute__ ((__always_inline__))
7518 @@ -9597,7 +9601,7 @@ __extension__ static __inline void __att
7519 vst3q_f32 (float32_t * __a, float32x4x3_t __b)
7521 union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
7522 - __builtin_neon_vst3v4sf (__a, __bu.__o);
7523 + __builtin_neon_vst3v4sf ((__builtin_neon_sf *) __a, __bu.__o);
7526 __extension__ static __inline void __attribute__ ((__always_inline__))
7527 @@ -9660,7 +9664,7 @@ __extension__ static __inline void __att
7528 vst3_lane_f32 (float32_t * __a, float32x2x3_t __b, const int __c)
7530 union { float32x2x3_t __i; __builtin_neon_ei __o; } __bu = { __b };
7531 - __builtin_neon_vst3_lanev2sf (__a, __bu.__o, __c);
7532 + __builtin_neon_vst3_lanev2sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
7535 __extension__ static __inline void __attribute__ ((__always_inline__))
7536 @@ -9716,7 +9720,7 @@ __extension__ static __inline void __att
7537 vst3q_lane_f32 (float32_t * __a, float32x4x3_t __b, const int __c)
7539 union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b };
7540 - __builtin_neon_vst3_lanev4sf (__a, __bu.__o, __c);
7541 + __builtin_neon_vst3_lanev4sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
7544 __extension__ static __inline void __attribute__ ((__always_inline__))
7545 @@ -9768,7 +9772,7 @@ __extension__ static __inline float32x2x
7546 vld4_f32 (const float32_t * __a)
7548 union { float32x2x4_t __i; __builtin_neon_oi __o; } __rv;
7549 - __rv.__o = __builtin_neon_vld4v2sf (__a);
7550 + __rv.__o = __builtin_neon_vld4v2sf ((const __builtin_neon_sf *) __a);
7554 @@ -9856,7 +9860,7 @@ __extension__ static __inline float32x4x
7555 vld4q_f32 (const float32_t * __a)
7557 union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv;
7558 - __rv.__o = __builtin_neon_vld4v4sf (__a);
7559 + __rv.__o = __builtin_neon_vld4v4sf ((const __builtin_neon_sf *) __a);
7563 @@ -9932,7 +9936,7 @@ vld4_lane_f32 (const float32_t * __a, fl
7565 union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
7566 union { float32x2x4_t __i; __builtin_neon_oi __o; } __rv;
7567 - __rv.__o = __builtin_neon_vld4_lanev2sf (__a, __bu.__o, __c);
7568 + __rv.__o = __builtin_neon_vld4_lanev2sf ((const __builtin_neon_sf *) __a, __bu.__o, __c);
7572 @@ -10004,7 +10008,7 @@ vld4q_lane_f32 (const float32_t * __a, f
7574 union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
7575 union { float32x4x4_t __i; __builtin_neon_xi __o; } __rv;
7576 - __rv.__o = __builtin_neon_vld4_lanev4sf (__a, __bu.__o, __c);
7577 + __rv.__o = __builtin_neon_vld4_lanev4sf ((const __builtin_neon_sf *) __a, __bu.__o, __c);
7581 @@ -10063,7 +10067,7 @@ __extension__ static __inline float32x2x
7582 vld4_dup_f32 (const float32_t * __a)
7584 union { float32x2x4_t __i; __builtin_neon_oi __o; } __rv;
7585 - __rv.__o = __builtin_neon_vld4_dupv2sf (__a);
7586 + __rv.__o = __builtin_neon_vld4_dupv2sf ((const __builtin_neon_sf *) __a);
7590 @@ -10148,7 +10152,7 @@ __extension__ static __inline void __att
7591 vst4_f32 (float32_t * __a, float32x2x4_t __b)
7593 union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
7594 - __builtin_neon_vst4v2sf (__a, __bu.__o);
7595 + __builtin_neon_vst4v2sf ((__builtin_neon_sf *) __a, __bu.__o);
7598 __extension__ static __inline void __attribute__ ((__always_inline__))
7599 @@ -10225,7 +10229,7 @@ __extension__ static __inline void __att
7600 vst4q_f32 (float32_t * __a, float32x4x4_t __b)
7602 union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
7603 - __builtin_neon_vst4v4sf (__a, __bu.__o);
7604 + __builtin_neon_vst4v4sf ((__builtin_neon_sf *) __a, __bu.__o);
7607 __extension__ static __inline void __attribute__ ((__always_inline__))
7608 @@ -10288,7 +10292,7 @@ __extension__ static __inline void __att
7609 vst4_lane_f32 (float32_t * __a, float32x2x4_t __b, const int __c)
7611 union { float32x2x4_t __i; __builtin_neon_oi __o; } __bu = { __b };
7612 - __builtin_neon_vst4_lanev2sf (__a, __bu.__o, __c);
7613 + __builtin_neon_vst4_lanev2sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
7616 __extension__ static __inline void __attribute__ ((__always_inline__))
7617 @@ -10344,7 +10348,7 @@ __extension__ static __inline void __att
7618 vst4q_lane_f32 (float32_t * __a, float32x4x4_t __b, const int __c)
7620 union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
7621 - __builtin_neon_vst4_lanev4sf (__a, __bu.__o, __c);
7622 + __builtin_neon_vst4_lanev4sf ((__builtin_neon_sf *) __a, __bu.__o, __c);
7625 __extension__ static __inline void __attribute__ ((__always_inline__))
7626 --- a/gcc/config/arm/bpabi-v6m.S
7627 +++ b/gcc/config/arm/bpabi-v6m.S
7628 @@ -69,9 +69,52 @@ FUNC_START aeabi_ulcmp
7630 #endif /* L_aeabi_ulcmp */
7632 +.macro test_div_by_zero signed
7641 + .ifc \signed, unsigned
7644 + mvn xxh, xxh @ 0xffffffff
7651 + mvn xxl, xxl @ 0xffffffff
7652 + lsr xxh, xxl, #1 @ 0x7fffffff
7655 + lsl xxh, xxh, #24 @ 0x80000000
7659 + @ tailcalls are tricky on v6-m.
7665 + @ We know we are not on armv4t, so pop pc is safe.
7669 + .word __aeabi_ldiv0 - 1b
7673 #ifdef L_aeabi_ldivmod
7675 FUNC_START aeabi_ldivmod
7676 + test_div_by_zero signed
7681 @@ -89,6 +132,8 @@ FUNC_START aeabi_ldivmod
7682 #ifdef L_aeabi_uldivmod
7684 FUNC_START aeabi_uldivmod
7685 + test_div_by_zero unsigned
7690 --- a/gcc/config/arm/bpabi.S
7691 +++ b/gcc/config/arm/bpabi.S
7692 @@ -64,20 +64,69 @@ ARM_FUNC_START aeabi_ulcmp
7694 #endif /* L_aeabi_ulcmp */
7696 +.macro test_div_by_zero signed
7697 +/* Tail-call to divide-by-zero handlers which may be overridden by the user,
7698 + so unwinding works properly. */
7699 +#if defined(__thumb2__)
7705 + .ifc \signed, unsigned
7707 + mov xxh, #0xffffffff
7713 + movlt xxh, #0x80000000
7715 + movgt xxh, #0x7fffffff
7716 + movgt xxl, #0xffffffff
7718 + b SYM (__aeabi_ldiv0) __PLT__
7721 + /* Note: Thumb-1 code calls via an ARM shim on processors which
7722 + support ARM mode. */
7728 + .ifc \signed, unsigned
7729 + movne xxh, #0xffffffff
7730 + movne xxl, #0xffffffff
7732 + movlt xxh, #0x80000000
7734 + movgt xxh, #0x7fffffff
7735 + movgt xxl, #0xffffffff
7737 + b SYM (__aeabi_ldiv0) __PLT__
7742 #ifdef L_aeabi_ldivmod
7744 ARM_FUNC_START aeabi_ldivmod
7745 + test_div_by_zero signed
7748 -#if defined(__thumb2__)
7749 +/* Low latency and Thumb-2 do_push implementations can't push sp directly. */
7750 +#if defined(__thumb2__) || defined(__irq_low_latency__)
7756 + stmfd sp!, {sp, lr}
7758 bl SYM(__gnu_ldivmod_helper) __PLT__
7765 #endif /* L_aeabi_ldivmod */
7766 @@ -85,17 +134,20 @@ ARM_FUNC_START aeabi_ldivmod
7767 #ifdef L_aeabi_uldivmod
7769 ARM_FUNC_START aeabi_uldivmod
7770 + test_div_by_zero unsigned
7773 -#if defined(__thumb2__)
7774 +/* Low latency and Thumb-2 do_push implementations can't push sp directly. */
7775 +#if defined(__thumb2__) || defined(__irq_low_latency__)
7781 + stmfd sp!, {sp, lr}
7783 bl SYM(__gnu_uldivmod_helper) __PLT__
7790 #endif /* L_aeabi_divmod */
7791 --- a/gcc/config/arm/bpabi.h
7792 +++ b/gcc/config/arm/bpabi.h
7795 /* Section 4.1 of the AAPCS requires the use of VFP format. */
7796 #undef FPUTYPE_DEFAULT
7797 -#define FPUTYPE_DEFAULT FPUTYPE_VFP
7798 +#define FPUTYPE_DEFAULT "vfp"
7800 /* TARGET_BIG_ENDIAN_DEFAULT is set in
7801 config.gcc for big endian configurations. */
7804 #define TARGET_FIX_V4BX_SPEC " %{mcpu=arm8|mcpu=arm810|mcpu=strongarm*|march=armv4:--fix-v4bx}"
7806 +#define BE8_LINK_SPEC " %{mbig-endian:%{march=armv7-a|mcpu=cortex-a5|mcpu=cortex-a8|mcpu=cortex-a9:%{!r:--be8}}}"
7808 /* Tell the assembler to build BPABI binaries. */
7809 #undef SUBTARGET_EXTRA_ASM_SPEC
7810 #define SUBTARGET_EXTRA_ASM_SPEC "%{mabi=apcs-gnu|mabi=atpcs:-meabi=gnu;:-meabi=5}" TARGET_FIX_V4BX_SPEC
7812 #define BPABI_LINK_SPEC \
7813 "%{mbig-endian:-EB} %{mlittle-endian:-EL} " \
7814 "%{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic} " \
7815 - "-X" SUBTARGET_EXTRA_LINK_SPEC TARGET_FIX_V4BX_SPEC
7816 + "-X" SUBTARGET_EXTRA_LINK_SPEC TARGET_FIX_V4BX_SPEC BE8_LINK_SPEC
7819 #define LINK_SPEC BPABI_LINK_SPEC
7821 #define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (muldi3, lmul)
7824 -#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixdfdi, d2lz)
7825 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixdfdi, d2lz) \
7826 + extern DWtype __fixdfdi (DFtype) __attribute__((pcs("aapcs"))); \
7827 + extern UDWtype __fixunsdfdi (DFtype) __asm__("__aeabi_d2ulz") __attribute__((pcs("aapcs")));
7830 -#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunsdfdi, d2ulz)
7831 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunsdfdi, d2ulz) \
7832 + extern UDWtype __fixunsdfdi (DFtype) __attribute__((pcs("aapcs")));
7835 -#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixsfdi, f2lz)
7836 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixsfdi, f2lz) \
7837 + extern DWtype __fixsfdi (SFtype) __attribute__((pcs("aapcs"))); \
7838 + extern UDWtype __fixunssfdi (SFtype) __asm__("__aeabi_f2ulz") __attribute__((pcs("aapcs")));
7841 -#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunssfdi, f2ulz)
7842 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunssfdi, f2ulz) \
7843 + extern UDWtype __fixunssfdi (SFtype) __attribute__((pcs("aapcs")));
7846 #define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatdidf, l2d)
7847 --- a/gcc/config/arm/constraints.md
7848 +++ b/gcc/config/arm/constraints.md
7850 ;; In ARM state, 'l' is an alias for 'r'
7852 ;; The following normal constraints have been used:
7853 -;; in ARM/Thumb-2 state: G, H, I, J, K, L, M
7854 +;; in ARM/Thumb-2 state: G, H, I, j, J, K, L, M
7855 ;; in Thumb-1 state: I, J, K, L, M, N, O
7857 ;; The following multi-letter normal constraints have been used:
7858 -;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv
7859 +;; in ARM/Thumb-2 state: Da, Db, Dc, Dn, Dl, DL, Dv, Dy
7860 +;; in Thumb-1 state: Pa, Pb
7862 ;; The following memory constraints have been used:
7863 -;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Us
7864 +;; in ARM/Thumb-2 state: Q, Ut, Uv, Uy, Un, Um, Us
7869 (define_register_constraint "h" "TARGET_THUMB ? HI_REGS : NO_REGS"
7870 "In Thumb state the core registers @code{r8}-@code{r15}.")
7872 +(define_constraint "j"
7873 + "A constant suitable for a MOVW instruction. (ARM/Thumb-2)"
7874 + (and (match_test "TARGET_32BIT && arm_arch_thumb2")
7875 + (ior (match_code "high")
7876 + (and (match_code "const_int")
7877 + (match_test "(ival & 0xffff0000) == 0")))))
7879 (define_register_constraint "k" "STACK_REG"
7880 "@internal The stack register.")
7882 @@ -116,11 +124,9 @@
7883 : ((ival >= 0 && ival <= 1020) && ((ival & 3) == 0))")))
7885 (define_constraint "N"
7886 - "In ARM/Thumb-2 state a constant suitable for a MOVW instruction.
7887 - In Thumb-1 state a constant in the range 0-31."
7888 + "Thumb-1 state a constant in the range 0-31."
7889 (and (match_code "const_int")
7890 - (match_test "TARGET_32BIT ? arm_arch_thumb2 && ((ival & 0xffff0000) == 0)
7891 - : (ival >= 0 && ival <= 31)")))
7892 + (match_test "!TARGET_32BIT && (ival >= 0 && ival <= 31)")))
7894 (define_constraint "O"
7895 "In Thumb-1 state a constant that is a multiple of 4 in the range
7896 @@ -129,6 +135,18 @@
7897 (match_test "TARGET_THUMB1 && ival >= -508 && ival <= 508
7898 && ((ival & 3) == 0)")))
7900 +(define_constraint "Pa"
7901 + "@internal In Thumb-1 state a constant in the range -510 to +510"
7902 + (and (match_code "const_int")
7903 + (match_test "TARGET_THUMB1 && ival >= -510 && ival <= 510
7904 + && (ival > 255 || ival < -255)")))
7906 +(define_constraint "Pb"
7907 + "@internal In Thumb-1 state a constant in the range -262 to +262"
7908 + (and (match_code "const_int")
7909 + (match_test "TARGET_THUMB1 && ival >= -262 && ival <= 262
7910 + && (ival > 255 || ival < -255)")))
7912 (define_constraint "G"
7913 "In ARM/Thumb-2 state a valid FPA immediate constant."
7914 (and (match_code "const_double")
7915 @@ -189,10 +207,17 @@
7916 (define_constraint "Dv"
7918 In ARM/Thumb-2 state a const_double which can be used with a VFP fconsts
7919 - or fconstd instruction."
7921 (and (match_code "const_double")
7922 (match_test "TARGET_32BIT && vfp3_const_double_rtx (op)")))
7924 +(define_constraint "Dy"
7926 + In ARM/Thumb-2 state a const_double which can be used with a VFP fconstd
7928 + (and (match_code "const_double")
7929 + (match_test "TARGET_32BIT && TARGET_VFP_DOUBLE && vfp3_const_double_rtx (op)")))
7931 (define_memory_constraint "Ut"
7933 In ARM/Thumb-2 state an address valid for loading/storing opaque structure
7934 @@ -214,17 +239,24 @@
7936 (define_memory_constraint "Un"
7938 + In ARM/Thumb-2 state a valid address for Neon doubleword vector
7939 + load/store instructions."
7940 + (and (match_code "mem")
7941 + (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 0)")))
7943 +(define_memory_constraint "Um"
7945 In ARM/Thumb-2 state a valid address for Neon element and structure
7946 load/store instructions."
7947 (and (match_code "mem")
7948 - (match_test "TARGET_32BIT && neon_vector_mem_operand (op, FALSE)")))
7949 + (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2)")))
7951 (define_memory_constraint "Us"
7953 In ARM/Thumb-2 state a valid address for non-offset loads/stores of
7954 quad-word values in four ARM registers."
7955 (and (match_code "mem")
7956 - (match_test "TARGET_32BIT && neon_vector_mem_operand (op, TRUE)")))
7957 + (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 1)")))
7959 (define_memory_constraint "Uq"
7962 +++ b/gcc/config/arm/fp16.c
7964 +/* Half-float conversion routines.
7966 + Copyright (C) 2008, 2009 Free Software Foundation, Inc.
7967 + Contributed by CodeSourcery.
7969 + This file is free software; you can redistribute it and/or modify it
7970 + under the terms of the GNU General Public License as published by the
7971 + Free Software Foundation; either version 3, or (at your option) any
7974 + This file is distributed in the hope that it will be useful, but
7975 + WITHOUT ANY WARRANTY; without even the implied warranty of
7976 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
7977 + General Public License for more details.
7979 + Under Section 7 of GPL version 3, you are granted additional
7980 + permissions described in the GCC Runtime Library Exception, version
7981 + 3.1, as published by the Free Software Foundation.
7983 + You should have received a copy of the GNU General Public License and
7984 + a copy of the GCC Runtime Library Exception along with this program;
7985 + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
7986 + <http://www.gnu.org/licenses/>. */
7988 +static inline unsigned short
7989 +__gnu_f2h_internal(unsigned int a, int ieee)
7991 + unsigned short sign = (a >> 16) & 0x8000;
7992 + int aexp = (a >> 23) & 0xff;
7993 + unsigned int mantissa = a & 0x007fffff;
7994 + unsigned int mask;
7995 + unsigned int increment;
8001 + return sign | 0x7e00 | (mantissa >> 13);
8004 + if (aexp == 0 && mantissa == 0)
8009 + /* Decimal point between bits 22 and 23. */
8010 + mantissa |= 0x00800000;
8013 + mask = 0x007fffff;
8016 + else if (aexp != -25)
8017 + mask >>= 24 + aexp;
8020 + mask = 0x00001fff;
8023 + if (mantissa & mask)
8025 + increment = (mask + 1) >> 1;
8026 + if ((mantissa & mask) == increment)
8027 + increment = mantissa & (increment << 1);
8028 + mantissa += increment;
8029 + if (mantissa >= 0x01000000)
8039 + return sign | 0x7c00;
8044 + return sign | 0x7fff;
8052 + mantissa >>= -14 - aexp;
8056 + /* We leave the leading 1 in the mantissa, and subtract one
8057 + from the exponent bias to compensate. */
8058 + return sign | (((aexp + 14) << 10) + (mantissa >> 13));
8062 +__gnu_h2f_internal(unsigned short a, int ieee)
8064 + unsigned int sign = (unsigned int)(a & 0x8000) << 16;
8065 + int aexp = (a >> 10) & 0x1f;
8066 + unsigned int mantissa = a & 0x3ff;
8068 + if (aexp == 0x1f && ieee)
8069 + return sign | 0x7f800000 | (mantissa << 13);
8075 + if (mantissa == 0)
8078 + shift = __builtin_clz(mantissa) - 21;
8079 + mantissa <<= shift;
8083 + return sign | (((aexp + 0x70) << 23) + (mantissa << 13));
8087 +__gnu_f2h_ieee(unsigned int a)
8089 + return __gnu_f2h_internal(a, 1);
8093 +__gnu_h2f_ieee(unsigned short a)
8095 + return __gnu_h2f_internal(a, 1);
8099 +__gnu_f2h_alternative(unsigned int x)
8101 + return __gnu_f2h_internal(x, 0);
8105 +__gnu_h2f_alternative(unsigned short a)
8107 + return __gnu_h2f_internal(a, 0);
8109 --- a/gcc/config/arm/fpa.md
8110 +++ b/gcc/config/arm/fpa.md
8111 @@ -599,10 +599,10 @@
8114 case 0: return \"mvf%?e\\t%0, %1\";
8115 - case 1: if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
8116 + case 1: if (TARGET_FPA_EMU2)
8117 return \"ldf%?e\\t%0, %1\";
8118 return \"lfm%?\\t%0, 1, %1\";
8119 - case 2: if (arm_fpu_arch == FPUTYPE_FPA_EMU2)
8120 + case 2: if (TARGET_FPA_EMU2)
8121 return \"stf%?e\\t%1, %0\";
8122 return \"sfm%?\\t%1, 1, %0\";
8125 +++ b/gcc/config/arm/hwdiv.md
8127 +;; ARM instruction patterns for hardware division
8128 +;; Copyright (C) 2005, 2006, 2007 Free Software Foundation, Inc.
8129 +;; Written by CodeSourcery, LLC.
8131 +;; This file is part of GCC.
8133 +;; GCC is free software; you can redistribute it and/or modify it
8134 +;; under the terms of the GNU General Public License as published by
8135 +;; the Free Software Foundation; either version 2, or (at your option)
8136 +;; any later version.
8138 +;; GCC is distributed in the hope that it will be useful, but
8139 +;; WITHOUT ANY WARRANTY; without even the implied warranty of
8140 +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
8141 +;; General Public License for more details.
8143 +;; You should have received a copy of the GNU General Public License
8144 +;; along with GCC; see the file COPYING. If not, write to
8145 +;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
8146 +;; Boston, MA 02110-1301, USA.
8148 +(define_insn "divsi3"
8149 + [(set (match_operand:SI 0 "s_register_operand" "=r")
8150 + (div:SI (match_operand:SI 1 "s_register_operand" "r")
8151 + (match_operand:SI 2 "s_register_operand" "r")))]
8153 + "sdiv%?\t%0, %1, %2"
8154 + [(set_attr "predicable" "yes")
8155 + (set_attr "insn" "sdiv")]
8158 +(define_insn "udivsi3"
8159 + [(set (match_operand:SI 0 "s_register_operand" "=r")
8160 + (udiv:SI (match_operand:SI 1 "s_register_operand" "r")
8161 + (match_operand:SI 2 "s_register_operand" "r")))]
8163 + "udiv%?\t%0, %1, %2"
8164 + [(set_attr "predicable" "yes")
8165 + (set_attr "insn" "udiv")]
8168 --- a/gcc/config/arm/ieee754-df.S
8169 +++ b/gcc/config/arm/ieee754-df.S
8170 @@ -83,7 +83,7 @@ ARM_FUNC_ALIAS aeabi_dsub subdf3
8171 ARM_FUNC_START adddf3
8172 ARM_FUNC_ALIAS aeabi_dadd adddf3
8174 -1: do_push {r4, r5, lr}
8175 +1: do_push (r4, r5, lr)
8177 @ Look for zeroes, equal values, INF, or NAN.
8178 shift1 lsl, r4, xh, #1
8179 @@ -427,7 +427,7 @@ ARM_FUNC_ALIAS aeabi_ui2d floatunsidf
8183 - do_push {r4, r5, lr}
8184 + do_push (r4, r5, lr)
8185 mov r4, #0x400 @ initial exponent
8186 add r4, r4, #(52-1 - 1)
8187 mov r5, #0 @ sign bit is 0
8188 @@ -447,7 +447,7 @@ ARM_FUNC_ALIAS aeabi_i2d floatsidf
8192 - do_push {r4, r5, lr}
8193 + do_push (r4, r5, lr)
8194 mov r4, #0x400 @ initial exponent
8195 add r4, r4, #(52-1 - 1)
8196 ands r5, r0, #0x80000000 @ sign bit in r5
8197 @@ -481,7 +481,7 @@ ARM_FUNC_ALIAS aeabi_f2d extendsfdf2
8198 RETc(eq) @ we are done already.
8200 @ value was denormalized. We can normalize it now.
8201 - do_push {r4, r5, lr}
8202 + do_push (r4, r5, lr)
8203 mov r4, #0x380 @ setup corresponding exponent
8204 and r5, xh, #0x80000000 @ move sign bit in r5
8205 bic xh, xh, #0x80000000
8206 @@ -508,9 +508,9 @@ ARM_FUNC_ALIAS aeabi_ul2d floatundidf
8208 adr ip, LSYM(f0_ret)
8209 @ Push pc as well so that RETLDM works correctly.
8210 - do_push {r4, r5, ip, lr, pc}
8211 + do_push (r4, r5, ip, lr, pc)
8213 - do_push {r4, r5, lr}
8214 + do_push (r4, r5, lr)
8218 @@ -534,9 +534,9 @@ ARM_FUNC_ALIAS aeabi_l2d floatdidf
8220 adr ip, LSYM(f0_ret)
8221 @ Push pc as well so that RETLDM works correctly.
8222 - do_push {r4, r5, ip, lr, pc}
8223 + do_push (r4, r5, ip, lr, pc)
8225 - do_push {r4, r5, lr}
8226 + do_push (r4, r5, lr)
8229 ands r5, ah, #0x80000000 @ sign bit in r5
8230 @@ -585,7 +585,7 @@ ARM_FUNC_ALIAS aeabi_l2d floatdidf
8231 @ Legacy code expects the result to be returned in f0. Copy it
8239 @@ -602,7 +602,7 @@ LSYM(f0_ret):
8241 ARM_FUNC_START muldf3
8242 ARM_FUNC_ALIAS aeabi_dmul muldf3
8243 - do_push {r4, r5, r6, lr}
8244 + do_push (r4, r5, r6, lr)
8246 @ Mask out exponents, trap any zero/denormal/INF/NAN.
8248 @@ -910,7 +910,7 @@ LSYM(Lml_n):
8249 ARM_FUNC_START divdf3
8250 ARM_FUNC_ALIAS aeabi_ddiv divdf3
8252 - do_push {r4, r5, r6, lr}
8253 + do_push (r4, r5, r6, lr)
8255 @ Mask out exponents, trap any zero/denormal/INF/NAN.
8257 @@ -1195,7 +1195,7 @@ ARM_FUNC_ALIAS aeabi_cdcmple aeabi_cdcmp
8259 @ The status-returning routines are required to preserve all
8260 @ registers except ip, lr, and cpsr.
8261 -6: do_push {r0, lr}
8262 +6: do_push (r0, lr)
8264 @ Set the Z flag correctly, and the C flag unconditionally.
8266 --- a/gcc/config/arm/ieee754-sf.S
8267 +++ b/gcc/config/arm/ieee754-sf.S
8268 @@ -481,7 +481,7 @@ LSYM(Lml_x):
8269 and r3, ip, #0x80000000
8271 @ Well, no way to make it shorter without the umull instruction.
8272 - do_push {r3, r4, r5}
8273 + do_push (r3, r4, r5)
8276 bic r0, r0, r4, lsl #16
8277 @@ -492,7 +492,7 @@ LSYM(Lml_x):
8279 adds r3, r3, r0, lsl #16
8280 adc r1, ip, r0, lsr #16
8281 - do_pop {r0, r4, r5}
8282 + do_pop (r0, r4, r5)
8286 @@ -882,7 +882,7 @@ ARM_FUNC_ALIAS aeabi_cfcmple aeabi_cfcmp
8288 @ The status-returning routines are required to preserve all
8289 @ registers except ip, lr, and cpsr.
8290 -6: do_push {r0, r1, r2, r3, lr}
8291 +6: do_push (r0, r1, r2, r3, lr)
8293 @ Set the Z flag correctly, and the C flag unconditionally.
8295 --- a/gcc/config/arm/lib1funcs.asm
8296 +++ b/gcc/config/arm/lib1funcs.asm
8297 @@ -27,8 +27,17 @@ see the files COPYING3 and COPYING.RUNTI
8298 #if defined(__ELF__) && defined(__linux__)
8299 .section .note.GNU-stack,"",%progbits
8302 +#endif /* __ELF__ and __linux__ */
8304 +#ifdef __ARM_EABI__
8305 +/* Some attributes that are common to all routines in this file. */
8306 + /* Tag_ABI_align8_needed: This code does not require 8-byte
8307 + alignment from the caller. */
8308 + /* .eabi_attribute 24, 0 -- default setting. */
8309 + /* Tag_ABI_align8_preserved: This code preserves 8-byte
8310 + alignment in any callee. */
8311 + .eabi_attribute 25, 1
8312 +#endif /* __ARM_EABI__ */
8313 /* ------------------------------------------------------------------------ */
8315 /* We need to know what prefix to add to function names. */
8316 @@ -233,8 +242,8 @@ LSYM(Lend_fde):
8317 .macro shift1 op, arg0, arg1, arg2
8318 \op \arg0, \arg1, \arg2
8320 -#define do_push push
8322 +#define do_push(...) push {__VA_ARGS__}
8323 +#define do_pop(...) pop {__VA_ARGS__}
8324 #define COND(op1, op2, cond) op1 ## op2 ## cond
8325 /* Perform an arithmetic operation with a variable shift operand. This
8326 requires two instructions and a scratch register on Thumb-2. */
8327 @@ -248,24 +257,133 @@ LSYM(Lend_fde):
8328 .macro shift1 op, arg0, arg1, arg2
8329 mov \arg0, \arg1, \op \arg2
8331 -#define do_push stmfd sp!,
8332 -#define do_pop ldmfd sp!,
8333 +#if defined(__low_irq_latency__)
8334 +#define do_push(...) \
8335 + _buildN1(do_push, _buildC1(__VA_ARGS__))( __VA_ARGS__)
8336 +#define _buildN1(BASE, X) _buildN2(BASE, X)
8337 +#define _buildN2(BASE, X) BASE##X
8338 +#define _buildC1(...) _buildC2(__VA_ARGS__,9,8,7,6,5,4,3,2,1)
8339 +#define _buildC2(a1,a2,a3,a4,a5,a6,a7,a8,a9,c,...) c
8341 +#define do_push1(r1) str r1, [sp, #-4]!
8342 +#define do_push2(r1, r2) str r2, [sp, #-4]! ; str r1, [sp, #-4]!
8343 +#define do_push3(r1, r2, r3) str r3, [sp, #-4]! ; str r2, [sp, #-4]!; str r1, [sp, #-4]!
8344 +#define do_push4(r1, r2, r3, r4) \
8345 + do_push3 (r2, r3, r4);\
8347 +#define do_push5(r1, r2, r3, r4, r5) \
8348 + do_push4 (r2, r3, r4, r5);\
8351 +#define do_pop(...) \
8352 +_buildN1(do_pop, _buildC1(__VA_ARGS__))( __VA_ARGS__)
8354 +#define do_pop1(r1) ldr r1, [sp], #4
8355 +#define do_pop2(r1, r2) ldr r1, [sp], #4 ; ldr r2, [sp], #4
8356 +#define do_pop3(r1, r2, r3) ldr r1, [sp], #4 ; str r2, [sp], #4; str r3, [sp], #4
8357 +#define do_pop4(r1, r2, r3, r4) \
8359 + do_pup3 (r2, r3, r4)
8360 +#define do_pop5(r1, r2, r3, r4, r5) \
8362 + do_pop4 (r2, r3, r4, r5)
8364 +#define do_push(...) stmfd sp!, { __VA_ARGS__}
8365 +#define do_pop(...) ldmfd sp!, {__VA_ARGS__}
8369 #define COND(op1, op2, cond) op1 ## cond ## op2
8370 .macro shiftop name, dest, src1, src2, shiftop, shiftreg, tmp
8371 \name \dest, \src1, \src2, \shiftop \shiftreg
8375 -.macro ARM_LDIV0 name
8376 +#ifdef __ARM_EABI__
8377 +.macro ARM_LDIV0 name signed
8379 + .ifc \signed, unsigned
8380 + movne r0, #0xffffffff
8382 + movgt r0, #0x7fffffff
8383 + movlt r0, #0x80000000
8385 + b SYM (__aeabi_idiv0) __PLT__
8388 +.macro ARM_LDIV0 name signed
8390 98: cfi_push 98b - __\name, 0xe, -0x8, 0x8
8391 bl SYM (__div0) __PLT__
8392 mov r0, #0 @ About as wrong as it could be.
8398 -.macro THUMB_LDIV0 name
8399 +#ifdef __ARM_EABI__
8400 +.macro THUMB_LDIV0 name signed
8401 +#if defined(__ARM_ARCH_6M__)
8402 + .ifc \signed, unsigned
8406 + mvn r0, r0 @ 0xffffffff
8414 + lsr r0, r0, #1 @ 0x7fffffff
8417 + lsl r0, r0, #24 @ 0x80000000
8425 + @ We know we are not on armv4t, so pop pc is safe.
8429 + .word __aeabi_idiv0 - 4b
8430 +#elif defined(__thumb2__)
8432 + .ifc \signed, unsigned
8434 + mov r0, #0xffffffff
8439 + movgt r0, #0x7fffffff
8441 + movlt r0, #0x80000000
8443 + b.w SYM(__aeabi_idiv0) __PLT__
8450 + .ifc \signed, unsigned
8451 + movne r0, #0xffffffff
8453 + movgt r0, #0x7fffffff
8454 + movlt r0, #0x80000000
8456 + b SYM(__aeabi_idiv0) __PLT__
8461 +.macro THUMB_LDIV0 name signed
8463 98: cfi_push 98b - __\name, 0xe, -0x4, 0x8
8465 @@ -277,18 +395,19 @@ LSYM(Lend_fde):
8471 .macro FUNC_END name
8475 -.macro DIV_FUNC_END name
8476 +.macro DIV_FUNC_END name signed
8477 cfi_start __\name, LSYM(Lend_div0)
8481 + THUMB_LDIV0 \name \signed
8484 + ARM_LDIV0 \name \signed
8486 cfi_end LSYM(Lend_div0)
8488 @@ -413,6 +532,12 @@ SYM (__\name):
8492 +#ifdef __ARM_EABI__
8494 + .weak SYM (__\name)
8499 /* Register aliases. */
8501 @@ -437,6 +562,43 @@ pc .req r15
8503 #if __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__)
8505 +#if defined (__thumb2__)
8506 + clz \curbit, \dividend
8507 + clz \result, \divisor
8508 + sub \curbit, \result, \curbit
8509 + rsb \curbit, \curbit, #31
8511 + add \curbit, \result, \curbit, lsl #4
8518 + .set shift, shift - 1
8519 + cmp.w \dividend, \divisor, lsl #shift
8521 + adc.w \result, \result, \result
8523 + subcs.w \dividend, \dividend, \divisor, lsl #shift
8525 +#elif defined(__ARM_TUNE_MARVELL_F__)
8526 + clz \curbit, \dividend
8527 + clz \result, \divisor
8528 + sub \curbit, \result, \curbit
8529 + mov \divisor, \divisor, lsl \curbit
8530 + rsb \curbit, \curbit, #31
8531 + mov \curbit, \curbit, lsl #2
8533 + add pc, pc, \curbit, lsl #2
8536 + cmp \dividend, \divisor
8537 + subcs \dividend, \dividend, \divisor
8538 + mov \divisor, \divisor, lsr #1
8539 + adc \result, \result, \result
8541 +#else /* ! defined(__ARM_TUNE_MARVELL_F__) */
8542 clz \curbit, \dividend
8543 clz \result, \divisor
8544 sub \curbit, \result, \curbit
8545 @@ -452,6 +614,7 @@ pc .req r15
8546 adc \result, \result, \result
8547 subcs \dividend, \dividend, \divisor, lsl #shift
8549 +#endif /* defined(__ARM_TUNE_MARVELL_F__) */
8551 #else /* __ARM_ARCH__ < 5 || defined (__OPTIMIZE_SIZE__) */
8552 #if __ARM_ARCH__ >= 5
8553 @@ -499,18 +662,23 @@ pc .req r15
8556 1: cmp \dividend, \divisor
8558 subhs \dividend, \dividend, \divisor
8559 orrhs \result, \result, \curbit
8560 cmp \dividend, \divisor, lsr #1
8562 subhs \dividend, \dividend, \divisor, lsr #1
8563 orrhs \result, \result, \curbit, lsr #1
8564 cmp \dividend, \divisor, lsr #2
8566 subhs \dividend, \dividend, \divisor, lsr #2
8567 orrhs \result, \result, \curbit, lsr #2
8568 cmp \dividend, \divisor, lsr #3
8570 subhs \dividend, \dividend, \divisor, lsr #3
8571 orrhs \result, \result, \curbit, lsr #3
8572 cmp \dividend, #0 @ Early termination?
8574 movnes \curbit, \curbit, lsr #4 @ No, any more bits to do?
8575 movne \divisor, \divisor, lsr #4
8577 @@ -799,13 +967,14 @@ LSYM(Lgot_result):
8578 /* ------------------------------------------------------------------------ */
8581 +#if defined(__ARM_ARCH_6M__)
8584 FUNC_ALIAS aeabi_uidiv udivsi3
8590 +LSYM(udivsi3_nodiv0):
8594 @@ -819,9 +988,16 @@ LSYM(Lgot_result):
8598 -#else /* ARM version. */
8599 +#else /* ARM/Thumb-2 version. */
8601 + ARM_FUNC_START udivsi3
8602 + ARM_FUNC_ALIAS aeabi_uidiv udivsi3
8604 + /* Note: if called via udivsi3_nodiv0, this will unnecessarily check
8605 + for division-by-zero a second time. */
8606 +LSYM(udivsi3_nodiv0):
8612 @@ -834,7 +1010,8 @@ LSYM(Lgot_result):
8622 @@ -845,19 +1022,24 @@ LSYM(Lgot_result):
8624 #endif /* ARM version */
8626 - DIV_FUNC_END udivsi3
8627 + DIV_FUNC_END udivsi3 unsigned
8629 +#if defined(__ARM_ARCH_6M__)
8630 FUNC_START aeabi_uidivmod
8636 + bl LSYM(udivsi3_nodiv0)
8642 +ARM_FUNC_START aeabi_uidivmod
8645 stmfd sp!, { r0, r1, lr }
8647 + bl LSYM(udivsi3_nodiv0)
8648 ldmfd sp!, { r1, r2, lr }
8651 @@ -904,19 +1086,20 @@ LSYM(Lover10):
8653 #endif /* ARM version. */
8655 - DIV_FUNC_END umodsi3
8656 + DIV_FUNC_END umodsi3 unsigned
8658 #endif /* L_umodsi3 */
8659 /* ------------------------------------------------------------------------ */
8662 +#if defined(__ARM_ARCH_6M__)
8665 FUNC_ALIAS aeabi_idiv divsi3
8671 +LSYM(divsi3_nodiv0):
8674 eor work, divisor @ Save the sign of the result.
8675 @@ -945,15 +1128,21 @@ LSYM(Lover12):
8679 -#else /* ARM version. */
8680 +#else /* ARM/Thumb-2 version. */
8682 + ARM_FUNC_START divsi3
8683 + ARM_FUNC_ALIAS aeabi_idiv divsi3
8686 - eor ip, r0, r1 @ save the sign of the result.
8688 +LSYM(divsi3_nodiv0):
8689 + eor ip, r0, r1 @ save the sign of the result.
8691 rsbmi r1, r1, #0 @ loops below use unsigned.
8692 subs r2, r1, #1 @ division by 1 or -1 ?
8696 rsbmi r3, r0, #0 @ positive dividend value
8699 @@ -963,14 +1152,18 @@ LSYM(Lover12):
8700 ARM_DIV_BODY r3, r1, r0, r2
8707 10: teq ip, r0 @ same sign ?
8716 moveq r0, ip, asr #31
8719 @@ -979,24 +1172,30 @@ LSYM(Lover12):
8727 #endif /* ARM version */
8729 - DIV_FUNC_END divsi3
8730 + DIV_FUNC_END divsi3 signed
8732 +#if defined(__ARM_ARCH_6M__)
8733 FUNC_START aeabi_idivmod
8739 + bl LSYM(divsi3_nodiv0)
8745 +ARM_FUNC_START aeabi_idivmod
8748 stmfd sp!, { r0, r1, lr }
8750 + bl LSYM(divsi3_nodiv0)
8751 ldmfd sp!, { r1, r2, lr }
8754 @@ -1062,21 +1261,25 @@ LSYM(Lover12):
8756 #endif /* ARM version */
8758 - DIV_FUNC_END modsi3
8759 + DIV_FUNC_END modsi3 signed
8761 #endif /* L_modsi3 */
8762 /* ------------------------------------------------------------------------ */
8766 - FUNC_ALIAS aeabi_idiv0 div0
8767 - FUNC_ALIAS aeabi_ldiv0 div0
8769 +#ifdef __ARM_EABI__
8772 + FUNC_START aeabi_idiv0
8773 + FUNC_START aeabi_ldiv0
8776 FUNC_END aeabi_ldiv0
8777 FUNC_END aeabi_idiv0
8784 #endif /* L_divmodsi_tools */
8785 /* ------------------------------------------------------------------------ */
8786 @@ -1086,16 +1289,49 @@ LSYM(Lover12):
8787 /* Constant taken from <asm/signal.h>. */
8790 +#ifdef __ARM_EABI__
8793 + ARM_FUNC_START aeabi_idiv0
8794 + ARM_FUNC_START aeabi_ldiv0
8802 bl SYM(raise) __PLT__
8805 +#ifdef __ARM_EABI__
8806 + FUNC_END aeabi_ldiv0
8807 + FUNC_END aeabi_idiv0
8812 #endif /* L_dvmd_lnx */
8813 +#ifdef L_clear_cache
8814 +#if defined __ARM_EABI__ && defined __linux__
8815 +@ EABI GNU/Linux call to cacheflush syscall.
8816 + ARM_FUNC_START clear_cache
8818 +#if __ARM_ARCH__ >= 7 || defined(__ARM_ARCH_6T2__)
8829 + FUNC_END clear_cache
8831 +#error "This is only for ARM EABI GNU/Linux"
8833 +#endif /* L_clear_cache */
8834 /* ------------------------------------------------------------------------ */
8835 /* Dword shift operations. */
8836 /* All the following Dword shift variants rely on the fact that
8837 @@ -1292,7 +1528,7 @@ FUNC_START clzdi2
8840 ARM_FUNC_START clzdi2
8846 --- a/gcc/config/arm/linux-eabi.h
8847 +++ b/gcc/config/arm/linux-eabi.h
8849 /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to
8850 use the GNU/Linux version, not the generic BPABI version. */
8852 -#define LINK_SPEC LINUX_TARGET_LINK_SPEC
8853 +#define LINK_SPEC LINUX_TARGET_LINK_SPEC BE8_LINK_SPEC
8855 /* Use the default LIBGCC_SPEC, not the version in linux-elf.h, as we
8856 do not use -lfloat. */
8859 -/* Clear the instruction cache from `beg' to `end'. This makes an
8860 - inline system call to SYS_cacheflush. */
8861 +/* Clear the instruction cache from `beg' to `end'. This is
8862 + implemented in lib1funcs.asm, so ensure an error if this definition
8864 #undef CLEAR_INSN_CACHE
8865 -#define CLEAR_INSN_CACHE(BEG, END) \
8867 - register unsigned long _beg __asm ("a1") = (unsigned long) (BEG); \
8868 - register unsigned long _end __asm ("a2") = (unsigned long) (END); \
8869 - register unsigned long _flg __asm ("a3") = 0; \
8870 - register unsigned long _scno __asm ("r7") = 0xf0002; \
8871 - __asm __volatile ("swi 0 @ sys_cacheflush" \
8873 - : "0" (_beg), "r" (_end), "r" (_flg), "r" (_scno)); \
8875 +#define CLEAR_INSN_CACHE(BEG, END) not used
8876 --- a/gcc/config/arm/linux-elf.h
8877 +++ b/gcc/config/arm/linux-elf.h
8880 /* NWFPE always understands FPA instructions. */
8881 #undef FPUTYPE_DEFAULT
8882 -#define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU3
8883 +#define FPUTYPE_DEFAULT "fpe3"
8885 /* Call the function profiler with a given profile label. */
8886 #undef ARM_FUNCTION_PROFILER
8888 +++ b/gcc/config/arm/marvell-f-vfp.md
8890 +;; Marvell 2850 VFP pipeline description
8891 +;; Copyright (C) 2007 Free Software Foundation, Inc.
8892 +;; Written by CodeSourcery, Inc.
8894 +;; This file is part of GCC.
8896 +;; GCC is distributed in the hope that it will be useful, but WITHOUT
8897 +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
8898 +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
8899 +;; License for more details.
8901 +;; You should have received a copy of the GNU General Public License
8902 +;; along with GCC; see the file COPYING. If not, write to
8903 +;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
8904 +;; Boston, MA 02110-1301, USA.
8906 +;; This automaton provides a pipeline description for the Marvell
8909 +;; The model given here assumes that the condition for all conditional
8910 +;; instructions is "true", i.e., that all of the instructions are
8911 +;; actually executed.
8913 +(define_automaton "marvell_f_vfp")
8915 +;; This is a single-issue VFPv2 implementation with the following execution
8918 +;; 1. Addition/subtraction unit; takes three cycles, pipelined.
8919 +;; 2. Multiplication unit; takes four cycles, pipelined.
8920 +;; 3. Add buffer, used for multiply-accumulate (see below).
8921 +;; 4. Divide/square root unit, not pipelined.
8922 +;; For single-precision: takes sixteen cycles, can accept another insn
8923 +;; after fifteen cycles.
8924 +;; For double-precision: takes thirty-one cycles, can accept another insn
8925 +;; after thirty cycles.
8926 +;; 5. Single-cycle unit, pipelined.
8927 +;; This does absolute value/copy/negate/compare in one cycle and
8928 +;; conversion in two cycles.
8930 +;; When all three operands of a multiply-accumulate instruction are ready,
8931 +;; one is issued to the add buffer (which can hold six operands in a FIFO)
8932 +;; and the two to be multiplied are issued to the multiply unit. After
8933 +;; four cycles in the multiply unit, one cycle is taken to issue the
8934 +;; operand from the add buffer plus the multiplication result to the
8935 +;; addition/subtraction unit. That issue takes priority over any add/sub
8936 +;; instruction waiting at the normal issue stage, but may be performed in
8937 +;; parallel with the issue of a non-add/sub instruction. The total time
8938 +;; for a multiply-accumulate instruction to pass through the execution
8939 +;; units is hence eight cycles.
8941 +;; We do not need to explicitly model the add buffer because it can
8942 +;; always issue the instruction at the head of its FIFO (due to the above
8943 +;; priority rule) and there are more spaces in the add buffer (six) than
8944 +;; there are stages (four) in the multiplication unit.
8946 +;; Two instructions may be retired at once from the head of an 8-entry
8947 +;; reorder buffer. Data from these first two instructions only may be
8948 +;; forwarded to the inputs of the issue unit. We assume that the
8949 +;; pressure on the reorder buffer will be sufficiently low that every
8950 +;; instruction entering it will be eligible for data forwarding. Since
8951 +;; data is forwarded to the issue unit and not the execution units (so
8952 +;; for example single-cycle instructions cannot be issued back-to-back),
8953 +;; the latencies given below are the cycle counts above plus one.
8955 +(define_cpu_unit "mf_vfp_issue" "marvell_f_vfp")
8956 +(define_cpu_unit "mf_vfp_add" "marvell_f_vfp")
8957 +(define_cpu_unit "mf_vfp_mul" "marvell_f_vfp")
8958 +(define_cpu_unit "mf_vfp_div" "marvell_f_vfp")
8959 +(define_cpu_unit "mf_vfp_single_cycle" "marvell_f_vfp")
8961 +;; An attribute to indicate whether our reservations are applicable.
8963 +(define_attr "marvell_f_vfp" "yes,no"
8964 + (const (if_then_else (and (eq_attr "tune" "marvell_f")
8965 + (eq_attr "fpu" "vfp"))
8966 + (const_string "yes") (const_string "no"))))
8968 +;; Reservations of functional units. The nothing*2 reservations at the
8969 +;; start of many of the reservation strings correspond to the decode
8970 +;; stages. We need to have these reservations so that we can correctly
8971 +;; reserve parts of the core's A1 pipeline for loads and stores. For
8972 +;; that case (since loads skip E1) the pipelines line up thus:
8973 +;; A1 pipe: Issue E2 OF WR WB ...
8974 +;; VFP pipe: Fetch Decode1 Decode2 Issue Execute1 ...
8975 +;; For a load, we need to make a reservation of E2, and thus we must
8976 +;; use Decode1 as the starting point for all VFP reservations here.
8978 +;; For reservations of pipelined VFP execution units we only reserve
8979 +;; the execution unit for the first execution cycle, omitting any trailing
8980 +;; "nothing" reservations.
8982 +(define_insn_reservation "marvell_f_vfp_add" 4
8983 + (and (eq_attr "marvell_f_vfp" "yes")
8984 + (eq_attr "type" "farith"))
8985 + "nothing*2,mf_vfp_issue,mf_vfp_add")
8987 +(define_insn_reservation "marvell_f_vfp_mul" 5
8988 + (and (eq_attr "marvell_f_vfp" "yes")
8989 + (eq_attr "type" "fmuls,fmuld"))
8990 + "nothing*2,mf_vfp_issue,mf_vfp_mul")
8992 +(define_insn_reservation "marvell_f_vfp_divs" 17
8993 + (and (eq_attr "marvell_f_vfp" "yes")
8994 + (eq_attr "type" "fdivs"))
8995 + "nothing*2,mf_vfp_issue,mf_vfp_div*15")
8997 +(define_insn_reservation "marvell_f_vfp_divd" 32
8998 + (and (eq_attr "marvell_f_vfp" "yes")
8999 + (eq_attr "type" "fdivd"))
9000 + "nothing*2,mf_vfp_issue,mf_vfp_div*30")
9002 +;; The DFA lookahead is small enough that the "add" reservation here
9003 +;; will always take priority over any addition/subtraction instruction
9004 +;; issued five cycles after the multiply-accumulate instruction, as
9006 +(define_insn_reservation "marvell_f_vfp_mac" 9
9007 + (and (eq_attr "marvell_f_vfp" "yes")
9008 + (eq_attr "type" "fmacs,fmacd"))
9009 + "nothing*2,mf_vfp_issue,mf_vfp_mul,nothing*4,mf_vfp_add")
9011 +(define_insn_reservation "marvell_f_vfp_single" 2
9012 + (and (eq_attr "marvell_f_vfp" "yes")
9013 + (eq_attr "type" "ffarith"))
9014 + "nothing*2,mf_vfp_issue,mf_vfp_single_cycle")
9016 +(define_insn_reservation "marvell_f_vfp_convert" 3
9017 + (and (eq_attr "marvell_f_vfp" "yes")
9018 + (eq_attr "type" "f_cvt"))
9019 + "nothing*2,mf_vfp_issue,mf_vfp_single_cycle")
9021 +(define_insn_reservation "marvell_f_vfp_load" 2
9022 + (and (eq_attr "marvell_f_vfp" "yes")
9023 + (eq_attr "type" "f_loads,f_loadd"))
9024 + "a1_e2+sram,a1_of,a1_wr+mf_vfp_issue,a1_wb+mf_vfp_single_cycle")
9026 +(define_insn_reservation "marvell_f_vfp_from_core" 2
9027 + (and (eq_attr "marvell_f_vfp" "yes")
9028 + (eq_attr "type" "r_2_f"))
9029 + "a1_e2,a1_of,a1_wr+mf_vfp_issue,a1_wb+mf_vfp_single_cycle")
9031 +;; The interaction between the core and VFP pipelines during VFP
9032 +;; store operations and core <-> VFP moves is not clear, so we guess.
9033 +(define_insn_reservation "marvell_f_vfp_store" 3
9034 + (and (eq_attr "marvell_f_vfp" "yes")
9035 + (eq_attr "type" "f_stores,f_stored"))
9036 + "a1_e2,a1_of,mf_vfp_issue,a1_wr+sram+mf_vfp_single_cycle")
9038 +(define_insn_reservation "marvell_f_vfp_to_core" 4
9039 + (and (eq_attr "marvell_f_vfp" "yes")
9040 + (eq_attr "type" "f_2_r"))
9041 + "a1_e2,a1_of,a1_wr+mf_vfp_issue,a1_wb+mf_vfp_single_cycle")
9044 +++ b/gcc/config/arm/marvell-f.md
9046 +;; Marvell 2850 pipeline description
9047 +;; Copyright (C) 2005, 2006, 2007 Free Software Foundation, Inc.
9048 +;; Written by Marvell and CodeSourcery, Inc.
9050 +;; This file is part of GCC.
9052 +;; GCC is free software; you can redistribute it and/or modify it
9053 +;; under the terms of the GNU General Public License as published
9054 +;; by the Free Software Foundation; either version 2, or (at your
9055 +;; option) any later version.
9057 +;; GCC is distributed in the hope that it will be useful, but WITHOUT
9058 +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
9059 +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
9060 +;; License for more details.
9062 +;; You should have received a copy of the GNU General Public License
9063 +;; along with GCC; see the file COPYING. If not, write to
9064 +;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
9065 +;; Boston, MA 02110-1301, USA.
9067 +;; This automaton provides a pipeline description for the Marvell
9070 +;; The model given here assumes that the condition for all conditional
9071 +;; instructions is "true", i.e., that all of the instructions are
9072 +;; actually executed.
9074 +(define_automaton "marvell_f")
9076 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9078 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9080 +;; This is a dual-issue processor with three pipelines:
9082 +;; 1. Arithmetic and load/store pipeline A1.
9083 +;; Issue | E1 | E2 | OF | WR | WB for load-store instructions
9084 +;; Issue | E1 | E2 | WB for arithmetic instructions
9086 +;; 2. Arithmetic pipeline A2.
9087 +;; Issue | E1 | E2 | WB
9089 +;; 3. Multiply and multiply-accumulate pipeline.
9090 +;; Issue | MAC1 | MAC2 | MAC3 | WB
9092 +;; There are various bypasses modelled to a greater or lesser extent.
9094 +;; Latencies in this file correspond to the number of cycles after
9095 +;; the issue stage that it takes for the result of the instruction to
9096 +;; be computed, or for its side-effects to occur.
9098 +(define_cpu_unit "a1_e1,a1_e2,a1_of,a1_wr,a1_wb" "marvell_f") ; ALU 1
9099 +(define_cpu_unit "a2_e1,a2_e2,a2_wb" "marvell_f") ; ALU 2
9100 +(define_cpu_unit "m_1,m_2,m_3,m_wb" "marvell_f") ; MAC
9102 +;; We define an SRAM cpu unit to enable us to describe conflicts
9103 +;; between loads at the E2 stage and stores at the WR stage.
9105 +(define_cpu_unit "sram" "marvell_f")
9107 +;; Handling of dual-issue constraints.
9109 +;; Certain pairs of instructions can be issued in parallel, and certain
9110 +;; pairs cannot. We divide a subset of the instructions into groups as
9113 +;; - data processing 1 (mov, mvn);
9114 +;; - data processing 2 (adc, add, and, bic, cmn, cmp, eor, orr, rsb,
9115 +;; rsc, sbc, sub, teq, tst);
9116 +;; - load single (ldr, ldrb, ldrbt, ldrt, ldrh, ldrsb, ldrsh);
9117 +;; - store single (str, strb, strbt, strt, strh);
9118 +;; - swap (swp, swpb);
9120 +;; - count leading zeros and DSP add/sub (clz, qadd, qdadd, qsub, qdsub);
9121 +;; - multiply 2 (mul, muls, smull, umull, smulxy, smulls, umulls);
9122 +;; - multiply 3 (mla, mlas, smlal, umlal, smlaxy, smlalxy, smlawx,
9123 +;; smlawy, smlals, umlals);
9124 +;; - branches (b, bl, blx, bx).
9126 +;; Ignoring conditional execution, it is a good approximation to the core
9127 +;; to model that two instructions may only be issued in parallel if the
9128 +;; following conditions are met.
9129 +;; I. The instructions both fall into one of the above groups and their
9130 +;; corresponding groups have a entry in the matrix below that is not X.
9131 +;; II. The second instruction does not read any register updated by the
9132 +;; first instruction (already enforced by the GCC scheduler).
9133 +;; III. The second instruction does not need the carry flag updated by the
9134 +;; first instruction. Currently we do not model this.
9136 +;; First Second instruction group
9138 +;; DP1 DP2 L S SWP PLD CLZ M2 M3 B
9140 +;; DP1 ok ok ok ok ok ok ok ok ok ok
9141 +;; DP2(1) ok ok ok ok ok ok ok ok ok ok
9142 +;; DP2(2) ok (2) ok (4) ok ok ok ok X ok
9144 +;; SWP } ok ok X X X X ok ok ok ok
9146 +;; S(3) ok ok X X X X ok ok ok ok
9147 +;; S(4) ok (2) X X X X ok ok X ok
9148 +;; CLZ ok ok ok ok ok ok ok ok ok ok
9149 +;; M2 ok ok ok ok ok ok ok X X ok
9150 +;; M3 ok (2) ok (4) ok ok ok X X ok
9151 +;; B ok ok ok ok ok ok ok ok ok ok
9153 +;; (1) without register shift
9154 +;; (2) with register shift
9155 +;; (3) with immediate offset
9156 +;; (4) with register offset
9158 +;; We define a fake cpu unit "reg_shift_lock" to enforce constraints
9159 +;; between instructions in groups DP2(2) and M3. All other
9160 +;; constraints are enforced automatically by virtue of the limited
9161 +;; number of pipelines available for the various operations, with
9162 +;; the exception of constraints involving S(4) that we do not model.
9164 +(define_cpu_unit "reg_shift_lock" "marvell_f")
9166 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9167 +;; ALU instructions
9168 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9170 +;; 1. Certain logic operations can be retired after the E1 stage if
9171 +;; the pipeline is not already retiring another instruction. In this
9172 +;; model we assume this behaviour always holds for mov, mvn, and, orr, eor
9173 +;; instructions. If a register shift is involved and the instruction is
9174 +;; not mov or mvn, then a dual-issue constraint must be enforced.
9176 +;; The first two cases are separate so they can be identified for
9179 +(define_insn_reservation "marvell_f_alu_early_retire" 1
9180 + (and (eq_attr "tune" "marvell_f")
9181 + (and (eq_attr "type" "alu")
9182 + (eq_attr "insn" "mov,mvn,and,orr,eor")))
9183 + "(a1_e1,a1_wb)|(a2_e1,a2_wb)")
9185 +(define_insn_reservation "marvell_f_alu_early_retire_shift" 1
9186 + (and (eq_attr "tune" "marvell_f")
9187 + (and (eq_attr "type" "alu_shift_reg")
9188 + (eq_attr "insn" "mov,mvn,and,orr,eor")))
9189 + "(a1_e1,a1_wb)|(a2_e1,a2_wb)")
9191 +(define_insn_reservation "marvell_f_alu_early_retire_reg_shift1" 1
9192 + (and (eq_attr "tune" "marvell_f")
9193 + (and (eq_attr "type" "alu_shift_reg")
9194 + (eq_attr "insn" "mov,mvn")))
9195 + "(a1_e1,a1_wb)|(a2_e1,a2_wb)")
9197 +(define_insn_reservation "marvell_f_alu_early_retire_reg_shift2" 1
9198 + (and (eq_attr "tune" "marvell_f")
9199 + (and (eq_attr "type" "alu_shift_reg")
9200 + (eq_attr "insn" "and,orr,eor")))
9201 + "(reg_shift_lock+a1_e1,a1_wb)|(reg_shift_lock+a2_e1,a2_wb)")
9203 +;; 2. ALU operations with no shifted operand. These bypass the E1 stage if
9204 +;; the E2 stage of the corresponding pipeline is clear; here, we always
9205 +;; model this scenario [*]. We give the operation a latency of 1 yet reserve
9206 +;; both E1 and E2 for it (thus preventing the GCC scheduler, in the case
9207 +;; where both E1 and E2 of one pipeline are clear, from issuing one
9208 +;; instruction to each).
9210 +;; [*] The non-bypass case is a latency of two, reserving E1 on the first
9211 +;; cycle and E2 on the next. Due to the way the scheduler works we
9212 +;; have to choose between taking this as the default and taking the
9213 +;; above case (with latency one) as the default; we choose the latter.
9215 +(define_insn_reservation "marvell_f_alu_op_bypass_e1" 1
9216 + (and (eq_attr "tune" "marvell_f")
9217 + (and (eq_attr "type" "alu")
9218 + (not (eq_attr "insn" "mov,mvn,and,orr,eor"))))
9219 + "(a1_e1+a1_e2,a1_wb)|(a2_e1+a2_e2,a2_wb)")
9221 +;; 3. ALU operations with a shift-by-constant operand.
9223 +(define_insn_reservation "marvell_f_alu_shift_op" 2
9224 + (and (eq_attr "tune" "marvell_f")
9225 + (and (eq_attr "type" "alu_shift")
9226 + (not (eq_attr "insn" "mov,mvn,and,orr,eor"))))
9227 + "(a1_e1,a1_e2,a1_wb)|(a2_e1,a2_e2,a2_wb)")
9229 +;; 4. ALU operations with a shift-by-register operand. Since the
9230 +;; instruction is never mov or mvn, a dual-issue constraint must
9233 +(define_insn_reservation "marvell_f_alu_shift_reg_op" 2
9234 + (and (eq_attr "tune" "marvell_f")
9235 + (and (eq_attr "type" "alu_shift_reg")
9236 + (not (eq_attr "insn" "mov,mvn,and,orr,eor"))))
9237 + "(reg_shift_lock+a1_e1,a1_e2,a1_wb)|(reg_shift_lock+a2_e1,a2_e2,a2_wb)")
9239 +;; Given an ALU operation with shift (I1) followed by another ALU
9240 +;; operation (I2), with I2 depending on the destination register Rd of I1
9241 +;; and with I2 not using that value as the amount or the starting value for
9242 +;; a shift, then I1 and I2 may be issued to the same pipeline on
9243 +;; consecutive cycles. In terms of this model that corresponds to I1
9244 +;; having a latency of one cycle. There are three cases for various
9245 +;; I1 and I2 as follows.
9247 +;; (a) I1 has a constant or register shift and I2 doesn't have a shift at all.
9248 +(define_bypass 1 "marvell_f_alu_shift_op,\
9249 + marvell_f_alu_shift_reg_op"
9250 + "marvell_f_alu_op_bypass_e1,marvell_f_alu_early_retire")
9252 +;; (b) I1 has a constant or register shift and I2 has a constant shift.
9253 +;; Rd must not provide the starting value for the shift.
9254 +(define_bypass 1 "marvell_f_alu_shift_op,\
9255 + marvell_f_alu_shift_reg_op"
9256 + "marvell_f_alu_shift_op,marvell_f_alu_early_retire_shift"
9257 + "arm_no_early_alu_shift_value_dep")
9259 +;; (c) I1 has a constant or register shift and I2 has a register shift.
9260 +;; Rd must not provide the amount by which to shift.
9261 +(define_bypass 1 "marvell_f_alu_shift_op,\
9262 + marvell_f_alu_shift_reg_op"
9263 + "marvell_f_alu_shift_reg_op,\
9264 + marvell_f_alu_early_retire_reg_shift1,\
9265 + marvell_f_alu_early_retire_reg_shift2"
9266 + "arm_no_early_alu_shift_dep")
9268 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9269 +;; Multiplication instructions
9270 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9272 +;; Multiplication instructions in group "Multiply 2".
9274 +(define_insn_reservation "marvell_f_multiply_2" 3
9275 + (and (eq_attr "tune" "marvell_f")
9276 + (eq_attr "insn" "mul,muls,smull,umull,smulxy,smulls,umulls"))
9277 + "m_1,m_2,m_3,m_wb")
9279 +;; Multiplication instructions in group "Multiply 3". There is a
9280 +;; dual-issue constraint with non-multiplication ALU instructions
9281 +;; to be respected here.
9283 +(define_insn_reservation "marvell_f_multiply_3" 3
9284 + (and (eq_attr "tune" "marvell_f")
9285 + (eq_attr "insn" "mla,mlas,smlal,umlal,smlaxy,smlalxy,smlawx,\
9286 + smlawy,smlals,umlals"))
9287 + "reg_shift_lock+m_1,m_2,m_3,m_wb")
9289 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9290 +;; Branch instructions
9291 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9293 +;; Conditional backward b instructions can have a zero-cycle penalty, and
9294 +;; other conditional b and bl instructions have a one-cycle penalty if
9295 +;; predicted correctly. Currently we model the zero-cycle case for all
9298 +(define_insn_reservation "marvell_f_branches" 0
9299 + (and (eq_attr "tune" "marvell_f")
9300 + (eq_attr "type" "branch"))
9303 +;; Call latencies are not predictable; a semi-arbitrary very large
9304 +;; number is used as "positive infinity" for such latencies.
9306 +(define_insn_reservation "marvell_f_call" 32
9307 + (and (eq_attr "tune" "marvell_f")
9308 + (eq_attr "type" "call"))
9311 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9312 +;; Load/store instructions
9313 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9315 +;; The models for load/store instructions do not accurately describe
9316 +;; the difference between operations with a base register writeback.
9317 +;; These models assume that all memory references hit in dcache.
9319 +;; 1. Load/store for single registers.
9321 +;; The worst case for a load is when the load result is needed in E1
9322 +;; (for example for a register shift), giving a latency of four. Loads
9323 +;; skip E1 and access memory at the E2 stage.
9325 +(define_insn_reservation "marvell_f_load1" 4
9326 + (and (eq_attr "tune" "marvell_f")
9327 + (eq_attr "type" "load1,load_byte"))
9328 + "a1_e2+sram,a1_of,a1_wr,a1_wb")
9330 +;; The result for a load may be bypassed (to be available at the same
9331 +;; time as the load arrives in the WR stage, so effectively at the OF
9332 +;; stage) to the Rn operand at E2 with a latency of two. The result may
9333 +;; be bypassed to a non-Rn operand at E2 with a latency of three. For
9334 +;; instructions without shifts, detection of an Rn bypass situation is
9335 +;; difficult (because some of the instruction patterns switch their
9336 +;; operands), and so we do not model that here. For instructions with
9337 +;; shifts, the operand used at E2 will always be Rn, and so we can
9338 +;; model the latency-two bypass for these.
9340 +(define_bypass 2 "marvell_f_load1"
9341 + "marvell_f_alu_shift_op"
9342 + "arm_no_early_alu_shift_value_dep")
9344 +(define_bypass 2 "marvell_f_load1"
9345 + "marvell_f_alu_shift_reg_op"
9346 + "arm_no_early_alu_shift_dep")
9348 +;; Stores write at the WR stage and loads read at the E2 stage, giving
9349 +;; a store latency of three.
9351 +(define_insn_reservation "marvell_f_store1" 3
9352 + (and (eq_attr "tune" "marvell_f")
9353 + (eq_attr "type" "store1"))
9354 + "a1_e2,a1_of,a1_wr+sram,a1_wb")
9356 +;; 2. Load/store for two consecutive registers. These may be dealt
9357 +;; with in the same number of cycles as single loads and stores.
9359 +(define_insn_reservation "marvell_f_load2" 4
9360 + (and (eq_attr "tune" "marvell_f")
9361 + (eq_attr "type" "load2"))
9362 + "a1_e2+sram,a1_of,a1_wr,a1_wb")
9364 +(define_insn_reservation "marvell_f_store2" 3
9365 + (and (eq_attr "tune" "marvell_f")
9366 + (eq_attr "type" "store2"))
9367 + "a1_e2,a1_of,a1_wr+sram,a1_wb")
9369 +;; The first word of a doubleword load is eligible for the latency-two
9370 +;; bypass described above for single loads, but this is not modelled here.
9371 +;; We do however assume that either word may also be bypassed with
9372 +;; latency three for ALU operations with shifts (where the shift value and
9373 +;; amount do not depend on the loaded value) and latency four for ALU
9374 +;; operations without shifts. The latency four case is of course the default.
9376 +(define_bypass 3 "marvell_f_load2"
9377 + "marvell_f_alu_shift_op"
9378 + "arm_no_early_alu_shift_value_dep")
9380 +(define_bypass 3 "marvell_f_load2"
9381 + "marvell_f_alu_shift_reg_op"
9382 + "arm_no_early_alu_shift_dep")
9384 +;; 3. Load/store for more than two registers.
9386 +;; These instructions stall for an extra cycle in the decode stage;
9387 +;; individual load/store instructions for each register are then issued.
9388 +;; The load/store multiple instruction itself is removed from the decode
9389 +;; stage at the same time as the final load/store instruction is issued.
9390 +;; To complicate matters, pairs of loads/stores referencing two
9391 +;; consecutive registers will be issued together as doubleword operations.
9392 +;; We model a 3-word load as an LDR plus an LDRD, and a 4-word load
9393 +;; as two LDRDs; thus, these are allocated the same latencies (the
9394 +;; latency for two consecutive loads plus one for the setup stall).
9395 +;; The extra stall is modelled by reserving E1.
9397 +(define_insn_reservation "marvell_f_load3_4" 6
9398 + (and (eq_attr "tune" "marvell_f")
9399 + (eq_attr "type" "load3,load4"))
9400 + "a1_e1,a1_e1+a1_e2+sram,a1_e2+sram+a1_of,a1_of+a1_wr,a1_wr+a1_wb,a1_wb")
9402 +;; Bypasses are possible for ldm as for single loads, but we do not
9403 +;; model them here since the order of the constituent loads is
9404 +;; difficult to predict.
9406 +(define_insn_reservation "marvell_f_store3_4" 5
9407 + (and (eq_attr "tune" "marvell_f")
9408 + (eq_attr "type" "store3,store4"))
9409 + "a1_e1,a1_e1+a1_e2,a1_e2+a1_of,a1_of+a1_wr+sram,a1_wr+sram+a1_wb,a1_wb")
9411 --- a/gcc/config/arm/neon-gen.ml
9412 +++ b/gcc/config/arm/neon-gen.ml
9413 @@ -122,6 +122,7 @@ let rec signed_ctype = function
9414 | T_uint16 | T_int16 -> T_intHI
9415 | T_uint32 | T_int32 -> T_intSI
9416 | T_uint64 | T_int64 -> T_intDI
9417 + | T_float32 -> T_floatSF
9418 | T_poly8 -> T_intQI
9419 | T_poly16 -> T_intHI
9420 | T_arrayof (n, elt) -> T_arrayof (n, signed_ctype elt)
9421 @@ -320,7 +321,7 @@ let deftypes () =
9423 Format.print_newline ();
9424 (* Extra types not in <stdint.h>. *)
9425 - Format.printf "typedef __builtin_neon_sf float32_t;\n";
9426 + Format.printf "typedef float float32_t;\n";
9427 Format.printf "typedef __builtin_neon_poly8 poly8_t;\n";
9428 Format.printf "typedef __builtin_neon_poly16 poly16_t;\n"
9430 @@ -399,7 +400,11 @@ let _ =
9434 +"#if defined (__vxworks) && defined (_WRS_KERNEL)";
9435 +"#include <vxWorks.h>";
9437 "#include <stdint.h>";
9442 --- a/gcc/config/arm/neon-testgen.ml
9443 +++ b/gcc/config/arm/neon-testgen.ml
9444 @@ -51,8 +51,8 @@ let emit_prologue chan test_name =
9445 Printf.fprintf chan "/* This file was autogenerated by neon-testgen. */\n\n";
9446 Printf.fprintf chan "/* { dg-do assemble } */\n";
9447 Printf.fprintf chan "/* { dg-require-effective-target arm_neon_ok } */\n";
9448 - Printf.fprintf chan
9449 - "/* { dg-options \"-save-temps -O0 -mfpu=neon -mfloat-abi=softfp\" } */\n";
9450 + Printf.fprintf chan "/* { dg-options \"-save-temps -O0\" } */\n";
9451 + Printf.fprintf chan "/* { dg-add-options arm_neon } */\n";
9452 Printf.fprintf chan "\n#include \"arm_neon.h\"\n\n";
9453 Printf.fprintf chan "void test_%s (void)\n{\n" test_name
9455 --- a/gcc/config/arm/neon.md
9456 +++ b/gcc/config/arm/neon.md
9461 - (UNSPEC_VZIP2 204)])
9462 + (UNSPEC_VZIP2 204)
9463 + (UNSPEC_MISALIGNED_ACCESS 205)])
9465 ;; Double-width vector modes.
9466 (define_mode_iterator VD [V8QI V4HI V2SI V2SF])
9468 "=w,Uv,w, w, ?r,?w,?r,?r, ?Us")
9469 (match_operand:VD 1 "general_operand"
9470 " w,w, Dn,Uvi, w, r, r, Usi,r"))]
9473 + && (register_operand (operands[0], <MODE>mode)
9474 + || register_operand (operands[1], <MODE>mode))"
9476 if (which_alternative == 2)
9480 /* FIXME: If the memory layout is changed in big-endian mode, output_move_vfp
9481 below must be changed to output_move_neon (which will use the
9482 - element/structure loads/stores), and the constraint changed to 'Un' instead
9483 + element/structure loads/stores), and the constraint changed to 'Um' instead
9486 switch (which_alternative)
9488 "=w,Un,w, w, ?r,?w,?r,?r, ?Us")
9489 (match_operand:VQXMOV 1 "general_operand"
9490 " w,w, Dn,Uni, w, r, r, Usi, r"))]
9493 + && (register_operand (operands[0], <MODE>mode)
9494 + || register_operand (operands[1], <MODE>mode))"
9496 if (which_alternative == 2)
9498 @@ -549,6 +554,11 @@
9499 (match_operand:TI 1 "general_operand" ""))]
9502 + if (can_create_pseudo_p ())
9504 + if (GET_CODE (operands[0]) != REG)
9505 + operands[1] = force_reg (TImode, operands[1]);
9509 (define_expand "mov<mode>"
9510 @@ -556,12 +566,19 @@
9511 (match_operand:VSTRUCT 1 "general_operand" ""))]
9514 + if (can_create_pseudo_p ())
9516 + if (GET_CODE (operands[0]) != REG)
9517 + operands[1] = force_reg (<MODE>mode, operands[1]);
9521 (define_insn "*neon_mov<mode>"
9522 [(set (match_operand:VSTRUCT 0 "nonimmediate_operand" "=w,Ut,w")
9523 (match_operand:VSTRUCT 1 "general_operand" " w,w, Ut"))]
9526 + && (register_operand (operands[0], <MODE>mode)
9527 + || register_operand (operands[1], <MODE>mode))"
9529 switch (which_alternative)
9531 @@ -658,6 +675,49 @@
9532 neon_disambiguate_copy (operands, dest, src, 4);
9535 +(define_expand "movmisalign<mode>"
9536 + [(set (match_operand:VDQX 0 "nonimmediate_operand" "")
9537 + (unspec:VDQX [(match_operand:VDQX 1 "general_operand" "")]
9538 + UNSPEC_MISALIGNED_ACCESS))]
9539 + "TARGET_NEON && !BYTES_BIG_ENDIAN"
9541 + if (!s_register_operand (operands[0], <MODE>mode)
9542 + && !s_register_operand (operands[1], <MODE>mode))
9546 +(define_insn "*movmisalign<mode>_neon_store"
9547 + [(set (match_operand:VDX 0 "memory_operand" "=Um")
9548 + (unspec:VDX [(match_operand:VDX 1 "s_register_operand" " w")]
9549 + UNSPEC_MISALIGNED_ACCESS))]
9550 + "TARGET_NEON && !BYTES_BIG_ENDIAN"
9551 + "vst1.<V_sz_elem>\t{%P1}, %A0"
9552 + [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
9554 +(define_insn "*movmisalign<mode>_neon_load"
9555 + [(set (match_operand:VDX 0 "s_register_operand" "=w")
9556 + (unspec:VDX [(match_operand:VDX 1 "memory_operand" " Um")]
9557 + UNSPEC_MISALIGNED_ACCESS))]
9558 + "TARGET_NEON && !BYTES_BIG_ENDIAN"
9559 + "vld1.<V_sz_elem>\t{%P0}, %A1"
9560 + [(set_attr "neon_type" "neon_vld1_1_2_regs")])
9562 +(define_insn "*movmisalign<mode>_neon_store"
9563 + [(set (match_operand:VQX 0 "memory_operand" "=Um")
9564 + (unspec:VQX [(match_operand:VQX 1 "s_register_operand" " w")]
9565 + UNSPEC_MISALIGNED_ACCESS))]
9566 + "TARGET_NEON && !BYTES_BIG_ENDIAN"
9567 + "vst1.<V_sz_elem>\t{%q1}, %A0"
9568 + [(set_attr "neon_type" "neon_vst1_1_2_regs_vst2_2_regs")])
9570 +(define_insn "*movmisalign<mode>_neon_load"
9571 + [(set (match_operand:VQX 0 "s_register_operand" "=w")
9572 + (unspec:VQX [(match_operand:VQX 1 "general_operand" " Um")]
9573 + UNSPEC_MISALIGNED_ACCESS))]
9574 + "TARGET_NEON && !BYTES_BIG_ENDIAN"
9575 + "vld1.<V_sz_elem>\t{%q0}, %A1"
9576 + [(set_attr "neon_type" "neon_vld1_1_2_regs")])
9578 (define_insn "vec_set<mode>_internal"
9579 [(set (match_operand:VD 0 "s_register_operand" "=w")
9581 @@ -862,6 +922,50 @@
9582 (const_string "neon_mul_qqq_8_16_32_ddd_32")))))]
9585 +(define_insn "*mul<mode>3add<mode>_neon"
9586 + [(set (match_operand:VDQ 0 "s_register_operand" "=w")
9587 + (plus:VDQ (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
9588 + (match_operand:VDQ 3 "s_register_operand" "w"))
9589 + (match_operand:VDQ 1 "s_register_operand" "0")))]
9591 + "vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
9592 + [(set (attr "neon_type")
9593 + (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
9594 + (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
9595 + (const_string "neon_fp_vmla_ddd")
9596 + (const_string "neon_fp_vmla_qqq"))
9597 + (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
9599 + (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
9600 + (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
9601 + (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
9602 + (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
9603 + (const_string "neon_mla_qqq_8_16")
9604 + (const_string "neon_mla_qqq_32_qqd_32_scalar")))))]
9607 +(define_insn "*mul<mode>3neg<mode>add<mode>_neon"
9608 + [(set (match_operand:VDQ 0 "s_register_operand" "=w")
9609 + (minus:VDQ (match_operand:VDQ 1 "s_register_operand" "0")
9610 + (mult:VDQ (match_operand:VDQ 2 "s_register_operand" "w")
9611 + (match_operand:VDQ 3 "s_register_operand" "w"))))]
9613 + "vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
9614 + [(set (attr "neon_type")
9615 + (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
9616 + (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
9617 + (const_string "neon_fp_vmla_ddd")
9618 + (const_string "neon_fp_vmla_qqq"))
9619 + (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
9621 + (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
9622 + (const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
9623 + (const_string "neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
9624 + (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
9625 + (const_string "neon_mla_qqq_8_16")
9626 + (const_string "neon_mla_qqq_32_qqd_32_scalar")))))]
9629 (define_insn "ior<mode>3"
9630 [(set (match_operand:VDQ 0 "s_register_operand" "=w,w")
9631 (ior:VDQ (match_operand:VDQ 1 "s_register_operand" "w,0")
9632 --- a/gcc/config/arm/neon.ml
9633 +++ b/gcc/config/arm/neon.ml
9634 @@ -50,7 +50,7 @@ type vectype = T_int8x8 | T_int8x16
9635 | T_ptrto of vectype | T_const of vectype
9639 + | T_intDI | T_floatSF
9641 (* The meanings of the following are:
9642 TImode : "Tetra", two registers (four words).
9643 @@ -1693,6 +1693,7 @@ let string_of_vectype vt =
9644 | T_intHI -> "__builtin_neon_hi"
9645 | T_intSI -> "__builtin_neon_si"
9646 | T_intDI -> "__builtin_neon_di"
9647 + | T_floatSF -> "__builtin_neon_sf"
9648 | T_arrayof (num, base) ->
9649 let basename = name (fun x -> x) base in
9650 affix (Printf.sprintf "%sx%d" basename num)
9651 --- a/gcc/config/arm/netbsd-elf.h
9652 +++ b/gcc/config/arm/netbsd-elf.h
9653 @@ -153,5 +153,5 @@ do \
9656 #undef FPUTYPE_DEFAULT
9657 -#define FPUTYPE_DEFAULT FPUTYPE_VFP
9658 +#define FPUTYPE_DEFAULT "vfp"
9661 +++ b/gcc/config/arm/nocrt0.h
9663 +/* Definitions for generic libgloss based cofigs where crt0 is supplied by
9664 + the linker script.
9665 + Copyright (C) 2006 Free Software Foundation, Inc.
9667 + This file is part of GCC.
9669 + GCC is free software; you can redistribute it and/or modify it
9670 + under the terms of the GNU General Public License as published
9671 + by the Free Software Foundation; either version 3, or (at your
9672 + option) any later version.
9674 + GCC is distributed in the hope that it will be useful, but WITHOUT
9675 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
9676 + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
9677 + License for more details.
9679 + You should have received a copy of the GNU General Public License
9680 + along with GCC; see the file COPYING3. If not see
9681 + <http://www.gnu.org/licenses/>. */
9683 +#undef STARTFILE_SPEC
9684 +#define STARTFILE_SPEC " crti%O%s crtbegin%O%s"
9687 +#define LIB_SPEC "-lc"
9688 --- a/gcc/config/arm/predicates.md
9689 +++ b/gcc/config/arm/predicates.md
9691 || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS));
9694 +(define_special_predicate "subreg_lowpart_operator"
9695 + (and (match_code "subreg")
9696 + (match_test "subreg_lowpart_p (op)")))
9698 ;; Reg, subreg(reg) or const_int.
9699 (define_predicate "reg_or_int_operand"
9700 (ior (match_code "const_int")
9701 @@ -168,6 +172,11 @@
9702 (and (match_code "plus,minus,ior,xor,and")
9703 (match_test "mode == GET_MODE (op)")))
9705 +;; True for plus/minus operators
9706 +(define_special_predicate "plusminus_operator"
9707 + (and (match_code "plus,minus")
9708 + (match_test "mode == GET_MODE (op)")))
9710 ;; True for logical binary operators.
9711 (define_special_predicate "logical_binary_operator"
9712 (and (match_code "ior,xor,and")
9714 HOST_WIDE_INT i = 1, base = 0;
9717 + if (low_irq_latency)
9721 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
9724 HOST_WIDE_INT i = 1, base = 0;
9727 + if (low_irq_latency)
9731 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
9733 --- a/gcc/config/arm/sfp-machine.h
9734 +++ b/gcc/config/arm/sfp-machine.h
9736 #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
9737 #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
9739 +#define _FP_NANFRAC_H ((_FP_QNANBIT_H << 1) - 1)
9740 #define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
9741 #define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
9742 #define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
9743 +#define _FP_NANSIGN_H 0
9744 #define _FP_NANSIGN_S 0
9745 #define _FP_NANSIGN_D 0
9746 #define _FP_NANSIGN_Q 0
9748 #define __fixdfdi __aeabi_d2lz
9749 #define __fixunsdfdi __aeabi_d2ulz
9750 #define __floatdidf __aeabi_l2d
9751 +#define __extendhfsf2 __gnu_h2f_ieee
9752 +#define __truncsfhf2 __gnu_f2h_ieee
9754 #endif /* __ARM_EABI__ */
9755 --- a/gcc/config/arm/t-arm
9756 +++ b/gcc/config/arm/t-arm
9757 @@ -13,7 +13,9 @@ MD_INCLUDES= $(srcdir)/config/arm/arm-t
9758 $(srcdir)/config/arm/iwmmxt.md \
9759 $(srcdir)/config/arm/vfp.md \
9760 $(srcdir)/config/arm/neon.md \
9761 - $(srcdir)/config/arm/thumb2.md
9762 + $(srcdir)/config/arm/thumb2.md \
9763 + $(srcdir)/config/arm/marvell-f.md \
9764 + $(srcdir)/config/arm/hwdiv.md
9766 s-config s-conditions s-flags s-codes s-constants s-emit s-recog s-preds \
9767 s-opinit s-extract s-peep s-attr s-attrtab s-output: $(MD_INCLUDES)
9768 --- a/gcc/config/arm/t-arm-elf
9769 +++ b/gcc/config/arm/t-arm-elf
9770 @@ -24,10 +24,18 @@ MULTILIB_MATCHES =
9771 #MULTILIB_MATCHES += march?armv7=march?armv7-a
9772 #MULTILIB_MATCHES += march?armv7=march?armv7-r
9773 #MULTILIB_MATCHES += march?armv7=march?armv7-m
9774 +#MULTILIB_MATCHES += march?armv7=march?armv7e-m
9775 #MULTILIB_MATCHES += march?armv7=mcpu?cortex-a8
9776 #MULTILIB_MATCHES += march?armv7=mcpu?cortex-r4
9777 #MULTILIB_MATCHES += march?armv7=mcpu?cortex-m3
9779 +# Not quite true. We can support hard-vfp calling in Thumb2, but how do we
9780 +# express that here? Also, we really need architecture v5e or later
9782 +MULTILIB_OPTIONS += mfloat-abi=hard
9783 +MULTILIB_DIRNAMES += fpu
9784 +MULTILIB_EXCEPTIONS += *mthumb/*mfloat-abi=hard*
9786 # MULTILIB_OPTIONS += mcpu=ep9312
9787 # MULTILIB_DIRNAMES += ep9312
9788 # MULTILIB_EXCEPTIONS += *mthumb/*mcpu=ep9312*
9790 +++ b/gcc/config/arm/t-asa
9792 +# Overrides for ASA
9794 +# Here is the expected output from xgcc -print-multi-lib.
9796 +# .;@fno-omit-frame-pointer@mapcs-frame
9797 +# armv4t;@march=armv4t@fno-omit-frame-pointer@mapcs-frame
9798 +# armv6;@march=armv6@fno-omit-frame-pointer@mapcs-frame
9799 +# armv7a;@march=armv7-a@fno-omit-frame-pointer@mapcs-frame
9800 +# armv6f;@march=armv6@mfloat-abi=softfp@fno-omit-frame-pointer@mapcs-frame
9801 +# armv7af;@march=armv7-a@mfpu=neon@mfloat-abi=softfp@fno-omit-frame-pointer@mapcs-frame
9802 +# thumb2;@mthumb@march=armv7-a@fno-omit-frame-pointer@mapcs-frame
9803 +# thumb2f;@mthumb@march=armv7-a@mfpu=neon@mfloat-abi=softfp@fno-omit-frame-pointer@mapcs-frame
9805 +MULTILIB_OPTIONS = mthumb march=armv4t/march=armv6/march=armv7-a mfpu=neon mfloat-abi=softfp
9806 +MULTILIB_DIRNAMES = thumb v4t v6 v7a neon softfp
9809 +MULTILIB_EXTRA_OPTS = fno-omit-frame-pointer mapcs-frame
9811 +MULTILIB_EXCEPTIONS = mthumb
9812 +MULTILIB_EXCEPTIONS += mfpu=neon*
9813 +MULTILIB_EXCEPTIONS += mfloat-abi=softfp
9814 +MULTILIB_EXCEPTIONS += *march=armv4t*/*mfpu=neon*
9815 +MULTILIB_EXCEPTIONS += *march=armv4t*/*mfloat-abi=softfp*
9816 +MULTILIB_EXCEPTIONS += march=armv6/*mfpu=neon*
9817 +MULTILIB_EXCEPTIONS += mthumb/mfpu=neon
9818 +MULTILIB_EXCEPTIONS += mthumb/mfloat-abi=softfp
9819 +MULTILIB_EXCEPTIONS += mthumb/mfpu=neon*
9820 +MULTILIB_EXCEPTIONS += mthumb/march=armv6/mfpu=neon*
9822 +MULTILIB_OSDIRNAMES = march.armv4t=!armv4t
9823 +MULTILIB_OSDIRNAMES += march.armv6=!armv6
9824 +MULTILIB_OSDIRNAMES += march.armv6/mfloat-abi.softfp=!armv6f
9825 +MULTILIB_OSDIRNAMES += march.armv7-a=!armv7a
9826 +MULTILIB_OSDIRNAMES += march.armv7-a/mfpu.neon/mfloat-abi.softfp=!armv7af
9827 +MULTILIB_OSDIRNAMES += mthumb/march.armv7-a=!thumb2
9828 +MULTILIB_OSDIRNAMES += mthumb/march.armv7-a/mfpu.neon/mfloat-abi.softfp=!thumb2f
9830 +MULTILIB_ALIASES = march?armv4t=mthumb/march?armv4t
9831 +MULTILIB_ALIASES += march?armv6=mthumb/march?armv6
9832 +MULTILIB_ALIASES += march?armv6/mfloat-abi?softfp=mthumb/march?armv6/mfloat-abi?softfp
9833 +MULTILIB_ALIASES += march?armv7-a/mfpu?neon/mfloat-abi?softfp=march?armv7-a/mfpu?neon
9834 +MULTILIB_ALIASES += march?armv7-a/mfpu?neon/mfloat-abi?softfp=march?armv7-a/mfloat-abi?softfp
9835 +MULTILIB_ALIASES += mthumb/march?armv7-a/mfpu?neon/mfloat-abi?softfp=mthumb/march?armv7-a/mfpu?neon
9836 +MULTILIB_ALIASES += mthumb/march?armv7-a/mfpu?neon/mfloat-abi?softfp=mthumb/march?armv7-a/mfloat-abi?softfp
9837 --- a/gcc/config/arm/t-bpabi
9838 +++ b/gcc/config/arm/t-bpabi
9840 # Add the bpabi.S functions.
9841 -LIB1ASMFUNCS += _aeabi_lcmp _aeabi_ulcmp _aeabi_ldivmod _aeabi_uldivmod
9842 +LIB1ASMFUNCS += _aeabi_lcmp _aeabi_ulcmp _aeabi_ldivmod _aeabi_uldivmod \
9843 + _aeabi_idiv0 _aeabi_ldiv0
9845 # Add the BPABI C functions.
9846 LIB2FUNCS_EXTRA = $(srcdir)/config/arm/bpabi.c \
9847 $(srcdir)/config/arm/unaligned-funcs.c
9849 +LIB2FUNCS_STATIC_EXTRA = $(srcdir)/config/arm/fp16.c
9851 UNWIND_H = $(srcdir)/config/arm/unwind-arm.h
9852 LIB2ADDEH = $(srcdir)/config/arm/unwind-arm.c \
9853 $(srcdir)/config/arm/libunwind.S \
9854 --- a/gcc/config/arm/t-linux-eabi
9855 +++ b/gcc/config/arm/t-linux-eabi
9856 @@ -6,8 +6,8 @@ TARGET_LIBGCC2_CFLAGS = -fPIC
9860 -# Use a version of div0 which raises SIGFPE.
9861 -LIB1ASMFUNCS := $(filter-out _dvmd_tls,$(LIB1ASMFUNCS)) _dvmd_lnx
9862 +# Use a version of div0 which raises SIGFPE, and a special __clear_cache.
9863 +LIB1ASMFUNCS := $(filter-out _dvmd_tls,$(LIB1ASMFUNCS)) _dvmd_lnx _clear_cache
9865 # Multilib the standard Linux files. Don't include crti.o or crtn.o,
9866 # which are provided by glibc.
9867 --- a/gcc/config/arm/t-symbian
9868 +++ b/gcc/config/arm/t-symbian
9869 @@ -17,6 +17,9 @@ UNWIND_H = $(srcdir)/config/arm/unwind-a
9870 LIB2ADDEH = $(srcdir)/unwind-c.c $(srcdir)/config/arm/pr-support.c
9871 LIB2ADDEHDEP = $(UNWIND_H)
9873 +# Include half-float helpers.
9874 +LIB2FUNCS_STATIC_EXTRA = $(srcdir)/config/arm/fp16.c
9876 # Create a multilib for processors with VFP floating-point, and a
9877 # multilib for those without -- using the soft-float ABI in both
9878 # cases. Symbian OS object should be compiled with interworking
9879 --- a/gcc/config/arm/thumb2.md
9880 +++ b/gcc/config/arm/thumb2.md
9882 ;; changes made in armv5t as "thumb2". These are considered part
9883 ;; the 16-bit Thumb-1 instruction set.
9885 +(include "hwdiv.md")
9887 (define_insn "*thumb2_incscc"
9888 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
9889 (plus:SI (match_operator:SI 2 "arm_comparison_operator"
9890 @@ -172,34 +174,6 @@
9891 (set_attr "length" "8")]
9894 -(define_insn "*thumb2_abssi2"
9895 - [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
9896 - (abs:SI (match_operand:SI 1 "s_register_operand" "0,r")))
9897 - (clobber (reg:CC CC_REGNUM))]
9900 - cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
9901 - eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31"
9902 - [(set_attr "conds" "clob,*")
9903 - (set_attr "shift" "1")
9904 - ;; predicable can't be set based on the variant, so left as no
9905 - (set_attr "length" "10,8")]
9908 -(define_insn "*thumb2_neg_abssi2"
9909 - [(set (match_operand:SI 0 "s_register_operand" "=r,&r")
9910 - (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))))
9911 - (clobber (reg:CC CC_REGNUM))]
9914 - cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
9915 - eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31"
9916 - [(set_attr "conds" "clob,*")
9917 - (set_attr "shift" "1")
9918 - ;; predicable can't be set based on the variant, so left as no
9919 - (set_attr "length" "10,8")]
9922 (define_insn "*thumb2_movdi"
9923 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m")
9924 (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r"))]
9925 @@ -223,9 +197,14 @@
9926 (set_attr "neg_pool_range" "*,*,*,0,*")]
9929 +;; We have two alternatives here for memory loads (and similarly for stores)
9930 +;; to reflect the fact that the permissible constant pool ranges differ
9931 +;; between ldr instructions taking low regs and ldr instructions taking high
9932 +;; regs. The high register alternatives are not taken into account when
9933 +;; choosing register preferences in order to reflect their expense.
9934 (define_insn "*thumb2_movsi_insn"
9935 - [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m")
9936 - (match_operand:SI 1 "general_operand" "rk ,I,K,N,mi,rk"))]
9937 + [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l,*hk,m,*m")
9938 + (match_operand:SI 1 "general_operand" "rk ,I,K,j,mi,*mi,l,*hk"))]
9939 "TARGET_THUMB2 && ! TARGET_IWMMXT
9940 && !(TARGET_HARD_FLOAT && TARGET_VFP)
9941 && ( register_operand (operands[0], SImode)
9942 @@ -236,11 +215,13 @@
9949 - [(set_attr "type" "*,*,*,*,load1,store1")
9950 + [(set_attr "type" "*,*,*,*,load1,load1,store1,store1")
9951 (set_attr "predicable" "yes")
9952 - (set_attr "pool_range" "*,*,*,*,4096,*")
9953 - (set_attr "neg_pool_range" "*,*,*,*,0,*")]
9954 + (set_attr "pool_range" "*,*,*,*,1020,4096,*,*")
9955 + (set_attr "neg_pool_range" "*,*,*,*,0,0,*,*")]
9958 ;; ??? We can probably do better with thumb2
9959 @@ -1128,27 +1109,7 @@
9960 return \"add%!\\t%0, %1, %2\";
9962 [(set_attr "predicable" "yes")
9963 - (set_attr "length" "2")]
9966 -(define_insn "divsi3"
9967 - [(set (match_operand:SI 0 "s_register_operand" "=r")
9968 - (div:SI (match_operand:SI 1 "s_register_operand" "r")
9969 - (match_operand:SI 2 "s_register_operand" "r")))]
9970 - "TARGET_THUMB2 && arm_arch_hwdiv"
9971 - "sdiv%?\t%0, %1, %2"
9972 - [(set_attr "predicable" "yes")
9973 - (set_attr "insn" "sdiv")]
9976 -(define_insn "udivsi3"
9977 - [(set (match_operand:SI 0 "s_register_operand" "=r")
9978 - (udiv:SI (match_operand:SI 1 "s_register_operand" "r")
9979 - (match_operand:SI 2 "s_register_operand" "r")))]
9980 - "TARGET_THUMB2 && arm_arch_hwdiv"
9981 - "udiv%?\t%0, %1, %2"
9982 - [(set_attr "predicable" "yes")
9983 - (set_attr "insn" "udiv")]
9984 + (set_attr "length" "4")]
9987 (define_insn "*thumb2_subsi_short"
9988 @@ -1162,6 +1123,71 @@
9989 (set_attr "length" "2")]
9992 +;; 16-bit encodings of "muls" and "mul<c>". We only use these when
9993 +;; optimizing for size since "muls" is slow on all known
9994 +;; implementations and since "mul<c>" will be generated by
9995 +;; "*arm_mulsi3_v6" anyhow. The assembler will use a 16-bit encoding
9996 +;; for "mul<c>" whenever possible anyhow.
9998 + [(set (match_operand:SI 0 "low_register_operand" "")
9999 + (mult:SI (match_operand:SI 1 "low_register_operand" "")
10001 + "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
10003 + [(set (match_dup 0)
10004 + (mult:SI (match_dup 0) (match_dup 1)))
10005 + (clobber (reg:CC CC_REGNUM))])]
10010 + [(set (match_operand:SI 0 "low_register_operand" "")
10011 + (mult:SI (match_dup 0)
10012 + (match_operand:SI 1 "low_register_operand" "")))]
10013 + "TARGET_THUMB2 && optimize_size && peep2_regno_dead_p (0, CC_REGNUM)"
10015 + [(set (match_dup 0)
10016 + (mult:SI (match_dup 0) (match_dup 1)))
10017 + (clobber (reg:CC CC_REGNUM))])]
10021 +(define_insn "*thumb2_mulsi_short"
10022 + [(set (match_operand:SI 0 "low_register_operand" "=l")
10023 + (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
10024 + (match_operand:SI 2 "low_register_operand" "l")))
10025 + (clobber (reg:CC CC_REGNUM))]
10026 + "TARGET_THUMB2 && optimize_size && reload_completed"
10027 + "mul%!\\t%0, %2, %0"
10028 + [(set_attr "predicable" "yes")
10029 + (set_attr "length" "2")
10030 + (set_attr "insn" "muls")])
10032 +(define_insn "*thumb2_mulsi_short_compare0"
10033 + [(set (reg:CC_NOOV CC_REGNUM)
10035 + (mult:SI (match_operand:SI 1 "register_operand" "%0")
10036 + (match_operand:SI 2 "register_operand" "l"))
10038 + (set (match_operand:SI 0 "register_operand" "=l")
10039 + (mult:SI (match_dup 1) (match_dup 2)))]
10040 + "TARGET_THUMB2 && optimize_size"
10041 + "muls\\t%0, %2, %0"
10042 + [(set_attr "length" "2")
10043 + (set_attr "insn" "muls")])
10045 +(define_insn "*thumb2_mulsi_short_compare0_scratch"
10046 + [(set (reg:CC_NOOV CC_REGNUM)
10048 + (mult:SI (match_operand:SI 1 "register_operand" "%0")
10049 + (match_operand:SI 2 "register_operand" "l"))
10051 + (clobber (match_scratch:SI 0 "=r"))]
10052 + "TARGET_THUMB2 && optimize_size"
10053 + "muls\\t%0, %2, %0"
10054 + [(set_attr "length" "2")
10055 + (set_attr "insn" "muls")])
10057 (define_insn "*thumb2_cbz"
10058 [(set (pc) (if_then_else
10059 (eq (match_operand:SI 0 "s_register_operand" "l,?r")
10060 @@ -1171,7 +1197,7 @@
10061 (clobber (reg:CC CC_REGNUM))]
10064 - if (get_attr_length (insn) == 2 && which_alternative == 0)
10065 + if (get_attr_length (insn) == 2)
10066 return \"cbz\\t%0, %l1\";
10068 return \"cmp\\t%0, #0\;beq\\t%l1\";
10069 @@ -1179,7 +1205,8 @@
10070 [(set (attr "length")
10072 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
10073 - (le (minus (match_dup 1) (pc)) (const_int 128)))
10074 + (le (minus (match_dup 1) (pc)) (const_int 128))
10075 + (eq (symbol_ref ("which_alternative")) (const_int 0)))
10079 @@ -1193,7 +1220,7 @@
10080 (clobber (reg:CC CC_REGNUM))]
10083 - if (get_attr_length (insn) == 2 && which_alternative == 0)
10084 + if (get_attr_length (insn) == 2)
10085 return \"cbnz\\t%0, %l1\";
10087 return \"cmp\\t%0, #0\;bne\\t%l1\";
10088 @@ -1201,7 +1228,8 @@
10089 [(set (attr "length")
10091 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
10092 - (le (minus (match_dup 1) (pc)) (const_int 128)))
10093 + (le (minus (match_dup 1) (pc)) (const_int 128))
10094 + (eq (symbol_ref ("which_alternative")) (const_int 0)))
10098 --- a/gcc/config/arm/uclinux-eabi.h
10099 +++ b/gcc/config/arm/uclinux-eabi.h
10101 #undef ARM_DEFAULT_ABI
10102 #define ARM_DEFAULT_ABI ARM_ABI_AAPCS_LINUX
10104 +#undef LINK_GCC_C_SEQUENCE_SPEC
10105 +#define LINK_GCC_C_SEQUENCE_SPEC \
10106 + "--start-group %G %L --end-group"
10108 /* Clear the instruction cache from `beg' to `end'. This makes an
10109 inline system call to SYS_cacheflush. */
10110 #undef CLEAR_INSN_CACHE
10111 --- a/gcc/config/arm/unwind-arm.c
10112 +++ b/gcc/config/arm/unwind-arm.c
10113 @@ -1000,7 +1000,6 @@ __gnu_Unwind_Backtrace(_Unwind_Trace_Fn
10114 while (code != _URC_END_OF_STACK
10115 && code != _URC_FAILURE);
10118 restore_non_core_regs (&saved_vrs);
10121 @@ -1168,6 +1167,9 @@ __gnu_unwind_pr_common (_Unwind_State st
10123 matched = (void *)(ucbp + 1);
10124 rtti = _Unwind_decode_target2 ((_uw) &data[i + 1]);
10125 + /* There is no way to encode an exception
10126 + specification for 'class X * &', so
10127 + always pass false for is_reference. */
10128 if (__cxa_type_match (ucbp, (type_info *) rtti, 0,
10131 @@ -1197,8 +1199,6 @@ __gnu_unwind_pr_common (_Unwind_State st
10132 ucbp->barrier_cache.bitpattern[4] = (_uw) &data[1];
10134 if (data[0] & uint32_highbit)
10135 - phase2_call_unexpected_after_unwind = 1;
10138 data += rtti_count + 1;
10139 /* Setup for entry to the handler. */
10140 @@ -1208,6 +1208,8 @@ __gnu_unwind_pr_common (_Unwind_State st
10141 _Unwind_SetGR (context, 0, (_uw) ucbp);
10142 return _URC_INSTALL_CONTEXT;
10145 + phase2_call_unexpected_after_unwind = 1;
10147 if (data[0] & uint32_highbit)
10149 --- a/gcc/config/arm/unwind-arm.h
10150 +++ b/gcc/config/arm/unwind-arm.h
10151 @@ -229,9 +229,10 @@ extern "C" {
10154 #if (defined(linux) && !defined(__uClinux__)) || defined(__NetBSD__)
10155 - /* Pc-relative indirect. */
10156 + /* Pc-relative indirect. Propagate the bottom 2 bits, which can
10157 + contain referenceness information in gnu unwinding tables. */
10159 - tmp = *(_Unwind_Word *) tmp;
10160 + tmp = *(_Unwind_Word *) (tmp & ~(_Unwind_Word)3) | (tmp & 3);
10161 #elif defined(__symbian__) || defined(__uClinux__)
10162 /* Absolute pointer. Nothing more to do. */
10164 --- a/gcc/config/arm/vec-common.md
10165 +++ b/gcc/config/arm/vec-common.md
10168 || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
10170 + if (can_create_pseudo_p ())
10172 + if (GET_CODE (operands[0]) != REG)
10173 + operands[1] = force_reg (<MODE>mode, operands[1]);
10177 ;; Vector arithmetic. Expanders are blank, then unnamed insns implement
10178 --- a/gcc/config/arm/vfp.md
10179 +++ b/gcc/config/arm/vfp.md
10181 ;; problems because small constants get converted into adds.
10182 (define_insn "*arm_movsi_vfp"
10183 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m ,*t,r,*t,*t, *Uv")
10184 - (match_operand:SI 1 "general_operand" "rk, I,K,N,mi,rk,r,*t,*t,*Uvi,*t"))]
10185 + (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,rk,r,*t,*t,*Uvi,*t"))]
10186 "TARGET_ARM && TARGET_VFP && TARGET_HARD_FLOAT
10187 && ( s_register_operand (operands[0], SImode)
10188 || s_register_operand (operands[1], SImode))"
10189 @@ -82,13 +82,17 @@
10191 [(set_attr "predicable" "yes")
10192 (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_loads,f_stores")
10193 + (set_attr "neon_type" "*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
10194 + (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*")
10195 (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
10196 (set_attr "neg_pool_range" "*,*,*,*,4084,*,*,*,*,1008,*")]
10199 +;; See thumb2.md:thumb2_movsi_insn for an explanation of the split
10200 +;; high/low register alternatives for loads and stores here.
10201 (define_insn "*thumb2_movsi_vfp"
10202 - [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk,m,*t,r, *t,*t, *Uv")
10203 - (match_operand:SI 1 "general_operand" "rk, I,K,N,mi,rk,r,*t,*t,*Uvi,*t"))]
10204 + [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,l,*hk,m,*m,*t,r, *t,*t, *Uv")
10205 + (match_operand:SI 1 "general_operand" "rk, I,K,j,mi,*mi,l,*hk,r,*t,*t,*Uvi,*t"))]
10206 "TARGET_THUMB2 && TARGET_VFP && TARGET_HARD_FLOAT
10207 && ( s_register_operand (operands[0], SImode)
10208 || s_register_operand (operands[1], SImode))"
10209 @@ -102,25 +106,29 @@
10211 return \"movw%?\\t%0, %1\";
10213 - return \"ldr%?\\t%0, %1\";
10215 - return \"str%?\\t%1, %0\";
10216 + return \"ldr%?\\t%0, %1\";
10218 - return \"fmsr%?\\t%0, %1\\t%@ int\";
10220 - return \"fmrs%?\\t%0, %1\\t%@ int\";
10221 + return \"str%?\\t%1, %0\";
10223 + return \"fmsr%?\\t%0, %1\\t%@ int\";
10225 + return \"fmrs%?\\t%0, %1\\t%@ int\";
10227 return \"fcpys%?\\t%0, %1\\t%@ int\";
10229 + case 11: case 12:
10230 return output_move_vfp (operands);
10232 gcc_unreachable ();
10235 [(set_attr "predicable" "yes")
10236 - (set_attr "type" "*,*,*,*,load1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
10237 - (set_attr "pool_range" "*,*,*,*,4096,*,*,*,*,1020,*")
10238 - (set_attr "neg_pool_range" "*,*,*,*, 0,*,*,*,*,1008,*")]
10239 + (set_attr "type" "*,*,*,*,load1,load1,store1,store1,r_2_f,f_2_r,fcpys,f_load,f_store")
10240 + (set_attr "neon_type" "*,*,*,*,*,*,*,*,neon_mcr,neon_mrc,neon_vmov,*,*")
10241 + (set_attr "insn" "mov,mov,mvn,mov,*,*,*,*,*,*,*,*,*")
10242 + (set_attr "pool_range" "*,*,*,*,1020,4096,*,*,*,*,*,1020,*")
10243 + (set_attr "neg_pool_range" "*,*,*,*, 0, 0,*,*,*,*,*,1008,*")]
10247 @@ -145,7 +153,10 @@
10249 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
10251 - return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
10252 + if (TARGET_VFP_SINGLE)
10253 + return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
10255 + return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
10257 return output_move_vfp (operands);
10259 @@ -153,7 +164,14 @@
10262 [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
10263 - (set_attr "length" "8,8,8,4,4,4,4,4")
10264 + (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
10265 + (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
10266 + (eq_attr "alternative" "5")
10268 + (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1))
10272 (set_attr "pool_range" "*,1020,*,*,*,*,1020,*")
10273 (set_attr "neg_pool_range" "*,1008,*,*,*,*,1008,*")]
10275 @@ -172,7 +190,10 @@
10277 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
10279 - return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
10280 + if (TARGET_VFP_SINGLE)
10281 + return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
10283 + return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
10285 return output_move_vfp (operands);
10287 @@ -180,11 +201,123 @@
10290 [(set_attr "type" "*,load2,store2,r_2_f,f_2_r,ffarithd,f_load,f_store")
10291 - (set_attr "length" "8,8,8,4,4,4,4,4")
10292 + (set_attr "neon_type" "*,*,*,neon_mcr_2_mcrr,neon_mrrc,neon_vmov,*,*")
10293 + (set (attr "length") (cond [(eq_attr "alternative" "0,1,2") (const_int 8)
10294 + (eq_attr "alternative" "5")
10296 + (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1))
10300 (set_attr "pool_range" "*,4096,*,*,*,*,1020,*")
10301 (set_attr "neg_pool_range" "*, 0,*,*,*,*,1008,*")]
10305 +(define_insn "*movhf_vfp_neon"
10306 + [(set (match_operand:HF 0 "nonimmediate_operand" "= t,Um,r,m,t,r,t,r,r")
10307 + (match_operand:HF 1 "general_operand" " Um, t,m,r,t,r,r,t,F"))]
10308 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_NEON_FP16
10309 + && ( s_register_operand (operands[0], HFmode)
10310 + || s_register_operand (operands[1], HFmode))"
10312 + switch (which_alternative)
10314 + case 0: /* S register from memory */
10315 + return \"vld1.16\\t{%z0}, %A1\";
10316 + case 1: /* memory from S register */
10317 + return \"vst1.16\\t{%z1}, %A0\";
10318 + case 2: /* ARM register from memory */
10319 + return \"ldrh\\t%0, %1\\t%@ __fp16\";
10320 + case 3: /* memory from ARM register */
10321 + return \"strh\\t%1, %0\\t%@ __fp16\";
10322 + case 4: /* S register from S register */
10323 + return \"fcpys\\t%0, %1\";
10324 + case 5: /* ARM register from ARM register */
10325 + return \"mov\\t%0, %1\\t%@ __fp16\";
10326 + case 6: /* S register from ARM register */
10327 + return \"fmsr\\t%0, %1\";
10328 + case 7: /* ARM register from S register */
10329 + return \"fmrs\\t%0, %1\";
10330 + case 8: /* ARM register from constant */
10332 + REAL_VALUE_TYPE r;
10336 + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
10337 + bits = real_to_target (NULL, &r, HFmode);
10338 + ops[0] = operands[0];
10339 + ops[1] = GEN_INT (bits);
10340 + ops[2] = GEN_INT (bits & 0xff00);
10341 + ops[3] = GEN_INT (bits & 0x00ff);
10343 + if (arm_arch_thumb2)
10344 + output_asm_insn (\"movw\\t%0, %1\", ops);
10346 + output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
10350 + gcc_unreachable ();
10353 + [(set_attr "conds" "unconditional")
10354 + (set_attr "type" "*,*,load1,store1,fcpys,*,r_2_f,f_2_r,*")
10355 + (set_attr "neon_type" "neon_vld1_1_2_regs,neon_vst1_1_2_regs_vst2_2_regs,*,*,*,*,*,*,*")
10356 + (set_attr "length" "4,4,4,4,4,4,4,4,8")]
10359 +;; FP16 without element load/store instructions.
10360 +(define_insn "*movhf_vfp"
10361 + [(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,t,r,t,r,r")
10362 + (match_operand:HF 1 "general_operand" " m,r,t,r,r,t,F"))]
10363 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16 && !TARGET_NEON_FP16
10364 + && ( s_register_operand (operands[0], HFmode)
10365 + || s_register_operand (operands[1], HFmode))"
10367 + switch (which_alternative)
10369 + case 0: /* ARM register from memory */
10370 + return \"ldrh\\t%0, %1\\t%@ __fp16\";
10371 + case 1: /* memory from ARM register */
10372 + return \"strh\\t%1, %0\\t%@ __fp16\";
10373 + case 2: /* S register from S register */
10374 + return \"fcpys\\t%0, %1\";
10375 + case 3: /* ARM register from ARM register */
10376 + return \"mov\\t%0, %1\\t%@ __fp16\";
10377 + case 4: /* S register from ARM register */
10378 + return \"fmsr\\t%0, %1\";
10379 + case 5: /* ARM register from S register */
10380 + return \"fmrs\\t%0, %1\";
10381 + case 6: /* ARM register from constant */
10383 + REAL_VALUE_TYPE r;
10387 + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
10388 + bits = real_to_target (NULL, &r, HFmode);
10389 + ops[0] = operands[0];
10390 + ops[1] = GEN_INT (bits);
10391 + ops[2] = GEN_INT (bits & 0xff00);
10392 + ops[3] = GEN_INT (bits & 0x00ff);
10394 + if (arm_arch_thumb2)
10395 + output_asm_insn (\"movw\\t%0, %1\", ops);
10397 + output_asm_insn (\"mov\\t%0, %2\;orr\\t%0, %0, %3\", ops);
10401 + gcc_unreachable ();
10404 + [(set_attr "conds" "unconditional")
10405 + (set_attr "type" "load1,store1,fcpys,*,r_2_f,f_2_r,*")
10406 + (set_attr "length" "4,4,4,4,4,4,8")]
10411 ;; Disparage the w<->r cases because reloading an invalid address is
10412 @@ -222,6 +355,8 @@
10413 [(set_attr "predicable" "yes")
10415 "r_2_f,f_2_r,fconsts,f_loads,f_stores,load1,store1,fcpys,*")
10416 + (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
10417 + (set_attr "insn" "*,*,*,*,*,*,*,*,mov")
10418 (set_attr "pool_range" "*,*,*,1020,*,4096,*,*,*")
10419 (set_attr "neg_pool_range" "*,*,*,1008,*,4080,*,*,*")]
10421 @@ -258,6 +393,8 @@
10422 [(set_attr "predicable" "yes")
10424 "r_2_f,f_2_r,fconsts,f_load,f_store,load1,store1,fcpys,*")
10425 + (set_attr "neon_type" "neon_mcr,neon_mrc,*,*,*,*,*,neon_vmov,*")
10426 + (set_attr "insn" "*,*,*,*,*,*,*,*,mov")
10427 (set_attr "pool_range" "*,*,*,1020,*,4092,*,*,*")
10428 (set_attr "neg_pool_range" "*,*,*,1008,*,0,*,*,*")]
10430 @@ -267,7 +404,7 @@
10432 (define_insn "*movdf_vfp"
10433 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
10434 - (match_operand:DF 1 "soft_df_operand" " ?r,w,Dv,mF,r,UvF,w, w,r"))]
10435 + (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))]
10436 "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP
10437 && ( register_operand (operands[0], DFmode)
10438 || register_operand (operands[1], DFmode))"
10439 @@ -280,13 +417,17 @@
10441 return \"fmrrd%?\\t%Q0, %R0, %P1\";
10443 + gcc_assert (TARGET_VFP_DOUBLE);
10444 return \"fconstd%?\\t%P0, #%G1\";
10446 return output_move_double (operands);
10448 return output_move_vfp (operands);
10450 - return \"fcpyd%?\\t%P0, %P1\";
10451 + if (TARGET_VFP_SINGLE)
10452 + return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
10454 + return \"fcpyd%?\\t%P0, %P1\";
10458 @@ -296,14 +437,21 @@
10461 "r_2_f,f_2_r,fconstd,f_loadd,f_stored,load2,store2,ffarithd,*")
10462 - (set_attr "length" "4,4,4,8,8,4,4,4,8")
10463 + (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
10464 + (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
10465 + (eq_attr "alternative" "7")
10467 + (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1))
10471 (set_attr "pool_range" "*,*,*,1020,*,1020,*,*,*")
10472 (set_attr "neg_pool_range" "*,*,*,1008,*,1008,*,*,*")]
10475 (define_insn "*thumb2_movdf_vfp"
10476 [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=w,?r,w ,r, m,w ,Uv,w,r")
10477 - (match_operand:DF 1 "soft_df_operand" " ?r,w,Dv,mF,r,UvF,w, w,r"))]
10478 + (match_operand:DF 1 "soft_df_operand" " ?r,w,Dy,mF,r,UvF,w, w,r"))]
10479 "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
10482 @@ -314,13 +462,17 @@
10484 return \"fmrrd%?\\t%Q0, %R0, %P1\";
10486 + gcc_assert (TARGET_VFP_DOUBLE);
10487 return \"fconstd%?\\t%P0, #%G1\";
10488 case 3: case 4: case 8:
10489 return output_move_double (operands);
10491 return output_move_vfp (operands);
10493 - return \"fcpyd%?\\t%P0, %P1\";
10494 + if (TARGET_VFP_SINGLE)
10495 + return \"fcpys%?\\t%0, %1\;fcpys%?\\t%p0, %p1\";
10497 + return \"fcpyd%?\\t%P0, %P1\";
10501 @@ -328,7 +480,14 @@
10504 "r_2_f,f_2_r,fconstd,load2,store2,f_load,f_store,ffarithd,*")
10505 - (set_attr "length" "4,4,4,8,8,4,4,4,8")
10506 + (set_attr "neon_type" "neon_mcr_2_mcrr,neon_mrrc,*,*,*,*,*,neon_vmov,*")
10507 + (set (attr "length") (cond [(eq_attr "alternative" "3,4,8") (const_int 8)
10508 + (eq_attr "alternative" "7")
10510 + (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1))
10514 (set_attr "pool_range" "*,*,*,4096,*,1020,*,*,*")
10515 (set_attr "neg_pool_range" "*,*,*,0,*,1008,*,*,*")]
10517 @@ -356,7 +515,8 @@
10518 fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
10519 [(set_attr "conds" "use")
10520 (set_attr "length" "4,4,8,4,4,8,4,4,8")
10521 - (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
10522 + (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
10523 + (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")]
10526 (define_insn "*thumb2_movsfcc_vfp"
10527 @@ -379,7 +539,8 @@
10528 ite\\t%D3\;fmrs%D3\\t%0, %2\;fmrs%d3\\t%0, %1"
10529 [(set_attr "conds" "use")
10530 (set_attr "length" "6,6,10,6,6,10,6,6,10")
10531 - (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
10532 + (set_attr "type" "fcpys,fcpys,fcpys,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
10533 + (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr,neon_mcr,neon_mcr,neon_mrc,neon_mrc,neon_mrc")]
10536 (define_insn "*movdfcc_vfp"
10537 @@ -389,7 +550,7 @@
10538 [(match_operand 4 "cc_register" "") (const_int 0)])
10539 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
10540 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
10541 - "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP"
10542 + "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10544 fcpyd%D3\\t%P0, %P2
10545 fcpyd%d3\\t%P0, %P1
10546 @@ -402,7 +563,8 @@
10547 fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
10548 [(set_attr "conds" "use")
10549 (set_attr "length" "4,4,8,4,4,8,4,4,8")
10550 - (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
10551 + (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
10552 + (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")]
10555 (define_insn "*thumb2_movdfcc_vfp"
10556 @@ -412,7 +574,7 @@
10557 [(match_operand 4 "cc_register" "") (const_int 0)])
10558 (match_operand:DF 1 "s_register_operand" "0,w,w,0,?r,?r,0,w,w")
10559 (match_operand:DF 2 "s_register_operand" "w,0,w,?r,0,?r,w,0,w")))]
10560 - "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP"
10561 + "TARGET_THUMB2 && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10563 it\\t%D3\;fcpyd%D3\\t%P0, %P2
10564 it\\t%d3\;fcpyd%d3\\t%P0, %P1
10565 @@ -425,7 +587,8 @@
10566 ite\\t%D3\;fmrrd%D3\\t%Q0, %R0, %P2\;fmrrd%d3\\t%Q0, %R0, %P1"
10567 [(set_attr "conds" "use")
10568 (set_attr "length" "6,6,10,6,6,10,6,6,10")
10569 - (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")]
10570 + (set_attr "type" "ffarithd,ffarithd,ffarithd,r_2_f,r_2_f,r_2_f,f_2_r,f_2_r,f_2_r")
10571 + (set_attr "neon_type" "neon_vmov,neon_vmov,neon_vmov,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mcr_2_mcrr,neon_mrrc,neon_mrrc,neon_mrrc")]
10575 @@ -443,7 +606,7 @@
10576 (define_insn "*absdf2_vfp"
10577 [(set (match_operand:DF 0 "s_register_operand" "=w")
10578 (abs:DF (match_operand:DF 1 "s_register_operand" "w")))]
10579 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10580 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10581 "fabsd%?\\t%P0, %P1"
10582 [(set_attr "predicable" "yes")
10583 (set_attr "type" "ffarithd")]
10584 @@ -463,12 +626,12 @@
10585 (define_insn_and_split "*negdf2_vfp"
10586 [(set (match_operand:DF 0 "s_register_operand" "=w,?r,?r")
10587 (neg:DF (match_operand:DF 1 "s_register_operand" "w,0,r")))]
10588 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10589 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10594 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP && reload_completed
10595 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE && reload_completed
10596 && arm_general_register_operand (operands[0], DFmode)"
10597 [(set (match_dup 0) (match_dup 1))]
10599 @@ -523,7 +686,7 @@
10600 [(set (match_operand:DF 0 "s_register_operand" "=w")
10601 (plus:DF (match_operand:DF 1 "s_register_operand" "w")
10602 (match_operand:DF 2 "s_register_operand" "w")))]
10603 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10604 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10605 "faddd%?\\t%P0, %P1, %P2"
10606 [(set_attr "predicable" "yes")
10607 (set_attr "type" "faddd")]
10608 @@ -544,7 +707,7 @@
10609 [(set (match_operand:DF 0 "s_register_operand" "=w")
10610 (minus:DF (match_operand:DF 1 "s_register_operand" "w")
10611 (match_operand:DF 2 "s_register_operand" "w")))]
10612 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10613 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10614 "fsubd%?\\t%P0, %P1, %P2"
10615 [(set_attr "predicable" "yes")
10616 (set_attr "type" "faddd")]
10617 @@ -567,7 +730,7 @@
10618 [(set (match_operand:DF 0 "s_register_operand" "+w")
10619 (div:DF (match_operand:DF 1 "s_register_operand" "w")
10620 (match_operand:DF 2 "s_register_operand" "w")))]
10621 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10622 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10623 "fdivd%?\\t%P0, %P1, %P2"
10624 [(set_attr "predicable" "yes")
10625 (set_attr "type" "fdivd")]
10626 @@ -590,7 +753,7 @@
10627 [(set (match_operand:DF 0 "s_register_operand" "+w")
10628 (mult:DF (match_operand:DF 1 "s_register_operand" "w")
10629 (match_operand:DF 2 "s_register_operand" "w")))]
10630 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10631 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10632 "fmuld%?\\t%P0, %P1, %P2"
10633 [(set_attr "predicable" "yes")
10634 (set_attr "type" "fmuld")]
10635 @@ -611,7 +774,7 @@
10636 [(set (match_operand:DF 0 "s_register_operand" "+w")
10637 (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
10638 (match_operand:DF 2 "s_register_operand" "w")))]
10639 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10640 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10641 "fnmuld%?\\t%P0, %P1, %P2"
10642 [(set_attr "predicable" "yes")
10643 (set_attr "type" "fmuld")]
10644 @@ -626,7 +789,8 @@
10645 (plus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
10646 (match_operand:SF 3 "s_register_operand" "t"))
10647 (match_operand:SF 1 "s_register_operand" "0")))]
10648 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10649 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP
10650 + && (!arm_tune_marvell_f || optimize_size)"
10651 "fmacs%?\\t%0, %2, %3"
10652 [(set_attr "predicable" "yes")
10653 (set_attr "type" "fmacs")]
10654 @@ -637,7 +801,8 @@
10655 (plus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
10656 (match_operand:DF 3 "s_register_operand" "w"))
10657 (match_operand:DF 1 "s_register_operand" "0")))]
10658 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10659 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE
10660 + && (!arm_tune_marvell_f || optimize_size)"
10661 "fmacd%?\\t%P0, %P2, %P3"
10662 [(set_attr "predicable" "yes")
10663 (set_attr "type" "fmacd")]
10664 @@ -649,7 +814,8 @@
10665 (minus:SF (mult:SF (match_operand:SF 2 "s_register_operand" "t")
10666 (match_operand:SF 3 "s_register_operand" "t"))
10667 (match_operand:SF 1 "s_register_operand" "0")))]
10668 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10669 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP
10670 + && (!arm_tune_marvell_f || optimize_size)"
10671 "fmscs%?\\t%0, %2, %3"
10672 [(set_attr "predicable" "yes")
10673 (set_attr "type" "fmacs")]
10674 @@ -660,7 +826,8 @@
10675 (minus:DF (mult:DF (match_operand:DF 2 "s_register_operand" "w")
10676 (match_operand:DF 3 "s_register_operand" "w"))
10677 (match_operand:DF 1 "s_register_operand" "0")))]
10678 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10679 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE
10680 + && (!arm_tune_marvell_f || optimize_size)"
10681 "fmscd%?\\t%P0, %P2, %P3"
10682 [(set_attr "predicable" "yes")
10683 (set_attr "type" "fmacd")]
10684 @@ -672,7 +839,8 @@
10685 (minus:SF (match_operand:SF 1 "s_register_operand" "0")
10686 (mult:SF (match_operand:SF 2 "s_register_operand" "t")
10687 (match_operand:SF 3 "s_register_operand" "t"))))]
10688 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10689 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP
10690 + && (!arm_tune_marvell_f || optimize_size)"
10691 "fnmacs%?\\t%0, %2, %3"
10692 [(set_attr "predicable" "yes")
10693 (set_attr "type" "fmacs")]
10694 @@ -683,7 +851,8 @@
10695 (minus:DF (match_operand:DF 1 "s_register_operand" "0")
10696 (mult:DF (match_operand:DF 2 "s_register_operand" "w")
10697 (match_operand:DF 3 "s_register_operand" "w"))))]
10698 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10699 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE
10700 + && (!arm_tune_marvell_f || optimize_size)"
10701 "fnmacd%?\\t%P0, %P2, %P3"
10702 [(set_attr "predicable" "yes")
10703 (set_attr "type" "fmacd")]
10704 @@ -697,7 +866,8 @@
10705 (neg:SF (match_operand:SF 2 "s_register_operand" "t"))
10706 (match_operand:SF 3 "s_register_operand" "t"))
10707 (match_operand:SF 1 "s_register_operand" "0")))]
10708 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10709 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP
10710 + && (!arm_tune_marvell_f || optimize_size)"
10711 "fnmscs%?\\t%0, %2, %3"
10712 [(set_attr "predicable" "yes")
10713 (set_attr "type" "fmacs")]
10714 @@ -709,7 +879,8 @@
10715 (neg:DF (match_operand:DF 2 "s_register_operand" "w"))
10716 (match_operand:DF 3 "s_register_operand" "w"))
10717 (match_operand:DF 1 "s_register_operand" "0")))]
10718 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10719 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE
10720 + && (!arm_tune_marvell_f || optimize_size)"
10721 "fnmscd%?\\t%P0, %P2, %P3"
10722 [(set_attr "predicable" "yes")
10723 (set_attr "type" "fmacd")]
10724 @@ -721,7 +892,7 @@
10725 (define_insn "*extendsfdf2_vfp"
10726 [(set (match_operand:DF 0 "s_register_operand" "=w")
10727 (float_extend:DF (match_operand:SF 1 "s_register_operand" "t")))]
10728 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10729 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10730 "fcvtds%?\\t%P0, %1"
10731 [(set_attr "predicable" "yes")
10732 (set_attr "type" "f_cvt")]
10733 @@ -730,12 +901,30 @@
10734 (define_insn "*truncdfsf2_vfp"
10735 [(set (match_operand:SF 0 "s_register_operand" "=t")
10736 (float_truncate:SF (match_operand:DF 1 "s_register_operand" "w")))]
10737 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10738 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10739 "fcvtsd%?\\t%0, %P1"
10740 [(set_attr "predicable" "yes")
10741 (set_attr "type" "f_cvt")]
10744 +(define_insn "extendhfsf2"
10745 + [(set (match_operand:SF 0 "s_register_operand" "=t")
10746 + (float_extend:SF (match_operand:HF 1 "s_register_operand" "t")))]
10747 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
10748 + "vcvtb%?.f32.f16\\t%0, %1"
10749 + [(set_attr "predicable" "yes")
10750 + (set_attr "type" "f_cvt")]
10753 +(define_insn "truncsfhf2"
10754 + [(set (match_operand:HF 0 "s_register_operand" "=t")
10755 + (float_truncate:HF (match_operand:SF 1 "s_register_operand" "t")))]
10756 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FP16"
10757 + "vcvtb%?.f16.f32\\t%0, %1"
10758 + [(set_attr "predicable" "yes")
10759 + (set_attr "type" "f_cvt")]
10762 (define_insn "*truncsisf2_vfp"
10763 [(set (match_operand:SI 0 "s_register_operand" "=t")
10764 (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "t"))))]
10765 @@ -748,7 +937,7 @@
10766 (define_insn "*truncsidf2_vfp"
10767 [(set (match_operand:SI 0 "s_register_operand" "=t")
10768 (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "w"))))]
10769 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10770 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10771 "ftosizd%?\\t%0, %P1"
10772 [(set_attr "predicable" "yes")
10773 (set_attr "type" "f_cvt")]
10774 @@ -767,7 +956,7 @@
10775 (define_insn "fixuns_truncdfsi2"
10776 [(set (match_operand:SI 0 "s_register_operand" "=t")
10777 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "t"))))]
10778 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10779 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10780 "ftouizd%?\\t%0, %P1"
10781 [(set_attr "predicable" "yes")
10782 (set_attr "type" "f_cvt")]
10783 @@ -786,7 +975,7 @@
10784 (define_insn "*floatsidf2_vfp"
10785 [(set (match_operand:DF 0 "s_register_operand" "=w")
10786 (float:DF (match_operand:SI 1 "s_register_operand" "t")))]
10787 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10788 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10789 "fsitod%?\\t%P0, %1"
10790 [(set_attr "predicable" "yes")
10791 (set_attr "type" "f_cvt")]
10792 @@ -805,7 +994,7 @@
10793 (define_insn "floatunssidf2"
10794 [(set (match_operand:DF 0 "s_register_operand" "=w")
10795 (unsigned_float:DF (match_operand:SI 1 "s_register_operand" "t")))]
10796 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10797 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10798 "fuitod%?\\t%P0, %1"
10799 [(set_attr "predicable" "yes")
10800 (set_attr "type" "f_cvt")]
10801 @@ -826,7 +1015,7 @@
10802 (define_insn "*sqrtdf2_vfp"
10803 [(set (match_operand:DF 0 "s_register_operand" "=w")
10804 (sqrt:DF (match_operand:DF 1 "s_register_operand" "w")))]
10805 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10806 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10807 "fsqrtd%?\\t%P0, %P1"
10808 [(set_attr "predicable" "yes")
10809 (set_attr "type" "fdivd")]
10810 @@ -878,9 +1067,9 @@
10811 [(set (reg:CCFP CC_REGNUM)
10812 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w")
10813 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
10814 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10815 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10817 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10818 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10819 [(set (reg:CCFP VFPCC_REGNUM)
10820 (compare:CCFP (match_dup 0)
10822 @@ -893,9 +1082,9 @@
10823 [(set (reg:CCFPE CC_REGNUM)
10824 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w")
10825 (match_operand:DF 1 "vfp_compare_operand" "wG")))]
10826 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10827 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10829 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10830 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10831 [(set (reg:CCFPE VFPCC_REGNUM)
10832 (compare:CCFPE (match_dup 0)
10834 @@ -935,7 +1124,7 @@
10835 [(set (reg:CCFP VFPCC_REGNUM)
10836 (compare:CCFP (match_operand:DF 0 "s_register_operand" "w,w")
10837 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
10838 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10839 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10843 @@ -947,7 +1136,7 @@
10844 [(set (reg:CCFPE VFPCC_REGNUM)
10845 (compare:CCFPE (match_operand:DF 0 "s_register_operand" "w,w")
10846 (match_operand:DF 1 "vfp_compare_operand" "w,G")))]
10847 - "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
10848 + "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
10850 fcmped%?\\t%P0, %P1
10852 --- a/gcc/config/arm/vxworks.h
10853 +++ b/gcc/config/arm/vxworks.h
10854 @@ -97,7 +97,7 @@ along with GCC; see the file COPYING3.
10855 /* There is no default multilib. */
10856 #undef MULTILIB_DEFAULTS
10858 -#define FPUTYPE_DEFAULT FPUTYPE_VFP
10859 +#define FPUTYPE_DEFAULT "vfp"
10861 #undef FUNCTION_PROFILER
10862 #define FUNCTION_PROFILER VXWORKS_FUNCTION_PROFILER
10864 +++ b/gcc/config/i386/atom.md
10866 +;; Atom Scheduling
10867 +;; Copyright (C) 2009 Free Software Foundation, Inc.
10869 +;; This file is part of GCC.
10871 +;; GCC is free software; you can redistribute it and/or modify
10872 +;; it under the terms of the GNU General Public License as published by
10873 +;; the Free Software Foundation; either version 3, or (at your option)
10874 +;; any later version.
10876 +;; GCC is distributed in the hope that it will be useful,
10877 +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
10878 +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10879 +;; GNU General Public License for more details.
10881 +;; You should have received a copy of the GNU General Public License
10882 +;; along with GCC; see the file COPYING3. If not see
10883 +;; <http://www.gnu.org/licenses/>.
10885 +;; Atom is an in-order core with two integer pipelines.
10888 +(define_attr "atom_unit" "sishuf,simul,jeu,complex,other"
10889 + (const_string "other"))
10891 +(define_attr "atom_sse_attr" "rcp,movdup,lfence,fence,prefetch,sqrt,mxcsr,other"
10892 + (const_string "other"))
10894 +(define_automaton "atom")
10896 +;; Atom has two ports: port 0 and port 1 connecting to all execution units
10897 +(define_cpu_unit "atom-port-0,atom-port-1" "atom")
10899 +;; EU: Execution Unit
10900 +;; Atom EUs are connected by port 0 or port 1.
10902 +(define_cpu_unit "atom-eu-0, atom-eu-1,
10903 + atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4"
10906 +;; Some EUs have duplicated copied and can be accessed via either
10907 +;; port 0 or port 1
10908 +;; (define_reservation "atom-port-either" "(atom-port-0 | atom-port-1)")
10910 +;;; Some instructions is dual-pipe execution, need both ports
10911 +;;; Complex multi-op macro-instructoins need both ports and all EUs
10912 +(define_reservation "atom-port-dual" "(atom-port-0 + atom-port-1)")
10913 +(define_reservation "atom-all-eu" "(atom-eu-0 + atom-eu-1 +
10914 + atom-imul-1 + atom-imul-2 + atom-imul-3 +
10917 +;;; Most of simple instructions have 1 cycle latency. Some of them
10918 +;;; issue in port 0, some in port 0 and some in either port.
10919 +(define_reservation "atom-simple-0" "(atom-port-0 + atom-eu-0)")
10920 +(define_reservation "atom-simple-1" "(atom-port-1 + atom-eu-1)")
10921 +(define_reservation "atom-simple-either" "(atom-simple-0 | atom-simple-1)")
10923 +;;; Some insn issues in port 0 with 3 cycle latency and 1 cycle tput
10924 +(define_reservation "atom-eu-0-3-1" "(atom-port-0 + atom-eu-0, nothing*2)")
10926 +;;; fmul insn can have 4 or 5 cycles latency
10927 +(define_reservation "atom-fmul-5c" "(atom-port-0 + atom-eu-0), nothing*4")
10928 +(define_reservation "atom-fmul-4c" "(atom-port-0 + atom-eu-0), nothing*3")
10930 +;;; fadd can has 5 cycles latency depends on instruction forms
10931 +(define_reservation "atom-fadd-5c" "(atom-port-1 + atom-eu-1), nothing*5")
10933 +;;; imul insn has 5 cycles latency
10934 +(define_reservation "atom-imul-32"
10935 + "atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4,
10937 +;;; imul instruction excludes other non-FP instructions.
10938 +(exclusion_set "atom-eu-0, atom-eu-1"
10939 + "atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4")
10941 +;;; dual-execution instructions can have 1,2,4,5 cycles latency depends on
10942 +;;; instruction forms
10943 +(define_reservation "atom-dual-1c" "(atom-port-dual + atom-eu-0 + atom-eu-1)")
10944 +(define_reservation "atom-dual-2c"
10945 + "(atom-port-dual + atom-eu-0 + atom-eu-1, nothing)")
10946 +(define_reservation "atom-dual-5c"
10947 + "(atom-port-dual + atom-eu-0 + atom-eu-1, nothing*4)")
10949 +;;; Complex macro-instruction has variants of latency, and uses both ports.
10950 +(define_reservation "atom-complex" "(atom-port-dual + atom-all-eu)")
10952 +(define_insn_reservation "atom_other" 9
10953 + (and (eq_attr "cpu" "atom")
10954 + (and (eq_attr "type" "other")
10955 + (eq_attr "atom_unit" "!jeu")))
10956 + "atom-complex, atom-all-eu*8")
10958 +;; return has type "other" with atom_unit "jeu"
10959 +(define_insn_reservation "atom_other_2" 1
10960 + (and (eq_attr "cpu" "atom")
10961 + (and (eq_attr "type" "other")
10962 + (eq_attr "atom_unit" "jeu")))
10965 +(define_insn_reservation "atom_multi" 9
10966 + (and (eq_attr "cpu" "atom")
10967 + (eq_attr "type" "multi"))
10968 + "atom-complex, atom-all-eu*8")
10970 +;; Normal alu insns without carry
10971 +(define_insn_reservation "atom_alu" 1
10972 + (and (eq_attr "cpu" "atom")
10973 + (and (eq_attr "type" "alu")
10974 + (and (eq_attr "memory" "none")
10975 + (eq_attr "use_carry" "0"))))
10976 + "atom-simple-either")
10978 +;; Normal alu insns without carry
10979 +(define_insn_reservation "atom_alu_mem" 1
10980 + (and (eq_attr "cpu" "atom")
10981 + (and (eq_attr "type" "alu")
10982 + (and (eq_attr "memory" "!none")
10983 + (eq_attr "use_carry" "0"))))
10984 + "atom-simple-either")
10986 +;; Alu insn consuming CF, such as add/sbb
10987 +(define_insn_reservation "atom_alu_carry" 1
10988 + (and (eq_attr "cpu" "atom")
10989 + (and (eq_attr "type" "alu")
10990 + (and (eq_attr "memory" "none")
10991 + (eq_attr "use_carry" "1"))))
10992 + "atom-simple-either")
10994 +;; Alu insn consuming CF, such as add/sbb
10995 +(define_insn_reservation "atom_alu_carry_mem" 1
10996 + (and (eq_attr "cpu" "atom")
10997 + (and (eq_attr "type" "alu")
10998 + (and (eq_attr "memory" "!none")
10999 + (eq_attr "use_carry" "1"))))
11000 + "atom-simple-either")
11002 +(define_insn_reservation "atom_alu1" 1
11003 + (and (eq_attr "cpu" "atom")
11004 + (and (eq_attr "type" "alu1")
11005 + (eq_attr "memory" "none")))
11006 + "atom-simple-either")
11008 +(define_insn_reservation "atom_alu1_mem" 1
11009 + (and (eq_attr "cpu" "atom")
11010 + (and (eq_attr "type" "alu1")
11011 + (eq_attr "memory" "!none")))
11012 + "atom-simple-either")
11014 +(define_insn_reservation "atom_negnot" 1
11015 + (and (eq_attr "cpu" "atom")
11016 + (and (eq_attr "type" "negnot")
11017 + (eq_attr "memory" "none")))
11018 + "atom-simple-either")
11020 +(define_insn_reservation "atom_negnot_mem" 1
11021 + (and (eq_attr "cpu" "atom")
11022 + (and (eq_attr "type" "negnot")
11023 + (eq_attr "memory" "!none")))
11024 + "atom-simple-either")
11026 +(define_insn_reservation "atom_imov" 1
11027 + (and (eq_attr "cpu" "atom")
11028 + (and (eq_attr "type" "imov")
11029 + (eq_attr "memory" "none")))
11030 + "atom-simple-either")
11032 +(define_insn_reservation "atom_imov_mem" 1
11033 + (and (eq_attr "cpu" "atom")
11034 + (and (eq_attr "type" "imov")
11035 + (eq_attr "memory" "!none")))
11036 + "atom-simple-either")
11039 +(define_insn_reservation "atom_imovx" 1
11040 + (and (eq_attr "cpu" "atom")
11041 + (and (eq_attr "type" "imovx")
11042 + (and (eq_attr "memory" "none")
11043 + (ior (and (match_operand:HI 0 "register_operand")
11044 + (match_operand:HI 1 "general_operand"))
11045 + (and (match_operand:SI 0 "register_operand")
11046 + (match_operand:SI 1 "general_operand"))))))
11047 + "atom-simple-either")
11049 +;; 16<-16, 32<-32, mem
11050 +(define_insn_reservation "atom_imovx_mem" 1
11051 + (and (eq_attr "cpu" "atom")
11052 + (and (eq_attr "type" "imovx")
11053 + (and (eq_attr "memory" "!none")
11054 + (ior (and (match_operand:HI 0 "register_operand")
11055 + (match_operand:HI 1 "general_operand"))
11056 + (and (match_operand:SI 0 "register_operand")
11057 + (match_operand:SI 1 "general_operand"))))))
11058 + "atom-simple-either")
11060 +;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8
11061 +(define_insn_reservation "atom_imovx_2" 1
11062 + (and (eq_attr "cpu" "atom")
11063 + (and (eq_attr "type" "imovx")
11064 + (and (eq_attr "memory" "none")
11065 + (ior (match_operand:QI 0 "register_operand")
11066 + (ior (and (match_operand:SI 0 "register_operand")
11067 + (not (match_operand:SI 1 "general_operand")))
11068 + (match_operand:DI 0 "register_operand"))))))
11071 +;; 32<-16, 32<-8, 64<-16, 64<-8, 64<-32, 8<-8, mem
11072 +(define_insn_reservation "atom_imovx_2_mem" 1
11073 + (and (eq_attr "cpu" "atom")
11074 + (and (eq_attr "type" "imovx")
11075 + (and (eq_attr "memory" "!none")
11076 + (ior (match_operand:QI 0 "register_operand")
11077 + (ior (and (match_operand:SI 0 "register_operand")
11078 + (not (match_operand:SI 1 "general_operand")))
11079 + (match_operand:DI 0 "register_operand"))))))
11083 +(define_insn_reservation "atom_imovx_3" 3
11084 + (and (eq_attr "cpu" "atom")
11085 + (and (eq_attr "type" "imovx")
11086 + (and (match_operand:HI 0 "register_operand")
11087 + (match_operand:QI 1 "general_operand"))))
11088 + "atom-complex, atom-all-eu*2")
11090 +(define_insn_reservation "atom_lea" 1
11091 + (and (eq_attr "cpu" "atom")
11092 + (and (eq_attr "type" "lea")
11093 + (eq_attr "mode" "!HI")))
11094 + "atom-simple-either")
11096 +;; lea 16bit address is complex insn
11097 +(define_insn_reservation "atom_lea_2" 2
11098 + (and (eq_attr "cpu" "atom")
11099 + (and (eq_attr "type" "lea")
11100 + (eq_attr "mode" "HI")))
11101 + "atom-complex, atom-all-eu")
11103 +(define_insn_reservation "atom_incdec" 1
11104 + (and (eq_attr "cpu" "atom")
11105 + (and (eq_attr "type" "incdec")
11106 + (eq_attr "memory" "none")))
11107 + "atom-simple-either")
11109 +(define_insn_reservation "atom_incdec_mem" 1
11110 + (and (eq_attr "cpu" "atom")
11111 + (and (eq_attr "type" "incdec")
11112 + (eq_attr "memory" "!none")))
11113 + "atom-simple-either")
11115 +;; simple shift instruction use SHIFT eu, none memory
11116 +(define_insn_reservation "atom_ishift" 1
11117 + (and (eq_attr "cpu" "atom")
11118 + (and (eq_attr "type" "ishift")
11119 + (and (eq_attr "memory" "none") (eq_attr "prefix_0f" "0"))))
11122 +;; simple shift instruction use SHIFT eu, memory
11123 +(define_insn_reservation "atom_ishift_mem" 1
11124 + (and (eq_attr "cpu" "atom")
11125 + (and (eq_attr "type" "ishift")
11126 + (and (eq_attr "memory" "!none") (eq_attr "prefix_0f" "0"))))
11129 +;; DF shift (prefixed with 0f) is complex insn with latency of 7 cycles
11130 +(define_insn_reservation "atom_ishift_3" 7
11131 + (and (eq_attr "cpu" "atom")
11132 + (and (eq_attr "type" "ishift")
11133 + (eq_attr "prefix_0f" "1")))
11134 + "atom-complex, atom-all-eu*6")
11136 +(define_insn_reservation "atom_ishift1" 1
11137 + (and (eq_attr "cpu" "atom")
11138 + (and (eq_attr "type" "ishift1")
11139 + (eq_attr "memory" "none")))
11142 +(define_insn_reservation "atom_ishift1_mem" 1
11143 + (and (eq_attr "cpu" "atom")
11144 + (and (eq_attr "type" "ishift1")
11145 + (eq_attr "memory" "!none")))
11148 +(define_insn_reservation "atom_rotate" 1
11149 + (and (eq_attr "cpu" "atom")
11150 + (and (eq_attr "type" "rotate")
11151 + (eq_attr "memory" "none")))
11154 +(define_insn_reservation "atom_rotate_mem" 1
11155 + (and (eq_attr "cpu" "atom")
11156 + (and (eq_attr "type" "rotate")
11157 + (eq_attr "memory" "!none")))
11160 +(define_insn_reservation "atom_rotate1" 1
11161 + (and (eq_attr "cpu" "atom")
11162 + (and (eq_attr "type" "rotate1")
11163 + (eq_attr "memory" "none")))
11166 +(define_insn_reservation "atom_rotate1_mem" 1
11167 + (and (eq_attr "cpu" "atom")
11168 + (and (eq_attr "type" "rotate1")
11169 + (eq_attr "memory" "!none")))
11172 +(define_insn_reservation "atom_imul" 5
11173 + (and (eq_attr "cpu" "atom")
11174 + (and (eq_attr "type" "imul")
11175 + (and (eq_attr "memory" "none") (eq_attr "mode" "SI"))))
11178 +(define_insn_reservation "atom_imul_mem" 5
11179 + (and (eq_attr "cpu" "atom")
11180 + (and (eq_attr "type" "imul")
11181 + (and (eq_attr "memory" "!none") (eq_attr "mode" "SI"))))
11184 +;; latency set to 10 as common 64x64 imul
11185 +(define_insn_reservation "atom_imul_3" 10
11186 + (and (eq_attr "cpu" "atom")
11187 + (and (eq_attr "type" "imul")
11188 + (eq_attr "mode" "!SI")))
11189 + "atom-complex, atom-all-eu*9")
11191 +(define_insn_reservation "atom_idiv" 65
11192 + (and (eq_attr "cpu" "atom")
11193 + (eq_attr "type" "idiv"))
11194 + "atom-complex, atom-all-eu*32, nothing*32")
11196 +(define_insn_reservation "atom_icmp" 1
11197 + (and (eq_attr "cpu" "atom")
11198 + (and (eq_attr "type" "icmp")
11199 + (eq_attr "memory" "none")))
11200 + "atom-simple-either")
11202 +(define_insn_reservation "atom_icmp_mem" 1
11203 + (and (eq_attr "cpu" "atom")
11204 + (and (eq_attr "type" "icmp")
11205 + (eq_attr "memory" "!none")))
11206 + "atom-simple-either")
11208 +(define_insn_reservation "atom_test" 1
11209 + (and (eq_attr "cpu" "atom")
11210 + (and (eq_attr "type" "test")
11211 + (eq_attr "memory" "none")))
11212 + "atom-simple-either")
11214 +(define_insn_reservation "atom_test_mem" 1
11215 + (and (eq_attr "cpu" "atom")
11216 + (and (eq_attr "type" "test")
11217 + (eq_attr "memory" "!none")))
11218 + "atom-simple-either")
11220 +(define_insn_reservation "atom_ibr" 1
11221 + (and (eq_attr "cpu" "atom")
11222 + (and (eq_attr "type" "ibr")
11223 + (eq_attr "memory" "!load")))
11226 +;; complex if jump target is from address
11227 +(define_insn_reservation "atom_ibr_2" 2
11228 + (and (eq_attr "cpu" "atom")
11229 + (and (eq_attr "type" "ibr")
11230 + (eq_attr "memory" "load")))
11231 + "atom-complex, atom-all-eu")
11233 +(define_insn_reservation "atom_setcc" 1
11234 + (and (eq_attr "cpu" "atom")
11235 + (and (eq_attr "type" "setcc")
11236 + (eq_attr "memory" "!store")))
11237 + "atom-simple-either")
11239 +;; 2 cycles complex if target is in memory
11240 +(define_insn_reservation "atom_setcc_2" 2
11241 + (and (eq_attr "cpu" "atom")
11242 + (and (eq_attr "type" "setcc")
11243 + (eq_attr "memory" "store")))
11244 + "atom-complex, atom-all-eu")
11246 +(define_insn_reservation "atom_icmov" 1
11247 + (and (eq_attr "cpu" "atom")
11248 + (and (eq_attr "type" "icmov")
11249 + (eq_attr "memory" "none")))
11250 + "atom-simple-either")
11252 +(define_insn_reservation "atom_icmov_mem" 1
11253 + (and (eq_attr "cpu" "atom")
11254 + (and (eq_attr "type" "icmov")
11255 + (eq_attr "memory" "!none")))
11256 + "atom-simple-either")
11258 +;; UCODE if segreg, ignored
11259 +(define_insn_reservation "atom_push" 2
11260 + (and (eq_attr "cpu" "atom")
11261 + (eq_attr "type" "push"))
11264 +;; pop r64 is 1 cycle. UCODE if segreg, ignored
11265 +(define_insn_reservation "atom_pop" 1
11266 + (and (eq_attr "cpu" "atom")
11267 + (and (eq_attr "type" "pop")
11268 + (eq_attr "mode" "DI")))
11271 +;; pop non-r64 is 2 cycles. UCODE if segreg, ignored
11272 +(define_insn_reservation "atom_pop_2" 2
11273 + (and (eq_attr "cpu" "atom")
11274 + (and (eq_attr "type" "pop")
11275 + (eq_attr "mode" "!DI")))
11278 +;; UCODE if segreg, ignored
11279 +(define_insn_reservation "atom_call" 1
11280 + (and (eq_attr "cpu" "atom")
11281 + (eq_attr "type" "call"))
11284 +(define_insn_reservation "atom_callv" 1
11285 + (and (eq_attr "cpu" "atom")
11286 + (eq_attr "type" "callv"))
11289 +(define_insn_reservation "atom_leave" 3
11290 + (and (eq_attr "cpu" "atom")
11291 + (eq_attr "type" "leave"))
11292 + "atom-complex, atom-all-eu*2")
11294 +(define_insn_reservation "atom_str" 3
11295 + (and (eq_attr "cpu" "atom")
11296 + (eq_attr "type" "str"))
11297 + "atom-complex, atom-all-eu*2")
11299 +(define_insn_reservation "atom_sselog" 1
11300 + (and (eq_attr "cpu" "atom")
11301 + (and (eq_attr "type" "sselog")
11302 + (eq_attr "memory" "none")))
11303 + "atom-simple-either")
11305 +(define_insn_reservation "atom_sselog_mem" 1
11306 + (and (eq_attr "cpu" "atom")
11307 + (and (eq_attr "type" "sselog")
11308 + (eq_attr "memory" "!none")))
11309 + "atom-simple-either")
11311 +(define_insn_reservation "atom_sselog1" 1
11312 + (and (eq_attr "cpu" "atom")
11313 + (and (eq_attr "type" "sselog1")
11314 + (eq_attr "memory" "none")))
11317 +(define_insn_reservation "atom_sselog1_mem" 1
11318 + (and (eq_attr "cpu" "atom")
11319 + (and (eq_attr "type" "sselog1")
11320 + (eq_attr "memory" "!none")))
11323 +;; not pmad, not psad
11324 +(define_insn_reservation "atom_sseiadd" 1
11325 + (and (eq_attr "cpu" "atom")
11326 + (and (eq_attr "type" "sseiadd")
11327 + (and (not (match_operand:V2DI 0 "register_operand"))
11328 + (and (eq_attr "atom_unit" "!simul")
11329 + (eq_attr "atom_unit" "!complex")))))
11330 + "atom-simple-either")
11332 +;; pmad, psad and 64
11333 +(define_insn_reservation "atom_sseiadd_2" 4
11334 + (and (eq_attr "cpu" "atom")
11335 + (and (eq_attr "type" "sseiadd")
11336 + (and (not (match_operand:V2DI 0 "register_operand"))
11337 + (and (eq_attr "atom_unit" "simul" )
11338 + (eq_attr "mode" "DI")))))
11341 +;; pmad, psad and 128
11342 +(define_insn_reservation "atom_sseiadd_3" 5
11343 + (and (eq_attr "cpu" "atom")
11344 + (and (eq_attr "type" "sseiadd")
11345 + (and (not (match_operand:V2DI 0 "register_operand"))
11346 + (and (eq_attr "atom_unit" "simul" )
11347 + (eq_attr "mode" "TI")))))
11350 +;; if paddq(64 bit op), phadd/phsub
11351 +(define_insn_reservation "atom_sseiadd_4" 6
11352 + (and (eq_attr "cpu" "atom")
11353 + (and (eq_attr "type" "sseiadd")
11354 + (ior (match_operand:V2DI 0 "register_operand")
11355 + (eq_attr "atom_unit" "complex"))))
11356 + "atom-complex, atom-all-eu*5")
11358 +;; if immediate op.
11359 +(define_insn_reservation "atom_sseishft" 1
11360 + (and (eq_attr "cpu" "atom")
11361 + (and (eq_attr "type" "sseishft")
11362 + (and (eq_attr "atom_unit" "!sishuf")
11363 + (match_operand 2 "immediate_operand"))))
11364 + "atom-simple-either")
11366 +;; if palignr or psrldq
11367 +(define_insn_reservation "atom_sseishft_2" 1
11368 + (and (eq_attr "cpu" "atom")
11369 + (and (eq_attr "type" "sseishft")
11370 + (and (eq_attr "atom_unit" "sishuf")
11371 + (match_operand 2 "immediate_operand"))))
11375 +(define_insn_reservation "atom_sseishft_3" 2
11376 + (and (eq_attr "cpu" "atom")
11377 + (and (eq_attr "type" "sseishft")
11378 + (not (match_operand 2 "immediate_operand"))))
11379 + "atom-complex, atom-all-eu")
11381 +(define_insn_reservation "atom_sseimul" 1
11382 + (and (eq_attr "cpu" "atom")
11383 + (eq_attr "type" "sseimul"))
11386 +;; rcpss or rsqrtss
11387 +(define_insn_reservation "atom_sse" 4
11388 + (and (eq_attr "cpu" "atom")
11389 + (and (eq_attr "type" "sse")
11390 + (and (eq_attr "atom_sse_attr" "rcp") (eq_attr "mode" "SF"))))
11393 +;; movshdup, movsldup. Suggest to type sseishft
11394 +(define_insn_reservation "atom_sse_2" 1
11395 + (and (eq_attr "cpu" "atom")
11396 + (and (eq_attr "type" "sse")
11397 + (eq_attr "atom_sse_attr" "movdup")))
11401 +(define_insn_reservation "atom_sse_3" 1
11402 + (and (eq_attr "cpu" "atom")
11403 + (and (eq_attr "type" "sse")
11404 + (eq_attr "atom_sse_attr" "lfence")))
11405 + "atom-simple-either")
11407 +;; sfence,clflush,mfence, prefetch
11408 +(define_insn_reservation "atom_sse_4" 1
11409 + (and (eq_attr "cpu" "atom")
11410 + (and (eq_attr "type" "sse")
11411 + (ior (eq_attr "atom_sse_attr" "fence")
11412 + (eq_attr "atom_sse_attr" "prefetch"))))
11415 +;; rcpps, rsqrtss, sqrt, ldmxcsr
11416 +(define_insn_reservation "atom_sse_5" 7
11417 + (and (eq_attr "cpu" "atom")
11418 + (and (eq_attr "type" "sse")
11419 + (ior (ior (eq_attr "atom_sse_attr" "sqrt")
11420 + (eq_attr "atom_sse_attr" "mxcsr"))
11421 + (and (eq_attr "atom_sse_attr" "rcp")
11422 + (eq_attr "mode" "V4SF")))))
11423 + "atom-complex, atom-all-eu*6")
11426 +(define_insn_reservation "atom_ssemov" 1
11427 + (and (eq_attr "cpu" "atom")
11428 + (and (eq_attr "type" "ssemov")
11429 + (and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "xy"))))
11430 + "atom-simple-either")
11433 +(define_insn_reservation "atom_ssemov_2" 1
11434 + (and (eq_attr "cpu" "atom")
11435 + (and (eq_attr "type" "ssemov")
11436 + (and (match_operand 0 "register_operand" "xy") (match_operand 1 "register_operand" "r"))))
11440 +(define_insn_reservation "atom_ssemov_3" 3
11441 + (and (eq_attr "cpu" "atom")
11442 + (and (eq_attr "type" "ssemov")
11443 + (and (match_operand 0 "register_operand" "r") (match_operand 1 "register_operand" "xy"))))
11447 +(define_insn_reservation "atom_ssemov_4" 1
11448 + (and (eq_attr "cpu" "atom")
11449 + (and (eq_attr "type" "ssemov")
11450 + (and (eq_attr "movu" "0") (eq_attr "memory" "!none"))))
11454 +(define_insn_reservation "atom_ssemov_5" 2
11455 + (and (eq_attr "cpu" "atom")
11456 + (and (eq_attr "type" "ssemov")
11457 + (ior (eq_attr "movu" "1") (eq_attr "memory" "!none"))))
11458 + "atom-complex, atom-all-eu")
11460 +;; no memory simple
11461 +(define_insn_reservation "atom_sseadd" 5
11462 + (and (eq_attr "cpu" "atom")
11463 + (and (eq_attr "type" "sseadd")
11464 + (and (eq_attr "memory" "none")
11465 + (and (eq_attr "mode" "!V2DF")
11466 + (eq_attr "atom_unit" "!complex")))))
11470 +(define_insn_reservation "atom_sseadd_mem" 5
11471 + (and (eq_attr "cpu" "atom")
11472 + (and (eq_attr "type" "sseadd")
11473 + (and (eq_attr "memory" "!none")
11474 + (and (eq_attr "mode" "!V2DF")
11475 + (eq_attr "atom_unit" "!complex")))))
11478 +;; maxps, minps, *pd, hadd, hsub
11479 +(define_insn_reservation "atom_sseadd_3" 8
11480 + (and (eq_attr "cpu" "atom")
11481 + (and (eq_attr "type" "sseadd")
11482 + (ior (eq_attr "mode" "V2DF") (eq_attr "atom_unit" "complex"))))
11483 + "atom-complex, atom-all-eu*7")
11485 +;; Except dppd/dpps
11486 +(define_insn_reservation "atom_ssemul" 5
11487 + (and (eq_attr "cpu" "atom")
11488 + (and (eq_attr "type" "ssemul")
11489 + (eq_attr "mode" "!SF")))
11492 +;; Except dppd/dpps, 4 cycle if mulss
11493 +(define_insn_reservation "atom_ssemul_2" 4
11494 + (and (eq_attr "cpu" "atom")
11495 + (and (eq_attr "type" "ssemul")
11496 + (eq_attr "mode" "SF")))
11499 +(define_insn_reservation "atom_ssecmp" 1
11500 + (and (eq_attr "cpu" "atom")
11501 + (eq_attr "type" "ssecmp"))
11502 + "atom-simple-either")
11504 +(define_insn_reservation "atom_ssecomi" 10
11505 + (and (eq_attr "cpu" "atom")
11506 + (eq_attr "type" "ssecomi"))
11507 + "atom-complex, atom-all-eu*9")
11509 +;; no memory and cvtpi2ps, cvtps2pi, cvttps2pi
11510 +(define_insn_reservation "atom_ssecvt" 5
11511 + (and (eq_attr "cpu" "atom")
11512 + (and (eq_attr "type" "ssecvt")
11513 + (ior (and (match_operand:V2SI 0 "register_operand")
11514 + (match_operand:V4SF 1 "register_operand"))
11515 + (and (match_operand:V4SF 0 "register_operand")
11516 + (match_operand:V2SI 1 "register_operand")))))
11519 +;; memory and cvtpi2ps, cvtps2pi, cvttps2pi
11520 +(define_insn_reservation "atom_ssecvt_2" 5
11521 + (and (eq_attr "cpu" "atom")
11522 + (and (eq_attr "type" "ssecvt")
11523 + (ior (and (match_operand:V2SI 0 "register_operand")
11524 + (match_operand:V4SF 1 "memory_operand"))
11525 + (and (match_operand:V4SF 0 "register_operand")
11526 + (match_operand:V2SI 1 "memory_operand")))))
11529 +;; otherwise. 7 cycles average for cvtss2sd
11530 +(define_insn_reservation "atom_ssecvt_3" 7
11531 + (and (eq_attr "cpu" "atom")
11532 + (and (eq_attr "type" "ssecvt")
11533 + (not (ior (and (match_operand:V2SI 0 "register_operand")
11534 + (match_operand:V4SF 1 "nonimmediate_operand"))
11535 + (and (match_operand:V4SF 0 "register_operand")
11536 + (match_operand:V2SI 1 "nonimmediate_operand"))))))
11537 + "atom-complex, atom-all-eu*6")
11539 +;; memory and cvtsi2sd
11540 +(define_insn_reservation "atom_sseicvt" 5
11541 + (and (eq_attr "cpu" "atom")
11542 + (and (eq_attr "type" "sseicvt")
11543 + (and (match_operand:V2DF 0 "register_operand")
11544 + (match_operand:SI 1 "memory_operand"))))
11547 +;; otherwise. 8 cycles average for cvtsd2si
11548 +(define_insn_reservation "atom_sseicvt_2" 8
11549 + (and (eq_attr "cpu" "atom")
11550 + (and (eq_attr "type" "sseicvt")
11551 + (not (and (match_operand:V2DF 0 "register_operand")
11552 + (match_operand:SI 1 "memory_operand")))))
11553 + "atom-complex, atom-all-eu*7")
11555 +(define_insn_reservation "atom_ssediv" 62
11556 + (and (eq_attr "cpu" "atom")
11557 + (eq_attr "type" "ssediv"))
11558 + "atom-complex, atom-all-eu*12, nothing*49")
11560 +;; simple for fmov
11561 +(define_insn_reservation "atom_fmov" 1
11562 + (and (eq_attr "cpu" "atom")
11563 + (and (eq_attr "type" "fmov")
11564 + (eq_attr "memory" "none")))
11565 + "atom-simple-either")
11567 +;; simple for fmov
11568 +(define_insn_reservation "atom_fmov_mem" 1
11569 + (and (eq_attr "cpu" "atom")
11570 + (and (eq_attr "type" "fmov")
11571 + (eq_attr "memory" "!none")))
11572 + "atom-simple-either")
11574 +;; Define bypass here
11576 +;; There will be no stall from lea to non-mem EX insns
11577 +(define_bypass 0 "atom_lea"
11579 + atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
11580 + atom_incdec, atom_setcc, atom_icmov, atom_pop")
11582 +(define_bypass 0 "atom_lea"
11583 + "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
11584 + atom_imovx_mem, atom_imovx_2_mem,
11585 + atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
11586 + "!ix86_agi_dependent")
11588 +;; There will be 3 cycles stall from EX insns to AGAN insns LEA
11589 +(define_bypass 4 "atom_alu_carry,
11590 + atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
11591 + atom_incdec,atom_ishift,atom_ishift1,atom_rotate,
11592 + atom_rotate1, atom_setcc, atom_icmov, atom_pop,
11593 + atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
11594 + atom_imovx_mem, atom_imovx_2_mem,
11595 + atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
11598 +;; There will be 3 cycles stall from EX insns to insns need addr calculation
11599 +(define_bypass 4 "atom_alu_carry,
11600 + atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
11601 + atom_incdec,atom_ishift,atom_ishift1,atom_rotate,
11602 + atom_rotate1, atom_setcc, atom_icmov, atom_pop,
11603 + atom_imovx_mem, atom_imovx_2_mem,
11604 + atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
11605 + atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
11606 + "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
11607 + atom_negnot_mem, atom_imov_mem, atom_incdec_mem,
11608 + atom_imovx_mem, atom_imovx_2_mem,
11609 + atom_imul_mem, atom_icmp_mem,
11610 + atom_test_mem, atom_icmov_mem, atom_sselog_mem,
11611 + atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem,
11612 + atom_ishift_mem, atom_ishift1_mem,
11613 + atom_rotate_mem, atom_rotate1_mem"
11614 + "ix86_agi_dependent")
11616 +;; Stall from imul to lea is 8 cycles.
11617 +(define_bypass 9 "atom_imul, atom_imul_mem" "atom_lea")
11619 +;; Stall from imul to memory address is 8 cycles.
11620 +(define_bypass 9 "atom_imul, atom_imul_mem"
11621 + "atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
11622 + atom_negnot_mem, atom_imov_mem, atom_incdec_mem,
11623 + atom_ishift_mem, atom_ishift1_mem, atom_rotate_mem,
11624 + atom_rotate1_mem, atom_imul_mem, atom_icmp_mem,
11625 + atom_test_mem, atom_icmov_mem, atom_sselog_mem,
11626 + atom_sselog1_mem, atom_fmov_mem, atom_sseadd_mem"
11627 + "ix86_agi_dependent")
11629 +;; There will be 0 cycle stall from cmp/test to jcc
11631 +;; There will be 1 cycle stall from flag producer to cmov and adc/sbb
11632 +(define_bypass 2 "atom_icmp, atom_test, atom_alu, atom_alu_carry,
11633 + atom_alu1, atom_negnot, atom_incdec, atom_ishift,
11634 + atom_ishift1, atom_rotate, atom_rotate1"
11635 + "atom_icmov, atom_alu_carry")
11637 +;; lea to shift count stall is 2 cycles
11638 +(define_bypass 3 "atom_lea"
11639 + "atom_ishift, atom_ishift1, atom_rotate, atom_rotate1,
11640 + atom_ishift_mem, atom_ishift1_mem,
11641 + atom_rotate_mem, atom_rotate1_mem"
11642 + "ix86_dep_by_shift_count")
11644 +;; lea to shift source stall is 1 cycle
11645 +(define_bypass 2 "atom_lea"
11646 + "atom_ishift, atom_ishift1, atom_rotate, atom_rotate1"
11647 + "!ix86_dep_by_shift_count")
11649 +;; non-lea to shift count stall is 1 cycle
11650 +(define_bypass 2 "atom_alu_carry,
11651 + atom_alu,atom_alu1,atom_negnot,atom_imov,atom_imovx,
11652 + atom_incdec,atom_ishift,atom_ishift1,atom_rotate,
11653 + atom_rotate1, atom_setcc, atom_icmov, atom_pop,
11654 + atom_alu_mem, atom_alu_carry_mem, atom_alu1_mem,
11655 + atom_imovx_mem, atom_imovx_2_mem,
11656 + atom_imov_mem, atom_icmov_mem, atom_fmov_mem"
11657 + "atom_ishift, atom_ishift1, atom_rotate, atom_rotate1,
11658 + atom_ishift_mem, atom_ishift1_mem,
11659 + atom_rotate_mem, atom_rotate1_mem"
11660 + "ix86_dep_by_shift_count")
11661 --- a/gcc/config/i386/cpuid.h
11662 +++ b/gcc/config/i386/cpuid.h
11664 #define bit_CMPXCHG16B (1 << 13)
11665 #define bit_SSE4_1 (1 << 19)
11666 #define bit_SSE4_2 (1 << 20)
11667 +#define bit_MOVBE (1 << 22)
11668 #define bit_POPCNT (1 << 23)
11669 #define bit_AES (1 << 25)
11670 #define bit_XSAVE (1 << 26)
11671 --- a/gcc/config/i386/cygming.h
11672 +++ b/gcc/config/i386/cygming.h
11673 @@ -34,7 +34,7 @@ along with GCC; see the file COPYING3.
11676 #undef TARGET_64BIT_MS_ABI
11677 -#define TARGET_64BIT_MS_ABI (!cfun ? DEFAULT_ABI == MS_ABI : TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
11678 +#define TARGET_64BIT_MS_ABI (!cfun ? ix86_abi == MS_ABI : TARGET_64BIT && cfun->machine->call_abi == MS_ABI)
11681 #define DEFAULT_ABI (TARGET_64BIT ? MS_ABI : SYSV_ABI)
11682 @@ -202,7 +202,7 @@ do { \
11683 #define CHECK_STACK_LIMIT 4000
11685 #undef STACK_BOUNDARY
11686 -#define STACK_BOUNDARY (DEFAULT_ABI == MS_ABI ? 128 : BITS_PER_WORD)
11687 +#define STACK_BOUNDARY (ix86_abi == MS_ABI ? 128 : BITS_PER_WORD)
11689 /* By default, target has a 80387, uses IEEE compatible arithmetic,
11690 returns float values in the 387 and needs stack probes.
11691 --- a/gcc/config/i386/cygming.opt
11692 +++ b/gcc/config/i386/cygming.opt
11693 @@ -45,3 +45,7 @@ Set Windows defines
11696 Create GUI application
11698 +mpe-aligned-commons
11699 +Target Var(use_pe_aligned_common) Init(HAVE_GAS_ALIGNED_COMM)
11700 +Use the GNU extension to the PE format for aligned common data
11701 --- a/gcc/config/i386/driver-i386.c
11702 +++ b/gcc/config/i386/driver-i386.c
11703 @@ -378,7 +378,7 @@ const char *host_detect_local_cpu (int a
11704 /* Extended features */
11705 unsigned int has_lahf_lm = 0, has_sse4a = 0;
11706 unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
11707 - unsigned int has_sse4_1 = 0, has_sse4_2 = 0;
11708 + unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
11709 unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0;
11710 unsigned int has_pclmul = 0;
11712 @@ -398,9 +398,22 @@ const char *host_detect_local_cpu (int a
11714 __cpuid (1, eax, ebx, ecx, edx);
11716 - /* We don't care for extended family. */
11717 model = (eax >> 4) & 0x0f;
11718 family = (eax >> 8) & 0x0f;
11719 + if (vendor == SIG_INTEL)
11721 + unsigned int extended_model, extended_family;
11723 + extended_model = (eax >> 12) & 0xf0;
11724 + extended_family = (eax >> 20) & 0xff;
11725 + if (family == 0x0f)
11727 + family += extended_family;
11728 + model += extended_model;
11730 + else if (family == 0x06)
11731 + model += extended_model;
11734 has_sse3 = ecx & bit_SSE3;
11735 has_ssse3 = ecx & bit_SSSE3;
11736 @@ -408,6 +421,7 @@ const char *host_detect_local_cpu (int a
11737 has_sse4_2 = ecx & bit_SSE4_2;
11738 has_avx = ecx & bit_AVX;
11739 has_cmpxchg16b = ecx & bit_CMPXCHG16B;
11740 + has_movbe = ecx & bit_MOVBE;
11741 has_popcnt = ecx & bit_POPCNT;
11742 has_aes = ecx & bit_AES;
11743 has_pclmul = ecx & bit_PCLMUL;
11744 @@ -505,8 +519,8 @@ const char *host_detect_local_cpu (int a
11746 case PROCESSOR_PENTIUMPRO:
11748 - /* It is Core 2 Duo. */
11750 + /* It is Core 2 or Atom. */
11751 + cpu = (model == 28) ? "atom" : "core2";
11755 @@ -597,6 +611,8 @@ const char *host_detect_local_cpu (int a
11756 options = concat (options, "-mcx16 ", NULL);
11758 options = concat (options, "-msahf ", NULL);
11760 + options = concat (options, "-mmovbe ", NULL);
11762 options = concat (options, "-maes ", NULL);
11764 --- a/gcc/config/i386/i386-c.c
11765 +++ b/gcc/config/i386/i386-c.c
11766 @@ -119,6 +119,10 @@ ix86_target_macros_internal (int isa_fla
11767 def_or_undef (parse_in, "__core2");
11768 def_or_undef (parse_in, "__core2__");
11770 + case PROCESSOR_ATOM:
11771 + def_or_undef (parse_in, "__atom");
11772 + def_or_undef (parse_in, "__atom__");
11774 /* use PROCESSOR_max to not set/unset the arch macro. */
11775 case PROCESSOR_max:
11777 @@ -187,6 +191,9 @@ ix86_target_macros_internal (int isa_fla
11778 case PROCESSOR_CORE2:
11779 def_or_undef (parse_in, "__tune_core2__");
11781 + case PROCESSOR_ATOM:
11782 + def_or_undef (parse_in, "__tune_atom__");
11784 case PROCESSOR_GENERIC32:
11785 case PROCESSOR_GENERIC64:
11787 --- a/gcc/config/i386/i386-protos.h
11788 +++ b/gcc/config/i386/i386-protos.h
11789 @@ -86,6 +86,9 @@ extern void ix86_fixup_binary_operands_n
11790 extern void ix86_expand_binary_operator (enum rtx_code,
11791 enum machine_mode, rtx[]);
11792 extern int ix86_binary_operator_ok (enum rtx_code, enum machine_mode, rtx[]);
11793 +extern bool ix86_lea_for_add_ok (enum rtx_code, rtx, rtx[]);
11794 +extern bool ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn);
11795 +extern bool ix86_agi_dependent (rtx set_insn, rtx use_insn);
11796 extern void ix86_expand_unary_operator (enum rtx_code, enum machine_mode,
11798 extern rtx ix86_build_const_vector (enum machine_mode, bool, rtx);
11799 @@ -140,9 +143,8 @@ extern int ix86_function_arg_boundary (e
11800 extern bool ix86_sol10_return_in_memory (const_tree,const_tree);
11801 extern rtx ix86_force_to_memory (enum machine_mode, rtx);
11802 extern void ix86_free_from_memory (enum machine_mode);
11803 -extern int ix86_cfun_abi (void);
11804 -extern int ix86_function_abi (const_tree);
11805 -extern int ix86_function_type_abi (const_tree);
11806 +extern enum calling_abi ix86_cfun_abi (void);
11807 +extern enum calling_abi ix86_function_type_abi (const_tree);
11808 extern void ix86_call_abi_override (const_tree);
11809 extern tree ix86_fn_abi_va_list (tree);
11810 extern tree ix86_canonical_va_list_type (tree);
11811 --- a/gcc/config/i386/i386.c
11812 +++ b/gcc/config/i386/i386.c
11813 @@ -1036,6 +1036,79 @@ struct processor_costs core2_cost = {
11814 1, /* cond_not_taken_branch_cost. */
11818 +struct processor_costs atom_cost = {
11819 + COSTS_N_INSNS (1), /* cost of an add instruction */
11820 + COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */
11821 + COSTS_N_INSNS (1), /* variable shift costs */
11822 + COSTS_N_INSNS (1), /* constant shift costs */
11823 + {COSTS_N_INSNS (3), /* cost of starting multiply for QI */
11824 + COSTS_N_INSNS (4), /* HI */
11825 + COSTS_N_INSNS (3), /* SI */
11826 + COSTS_N_INSNS (4), /* DI */
11827 + COSTS_N_INSNS (2)}, /* other */
11828 + 0, /* cost of multiply per each bit set */
11829 + {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */
11830 + COSTS_N_INSNS (26), /* HI */
11831 + COSTS_N_INSNS (42), /* SI */
11832 + COSTS_N_INSNS (74), /* DI */
11833 + COSTS_N_INSNS (74)}, /* other */
11834 + COSTS_N_INSNS (1), /* cost of movsx */
11835 + COSTS_N_INSNS (1), /* cost of movzx */
11836 + 8, /* "large" insn */
11837 + 17, /* MOVE_RATIO */
11838 + 2, /* cost for loading QImode using movzbl */
11839 + {4, 4, 4}, /* cost of loading integer registers
11840 + in QImode, HImode and SImode.
11841 + Relative to reg-reg move (2). */
11842 + {4, 4, 4}, /* cost of storing integer registers */
11843 + 4, /* cost of reg,reg fld/fst */
11844 + {12, 12, 12}, /* cost of loading fp registers
11845 + in SFmode, DFmode and XFmode */
11846 + {6, 6, 8}, /* cost of storing fp registers
11847 + in SFmode, DFmode and XFmode */
11848 + 2, /* cost of moving MMX register */
11849 + {8, 8}, /* cost of loading MMX registers
11850 + in SImode and DImode */
11851 + {8, 8}, /* cost of storing MMX registers
11852 + in SImode and DImode */
11853 + 2, /* cost of moving SSE register */
11854 + {8, 8, 8}, /* cost of loading SSE registers
11855 + in SImode, DImode and TImode */
11856 + {8, 8, 8}, /* cost of storing SSE registers
11857 + in SImode, DImode and TImode */
11858 + 5, /* MMX or SSE register to integer */
11859 + 32, /* size of l1 cache. */
11860 + 256, /* size of l2 cache. */
11861 + 64, /* size of prefetch block */
11862 + 6, /* number of parallel prefetches */
11863 + 3, /* Branch cost */
11864 + COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */
11865 + COSTS_N_INSNS (8), /* cost of FMUL instruction. */
11866 + COSTS_N_INSNS (20), /* cost of FDIV instruction. */
11867 + COSTS_N_INSNS (8), /* cost of FABS instruction. */
11868 + COSTS_N_INSNS (8), /* cost of FCHS instruction. */
11869 + COSTS_N_INSNS (40), /* cost of FSQRT instruction. */
11870 + {{libcall, {{11, loop}, {-1, rep_prefix_4_byte}}},
11871 + {libcall, {{32, loop}, {64, rep_prefix_4_byte},
11872 + {8192, rep_prefix_8_byte}, {-1, libcall}}}},
11873 + {{libcall, {{8, loop}, {15, unrolled_loop},
11874 + {2048, rep_prefix_4_byte}, {-1, libcall}}},
11875 + {libcall, {{24, loop}, {32, unrolled_loop},
11876 + {8192, rep_prefix_8_byte}, {-1, libcall}}}},
11877 + 1, /* scalar_stmt_cost. */
11878 + 1, /* scalar load_cost. */
11879 + 1, /* scalar_store_cost. */
11880 + 1, /* vec_stmt_cost. */
11881 + 1, /* vec_to_scalar_cost. */
11882 + 1, /* scalar_to_vec_cost. */
11883 + 1, /* vec_align_load_cost. */
11884 + 2, /* vec_unalign_load_cost. */
11885 + 1, /* vec_store_cost. */
11886 + 3, /* cond_taken_branch_cost. */
11887 + 1, /* cond_not_taken_branch_cost. */
11890 /* Generic64 should produce code tuned for Nocona and K8. */
11892 struct processor_costs generic64_cost = {
11893 @@ -1194,6 +1267,7 @@ const struct processor_costs *ix86_cost
11894 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
11895 #define m_NOCONA (1<<PROCESSOR_NOCONA)
11896 #define m_CORE2 (1<<PROCESSOR_CORE2)
11897 +#define m_ATOM (1<<PROCESSOR_ATOM)
11899 #define m_GEODE (1<<PROCESSOR_GEODE)
11900 #define m_K6 (1<<PROCESSOR_K6)
11901 @@ -1231,10 +1305,11 @@ static unsigned int initial_ix86_tune_fe
11904 /* X86_TUNE_UNROLL_STRLEN */
11905 - m_486 | m_PENT | m_PPRO | m_AMD_MULTIPLE | m_K6 | m_CORE2 | m_GENERIC,
11906 + m_486 | m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_K6
11907 + | m_CORE2 | m_GENERIC,
11909 /* X86_TUNE_DEEP_BRANCH_PREDICTION */
11910 - m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
11911 + m_ATOM | m_PPRO | m_K6_GEODE | m_AMD_MULTIPLE | m_PENT4 | m_GENERIC,
11913 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
11914 on simulation result. But after P4 was made, no performance benefit
11915 @@ -1246,12 +1321,12 @@ static unsigned int initial_ix86_tune_fe
11918 /* X86_TUNE_USE_SAHF */
11919 - m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
11920 + m_ATOM | m_PPRO | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_PENT4
11921 | m_NOCONA | m_CORE2 | m_GENERIC,
11923 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
11924 partial dependencies. */
11925 - m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA
11926 + m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA
11927 | m_CORE2 | m_GENERIC | m_GEODE /* m_386 | m_K6 */,
11929 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
11930 @@ -1271,13 +1346,13 @@ static unsigned int initial_ix86_tune_fe
11931 m_386 | m_486 | m_K6_GEODE,
11933 /* X86_TUNE_USE_SIMODE_FIOP */
11934 - ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_CORE2 | m_GENERIC),
11935 + ~(m_PPRO | m_AMD_MULTIPLE | m_PENT | m_ATOM | m_CORE2 | m_GENERIC),
11937 /* X86_TUNE_USE_MOV0 */
11940 /* X86_TUNE_USE_CLTD */
11941 - ~(m_PENT | m_K6 | m_CORE2 | m_GENERIC),
11942 + ~(m_PENT | m_ATOM | m_K6 | m_CORE2 | m_GENERIC),
11944 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
11946 @@ -1292,8 +1367,8 @@ static unsigned int initial_ix86_tune_fe
11947 ~(m_PENT | m_PPRO),
11949 /* X86_TUNE_PROMOTE_QIMODE */
11950 - m_K6_GEODE | m_PENT | m_386 | m_486 | m_AMD_MULTIPLE | m_CORE2
11951 - | m_GENERIC /* | m_PENT4 ? */,
11952 + m_K6_GEODE | m_PENT | m_ATOM | m_386 | m_486 | m_AMD_MULTIPLE
11953 + | m_CORE2 | m_GENERIC /* | m_PENT4 ? */,
11955 /* X86_TUNE_FAST_PREFIX */
11956 ~(m_PENT | m_486 | m_386),
11957 @@ -1317,26 +1392,28 @@ static unsigned int initial_ix86_tune_fe
11960 /* X86_TUNE_ADD_ESP_4: Enable if add/sub is preferred over 1/2 push/pop. */
11961 - m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
11962 + m_ATOM | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT4 | m_NOCONA
11963 + | m_CORE2 | m_GENERIC,
11965 /* X86_TUNE_ADD_ESP_8 */
11966 - m_AMD_MULTIPLE | m_PPRO | m_K6_GEODE | m_386
11967 + m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_K6_GEODE | m_386
11968 | m_486 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
11970 /* X86_TUNE_SUB_ESP_4 */
11971 - m_AMD_MULTIPLE | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
11972 + m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_PENT4 | m_NOCONA | m_CORE2
11975 /* X86_TUNE_SUB_ESP_8 */
11976 - m_AMD_MULTIPLE | m_PPRO | m_386 | m_486
11977 + m_AMD_MULTIPLE | m_ATOM | m_PPRO | m_386 | m_486
11978 | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
11980 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
11981 for DFmode copies */
11982 - ~(m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
11983 + ~(m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
11984 | m_GENERIC | m_GEODE),
11986 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
11987 - m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
11988 + m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
11990 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
11991 conflict here in between PPro/Pentium4 based chips that thread 128bit
11992 @@ -1347,7 +1424,8 @@ static unsigned int initial_ix86_tune_fe
11993 shows that disabling this option on P4 brings over 20% SPECfp regression,
11994 while enabling it on K8 brings roughly 2.4% regression that can be partly
11995 masked by careful scheduling of moves. */
11996 - m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC | m_AMDFAM10,
11997 + m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC
12000 /* X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL */
12002 @@ -1365,13 +1443,13 @@ static unsigned int initial_ix86_tune_fe
12003 m_PPRO | m_PENT4 | m_NOCONA,
12005 /* X86_TUNE_MEMORY_MISMATCH_STALL */
12006 - m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
12007 + m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
12009 /* X86_TUNE_PROLOGUE_USING_MOVE */
12010 - m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
12011 + m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
12013 /* X86_TUNE_EPILOGUE_USING_MOVE */
12014 - m_ATHLON_K8 | m_PPRO | m_CORE2 | m_GENERIC,
12015 + m_ATHLON_K8 | m_ATOM | m_PPRO | m_CORE2 | m_GENERIC,
12017 /* X86_TUNE_SHIFT1 */
12019 @@ -1380,29 +1458,32 @@ static unsigned int initial_ix86_tune_fe
12022 /* X86_TUNE_INTER_UNIT_MOVES */
12023 - ~(m_AMD_MULTIPLE | m_GENERIC),
12024 + ~(m_AMD_MULTIPLE | m_ATOM | m_GENERIC),
12026 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
12029 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
12030 than 4 branch instructions in the 16 byte window. */
12031 - m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2 | m_GENERIC,
12032 + m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_CORE2
12035 /* X86_TUNE_SCHEDULE */
12036 - m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_CORE2 | m_GENERIC,
12037 + m_PPRO | m_AMD_MULTIPLE | m_K6_GEODE | m_PENT | m_ATOM | m_CORE2
12040 /* X86_TUNE_USE_BT */
12041 - m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
12042 + m_AMD_MULTIPLE | m_ATOM | m_CORE2 | m_GENERIC,
12044 /* X86_TUNE_USE_INCDEC */
12045 - ~(m_PENT4 | m_NOCONA | m_GENERIC),
12046 + ~(m_PENT4 | m_NOCONA | m_GENERIC | m_ATOM),
12048 /* X86_TUNE_PAD_RETURNS */
12049 m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
12051 /* X86_TUNE_EXT_80387_CONSTANTS */
12052 - m_K6_GEODE | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC,
12053 + m_K6_GEODE | m_ATHLON_K8 | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO
12054 + | m_CORE2 | m_GENERIC,
12056 /* X86_TUNE_SHORTEN_X87_SSE */
12058 @@ -1447,6 +1528,10 @@ static unsigned int initial_ix86_tune_fe
12059 with a subsequent conditional jump instruction into a single
12060 compare-and-branch uop. */
12063 + /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
12064 + will impact LEA instruction selection. */
12068 /* Feature tests against the various architecture variations. */
12069 @@ -1472,10 +1557,11 @@ static unsigned int initial_ix86_arch_fe
12072 static const unsigned int x86_accumulate_outgoing_args
12073 - = m_AMD_MULTIPLE | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2 | m_GENERIC;
12074 + = m_AMD_MULTIPLE | m_ATOM | m_PENT4 | m_NOCONA | m_PPRO | m_CORE2
12077 static const unsigned int x86_arch_always_fancy_math_387
12078 - = m_PENT | m_PPRO | m_AMD_MULTIPLE | m_PENT4
12079 + = m_PENT | m_ATOM | m_PPRO | m_AMD_MULTIPLE | m_PENT4
12080 | m_NOCONA | m_CORE2 | m_GENERIC;
12082 static enum stringop_alg stringop_alg = no_stringop;
12083 @@ -1743,6 +1829,9 @@ static unsigned int ix86_default_incomin
12084 /* Alignment for incoming stack boundary in bits. */
12085 unsigned int ix86_incoming_stack_boundary;
12087 +/* The abi used by target. */
12088 +enum calling_abi ix86_abi;
12090 /* Values 1-5: see jump.c */
12091 int ix86_branch_cost;
12093 @@ -1819,6 +1908,8 @@ static bool ix86_valid_target_attribute_
12094 static bool ix86_can_inline_p (tree, tree);
12095 static void ix86_set_current_function (tree);
12097 +static enum calling_abi ix86_function_abi (const_tree);
12100 /* The svr4 ABI for the i386 says that records and unions are returned
12102 @@ -1880,6 +1971,7 @@ static int ix86_isa_flags_explicit;
12103 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
12104 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
12105 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
12106 +#define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
12108 /* Define a set of ISAs which aren't available when a given ISA is
12109 disabled. MMX and SSE ISAs are handled separately. */
12110 @@ -1921,6 +2013,7 @@ static int ix86_isa_flags_explicit;
12111 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
12112 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
12113 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
12114 +#define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
12116 /* Vectorization library interface and handlers. */
12117 tree (*ix86_veclib_handler)(enum built_in_function, tree, tree) = NULL;
12118 @@ -1953,7 +2046,8 @@ static const struct ptt processor_target
12119 {&core2_cost, 16, 10, 16, 10, 16},
12120 {&generic32_cost, 16, 7, 16, 7, 16},
12121 {&generic64_cost, 16, 10, 16, 10, 16},
12122 - {&amdfam10_cost, 32, 24, 32, 7, 32}
12123 + {&amdfam10_cost, 32, 24, 32, 7, 32},
12124 + {&atom_cost, 16, 7, 16, 7, 16}
12127 static const char *const cpu_names[TARGET_CPU_DEFAULT_max] =
12128 @@ -1971,6 +2065,7 @@ static const char *const cpu_names[TARGE
12136 @@ -2209,6 +2304,19 @@ ix86_handle_option (size_t code, const c
12143 + ix86_isa_flags |= OPTION_MASK_ISA_MOVBE_SET;
12144 + ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_SET;
12148 + ix86_isa_flags &= ~OPTION_MASK_ISA_MOVBE_UNSET;
12149 + ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
12156 @@ -2271,6 +2379,7 @@ ix86_target_string (int isa, int flags,
12157 { "-mmmx", OPTION_MASK_ISA_MMX },
12158 { "-mabm", OPTION_MASK_ISA_ABM },
12159 { "-mpopcnt", OPTION_MASK_ISA_POPCNT },
12160 + { "-mmovbe", OPTION_MASK_ISA_MOVBE },
12161 { "-maes", OPTION_MASK_ISA_AES },
12162 { "-mpclmul", OPTION_MASK_ISA_PCLMUL },
12164 @@ -2487,7 +2596,8 @@ override_options (bool main_args_p)
12166 PTA_PCLMUL = 1 << 18,
12168 - PTA_FMA = 1 << 20
12169 + PTA_FMA = 1 << 20,
12170 + PTA_MOVBE = 1 << 21
12174 @@ -2529,6 +2639,9 @@ override_options (bool main_args_p)
12175 {"core2", PROCESSOR_CORE2, CPU_CORE2,
12176 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
12177 | PTA_SSSE3 | PTA_CX16},
12178 + {"atom", PROCESSOR_ATOM, CPU_ATOM,
12179 + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
12180 + | PTA_SSSE3 | PTA_CX16 | PTA_MOVBE},
12181 {"geode", PROCESSOR_GEODE, CPU_GEODE,
12182 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A |PTA_PREFETCH_SSE},
12183 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
12184 @@ -2716,6 +2829,20 @@ override_options (bool main_args_p)
12185 error ("bad value (%s) for %sarch=%s %s",
12186 ix86_arch_string, prefix, suffix, sw);
12188 + /* Validate -mabi= value. */
12189 + if (ix86_abi_string)
12191 + if (strcmp (ix86_abi_string, "sysv") == 0)
12192 + ix86_abi = SYSV_ABI;
12193 + else if (strcmp (ix86_abi_string, "ms") == 0)
12194 + ix86_abi = MS_ABI;
12196 + error ("unknown ABI (%s) for %sabi=%s %s",
12197 + ix86_abi_string, prefix, suffix, sw);
12200 + ix86_abi = DEFAULT_ABI;
12202 if (ix86_cmodel_string != 0)
12204 if (!strcmp (ix86_cmodel_string, "small"))
12205 @@ -2828,6 +2955,9 @@ override_options (bool main_args_p)
12206 if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF))
12207 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
12208 ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
12209 + if (processor_alias_table[i].flags & PTA_MOVBE
12210 + && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVBE))
12211 + ix86_isa_flags |= OPTION_MASK_ISA_MOVBE;
12212 if (processor_alias_table[i].flags & PTA_AES
12213 && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
12214 ix86_isa_flags |= OPTION_MASK_ISA_AES;
12215 @@ -4592,14 +4722,14 @@ ix86_function_arg_regno_p (int regno)
12218 /* RAX is used as hidden argument to va_arg functions. */
12219 - if (DEFAULT_ABI == SYSV_ABI && regno == AX_REG)
12220 + if (ix86_abi == SYSV_ABI && regno == AX_REG)
12223 - if (DEFAULT_ABI == MS_ABI)
12224 + if (ix86_abi == MS_ABI)
12225 parm_regs = x86_64_ms_abi_int_parameter_registers;
12227 parm_regs = x86_64_int_parameter_registers;
12228 - for (i = 0; i < (DEFAULT_ABI == MS_ABI ? X64_REGPARM_MAX
12229 + for (i = 0; i < (ix86_abi == MS_ABI ? X64_REGPARM_MAX
12230 : X86_64_REGPARM_MAX); i++)
12231 if (regno == parm_regs[i])
12233 @@ -4627,7 +4757,7 @@ ix86_must_pass_in_stack (enum machine_mo
12235 ix86_reg_parm_stack_space (const_tree fndecl)
12237 - int call_abi = SYSV_ABI;
12238 + enum calling_abi call_abi = SYSV_ABI;
12239 if (fndecl != NULL_TREE && TREE_CODE (fndecl) == FUNCTION_DECL)
12240 call_abi = ix86_function_abi (fndecl);
12242 @@ -4639,37 +4769,39 @@ ix86_reg_parm_stack_space (const_tree fn
12244 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
12248 ix86_function_type_abi (const_tree fntype)
12250 if (TARGET_64BIT && fntype != NULL)
12253 - if (DEFAULT_ABI == SYSV_ABI)
12254 - abi = lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)) ? MS_ABI : SYSV_ABI;
12256 - abi = lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)) ? SYSV_ABI : MS_ABI;
12258 + enum calling_abi abi = ix86_abi;
12259 + if (abi == SYSV_ABI)
12261 + if (lookup_attribute ("ms_abi", TYPE_ATTRIBUTES (fntype)))
12264 + else if (lookup_attribute ("sysv_abi", TYPE_ATTRIBUTES (fntype)))
12268 - return DEFAULT_ABI;
12273 +static enum calling_abi
12274 ix86_function_abi (const_tree fndecl)
12277 - return DEFAULT_ABI;
12279 return ix86_function_type_abi (TREE_TYPE (fndecl));
12282 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
12286 ix86_cfun_abi (void)
12288 if (! cfun || ! TARGET_64BIT)
12289 - return DEFAULT_ABI;
12291 return cfun->machine->call_abi;
12294 @@ -4683,7 +4815,7 @@ void
12295 ix86_call_abi_override (const_tree fndecl)
12297 if (fndecl == NULL_TREE)
12298 - cfun->machine->call_abi = DEFAULT_ABI;
12299 + cfun->machine->call_abi = ix86_abi;
12301 cfun->machine->call_abi = ix86_function_type_abi (TREE_TYPE (fndecl));
12303 @@ -4724,8 +4856,8 @@ init_cumulative_args (CUMULATIVE_ARGS *c
12304 cum->nregs = ix86_regparm;
12307 - if (cum->call_abi != DEFAULT_ABI)
12308 - cum->nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX
12309 + if (cum->call_abi != ix86_abi)
12310 + cum->nregs = ix86_abi != SYSV_ABI ? X86_64_REGPARM_MAX
12314 @@ -4733,8 +4865,8 @@ init_cumulative_args (CUMULATIVE_ARGS *c
12315 cum->sse_nregs = SSE_REGPARM_MAX;
12318 - if (cum->call_abi != DEFAULT_ABI)
12319 - cum->sse_nregs = DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
12320 + if (cum->call_abi != ix86_abi)
12321 + cum->sse_nregs = ix86_abi != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
12322 : X64_SSE_REGPARM_MAX;
12325 @@ -5700,7 +5832,7 @@ function_arg_advance (CUMULATIVE_ARGS *c
12327 mode = type_natural_mode (type, NULL);
12329 - if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
12330 + if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
12331 function_arg_advance_ms_64 (cum, bytes, words);
12332 else if (TARGET_64BIT)
12333 function_arg_advance_64 (cum, mode, type, words, named);
12334 @@ -5846,9 +5978,9 @@ function_arg_64 (CUMULATIVE_ARGS *cum, e
12335 if (mode == VOIDmode)
12336 return GEN_INT (cum->maybe_vaarg
12337 ? (cum->sse_nregs < 0
12338 - ? (cum->call_abi == DEFAULT_ABI
12339 + ? (cum->call_abi == ix86_abi
12341 - : (DEFAULT_ABI != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
12342 + : (ix86_abi != SYSV_ABI ? X86_64_SSE_REGPARM_MAX
12343 : X64_SSE_REGPARM_MAX))
12346 @@ -5942,7 +6074,7 @@ function_arg (CUMULATIVE_ARGS *cum, enum
12347 if (type && TREE_CODE (type) == VECTOR_TYPE)
12348 mode = type_natural_mode (type, cum);
12350 - if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
12351 + if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
12352 return function_arg_ms_64 (cum, mode, omode, named, bytes);
12353 else if (TARGET_64BIT)
12354 return function_arg_64 (cum, mode, omode, type, named);
12355 @@ -5962,7 +6094,7 @@ ix86_pass_by_reference (CUMULATIVE_ARGS
12356 const_tree type, bool named ATTRIBUTE_UNUSED)
12358 /* See Windows x64 Software Convention. */
12359 - if (TARGET_64BIT && (cum ? cum->call_abi : DEFAULT_ABI) == MS_ABI)
12360 + if (TARGET_64BIT && (cum ? cum->call_abi : ix86_abi) == MS_ABI)
12362 int msize = (int) GET_MODE_SIZE (mode);
12364 @@ -6102,7 +6234,7 @@ ix86_function_value_regno_p (int regno)
12365 /* TODO: The function should depend on current function ABI but
12366 builtins.c would need updating then. Therefore we use the
12368 - if (TARGET_64BIT && DEFAULT_ABI == MS_ABI)
12369 + if (TARGET_64BIT && ix86_abi == MS_ABI)
12371 return TARGET_FLOAT_RETURNS_IN_80387;
12373 @@ -6498,13 +6630,13 @@ ix86_build_builtin_va_list_abi (enum cal
12375 ix86_build_builtin_va_list (void)
12377 - tree ret = ix86_build_builtin_va_list_abi (DEFAULT_ABI);
12378 + tree ret = ix86_build_builtin_va_list_abi (ix86_abi);
12380 /* Initialize abi specific va_list builtin types. */
12384 - if (DEFAULT_ABI == MS_ABI)
12385 + if (ix86_abi == MS_ABI)
12387 t = ix86_build_builtin_va_list_abi (SYSV_ABI);
12388 if (TREE_CODE (t) != RECORD_TYPE)
12389 @@ -6518,7 +6650,7 @@ ix86_build_builtin_va_list (void)
12390 t = build_variant_type_copy (t);
12391 sysv_va_list_type_node = t;
12393 - if (DEFAULT_ABI != MS_ABI)
12394 + if (ix86_abi != MS_ABI)
12396 t = ix86_build_builtin_va_list_abi (MS_ABI);
12397 if (TREE_CODE (t) != RECORD_TYPE)
12398 @@ -6551,8 +6683,8 @@ setup_incoming_varargs_64 (CUMULATIVE_AR
12400 int regparm = ix86_regparm;
12402 - if (cum->call_abi != DEFAULT_ABI)
12403 - regparm = DEFAULT_ABI != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
12404 + if (cum->call_abi != ix86_abi)
12405 + regparm = ix86_abi != SYSV_ABI ? X86_64_REGPARM_MAX : X64_REGPARM_MAX;
12407 /* GPR size of varargs save area. */
12408 if (cfun->va_list_gpr_size)
12409 @@ -6705,7 +6837,7 @@ is_va_list_char_pointer (tree type)
12411 canonic = ix86_canonical_va_list_type (type);
12412 return (canonic == ms_va_list_type_node
12413 - || (DEFAULT_ABI == MS_ABI && canonic == va_list_type_node));
12414 + || (ix86_abi == MS_ABI && canonic == va_list_type_node));
12417 /* Implement va_start. */
12418 @@ -12994,6 +13126,316 @@ ix86_expand_unary_operator (enum rtx_cod
12419 emit_move_insn (operands[0], dst);
12422 +#define LEA_SEARCH_THRESHOLD 12
12424 +/* Search backward for non-agu definition of register number REGNO1
12425 + or register number REGNO2 in INSN's basic block until
12426 + 1. Pass LEA_SEARCH_THRESHOLD instructions, or
12427 + 2. Reach BB boundary, or
12428 + 3. Reach agu definition.
12429 + Returns the distance between the non-agu definition point and INSN.
12430 + If no definition point, returns -1. */
12433 +distance_non_agu_define (unsigned int regno1, unsigned int regno2,
12436 + basic_block bb = BLOCK_FOR_INSN (insn);
12437 + int distance = 0;
12439 + enum attr_type insn_type;
12441 + if (insn != BB_HEAD (bb))
12443 + rtx prev = PREV_INSN (insn);
12444 + while (prev && distance < LEA_SEARCH_THRESHOLD)
12446 + if (INSN_P (prev))
12449 + for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
12450 + if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
12451 + && !DF_REF_IS_ARTIFICIAL (*def_rec)
12452 + && (regno1 == DF_REF_REGNO (*def_rec)
12453 + || regno2 == DF_REF_REGNO (*def_rec)))
12455 + insn_type = get_attr_type (prev);
12456 + if (insn_type != TYPE_LEA)
12460 + if (prev == BB_HEAD (bb))
12462 + prev = PREV_INSN (prev);
12466 + if (distance < LEA_SEARCH_THRESHOLD)
12469 + edge_iterator ei;
12470 + bool simple_loop = false;
12472 + FOR_EACH_EDGE (e, ei, bb->preds)
12473 + if (e->src == bb)
12475 + simple_loop = true;
12481 + rtx prev = BB_END (bb);
12484 + && distance < LEA_SEARCH_THRESHOLD)
12486 + if (INSN_P (prev))
12489 + for (def_rec = DF_INSN_DEFS (prev); *def_rec; def_rec++)
12490 + if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
12491 + && !DF_REF_IS_ARTIFICIAL (*def_rec)
12492 + && (regno1 == DF_REF_REGNO (*def_rec)
12493 + || regno2 == DF_REF_REGNO (*def_rec)))
12495 + insn_type = get_attr_type (prev);
12496 + if (insn_type != TYPE_LEA)
12500 + prev = PREV_INSN (prev);
12508 + /* get_attr_type may modify recog data. We want to make sure
12509 + that recog data is valid for instruction INSN, on which
12510 + distance_non_agu_define is called. INSN is unchanged here. */
12511 + extract_insn_cached (insn);
12515 +/* Return the distance between INSN and the next insn that uses
12516 + register number REGNO0 in memory address. Return -1 if no such
12517 + a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
12520 +distance_agu_use (unsigned int regno0, rtx insn)
12522 + basic_block bb = BLOCK_FOR_INSN (insn);
12523 + int distance = 0;
12527 + if (insn != BB_END (bb))
12529 + rtx next = NEXT_INSN (insn);
12530 + while (next && distance < LEA_SEARCH_THRESHOLD)
12532 + if (INSN_P (next))
12536 + for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
12537 + if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
12538 + || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
12539 + && regno0 == DF_REF_REGNO (*use_rec))
12541 + /* Return DISTANCE if OP0 is used in memory
12542 + address in NEXT. */
12546 + for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
12547 + if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
12548 + && !DF_REF_IS_ARTIFICIAL (*def_rec)
12549 + && regno0 == DF_REF_REGNO (*def_rec))
12551 + /* Return -1 if OP0 is set in NEXT. */
12555 + if (next == BB_END (bb))
12557 + next = NEXT_INSN (next);
12561 + if (distance < LEA_SEARCH_THRESHOLD)
12564 + edge_iterator ei;
12565 + bool simple_loop = false;
12567 + FOR_EACH_EDGE (e, ei, bb->succs)
12568 + if (e->dest == bb)
12570 + simple_loop = true;
12576 + rtx next = BB_HEAD (bb);
12579 + && distance < LEA_SEARCH_THRESHOLD)
12581 + if (INSN_P (next))
12585 + for (use_rec = DF_INSN_USES (next); *use_rec; use_rec++)
12586 + if ((DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_LOAD
12587 + || DF_REF_TYPE (*use_rec) == DF_REF_REG_MEM_STORE)
12588 + && regno0 == DF_REF_REGNO (*use_rec))
12590 + /* Return DISTANCE if OP0 is used in memory
12591 + address in NEXT. */
12595 + for (def_rec = DF_INSN_DEFS (next); *def_rec; def_rec++)
12596 + if (DF_REF_TYPE (*def_rec) == DF_REF_REG_DEF
12597 + && !DF_REF_IS_ARTIFICIAL (*def_rec)
12598 + && regno0 == DF_REF_REGNO (*def_rec))
12600 + /* Return -1 if OP0 is set in NEXT. */
12605 + next = NEXT_INSN (next);
12613 +/* Define this macro to tune LEA priority vs ADD, it take effect when
12614 + there is a dilemma of choicing LEA or ADD
12615 + Negative value: ADD is more preferred than LEA
12617 + Positive value: LEA is more preferred than ADD*/
12618 +#define IX86_LEA_PRIORITY 2
12620 +/* Return true if it is ok to optimize an ADD operation to LEA
12621 + operation to avoid flag register consumation. For the processors
12622 + like ATOM, if the destination register of LEA holds an actual
12623 + address which will be used soon, LEA is better and otherwise ADD
12627 +ix86_lea_for_add_ok (enum rtx_code code ATTRIBUTE_UNUSED,
12628 + rtx insn, rtx operands[])
12630 + unsigned int regno0 = true_regnum (operands[0]);
12631 + unsigned int regno1 = true_regnum (operands[1]);
12632 + unsigned int regno2;
12634 + if (!TARGET_OPT_AGU || optimize_function_for_size_p (cfun))
12635 + return regno0 != regno1;
12637 + regno2 = true_regnum (operands[2]);
12639 + /* If a = b + c, (a!=b && a!=c), must use lea form. */
12640 + if (regno0 != regno1 && regno0 != regno2)
12644 + int dist_define, dist_use;
12645 + dist_define = distance_non_agu_define (regno1, regno2, insn);
12646 + if (dist_define <= 0)
12649 + /* If this insn has both backward non-agu dependence and forward
12650 + agu dependence, the one with short distance take effect. */
12651 + dist_use = distance_agu_use (regno0, insn);
12652 + if (dist_use <= 0
12653 + || (dist_define + IX86_LEA_PRIORITY) < dist_use)
12660 +/* Return true if destination reg of SET_BODY is shift count of
12664 +ix86_dep_by_shift_count_body (const_rtx set_body, const_rtx use_body)
12670 + /* Retrieve destination of SET_BODY. */
12671 + switch (GET_CODE (set_body))
12674 + set_dest = SET_DEST (set_body);
12675 + if (!set_dest || !REG_P (set_dest))
12679 + for (i = XVECLEN (set_body, 0) - 1; i >= 0; i--)
12680 + if (ix86_dep_by_shift_count_body (XVECEXP (set_body, 0, i),
12688 + /* Retrieve shift count of USE_BODY. */
12689 + switch (GET_CODE (use_body))
12692 + shift_rtx = XEXP (use_body, 1);
12695 + for (i = XVECLEN (use_body, 0) - 1; i >= 0; i--)
12696 + if (ix86_dep_by_shift_count_body (set_body,
12697 + XVECEXP (use_body, 0, i)))
12705 + && (GET_CODE (shift_rtx) == ASHIFT
12706 + || GET_CODE (shift_rtx) == LSHIFTRT
12707 + || GET_CODE (shift_rtx) == ASHIFTRT
12708 + || GET_CODE (shift_rtx) == ROTATE
12709 + || GET_CODE (shift_rtx) == ROTATERT))
12711 + rtx shift_count = XEXP (shift_rtx, 1);
12713 + /* Return true if shift count is dest of SET_BODY. */
12714 + if (REG_P (shift_count)
12715 + && true_regnum (set_dest) == true_regnum (shift_count))
12722 +/* Return true if destination reg of SET_INSN is shift count of
12726 +ix86_dep_by_shift_count (const_rtx set_insn, const_rtx use_insn)
12728 + return ix86_dep_by_shift_count_body (PATTERN (set_insn),
12729 + PATTERN (use_insn));
12732 /* Return TRUE or FALSE depending on whether the unary operator meets the
12733 appropriate constraints. */
12735 @@ -18850,7 +19292,7 @@ ix86_init_machine_status (void)
12736 f = GGC_CNEW (struct machine_function);
12737 f->use_fast_prologue_epilogue_nregs = -1;
12738 f->tls_descriptor_call_expanded_p = 0;
12739 - f->call_abi = DEFAULT_ABI;
12740 + f->call_abi = ix86_abi;
12744 @@ -19111,6 +19553,7 @@ ix86_issue_rate (void)
12747 case PROCESSOR_PENTIUM:
12748 + case PROCESSOR_ATOM:
12752 @@ -19177,41 +19620,21 @@ ix86_flags_dependent (rtx insn, rtx dep_
12756 -/* A subroutine of ix86_adjust_cost -- return true iff INSN has a memory
12757 - address with operands set by DEP_INSN. */
12758 +/* Return true iff USE_INSN has a memory address with operands set by
12762 -ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type)
12764 +ix86_agi_dependent (rtx set_insn, rtx use_insn)
12768 - if (insn_type == TYPE_LEA
12769 - && TARGET_PENTIUM)
12771 - addr = PATTERN (insn);
12773 - if (GET_CODE (addr) == PARALLEL)
12774 - addr = XVECEXP (addr, 0, 0);
12776 - gcc_assert (GET_CODE (addr) == SET);
12778 - addr = SET_SRC (addr);
12783 - extract_insn_cached (insn);
12784 - for (i = recog_data.n_operands - 1; i >= 0; --i)
12785 - if (MEM_P (recog_data.operand[i]))
12787 - addr = XEXP (recog_data.operand[i], 0);
12794 - return modified_in_p (addr, dep_insn);
12796 + extract_insn_cached (use_insn);
12797 + for (i = recog_data.n_operands - 1; i >= 0; --i)
12798 + if (MEM_P (recog_data.operand[i]))
12800 + rtx addr = XEXP (recog_data.operand[i], 0);
12801 + return modified_in_p (addr, set_insn) != 0;
12807 @@ -19239,7 +19662,20 @@ ix86_adjust_cost (rtx insn, rtx link, rt
12809 case PROCESSOR_PENTIUM:
12810 /* Address Generation Interlock adds a cycle of latency. */
12811 - if (ix86_agi_dependent (insn, dep_insn, insn_type))
12812 + if (insn_type == TYPE_LEA)
12814 + rtx addr = PATTERN (insn);
12816 + if (GET_CODE (addr) == PARALLEL)
12817 + addr = XVECEXP (addr, 0, 0);
12819 + gcc_assert (GET_CODE (addr) == SET);
12821 + addr = SET_SRC (addr);
12822 + if (modified_in_p (addr, dep_insn))
12825 + else if (ix86_agi_dependent (dep_insn, insn))
12828 /* ??? Compares pair with jump/setcc. */
12829 @@ -19249,7 +19685,7 @@ ix86_adjust_cost (rtx insn, rtx link, rt
12830 /* Floating point stores require value to be ready one cycle earlier. */
12831 if (insn_type == TYPE_FMOV
12832 && get_attr_memory (insn) == MEMORY_STORE
12833 - && !ix86_agi_dependent (insn, dep_insn, insn_type))
12834 + && !ix86_agi_dependent (dep_insn, insn))
12838 @@ -19272,7 +19708,7 @@ ix86_adjust_cost (rtx insn, rtx link, rt
12839 in parallel with previous instruction in case
12840 previous instruction is not needed to compute the address. */
12841 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
12842 - && !ix86_agi_dependent (insn, dep_insn, insn_type))
12843 + && !ix86_agi_dependent (dep_insn, insn))
12845 /* Claim moves to take one cycle, as core can issue one load
12846 at time and the next load can start cycle later. */
12847 @@ -19301,7 +19737,7 @@ ix86_adjust_cost (rtx insn, rtx link, rt
12848 in parallel with previous instruction in case
12849 previous instruction is not needed to compute the address. */
12850 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
12851 - && !ix86_agi_dependent (insn, dep_insn, insn_type))
12852 + && !ix86_agi_dependent (dep_insn, insn))
12854 /* Claim moves to take one cycle, as core can issue one load
12855 at time and the next load can start cycle later. */
12856 @@ -19318,6 +19754,7 @@ ix86_adjust_cost (rtx insn, rtx link, rt
12857 case PROCESSOR_ATHLON:
12859 case PROCESSOR_AMDFAM10:
12860 + case PROCESSOR_ATOM:
12861 case PROCESSOR_GENERIC32:
12862 case PROCESSOR_GENERIC64:
12863 memory = get_attr_memory (insn);
12864 @@ -19326,7 +19763,7 @@ ix86_adjust_cost (rtx insn, rtx link, rt
12865 in parallel with previous instruction in case
12866 previous instruction is not needed to compute the address. */
12867 if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH)
12868 - && !ix86_agi_dependent (insn, dep_insn, insn_type))
12869 + && !ix86_agi_dependent (dep_insn, insn))
12871 enum attr_unit unit = get_attr_unit (insn);
12873 @@ -29606,14 +30043,11 @@ x86_builtin_vectorization_cost (bool run
12875 ix86_fn_abi_va_list (tree fndecl)
12880 return va_list_type_node;
12881 gcc_assert (fndecl != NULL_TREE);
12882 - abi = ix86_function_abi ((const_tree) fndecl);
12884 - if (abi == MS_ABI)
12885 + if (ix86_function_abi ((const_tree) fndecl) == MS_ABI)
12886 return ms_va_list_type_node;
12888 return sysv_va_list_type_node;
12889 --- a/gcc/config/i386/i386.h
12890 +++ b/gcc/config/i386/i386.h
12891 @@ -59,6 +59,7 @@ see the files COPYING3 and COPYING.RUNTI
12892 #define TARGET_ABM OPTION_ISA_ABM
12893 #define TARGET_POPCNT OPTION_ISA_POPCNT
12894 #define TARGET_SAHF OPTION_ISA_SAHF
12895 +#define TARGET_MOVBE OPTION_ISA_MOVBE
12896 #define TARGET_AES OPTION_ISA_AES
12897 #define TARGET_PCLMUL OPTION_ISA_PCLMUL
12898 #define TARGET_CMPXCHG16B OPTION_ISA_CX16
12899 @@ -236,6 +237,7 @@ extern const struct processor_costs ix86
12900 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)
12901 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)
12902 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
12903 +#define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)
12905 /* Feature tests against the various tunings. */
12906 enum ix86_tune_indices {
12907 @@ -300,6 +302,7 @@ enum ix86_tune_indices {
12908 X86_TUNE_USE_VECTOR_FP_CONVERTS,
12909 X86_TUNE_USE_VECTOR_CONVERTS,
12910 X86_TUNE_FUSE_CMP_AND_BRANCH,
12911 + X86_TUNE_OPT_AGU,
12915 @@ -387,6 +390,7 @@ extern unsigned char ix86_tune_features[
12916 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]
12917 #define TARGET_FUSE_CMP_AND_BRANCH \
12918 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]
12919 +#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]
12921 /* Feature tests against the various architecture variations. */
12922 enum ix86_arch_indices {
12923 @@ -470,7 +474,10 @@ enum calling_abi
12927 -/* The default abi form used by target. */
12928 +/* The abi used by target. */
12929 +extern enum calling_abi ix86_abi;
12931 +/* The default abi used by target. */
12932 #define DEFAULT_ABI SYSV_ABI
12934 /* Subtargets may reset this to 1 in order to enable 96-bit long double
12935 @@ -569,6 +576,7 @@ enum target_cpu_default
12936 TARGET_CPU_DEFAULT_prescott,
12937 TARGET_CPU_DEFAULT_nocona,
12938 TARGET_CPU_DEFAULT_core2,
12939 + TARGET_CPU_DEFAULT_atom,
12941 TARGET_CPU_DEFAULT_geode,
12942 TARGET_CPU_DEFAULT_k6,
12943 @@ -658,7 +666,7 @@ enum target_cpu_default
12945 /* Boundary (in *bits*) on which stack pointer should be aligned. */
12946 #define STACK_BOUNDARY \
12947 - (TARGET_64BIT && DEFAULT_ABI == MS_ABI ? 128 : BITS_PER_WORD)
12948 + (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD)
12950 /* Stack boundary of the main function guaranteed by OS. */
12951 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)
12952 @@ -1584,7 +1592,7 @@ typedef struct ix86_args {
12953 int maybe_vaarg; /* true for calls to possibly vardic fncts. */
12954 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should
12955 be passed in SSE registers. Otherwise 0. */
12956 - int call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
12957 + enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise
12958 MS_ABI for ms abi. */
12961 @@ -2230,6 +2238,7 @@ enum processor_type
12962 PROCESSOR_GENERIC32,
12963 PROCESSOR_GENERIC64,
12964 PROCESSOR_AMDFAM10,
12969 @@ -2403,7 +2412,7 @@ struct machine_function GTY(())
12970 int tls_descriptor_call_expanded_p;
12971 /* This value is used for amd64 targets and specifies the current abi
12972 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */
12974 + enum calling_abi call_abi;
12977 #define ix86_stack_locals (cfun->machine->stack_locals)
12978 --- a/gcc/config/i386/i386.md
12979 +++ b/gcc/config/i386/i386.md
12980 @@ -316,7 +316,7 @@
12984 -(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,
12985 +(define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,atom,
12986 generic64,amdfam10"
12987 (const (symbol_ref "ix86_schedule")))
12989 @@ -612,6 +612,12 @@
12990 (define_attr "i387_cw" "trunc,floor,ceil,mask_pm,uninitialized,any"
12991 (const_string "any"))
12993 +;; Define attribute to classify add/sub insns that consumes carry flag (CF)
12994 +(define_attr "use_carry" "0,1" (const_string "0"))
12996 +;; Define attribute to indicate unaligned ssemov insns
12997 +(define_attr "movu" "0,1" (const_string "0"))
12999 ;; Describe a user's asm statement.
13000 (define_asm_attributes
13001 [(set_attr "length" "128")
13002 @@ -727,6 +733,7 @@
13004 (include "athlon.md")
13005 (include "geode.md")
13006 +(include "atom.md")
13009 ;; Operand and operator predicates and constraints
13010 @@ -5790,6 +5797,7 @@
13011 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
13012 "adc{q}\t{%2, %0|%0, %2}"
13013 [(set_attr "type" "alu")
13014 + (set_attr "use_carry" "1")
13015 (set_attr "pent_pair" "pu")
13016 (set_attr "mode" "DI")])
13018 @@ -5864,6 +5872,7 @@
13019 "ix86_binary_operator_ok (PLUS, QImode, operands)"
13020 "adc{b}\t{%2, %0|%0, %2}"
13021 [(set_attr "type" "alu")
13022 + (set_attr "use_carry" "1")
13023 (set_attr "pent_pair" "pu")
13024 (set_attr "mode" "QI")])
13026 @@ -5876,6 +5885,7 @@
13027 "ix86_binary_operator_ok (PLUS, HImode, operands)"
13028 "adc{w}\t{%2, %0|%0, %2}"
13029 [(set_attr "type" "alu")
13030 + (set_attr "use_carry" "1")
13031 (set_attr "pent_pair" "pu")
13032 (set_attr "mode" "HI")])
13034 @@ -5888,6 +5898,7 @@
13035 "ix86_binary_operator_ok (PLUS, SImode, operands)"
13036 "adc{l}\t{%2, %0|%0, %2}"
13037 [(set_attr "type" "alu")
13038 + (set_attr "use_carry" "1")
13039 (set_attr "pent_pair" "pu")
13040 (set_attr "mode" "SI")])
13042 @@ -5901,6 +5912,7 @@
13043 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
13044 "adc{l}\t{%2, %k0|%k0, %2}"
13045 [(set_attr "type" "alu")
13046 + (set_attr "use_carry" "1")
13047 (set_attr "pent_pair" "pu")
13048 (set_attr "mode" "SI")])
13050 @@ -6130,9 +6142,9 @@
13051 (set_attr "mode" "SI")])
13053 (define_insn "*adddi_1_rex64"
13054 - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r")
13055 - (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r")
13056 - (match_operand:DI 2 "x86_64_general_operand" "rme,re,le")))
13057 + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,rm,r,r")
13058 + (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,r,r")
13059 + (match_operand:DI 2 "x86_64_general_operand" "rme,re,0,le")))
13060 (clobber (reg:CC FLAGS_REG))]
13061 "TARGET_64BIT && ix86_binary_operator_ok (PLUS, DImode, operands)"
13063 @@ -6153,6 +6165,10 @@
13067 + /* Use add as much as possible to replace lea for AGU optimization. */
13068 + if (which_alternative == 2 && TARGET_OPT_AGU)
13069 + return "add{q}\t{%1, %0|%0, %1}";
13071 gcc_assert (rtx_equal_p (operands[0], operands[1]));
13073 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
13074 @@ -6171,8 +6187,11 @@
13077 [(set (attr "type")
13078 - (cond [(eq_attr "alternative" "2")
13079 + (cond [(and (eq_attr "alternative" "2")
13080 + (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
13081 (const_string "lea")
13082 + (eq_attr "alternative" "3")
13083 + (const_string "lea")
13084 ; Current assemblers are broken and do not allow @GOTOFF in
13085 ; ought but a memory context.
13086 (match_operand:DI 2 "pic_symbolic_operand" "")
13087 @@ -6189,8 +6208,8 @@
13088 (plus:DI (match_operand:DI 1 "register_operand" "")
13089 (match_operand:DI 2 "x86_64_nonmemory_operand" "")))
13090 (clobber (reg:CC FLAGS_REG))]
13091 - "TARGET_64BIT && reload_completed
13092 - && true_regnum (operands[0]) != true_regnum (operands[1])"
13093 + "TARGET_64BIT && reload_completed
13094 + && ix86_lea_for_add_ok (PLUS, insn, operands)"
13095 [(set (match_dup 0)
13096 (plus:DI (match_dup 1)
13098 @@ -6394,9 +6413,9 @@
13101 (define_insn "*addsi_1"
13102 - [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r")
13103 - (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r")
13104 - (match_operand:SI 2 "general_operand" "g,ri,li")))
13105 + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,rm,r,r")
13106 + (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,r,r")
13107 + (match_operand:SI 2 "general_operand" "g,ri,0,li")))
13108 (clobber (reg:CC FLAGS_REG))]
13109 "ix86_binary_operator_ok (PLUS, SImode, operands)"
13111 @@ -6417,6 +6436,10 @@
13115 + /* Use add as much as possible to replace lea for AGU optimization. */
13116 + if (which_alternative == 2 && TARGET_OPT_AGU)
13117 + return "add{l}\t{%1, %0|%0, %1}";
13119 gcc_assert (rtx_equal_p (operands[0], operands[1]));
13121 /* Make things pretty and `subl $4,%eax' rather than `addl $-4, %eax'.
13122 @@ -6433,7 +6456,10 @@
13125 [(set (attr "type")
13126 - (cond [(eq_attr "alternative" "2")
13127 + (cond [(and (eq_attr "alternative" "2")
13128 + (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
13129 + (const_string "lea")
13130 + (eq_attr "alternative" "3")
13131 (const_string "lea")
13132 ; Current assemblers are broken and do not allow @GOTOFF in
13133 ; ought but a memory context.
13134 @@ -6451,8 +6477,7 @@
13135 (plus (match_operand 1 "register_operand" "")
13136 (match_operand 2 "nonmemory_operand" "")))
13137 (clobber (reg:CC FLAGS_REG))]
13138 - "reload_completed
13139 - && true_regnum (operands[0]) != true_regnum (operands[1])"
13140 + "reload_completed && ix86_lea_for_add_ok (PLUS, insn, operands)"
13144 @@ -7553,6 +7578,7 @@
13145 "TARGET_64BIT && ix86_binary_operator_ok (MINUS, DImode, operands)"
13146 "sbb{q}\t{%2, %0|%0, %2}"
13147 [(set_attr "type" "alu")
13148 + (set_attr "use_carry" "1")
13149 (set_attr "pent_pair" "pu")
13150 (set_attr "mode" "DI")])
13152 @@ -7601,6 +7627,7 @@
13153 "ix86_binary_operator_ok (MINUS, QImode, operands)"
13154 "sbb{b}\t{%2, %0|%0, %2}"
13155 [(set_attr "type" "alu")
13156 + (set_attr "use_carry" "1")
13157 (set_attr "pent_pair" "pu")
13158 (set_attr "mode" "QI")])
13160 @@ -7613,6 +7640,7 @@
13161 "ix86_binary_operator_ok (MINUS, HImode, operands)"
13162 "sbb{w}\t{%2, %0|%0, %2}"
13163 [(set_attr "type" "alu")
13164 + (set_attr "use_carry" "1")
13165 (set_attr "pent_pair" "pu")
13166 (set_attr "mode" "HI")])
13168 @@ -7625,6 +7653,7 @@
13169 "ix86_binary_operator_ok (MINUS, SImode, operands)"
13170 "sbb{l}\t{%2, %0|%0, %2}"
13171 [(set_attr "type" "alu")
13172 + (set_attr "use_carry" "1")
13173 (set_attr "pent_pair" "pu")
13174 (set_attr "mode" "SI")])
13176 @@ -15163,7 +15192,7 @@
13177 ? gen_rtx_REG (XCmode, FIRST_FLOAT_REG) : NULL),
13178 operands[0], const0_rtx,
13179 GEN_INT ((TARGET_64BIT
13180 - ? (DEFAULT_ABI == SYSV_ABI
13181 + ? (ix86_abi == SYSV_ABI
13182 ? X86_64_SSE_REGPARM_MAX
13183 : X64_SSE_REGPARM_MAX)
13184 : X86_32_SSE_REGPARM_MAX)
13185 @@ -15243,6 +15272,7 @@
13188 [(set_attr "length" "1")
13189 + (set_attr "atom_unit" "jeu")
13190 (set_attr "length_immediate" "0")
13191 (set_attr "modrm" "0")])
13193 @@ -15255,6 +15285,7 @@
13196 [(set_attr "length" "1")
13197 + (set_attr "atom_unit" "jeu")
13198 (set_attr "length_immediate" "0")
13199 (set_attr "prefix_rep" "1")
13200 (set_attr "modrm" "0")])
13201 @@ -15265,6 +15296,7 @@
13204 [(set_attr "length" "3")
13205 + (set_attr "atom_unit" "jeu")
13206 (set_attr "length_immediate" "2")
13207 (set_attr "modrm" "0")])
13209 @@ -15618,7 +15650,7 @@
13210 (bswap:SI (match_operand:SI 1 "register_operand" "")))]
13213 - if (!TARGET_BSWAP)
13214 + if (!(TARGET_BSWAP || TARGET_MOVBE))
13216 rtx x = operands[0];
13218 @@ -15630,6 +15662,21 @@
13222 +(define_insn "*bswapsi_movbe"
13223 + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m")
13224 + (bswap:SI (match_operand:SI 1 "nonimmediate_operand" "0,m,r")))]
13225 + "TARGET_MOVBE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
13228 + movbe\t{%1, %0|%0, %1}
13229 + movbe\t{%1, %0|%0, %1}"
13230 + [(set_attr "type" "*,imov,imov")
13231 + (set_attr "modrm" "*,1,1")
13232 + (set_attr "prefix_0f" "1")
13233 + (set_attr "prefix_extra" "*,1,1")
13234 + (set_attr "length" "2,*,*")
13235 + (set_attr "mode" "SI")])
13237 (define_insn "*bswapsi_1"
13238 [(set (match_operand:SI 0 "register_operand" "=r")
13239 (bswap:SI (match_operand:SI 1 "register_operand" "0")))]
13240 @@ -15658,7 +15705,29 @@
13241 [(set_attr "length" "4")
13242 (set_attr "mode" "HI")])
13244 -(define_insn "bswapdi2"
13245 +(define_expand "bswapdi2"
13246 + [(set (match_operand:DI 0 "register_operand" "")
13247 + (bswap:DI (match_operand:DI 1 "register_operand" "")))]
13251 +(define_insn "*bswapdi_movbe"
13252 + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
13253 + (bswap:DI (match_operand:DI 1 "nonimmediate_operand" "0,m,r")))]
13254 + "TARGET_64BIT && TARGET_MOVBE
13255 + && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
13258 + movbe\t{%1, %0|%0, %1}
13259 + movbe\t{%1, %0|%0, %1}"
13260 + [(set_attr "type" "*,imov,imov")
13261 + (set_attr "modrm" "*,1,1")
13262 + (set_attr "prefix_0f" "1")
13263 + (set_attr "prefix_extra" "*,1,1")
13264 + (set_attr "length" "3,*,*")
13265 + (set_attr "mode" "DI")])
13267 +(define_insn "*bswapdi_1"
13268 [(set (match_operand:DI 0 "register_operand" "=r")
13269 (bswap:DI (match_operand:DI 1 "register_operand" "0")))]
13271 @@ -16386,6 +16455,7 @@
13273 "%vrcpss\t{%1, %d0|%d0, %1}"
13274 [(set_attr "type" "sse")
13275 + (set_attr "atom_sse_attr" "rcp")
13276 (set_attr "prefix" "maybe_vex")
13277 (set_attr "mode" "SF")])
13279 @@ -16737,6 +16807,7 @@
13281 "%vrsqrtss\t{%1, %d0|%d0, %1}"
13282 [(set_attr "type" "sse")
13283 + (set_attr "atom_sse_attr" "rcp")
13284 (set_attr "prefix" "maybe_vex")
13285 (set_attr "mode" "SF")])
13287 @@ -16757,6 +16828,7 @@
13288 "SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH"
13289 "%vsqrts<ssemodefsuffix>\t{%1, %d0|%d0, %1}"
13290 [(set_attr "type" "sse")
13291 + (set_attr "atom_sse_attr" "sqrt")
13292 (set_attr "prefix" "maybe_vex")
13293 (set_attr "mode" "<MODE>")
13294 (set_attr "athlon_decode" "*")
13295 @@ -19810,6 +19882,7 @@
13296 ; Since we don't have the proper number of operands for an alu insn,
13297 ; fill in all the blanks.
13298 [(set_attr "type" "alu")
13299 + (set_attr "use_carry" "1")
13300 (set_attr "pent_pair" "pu")
13301 (set_attr "memory" "none")
13302 (set_attr "imm_disp" "false")
13303 @@ -19825,6 +19898,7 @@
13306 [(set_attr "type" "alu")
13307 + (set_attr "use_carry" "1")
13308 (set_attr "pent_pair" "pu")
13309 (set_attr "memory" "none")
13310 (set_attr "imm_disp" "false")
13311 @@ -19868,6 +19942,7 @@
13312 ; Since we don't have the proper number of operands for an alu insn,
13313 ; fill in all the blanks.
13314 [(set_attr "type" "alu")
13315 + (set_attr "use_carry" "1")
13316 (set_attr "pent_pair" "pu")
13317 (set_attr "memory" "none")
13318 (set_attr "imm_disp" "false")
13319 @@ -19883,6 +19958,7 @@
13322 [(set_attr "type" "alu")
13323 + (set_attr "use_carry" "1")
13324 (set_attr "pent_pair" "pu")
13325 (set_attr "memory" "none")
13326 (set_attr "imm_disp" "false")
13327 @@ -20215,7 +20291,8 @@
13330 [(set (attr "type")
13331 - (cond [(eq_attr "alternative" "0")
13332 + (cond [(and (eq_attr "alternative" "0")
13333 + (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
13334 (const_string "alu")
13335 (match_operand:SI 2 "const0_operand" "")
13336 (const_string "imov")
13337 @@ -20258,7 +20335,8 @@
13340 [(set (attr "type")
13341 - (cond [(eq_attr "alternative" "0")
13342 + (cond [(and (eq_attr "alternative" "0")
13343 + (eq (symbol_ref "TARGET_OPT_AGU") (const_int 0)))
13344 (const_string "alu")
13345 (match_operand:DI 2 "const0_operand" "")
13346 (const_string "imov")
13347 @@ -21746,6 +21824,7 @@
13348 return patterns[locality];
13350 [(set_attr "type" "sse")
13351 + (set_attr "atom_sse_attr" "prefetch")
13352 (set_attr "memory" "none")])
13354 (define_insn "*prefetch_sse_rex"
13355 @@ -21764,6 +21843,7 @@
13356 return patterns[locality];
13358 [(set_attr "type" "sse")
13359 + (set_attr "atom_sse_attr" "prefetch")
13360 (set_attr "memory" "none")])
13362 (define_insn "*prefetch_3dnow"
13363 --- a/gcc/config/i386/i386.opt
13364 +++ b/gcc/config/i386/i386.opt
13365 @@ -228,6 +228,10 @@ mtune=
13366 Target RejectNegative Joined Var(ix86_tune_string)
13367 Schedule code for given CPU
13370 +Target RejectNegative Joined Var(ix86_abi_string)
13371 +Generate code that conforms to the given ABI
13374 Target RejectNegative Joined Var(ix86_veclibabi_string)
13375 Vector library ABI to use
13376 @@ -335,6 +339,10 @@ msahf
13377 Target Report Mask(ISA_SAHF) Var(ix86_isa_flags) VarExists Save
13378 Support code generation of sahf instruction in 64bit x86-64 code.
13381 +Target Report Mask(ISA_MOVBE) Var(ix86_isa_flags) VarExists Save
13382 +Support code generation of movbe instruction.
13385 Target Report Mask(ISA_AES) Var(ix86_isa_flags) VarExists Save
13386 Support AES built-in functions and code generation
13387 --- a/gcc/config/i386/mingw32.h
13388 +++ b/gcc/config/i386/mingw32.h
13389 @@ -38,7 +38,7 @@ along with GCC; see the file COPYING3.
13390 builtin_define_std ("WINNT"); \
13391 builtin_define_with_int_value ("_INTEGRAL_MAX_BITS", \
13392 TYPE_PRECISION (intmax_type_node));\
13393 - if (TARGET_64BIT && DEFAULT_ABI == MS_ABI) \
13394 + if (TARGET_64BIT && ix86_abi == MS_ABI) \
13396 builtin_define ("__MINGW64__"); \
13397 builtin_define_std ("WIN64"); \
13398 --- a/gcc/config/i386/sse.md
13399 +++ b/gcc/config/i386/sse.md
13400 @@ -342,6 +342,7 @@
13401 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
13402 "vmovup<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
13403 [(set_attr "type" "ssemov")
13404 + (set_attr "movu" "1")
13405 (set_attr "prefix" "vex")
13406 (set_attr "mode" "<MODE>")])
13408 @@ -367,6 +368,7 @@
13409 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
13410 "movup<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
13411 [(set_attr "type" "ssemov")
13412 + (set_attr "movu" "1")
13413 (set_attr "mode" "<MODE>")])
13415 (define_insn "avx_movdqu<avxmodesuffix>"
13416 @@ -377,6 +379,7 @@
13417 "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
13418 "vmovdqu\t{%1, %0|%0, %1}"
13419 [(set_attr "type" "ssemov")
13420 + (set_attr "movu" "1")
13421 (set_attr "prefix" "vex")
13422 (set_attr "mode" "<avxvecmode>")])
13424 @@ -387,6 +390,7 @@
13425 "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
13426 "movdqu\t{%1, %0|%0, %1}"
13427 [(set_attr "type" "ssemov")
13428 + (set_attr "movu" "1")
13429 (set_attr "prefix_data16" "1")
13430 (set_attr "mode" "TI")])
13432 @@ -428,7 +432,7 @@
13435 "movntdq\t{%1, %0|%0, %1}"
13436 - [(set_attr "type" "ssecvt")
13437 + [(set_attr "type" "ssemov")
13438 (set_attr "prefix_data16" "1")
13439 (set_attr "mode" "TI")])
13441 @@ -438,7 +442,7 @@
13444 "movnti\t{%1, %0|%0, %1}"
13445 - [(set_attr "type" "ssecvt")
13446 + [(set_attr "type" "ssemov")
13447 (set_attr "mode" "V2DF")])
13449 (define_insn "avx_lddqu<avxmodesuffix>"
13450 @@ -449,6 +453,7 @@
13452 "vlddqu\t{%1, %0|%0, %1}"
13453 [(set_attr "type" "ssecvt")
13454 + (set_attr "movu" "1")
13455 (set_attr "prefix" "vex")
13456 (set_attr "mode" "<avxvecmode>")])
13458 @@ -458,7 +463,8 @@
13461 "lddqu\t{%1, %0|%0, %1}"
13462 - [(set_attr "type" "ssecvt")
13463 + [(set_attr "type" "ssemov")
13464 + (set_attr "movu" "1")
13465 (set_attr "prefix_rep" "1")
13466 (set_attr "mode" "TI")])
13468 @@ -765,6 +771,7 @@
13470 "%vrcpps\t{%1, %0|%0, %1}"
13471 [(set_attr "type" "sse")
13472 + (set_attr "atom_sse_attr" "rcp")
13473 (set_attr "prefix" "maybe_vex")
13474 (set_attr "mode" "V4SF")])
13476 @@ -791,6 +798,7 @@
13478 "rcpss\t{%1, %0|%0, %1}"
13479 [(set_attr "type" "sse")
13480 + (set_attr "atom_sse_attr" "rcp")
13481 (set_attr "mode" "SF")])
13483 (define_expand "sqrtv8sf2"
13484 @@ -836,6 +844,7 @@
13486 "%vsqrtps\t{%1, %0|%0, %1}"
13487 [(set_attr "type" "sse")
13488 + (set_attr "atom_sse_attr" "sqrt")
13489 (set_attr "prefix" "maybe_vex")
13490 (set_attr "mode" "V4SF")])
13492 @@ -880,6 +889,7 @@
13493 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
13494 "sqrts<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
13495 [(set_attr "type" "sse")
13496 + (set_attr "atom_sse_attr" "sqrt")
13497 (set_attr "mode" "<ssescalarmode>")])
13499 (define_expand "rsqrtv8sf2"
13500 @@ -1043,7 +1053,7 @@
13502 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
13503 "<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
13504 - [(set_attr "type" "sse")
13505 + [(set_attr "type" "sseadd")
13506 (set_attr "mode" "<ssescalarmode>")])
13508 ;; These versions of the min/max patterns implement exactly the operations
13509 @@ -1179,6 +1189,7 @@
13511 "addsubpd\t{%2, %0|%0, %2}"
13512 [(set_attr "type" "sseadd")
13513 + (set_attr "atom_unit" "complex")
13514 (set_attr "mode" "V2DF")])
13516 (define_insn "avx_h<plusminus_insn>v4df3"
13517 @@ -1302,6 +1313,7 @@
13519 "h<plusminus_mnemonic>ps\t{%2, %0|%0, %2}"
13520 [(set_attr "type" "sseadd")
13521 + (set_attr "atom_unit" "complex")
13522 (set_attr "prefix_rep" "1")
13523 (set_attr "mode" "V4SF")])
13525 @@ -5069,6 +5081,7 @@
13526 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
13527 "pmaddwd\t{%2, %0|%0, %2}"
13528 [(set_attr "type" "sseiadd")
13529 + (set_attr "atom_unit" "simul")
13530 (set_attr "prefix_data16" "1")
13531 (set_attr "mode" "TI")])
13533 @@ -7035,6 +7048,7 @@
13534 movq\t{%H1, %0|%0, %H1}
13535 mov{q}\t{%H1, %0|%0, %H1}"
13536 [(set_attr "type" "ssemov,sseishft,ssemov,imov")
13537 + (set_attr "atom_unit" "*,sishuf,*,*")
13538 (set_attr "memory" "*,none,*,*")
13539 (set_attr "mode" "V2SF,TI,TI,DI")])
13541 @@ -7067,6 +7081,7 @@
13542 psrldq\t{$8, %0|%0, 8}
13543 movq\t{%H1, %0|%0, %H1}"
13544 [(set_attr "type" "ssemov,sseishft,ssemov")
13545 + (set_attr "atom_unit" "*,sishuf,*")
13546 (set_attr "memory" "*,none,*")
13547 (set_attr "mode" "V2SF,TI,TI")])
13549 @@ -7624,6 +7639,7 @@
13551 "psadbw\t{%2, %0|%0, %2}"
13552 [(set_attr "type" "sseiadd")
13553 + (set_attr "atom_unit" "simul")
13554 (set_attr "prefix_data16" "1")
13555 (set_attr "mode" "TI")])
13557 @@ -7645,7 +7661,7 @@
13559 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
13560 "%vmovmskp<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
13561 - [(set_attr "type" "ssecvt")
13562 + [(set_attr "type" "ssemov")
13563 (set_attr "prefix" "maybe_vex")
13564 (set_attr "mode" "<MODE>")])
13566 @@ -7655,7 +7671,7 @@
13569 "%vpmovmskb\t{%1, %0|%0, %1}"
13570 - [(set_attr "type" "ssecvt")
13571 + [(set_attr "type" "ssemov")
13572 (set_attr "prefix_data16" "1")
13573 (set_attr "prefix" "maybe_vex")
13574 (set_attr "mode" "SI")])
13575 @@ -7678,7 +7694,7 @@
13576 "TARGET_SSE2 && !TARGET_64BIT"
13577 ;; @@@ check ordering of operands in intel/nonintel syntax
13578 "%vmaskmovdqu\t{%2, %1|%1, %2}"
13579 - [(set_attr "type" "ssecvt")
13580 + [(set_attr "type" "ssemov")
13581 (set_attr "prefix_data16" "1")
13582 (set_attr "prefix" "maybe_vex")
13583 (set_attr "mode" "TI")])
13584 @@ -7692,7 +7708,7 @@
13585 "TARGET_SSE2 && TARGET_64BIT"
13586 ;; @@@ check ordering of operands in intel/nonintel syntax
13587 "%vmaskmovdqu\t{%2, %1|%1, %2}"
13588 - [(set_attr "type" "ssecvt")
13589 + [(set_attr "type" "ssemov")
13590 (set_attr "prefix_data16" "1")
13591 (set_attr "prefix" "maybe_vex")
13592 (set_attr "mode" "TI")])
13593 @@ -7703,6 +7719,7 @@
13596 [(set_attr "type" "sse")
13597 + (set_attr "atom_sse_attr" "mxcsr")
13598 (set_attr "prefix" "maybe_vex")
13599 (set_attr "memory" "load")])
13601 @@ -7712,6 +7729,7 @@
13604 [(set_attr "type" "sse")
13605 + (set_attr "atom_sse_attr" "mxcsr")
13606 (set_attr "prefix" "maybe_vex")
13607 (set_attr "memory" "store")])
13609 @@ -7730,6 +7748,7 @@
13610 "TARGET_SSE || TARGET_3DNOW_A"
13612 [(set_attr "type" "sse")
13613 + (set_attr "atom_sse_attr" "fence")
13614 (set_attr "memory" "unknown")])
13616 (define_insn "sse2_clflush"
13617 @@ -7738,6 +7757,7 @@
13620 [(set_attr "type" "sse")
13621 + (set_attr "atom_sse_attr" "fence")
13622 (set_attr "memory" "unknown")])
13624 (define_expand "sse2_mfence"
13625 @@ -7755,6 +7775,7 @@
13626 "TARGET_64BIT || TARGET_SSE2"
13628 [(set_attr "type" "sse")
13629 + (set_attr "atom_sse_attr" "fence")
13630 (set_attr "memory" "unknown")])
13632 (define_expand "sse2_lfence"
13633 @@ -7772,6 +7793,7 @@
13636 [(set_attr "type" "sse")
13637 + (set_attr "atom_sse_attr" "lfence")
13638 (set_attr "memory" "unknown")])
13640 (define_insn "sse3_mwait"
13641 @@ -7895,6 +7917,7 @@
13643 "phaddw\t{%2, %0|%0, %2}"
13644 [(set_attr "type" "sseiadd")
13645 + (set_attr "atom_unit" "complex")
13646 (set_attr "prefix_data16" "1")
13647 (set_attr "prefix_extra" "1")
13648 (set_attr "mode" "TI")])
13649 @@ -7923,6 +7946,7 @@
13651 "phaddw\t{%2, %0|%0, %2}"
13652 [(set_attr "type" "sseiadd")
13653 + (set_attr "atom_unit" "complex")
13654 (set_attr "prefix_extra" "1")
13655 (set_attr "mode" "DI")])
13657 @@ -7977,6 +8001,7 @@
13659 "phaddd\t{%2, %0|%0, %2}"
13660 [(set_attr "type" "sseiadd")
13661 + (set_attr "atom_unit" "complex")
13662 (set_attr "prefix_data16" "1")
13663 (set_attr "prefix_extra" "1")
13664 (set_attr "mode" "TI")])
13665 @@ -7997,6 +8022,7 @@
13667 "phaddd\t{%2, %0|%0, %2}"
13668 [(set_attr "type" "sseiadd")
13669 + (set_attr "atom_unit" "complex")
13670 (set_attr "prefix_extra" "1")
13671 (set_attr "mode" "DI")])
13673 @@ -8083,6 +8109,7 @@
13675 "phaddsw\t{%2, %0|%0, %2}"
13676 [(set_attr "type" "sseiadd")
13677 + (set_attr "atom_unit" "complex")
13678 (set_attr "prefix_data16" "1")
13679 (set_attr "prefix_extra" "1")
13680 (set_attr "mode" "TI")])
13681 @@ -8111,6 +8138,7 @@
13683 "phaddsw\t{%2, %0|%0, %2}"
13684 [(set_attr "type" "sseiadd")
13685 + (set_attr "atom_unit" "complex")
13686 (set_attr "prefix_extra" "1")
13687 (set_attr "mode" "DI")])
13689 @@ -8197,6 +8225,7 @@
13691 "phsubw\t{%2, %0|%0, %2}"
13692 [(set_attr "type" "sseiadd")
13693 + (set_attr "atom_unit" "complex")
13694 (set_attr "prefix_data16" "1")
13695 (set_attr "prefix_extra" "1")
13696 (set_attr "mode" "TI")])
13697 @@ -8225,6 +8254,7 @@
13699 "phsubw\t{%2, %0|%0, %2}"
13700 [(set_attr "type" "sseiadd")
13701 + (set_attr "atom_unit" "complex")
13702 (set_attr "prefix_extra" "1")
13703 (set_attr "mode" "DI")])
13705 @@ -8279,6 +8309,7 @@
13707 "phsubd\t{%2, %0|%0, %2}"
13708 [(set_attr "type" "sseiadd")
13709 + (set_attr "atom_unit" "complex")
13710 (set_attr "prefix_data16" "1")
13711 (set_attr "prefix_extra" "1")
13712 (set_attr "mode" "TI")])
13713 @@ -8299,6 +8330,7 @@
13715 "phsubd\t{%2, %0|%0, %2}"
13716 [(set_attr "type" "sseiadd")
13717 + (set_attr "atom_unit" "complex")
13718 (set_attr "prefix_extra" "1")
13719 (set_attr "mode" "DI")])
13721 @@ -8385,6 +8417,7 @@
13723 "phsubsw\t{%2, %0|%0, %2}"
13724 [(set_attr "type" "sseiadd")
13725 + (set_attr "atom_unit" "complex")
13726 (set_attr "prefix_data16" "1")
13727 (set_attr "prefix_extra" "1")
13728 (set_attr "mode" "TI")])
13729 @@ -8413,6 +8446,7 @@
13731 "phsubsw\t{%2, %0|%0, %2}"
13732 [(set_attr "type" "sseiadd")
13733 + (set_attr "atom_unit" "complex")
13734 (set_attr "prefix_extra" "1")
13735 (set_attr "mode" "DI")])
13737 @@ -8519,6 +8553,7 @@
13739 "pmaddubsw\t{%2, %0|%0, %2}"
13740 [(set_attr "type" "sseiadd")
13741 + (set_attr "atom_unit" "simul")
13742 (set_attr "prefix_data16" "1")
13743 (set_attr "prefix_extra" "1")
13744 (set_attr "mode" "TI")])
13745 @@ -8557,6 +8592,7 @@
13747 "pmaddubsw\t{%2, %0|%0, %2}"
13748 [(set_attr "type" "sseiadd")
13749 + (set_attr "atom_unit" "simul")
13750 (set_attr "prefix_extra" "1")
13751 (set_attr "mode" "DI")])
13753 @@ -8764,6 +8800,7 @@
13754 return "palignr\t{%3, %2, %0|%0, %2, %3}";
13756 [(set_attr "type" "sseishft")
13757 + (set_attr "atom_unit" "sishuf")
13758 (set_attr "prefix_data16" "1")
13759 (set_attr "prefix_extra" "1")
13760 (set_attr "mode" "TI")])
13761 @@ -8780,6 +8817,7 @@
13762 return "palignr\t{%3, %2, %0|%0, %2, %3}";
13764 [(set_attr "type" "sseishft")
13765 + (set_attr "atom_unit" "sishuf")
13766 (set_attr "prefix_extra" "1")
13767 (set_attr "mode" "DI")])
13769 @@ -8966,7 +9004,7 @@
13772 "%vmovntdqa\t{%1, %0|%0, %1}"
13773 - [(set_attr "type" "ssecvt")
13774 + [(set_attr "type" "ssemov")
13775 (set_attr "prefix_extra" "1")
13776 (set_attr "prefix" "maybe_vex")
13777 (set_attr "mode" "TI")])
13778 --- a/gcc/config/i386/winnt.c
13779 +++ b/gcc/config/i386/winnt.c
13780 @@ -499,8 +499,11 @@ i386_pe_asm_output_aligned_decl_common (
13782 HOST_WIDE_INT rounded;
13784 - /* Compute as in assemble_noswitch_variable, since we don't actually
13785 - support aligned common. */
13786 + /* Compute as in assemble_noswitch_variable, since we don't have
13787 + support for aligned common on older binutils. We must also
13788 + avoid emitting a common symbol of size zero, as this is the
13789 + overloaded representation that indicates an undefined external
13790 + symbol in the PE object file format. */
13791 rounded = size ? size : 1;
13792 rounded += (BIGGEST_ALIGNMENT / BITS_PER_UNIT) - 1;
13793 rounded = (rounded / (BIGGEST_ALIGNMENT / BITS_PER_UNIT)
13794 @@ -510,9 +513,13 @@ i386_pe_asm_output_aligned_decl_common (
13796 fprintf (stream, "\t.comm\t");
13797 assemble_name (stream, name);
13798 - fprintf (stream, ", " HOST_WIDE_INT_PRINT_DEC "\t" ASM_COMMENT_START
13799 - " " HOST_WIDE_INT_PRINT_DEC "\n",
13801 + if (use_pe_aligned_common)
13802 + fprintf (stream, ", " HOST_WIDE_INT_PRINT_DEC ", %d\n",
13803 + size ? size : (HOST_WIDE_INT) 1,
13804 + exact_log2 (align) - exact_log2 (CHAR_BIT));
13806 + fprintf (stream, ", " HOST_WIDE_INT_PRINT_DEC "\t" ASM_COMMENT_START
13807 + " " HOST_WIDE_INT_PRINT_DEC "\n", rounded, size);
13810 /* The Microsoft linker requires that every function be marked as
13811 --- a/gcc/config/m68k/constraints.md
13812 +++ b/gcc/config/m68k/constraints.md
13813 @@ -124,6 +124,11 @@
13814 (and (match_code "const_int")
13815 (match_test "ival < -0x8000 || ival > 0x7FFF")))
13817 +(define_constraint "Cu"
13818 + "16-bit offset for wrapped symbols"
13819 + (and (match_code "const")
13820 + (match_test "m68k_unwrap_symbol (op, false) != op")))
13822 (define_constraint "CQ"
13823 "Integers valid for mvq."
13824 (and (match_code "const_int")
13825 --- a/gcc/config/m68k/lb1sf68.asm
13826 +++ b/gcc/config/m68k/lb1sf68.asm
13827 @@ -163,6 +163,8 @@ see the files COPYING3 and COPYING.RUNTI
13828 #if defined (__mcoldfire__) && !defined (__mcfisab__) && !defined (__mcfisac__)
13831 +#elif defined (__mcfisab__) || defined (__mcfisac__)
13836 @@ -202,6 +204,8 @@ see the files COPYING3 and COPYING.RUNTI
13837 #if defined (__mcoldfire__) && !defined (__mcfisab__) && !defined (__mcfisac__)
13840 +#elif defined (__mcfisab__) || defined (__mcfisac__)
13845 --- a/gcc/config/m68k/linux-unwind.h
13846 +++ b/gcc/config/m68k/linux-unwind.h
13847 @@ -77,9 +77,15 @@ m68k_fallback_frame_state (struct _Unwin
13848 fs->regs.reg[9].how = REG_SAVED_OFFSET;
13849 fs->regs.reg[9].loc.offset = (long) &sc->sc_a1 - cfa;
13851 +#ifdef __uClinux__
13852 + fs->regs.reg[13].how = REG_SAVED_OFFSET;
13853 + fs->regs.reg[13].loc.offset = (long) &sc->sc_a5 - cfa;
13856 fs->regs.reg[24].how = REG_SAVED_OFFSET;
13857 fs->regs.reg[24].loc.offset = (long) &sc->sc_pc - cfa;
13859 +#if defined __mcffpu__ && !defined __uClinux__
13860 if (*(int *) sc->sc_fpstate)
13862 int *fpregs = (int *) sc->sc_fpregs;
13863 @@ -89,11 +95,19 @@ m68k_fallback_frame_state (struct _Unwin
13864 fs->regs.reg[17].how = REG_SAVED_OFFSET;
13865 fs->regs.reg[17].loc.offset = (long) &fpregs[M68K_FP_SIZE/4] - cfa;
13867 +#elif defined __mcffpu__
13868 +# error Implement this when uClinux kernel is ported to an FPU architecture
13871 #ifdef __mcoldfire__
13872 /* move.l #__NR_rt_sigreturn,%d0; trap #0 */
13873 - else if (pc[0] == 0x203c && pc[1] == 0x0000 &&
13874 - pc[2] == 0x00ad && pc[3] == 0x4e40)
13875 + else if ((pc[0] == 0x203c && pc[1] == 0x0000 &&
13876 + pc[2] == 0x00ad && pc[3] == 0x4e40) ||
13877 + /* Don't ask me why, this is just what some kernels do:
13878 + moveq #-__NR_rt_sigreturn,%d0; andil 0xff,%d0; trap #0;
13880 + (pc[0] == 0x70ad && pc[1] == 0x0280 && pc[2] == 0x0000 &&
13881 + pc[3] == 0x00ff && pc[4] == 0x4e40 && pc[5] == 0x0000))
13883 /* moveq #~__NR_rt_sigreturn,%d0; not.b %d0; trap #0 */
13884 else if (pc[0] == 0x7052 && pc[1] == 0x4600 && pc[2] == 0x4e40)
13885 --- a/gcc/config/m68k/m68k-devices.def
13886 +++ b/gcc/config/m68k/m68k-devices.def
13888 /* 680x0 series processors. */
13889 M68K_DEVICE ("68000", m68000, "68000", "68000", 68000, isa_00, 0)
13890 M68K_DEVICE ("68010", m68010, "68010", "68000", 68010, isa_10, 0)
13891 -M68K_DEVICE ("68020", m68020, "68020", "68020", 68020, isa_20, FL_MMU)
13892 -M68K_DEVICE ("68030", m68030, "68030", "68020", 68030, isa_20, FL_MMU)
13893 +M68K_DEVICE ("68020", m68020, "68020", "68020", 68020, isa_20, FL_MMU | FL_UCLINUX)
13894 +M68K_DEVICE ("68030", m68030, "68030", "68020", 68030, isa_20, FL_MMU | FL_UCLINUX)
13895 M68K_DEVICE ("68040", m68040, "68040", "68040", 68040, isa_40, FL_MMU)
13896 M68K_DEVICE ("68060", m68060, "68060", "68060", 68060, isa_40, FL_MMU)
13897 M68K_DEVICE ("68302", m68302, "68302", "68000", 68000, isa_00, FL_MMU)
13898 @@ -81,7 +81,13 @@ M68K_DEVICE ("68332", m68332, "68332",
13899 M68K_DEVICE ("cpu32", cpu32, "cpu32", "cpu32", cpu32, isa_cpu32, FL_MMU)
13901 /* ColdFire CFV1 processor. */
13902 -M68K_DEVICE ("51qe", mcf51qe, "51qe", "51qe", cfv1, isa_c, FL_CF_USP)
13903 +/* For historical reasons, the 51 multilib is named 51qe. */
13904 +M68K_DEVICE ("51", mcf51, "51", "51qe", cfv1, isa_c, FL_CF_USP)
13905 +M68K_DEVICE ("51ac", mcf51ac, "51", "51qe", cfv1, isa_c, FL_CF_USP)
13906 +M68K_DEVICE ("51cn", mcf51cn, "51", "51qe", cfv1, isa_c, FL_CF_USP)
13907 +M68K_DEVICE ("51em", mcf51em, "51", "51qe", cfv1, isa_c, FL_CF_USP | FL_CF_MAC)
13908 +M68K_DEVICE ("51jm", mcf51jm, "51", "51qe", cfv1, isa_c, FL_CF_USP)
13909 +M68K_DEVICE ("51qe", mcf51qe, "51", "51qe", cfv1, isa_c, FL_CF_USP)
13911 /* ColdFire CFV2 processors. */
13912 M68K_DEVICE ("5202", mcf5202, "5206", "5206", cfv2, isa_a, 0)
13913 @@ -97,6 +103,7 @@ M68K_DEVICE ("5212", mcf5212, "5213",
13914 M68K_DEVICE ("5213", mcf5213, "5213", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_MAC)
13915 M68K_DEVICE ("5214", mcf5214, "5216", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13916 M68K_DEVICE ("5216", mcf5216, "5216", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13917 +M68K_DEVICE ("5221x", mcf5221x, "5221x", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_MAC)
13918 M68K_DEVICE ("52221", mcf52221, "52223", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_MAC)
13919 M68K_DEVICE ("52223", mcf52223, "52223", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_MAC)
13920 M68K_DEVICE ("52230", mcf52230, "52235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13921 @@ -107,6 +114,14 @@ M68K_DEVICE ("52234", mcf52234, "52235",
13922 M68K_DEVICE ("52235", mcf52235, "52235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13923 M68K_DEVICE ("5224", mcf5224, "5225", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_MAC)
13924 M68K_DEVICE ("5225", mcf5225, "5225", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_MAC)
13925 +M68K_DEVICE ("52252", mcf52252, "52259", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13926 +M68K_DEVICE ("52254", mcf52254, "52259", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13927 +M68K_DEVICE ("52255", mcf52255, "52259", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13928 +M68K_DEVICE ("52256", mcf52256, "52259", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13929 +M68K_DEVICE ("52258", mcf52258, "52259", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13930 +M68K_DEVICE ("52259", mcf52259, "52259", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13931 +M68K_DEVICE ("52274", mcf52274, "52277", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13932 +M68K_DEVICE ("52277", mcf52277, "52277", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13933 M68K_DEVICE ("5232", mcf5232, "5235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13934 M68K_DEVICE ("5233", mcf5233, "5235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13935 M68K_DEVICE ("5234", mcf5234, "5235", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13936 @@ -126,6 +141,13 @@ M68K_DEVICE ("5282", mcf5282, "5282",
13937 M68K_DEVICE ("528x", mcf528x, "5282", "5208", cfv2, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13939 /* CFV3 processors. */
13940 +M68K_DEVICE ("53011", mcf53011, "53017", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13941 +M68K_DEVICE ("53012", mcf53012, "53017", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13942 +M68K_DEVICE ("53013", mcf53013, "53017", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13943 +M68K_DEVICE ("53014", mcf53014, "53017", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13944 +M68K_DEVICE ("53015", mcf53015, "53017", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13945 +M68K_DEVICE ("53016", mcf53016, "53017", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13946 +M68K_DEVICE ("53017", mcf53017, "53017", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13947 M68K_DEVICE ("5307", mcf5307, "5307", "5307", cfv3, isa_a, FL_CF_HWDIV | FL_CF_MAC)
13948 M68K_DEVICE ("5327", mcf5327, "5329", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13949 M68K_DEVICE ("5328", mcf5328, "5329", "5329", cfv3, isa_aplus, FL_CF_HWDIV | FL_CF_EMAC)
13950 @@ -137,12 +159,17 @@ M68K_DEVICE ("537x", mcf537x, "5373",
13952 /* CFV4/CFV4e processors. */
13953 M68K_DEVICE ("5407", mcf5407, "5407", "5407", cfv4, isa_b, FL_CF_MAC)
13954 -M68K_DEVICE ("54450", mcf54450, "54455", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU)
13955 -M68K_DEVICE ("54451", mcf54451, "54455", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU)
13956 -M68K_DEVICE ("54452", mcf54452, "54455", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU)
13957 -M68K_DEVICE ("54453", mcf54453, "54455", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU)
13958 -M68K_DEVICE ("54454", mcf54454, "54455", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU)
13959 -M68K_DEVICE ("54455", mcf54455, "54455", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU)
13960 +M68K_DEVICE ("54410", mcf54410, "54418", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU | FL_UCLINUX)
13961 +M68K_DEVICE ("54415", mcf54415, "54418", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU | FL_UCLINUX)
13962 +M68K_DEVICE ("54416", mcf54416, "54418", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU | FL_UCLINUX)
13963 +M68K_DEVICE ("54417", mcf54417, "54418", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU | FL_UCLINUX)
13964 +M68K_DEVICE ("54418", mcf54418, "54418", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU | FL_UCLINUX)
13965 +M68K_DEVICE ("54450", mcf54450, "54455", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU | FL_UCLINUX)
13966 +M68K_DEVICE ("54451", mcf54451, "54455", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU | FL_UCLINUX)
13967 +M68K_DEVICE ("54452", mcf54452, "54455", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU | FL_UCLINUX)
13968 +M68K_DEVICE ("54453", mcf54453, "54455", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU | FL_UCLINUX)
13969 +M68K_DEVICE ("54454", mcf54454, "54455", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU | FL_UCLINUX)
13970 +M68K_DEVICE ("54455", mcf54455, "54455", "54455", cfv4, isa_c, FL_CF_HWDIV | FL_CF_USP | FL_CF_EMAC | FL_MMU | FL_UCLINUX)
13971 M68K_DEVICE ("5470", mcf5470, "5475", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU)
13972 M68K_DEVICE ("5471", mcf5471, "5475", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU)
13973 M68K_DEVICE ("5472", mcf5472, "5475", "5475", cfv4e, isa_b, FL_CF_USP | FL_CF_EMAC | FL_CF_FPU | FL_MMU)
13974 --- a/gcc/config/m68k/m68k-protos.h
13975 +++ b/gcc/config/m68k/m68k-protos.h
13976 @@ -54,19 +54,27 @@ extern void print_operand (FILE *, rtx,
13977 extern bool m68k_output_addr_const_extra (FILE *, rtx);
13978 extern void notice_update_cc (rtx, rtx);
13979 extern bool m68k_legitimate_base_reg_p (rtx, bool);
13980 -extern bool m68k_legitimate_index_reg_p (rtx, bool);
13981 +extern bool m68k_legitimate_index_reg_p (enum machine_mode, rtx, bool);
13982 extern bool m68k_illegitimate_symbolic_constant_p (rtx);
13983 extern bool m68k_legitimate_address_p (enum machine_mode, rtx, bool);
13984 extern bool m68k_matches_q_p (rtx);
13985 extern bool m68k_matches_u_p (rtx);
13986 extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx);
13987 +extern rtx m68k_legitimize_tls_address (rtx);
13988 +extern bool m68k_tls_reference_p (rtx, bool);
13989 +extern rtx m68k_legitimize_address (rtx, rtx, enum machine_mode);
13990 extern int valid_dbcc_comparison_p_2 (rtx, enum machine_mode);
13991 extern rtx m68k_libcall_value (enum machine_mode);
13992 extern rtx m68k_function_value (const_tree, const_tree);
13993 extern int emit_move_sequence (rtx *, enum machine_mode, rtx);
13994 extern bool m68k_movem_pattern_p (rtx, rtx, HOST_WIDE_INT, bool);
13995 extern const char *m68k_output_movem (rtx *, rtx, HOST_WIDE_INT, bool);
13996 +extern void m68k_final_prescan_insn (rtx, rtx *, int);
13998 +/* Functions from m68k.c used in constraints.md. */
13999 +extern rtx m68k_unwrap_symbol (rtx, bool);
14001 +/* Functions from m68k.c used in genattrtab. */
14002 #ifdef HAVE_ATTR_cpu
14003 extern enum attr_cpu m68k_sched_cpu;
14004 extern enum attr_mac m68k_sched_mac;
14005 --- a/gcc/config/m68k/m68k.c
14006 +++ b/gcc/config/m68k/m68k.c
14007 @@ -46,6 +46,7 @@ along with GCC; see the file COPYING3.
14008 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
14009 #include "sched-int.h"
14010 #include "insn-codes.h"
14013 enum reg_class regno_reg_class[] =
14015 @@ -146,10 +147,12 @@ static tree m68k_handle_fndecl_attribute
14016 static void m68k_compute_frame_layout (void);
14017 static bool m68k_save_reg (unsigned int regno, bool interrupt_handler);
14018 static bool m68k_ok_for_sibcall_p (tree, tree);
14019 +static bool m68k_tls_symbol_p (rtx);
14020 static bool m68k_rtx_costs (rtx, int, int, int *, bool);
14021 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
14022 static bool m68k_return_in_memory (const_tree, const_tree);
14024 +static void m68k_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
14027 /* Specify the identification number of the library being built */
14028 @@ -252,6 +255,14 @@ int m68k_last_compare_had_fp_operands;
14029 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
14032 +#ifdef HAVE_AS_TLS
14033 +#undef TARGET_HAVE_TLS
14034 +#define TARGET_HAVE_TLS (true)
14036 +#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
14037 +#define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
14040 static const struct attribute_spec m68k_attribute_table[] =
14042 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
14043 @@ -1150,8 +1161,7 @@ m68k_expand_prologue (void)
14044 current_frame.reg_mask, true, true));
14048 - && !TARGET_SEP_DATA
14049 + if (!TARGET_SEP_DATA
14050 && crtl->uses_pic_offset_table)
14051 insn = emit_insn (gen_load_got (pic_offset_table_rtx));
14053 @@ -1425,6 +1435,86 @@ m68k_legitimize_sibcall_address (rtx x)
14054 return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM));
14057 +/* Convert X to a legitimate address and return it if successful. Otherwise
14060 + For the 68000, we handle X+REG by loading X into a register R and
14061 + using R+REG. R will go in an address reg and indexing will be used.
14062 + However, if REG is a broken-out memory address or multiplication,
14063 + nothing needs to be done because REG can certainly go in an address reg. */
14066 +m68k_legitimize_address (rtx x, rtx oldx, enum machine_mode mode)
14068 + if (m68k_tls_symbol_p (x))
14069 + return m68k_legitimize_tls_address (x);
14071 + if (GET_CODE (x) == PLUS)
14073 + int ch = (x) != (oldx);
14076 +#define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
14078 + if (GET_CODE (XEXP (x, 0)) == MULT)
14081 + XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
14083 + if (GET_CODE (XEXP (x, 1)) == MULT)
14086 + XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
14090 + if (GET_CODE (XEXP (x, 1)) == REG
14091 + && GET_CODE (XEXP (x, 0)) == REG)
14093 + if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
14096 + x = force_operand (x, 0);
14100 + if (memory_address_p (mode, x))
14103 + if (GET_CODE (XEXP (x, 0)) == REG
14104 + || (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
14105 + && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
14106 + && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode))
14108 + rtx temp = gen_reg_rtx (Pmode);
14109 + rtx val = force_operand (XEXP (x, 1), 0);
14110 + emit_move_insn (temp, val);
14112 + XEXP (x, 1) = temp;
14113 + if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
14114 + && GET_CODE (XEXP (x, 0)) == REG)
14115 + x = force_operand (x, 0);
14117 + else if (GET_CODE (XEXP (x, 1)) == REG
14118 + || (GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
14119 + && GET_CODE (XEXP (XEXP (x, 1), 0)) == REG
14120 + && GET_MODE (XEXP (XEXP (x, 1), 0)) == HImode))
14122 + rtx temp = gen_reg_rtx (Pmode);
14123 + rtx val = force_operand (XEXP (x, 0), 0);
14124 + emit_move_insn (temp, val);
14126 + XEXP (x, 0) = temp;
14127 + if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
14128 + && GET_CODE (XEXP (x, 1)) == REG)
14129 + x = force_operand (x, 0);
14137 /* Output a dbCC; jCC sequence. Note we do not handle the
14138 floating point version of this sequence (Fdbcc). We also
14139 do not handle alternative conditions when CC_NO_OVERFLOW is
14140 @@ -1713,15 +1803,16 @@ m68k_legitimate_base_reg_p (rtx x, bool
14141 whether we need strict checking. */
14144 -m68k_legitimate_index_reg_p (rtx x, bool strict_p)
14145 +m68k_legitimate_index_reg_p (enum machine_mode mode, rtx x, bool strict_p)
14147 if (!strict_p && GET_CODE (x) == SUBREG)
14148 x = SUBREG_REG (x);
14152 - ? REGNO_OK_FOR_INDEX_P (REGNO (x))
14153 - : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x))));
14154 + ? REGNO_MODE_OK_FOR_INDEX_P (REGNO (x), mode)
14155 + : (MODE_OK_FOR_INDEX_P (mode)
14156 + && REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x)))));
14159 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
14160 @@ -1729,7 +1820,8 @@ m68k_legitimate_index_reg_p (rtx x, bool
14161 ADDRESS if so. STRICT_P says whether we need strict checking. */
14164 -m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address)
14165 +m68k_decompose_index (enum machine_mode mode, rtx x, bool strict_p,
14166 + struct m68k_address *address)
14170 @@ -1753,7 +1845,7 @@ m68k_decompose_index (rtx x, bool strict
14171 && GET_MODE (XEXP (x, 0)) == HImode)
14174 - if (m68k_legitimate_index_reg_p (x, strict_p))
14175 + if (m68k_legitimate_index_reg_p (mode, x, strict_p))
14177 address->scale = scale;
14178 address->index = x;
14179 @@ -1777,7 +1869,7 @@ m68k_illegitimate_symbolic_constant_p (r
14180 && !offset_within_block_p (base, INTVAL (offset)))
14184 + return m68k_tls_reference_p (x, false);
14187 /* Return true if X is a legitimate constant address that can reach
14188 @@ -1805,7 +1897,7 @@ m68k_legitimate_constant_address_p (rtx
14193 + return !m68k_tls_reference_p (x, false);
14196 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
14197 @@ -1872,15 +1964,17 @@ m68k_decompose_address (enum machine_mod
14198 /* Check for GOT loads. These are (bd,An,Xn) addresses if
14199 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
14202 - && GET_CODE (x) == PLUS
14203 - && XEXP (x, 0) == pic_offset_table_rtx
14204 - && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF
14205 - || GET_CODE (XEXP (x, 1)) == LABEL_REF))
14206 + if (GET_CODE (x) == PLUS
14207 + && XEXP (x, 0) == pic_offset_table_rtx)
14209 - address->base = XEXP (x, 0);
14210 - address->offset = XEXP (x, 1);
14212 + /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
14213 + they are invalid in this context. */
14214 + if (m68k_unwrap_symbol (XEXP (x, 1), false) != XEXP (x, 1))
14216 + address->base = XEXP (x, 0);
14217 + address->offset = XEXP (x, 1);
14222 /* The ColdFire FPU only accepts addressing modes 2-5. */
14223 @@ -1905,7 +1999,7 @@ m68k_decompose_address (enum machine_mod
14224 accesses to unplaced labels in other cases. */
14225 if (GET_CODE (x) == PLUS
14226 && m68k_jump_table_ref_p (XEXP (x, 1))
14227 - && m68k_decompose_index (XEXP (x, 0), strict_p, address))
14228 + && m68k_decompose_index (mode, XEXP (x, 0), strict_p, address))
14230 address->offset = XEXP (x, 1);
14232 @@ -1937,7 +2031,7 @@ m68k_decompose_address (enum machine_mod
14234 if (address->offset
14235 && symbolic_operand (address->offset, VOIDmode)
14236 - && m68k_decompose_index (x, strict_p, address))
14237 + && m68k_decompose_index (mode, x, strict_p, address))
14241 @@ -1956,14 +2050,14 @@ m68k_decompose_address (enum machine_mod
14242 if (GET_CODE (x) == PLUS)
14244 if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)
14245 - && m68k_decompose_index (XEXP (x, 1), strict_p, address))
14246 + && m68k_decompose_index (mode, XEXP (x, 1), strict_p, address))
14248 address->base = XEXP (x, 0);
14252 if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p)
14253 - && m68k_decompose_index (XEXP (x, 0), strict_p, address))
14254 + && m68k_decompose_index (mode, XEXP (x, 0), strict_p, address))
14256 address->base = XEXP (x, 1);
14258 @@ -2025,6 +2119,243 @@ m68k_matches_u_p (rtx x)
14259 && !address.index);
14262 +/* Return GOT pointer. */
14265 +m68k_get_gp (void)
14267 + if (pic_offset_table_rtx == NULL_RTX)
14268 + pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_REG);
14270 + crtl->uses_pic_offset_table = 1;
14272 + return pic_offset_table_rtx;
14275 +/* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
14277 +enum m68k_reloc { RELOC_GOT, RELOC_TLSGD, RELOC_TLSLDM, RELOC_TLSLDO,
14278 + RELOC_TLSIE, RELOC_TLSLE };
14280 +#define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
14282 +/* Wrap symbol X into unspec representing relocation RELOC.
14283 + BASE_REG - register that should be added to the result.
14284 + TEMP_REG - if non-null, temporary register. */
14287 +m68k_wrap_symbol (rtx x, enum m68k_reloc reloc, rtx base_reg, rtx temp_reg)
14291 + use_x_p = (base_reg == pic_offset_table_rtx) ? TARGET_XGOT : TARGET_XTLS;
14293 + if (TARGET_COLDFIRE && use_x_p)
14294 + /* When compiling with -mx{got, tls} switch the code will look like this:
14296 + move.l <X>@<RELOC>,<TEMP_REG>
14297 + add.l <BASE_REG>,<TEMP_REG> */
14299 + /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
14300 + to put @RELOC after reference. */
14301 + x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)),
14303 + x = gen_rtx_CONST (Pmode, x);
14305 + if (temp_reg == NULL)
14307 + gcc_assert (can_create_pseudo_p ());
14308 + temp_reg = gen_reg_rtx (Pmode);
14311 + emit_move_insn (temp_reg, x);
14312 + emit_insn (gen_addsi3 (temp_reg, temp_reg, base_reg));
14317 + x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)),
14319 + x = gen_rtx_CONST (Pmode, x);
14321 + x = gen_rtx_PLUS (Pmode, base_reg, x);
14327 +/* Helper for m68k_unwrap_symbol.
14328 + Also, if unwrapping was successful (that is if (ORIG != <return value>)),
14329 + sets *RELOC_PTR to relocation type for the symbol. */
14332 +m68k_unwrap_symbol_1 (rtx orig, bool unwrap_reloc32_p,
14333 + enum m68k_reloc *reloc_ptr)
14335 + if (GET_CODE (orig) == CONST)
14338 + enum m68k_reloc dummy;
14340 + x = XEXP (orig, 0);
14342 + if (reloc_ptr == NULL)
14343 + reloc_ptr = &dummy;
14345 + /* Handle an addend. */
14346 + if ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS)
14347 + && CONST_INT_P (XEXP (x, 1)))
14350 + if (GET_CODE (x) == UNSPEC)
14352 + switch (XINT (x, 1))
14354 + case UNSPEC_RELOC16:
14355 + orig = XVECEXP (x, 0, 0);
14356 + *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1));
14359 + case UNSPEC_RELOC32:
14360 + if (unwrap_reloc32_p)
14362 + orig = XVECEXP (x, 0, 0);
14363 + *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1));
14376 +/* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
14377 + UNSPEC_RELOC32 wrappers. */
14380 +m68k_unwrap_symbol (rtx orig, bool unwrap_reloc32_p)
14382 + return m68k_unwrap_symbol_1 (orig, unwrap_reloc32_p, NULL);
14385 +/* Helper for m68k_final_prescan_insn. */
14388 +m68k_final_prescan_insn_1 (rtx *x_ptr, void *data ATTRIBUTE_UNUSED)
14392 + if (m68k_unwrap_symbol (x, true) != x)
14393 + /* For rationale of the below, see comment in m68k_final_prescan_insn. */
14397 + gcc_assert (GET_CODE (x) == CONST);
14398 + plus = XEXP (x, 0);
14400 + if (GET_CODE (plus) == PLUS || GET_CODE (plus) == MINUS)
14405 + unspec = XEXP (plus, 0);
14406 + gcc_assert (GET_CODE (unspec) == UNSPEC);
14407 + addend = XEXP (plus, 1);
14408 + gcc_assert (CONST_INT_P (addend));
14410 + /* We now have all the pieces, rearrange them. */
14412 + /* Move symbol to plus. */
14413 + XEXP (plus, 0) = XVECEXP (unspec, 0, 0);
14415 + /* Move plus inside unspec. */
14416 + XVECEXP (unspec, 0, 0) = plus;
14418 + /* Move unspec to top level of const. */
14419 + XEXP (x, 0) = unspec;
14428 +/* Prescan insn before outputing assembler for it. */
14431 +m68k_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED,
14432 + rtx *operands, int n_operands)
14436 + /* Combine and, possibly, other optimizations may do good job
14438 + (const (unspec [(symbol)]))
14440 + (const (plus (unspec [(symbol)])
14442 + The problem with this is emitting @TLS or @GOT decorations.
14443 + The decoration is emitted when processing (unspec), so the
14444 + result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
14446 + It seems that the easiest solution to this is to convert such
14448 + (const (unspec [(plus (symbol)
14449 + (const_int N))])).
14450 + Note, that the top level of operand remains intact, so we don't have
14451 + to patch up anything outside of the operand. */
14453 + for (i = 0; i < n_operands; ++i)
14457 + op = operands[i];
14459 + for_each_rtx (&op, m68k_final_prescan_insn_1, NULL);
14463 +/* Move X to a register and add REG_EQUAL note pointing to ORIG.
14464 + If REG is non-null, use it; generate new pseudo otherwise. */
14467 +m68k_move_to_reg (rtx x, rtx orig, rtx reg)
14471 + if (reg == NULL_RTX)
14473 + gcc_assert (can_create_pseudo_p ());
14474 + reg = gen_reg_rtx (Pmode);
14477 + insn = emit_move_insn (reg, x);
14478 + /* Put a REG_EQUAL note on this insn, so that it can be optimized
14480 + set_unique_reg_note (insn, REG_EQUAL, orig);
14485 +/* Does the same as m68k_wrap_symbol, but returns a memory reference to
14489 +m68k_wrap_symbol_into_got_ref (rtx x, enum m68k_reloc reloc, rtx temp_reg)
14491 + x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), temp_reg);
14493 + x = gen_rtx_MEM (Pmode, x);
14494 + MEM_READONLY_P (x) = 1;
14499 /* Legitimize PIC addresses. If the address is already
14500 position-independent, we return ORIG. Newly generated
14501 position-independent addresses go to REG. If we need more
14502 @@ -2076,42 +2407,15 @@ legitimize_pic_address (rtx orig, enum m
14506 - if (TARGET_COLDFIRE && TARGET_XGOT)
14507 - /* When compiling with -mxgot switch the code for the above
14508 - example will look like this:
14511 - addl _foo@GOT, a0
14513 - movel #12345, a0@ */
14517 - /* Wrap ORIG in UNSPEC_GOTOFF to tip m68k_output_addr_const_extra
14518 - to put @GOT after reference. */
14519 - pic_offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, orig),
14521 - pic_offset = gen_rtx_CONST (Pmode, pic_offset);
14522 - emit_move_insn (reg, pic_offset);
14523 - emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
14524 - pic_ref = gen_rtx_MEM (Pmode, reg);
14527 - pic_ref = gen_rtx_MEM (Pmode,
14528 - gen_rtx_PLUS (Pmode,
14529 - pic_offset_table_rtx, orig));
14530 - crtl->uses_pic_offset_table = 1;
14531 - MEM_READONLY_P (pic_ref) = 1;
14532 - emit_move_insn (reg, pic_ref);
14534 + pic_ref = m68k_wrap_symbol_into_got_ref (orig, RELOC_GOT, reg);
14535 + pic_ref = m68k_move_to_reg (pic_ref, orig, reg);
14537 else if (GET_CODE (orig) == CONST)
14541 /* Make sure this has not already been legitimized. */
14542 - if (GET_CODE (XEXP (orig, 0)) == PLUS
14543 - && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
14544 + if (m68k_unwrap_symbol (orig, true) != orig)
14548 @@ -2124,13 +2428,257 @@ legitimize_pic_address (rtx orig, enum m
14549 base == reg ? 0 : reg);
14551 if (GET_CODE (orig) == CONST_INT)
14552 - return plus_constant (base, INTVAL (orig));
14553 - pic_ref = gen_rtx_PLUS (Pmode, base, orig);
14554 - /* Likewise, should we set special REG_NOTEs here? */
14555 + pic_ref = plus_constant (base, INTVAL (orig));
14557 + pic_ref = gen_rtx_PLUS (Pmode, base, orig);
14563 +/* The __tls_get_addr symbol. */
14564 +static GTY(()) rtx m68k_tls_get_addr;
14566 +/* Return SYMBOL_REF for __tls_get_addr. */
14569 +m68k_get_tls_get_addr (void)
14571 + if (m68k_tls_get_addr == NULL_RTX)
14572 + m68k_tls_get_addr = init_one_libfunc ("__tls_get_addr");
14574 + return m68k_tls_get_addr;
14577 +/* Return libcall result in A0 instead of usual D0. */
14578 +static bool m68k_libcall_value_in_a0_p = false;
14580 +/* Emit instruction sequence that calls __tls_get_addr. X is
14581 + the TLS symbol we are referencing and RELOC is the symbol type to use
14582 + (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
14583 + emitted. A pseudo register with result of __tls_get_addr call is
14587 +m68k_call_tls_get_addr (rtx x, rtx eqv, enum m68k_reloc reloc)
14593 + /* Emit the call sequence. */
14594 + start_sequence ();
14596 + /* FIXME: Unfortunately, emit_library_call_value does not
14597 + consider (plus (%a5) (const (unspec))) to be a good enough
14598 + operand for push, so it forces it into a register. The bad
14599 + thing about this is that combiner, due to copy propagation and other
14600 + optimizations, sometimes can not later fix this. As a consequence,
14601 + additional register may be allocated resulting in a spill.
14602 + For reference, see args processing loops in
14603 + calls.c:emit_library_call_value_1.
14604 + For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
14605 + x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), NULL_RTX);
14607 + /* __tls_get_addr() is not a libcall, but emitting a libcall_value
14608 + is the simpliest way of generating a call. The difference between
14609 + __tls_get_addr() and libcall is that the result is returned in D0
14610 + instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
14611 + which temporarily switches returning the result to A0. */
14613 + m68k_libcall_value_in_a0_p = true;
14614 + a0 = emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX, LCT_PURE,
14615 + Pmode, 1, x, Pmode);
14616 + m68k_libcall_value_in_a0_p = false;
14618 + insns = get_insns ();
14621 + gcc_assert (can_create_pseudo_p ());
14622 + dest = gen_reg_rtx (Pmode);
14623 + emit_libcall_block (insns, dest, a0, eqv);
14628 +/* The __tls_get_addr symbol. */
14629 +static GTY(()) rtx m68k_read_tp;
14631 +/* Return SYMBOL_REF for __m68k_read_tp. */
14634 +m68k_get_m68k_read_tp (void)
14636 + if (m68k_read_tp == NULL_RTX)
14637 + m68k_read_tp = init_one_libfunc ("__m68k_read_tp");
14639 + return m68k_read_tp;
14642 +/* Emit instruction sequence that calls __m68k_read_tp.
14643 + A pseudo register with result of __m68k_read_tp call is returned. */
14646 +m68k_call_m68k_read_tp (void)
14653 + start_sequence ();
14655 + /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
14656 + is the simpliest way of generating a call. The difference between
14657 + __m68k_read_tp() and libcall is that the result is returned in D0
14658 + instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
14659 + which temporarily switches returning the result to A0. */
14661 + /* Emit the call sequence. */
14662 + m68k_libcall_value_in_a0_p = true;
14663 + a0 = emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX, LCT_PURE,
14665 + m68k_libcall_value_in_a0_p = false;
14666 + insns = get_insns ();
14669 + /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
14670 + share the m68k_read_tp result with other IE/LE model accesses. */
14671 + eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), UNSPEC_RELOC32);
14673 + gcc_assert (can_create_pseudo_p ());
14674 + dest = gen_reg_rtx (Pmode);
14675 + emit_libcall_block (insns, dest, a0, eqv);
14680 +/* Return a legitimized address for accessing TLS SYMBOL_REF X.
14681 + For explanations on instructions sequences see TLS/NPTL ABI for m68k and
14685 +m68k_legitimize_tls_address (rtx orig)
14687 + switch (SYMBOL_REF_TLS_MODEL (orig))
14689 + case TLS_MODEL_GLOBAL_DYNAMIC:
14690 + orig = m68k_call_tls_get_addr (orig, orig, RELOC_TLSGD);
14693 + case TLS_MODEL_LOCAL_DYNAMIC:
14699 + /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
14700 + share the LDM result with other LD model accesses. */
14701 + eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
14704 + a0 = m68k_call_tls_get_addr (orig, eqv, RELOC_TLSLDM);
14706 + x = m68k_wrap_symbol (orig, RELOC_TLSLDO, a0, NULL_RTX);
14708 + if (can_create_pseudo_p ())
14709 + x = m68k_move_to_reg (x, orig, NULL_RTX);
14715 + case TLS_MODEL_INITIAL_EXEC:
14720 + a0 = m68k_call_m68k_read_tp ();
14722 + x = m68k_wrap_symbol_into_got_ref (orig, RELOC_TLSIE, NULL_RTX);
14723 + x = gen_rtx_PLUS (Pmode, x, a0);
14725 + if (can_create_pseudo_p ())
14726 + x = m68k_move_to_reg (x, orig, NULL_RTX);
14732 + case TLS_MODEL_LOCAL_EXEC:
14737 + a0 = m68k_call_m68k_read_tp ();
14739 + x = m68k_wrap_symbol (orig, RELOC_TLSLE, a0, NULL_RTX);
14741 + if (can_create_pseudo_p ())
14742 + x = m68k_move_to_reg (x, orig, NULL_RTX);
14749 + gcc_unreachable ();
14755 +/* Return true if X is a TLS symbol. */
14758 +m68k_tls_symbol_p (rtx x)
14760 + if (!TARGET_HAVE_TLS)
14763 + if (GET_CODE (x) != SYMBOL_REF)
14766 + return SYMBOL_REF_TLS_MODEL (x) != 0;
14769 +/* Helper for m68k_tls_referenced_p. */
14772 +m68k_tls_reference_p_1 (rtx *x_ptr, void *data ATTRIBUTE_UNUSED)
14774 + /* Note: this is not the same as m68k_tls_symbol_p. */
14775 + if (GET_CODE (*x_ptr) == SYMBOL_REF)
14776 + return SYMBOL_REF_TLS_MODEL (*x_ptr) != 0 ? 1 : 0;
14778 + /* Don't recurse into legitimate TLS references. */
14779 + if (m68k_tls_reference_p (*x_ptr, true))
14785 +/* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
14786 + though illegitimate one.
14787 + If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
14790 +m68k_tls_reference_p (rtx x, bool legitimate_p)
14792 + if (!TARGET_HAVE_TLS)
14795 + if (!legitimate_p)
14796 + return for_each_rtx (&x, m68k_tls_reference_p_1, NULL) == 1 ? true : false;
14799 + enum m68k_reloc reloc = RELOC_GOT;
14801 + return (m68k_unwrap_symbol_1 (x, true, &reloc) != x
14802 + && TLS_RELOC_P (reloc));
14808 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
14809 @@ -3918,18 +4466,92 @@ print_operand (FILE *file, rtx op, int l
14813 +/* Return string for TLS relocation RELOC. */
14815 +static const char *
14816 +m68k_get_reloc_decoration (enum m68k_reloc reloc)
14818 + /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
14819 + gcc_assert (MOTOROLA || reloc == RELOC_GOT);
14826 + if (flag_pic == 1 && TARGET_68020)
14833 + if (TARGET_68020)
14835 + switch (flag_pic)
14847 + case RELOC_TLSGD:
14850 + case RELOC_TLSLDM:
14851 + return "@TLSLDM";
14853 + case RELOC_TLSLDO:
14854 + return "@TLSLDO";
14856 + case RELOC_TLSIE:
14859 + case RELOC_TLSLE:
14863 + gcc_unreachable ();
14867 /* m68k implementation of OUTPUT_ADDR_CONST_EXTRA. */
14870 m68k_output_addr_const_extra (FILE *file, rtx x)
14872 - if (GET_CODE (x) != UNSPEC || XINT (x, 1) != UNSPEC_GOTOFF)
14874 + if (GET_CODE (x) == UNSPEC)
14876 + switch (XINT (x, 1))
14878 + case UNSPEC_RELOC16:
14879 + case UNSPEC_RELOC32:
14880 + output_addr_const (file, XVECEXP (x, 0, 0));
14881 + fputs (m68k_get_reloc_decoration (INTVAL (XVECEXP (x, 0, 1))), file);
14884 - output_addr_const (file, XVECEXP (x, 0, 0));
14885 - /* ??? What is the non-MOTOROLA syntax? */
14886 - fputs ("@GOT", file);
14896 +/* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
14899 +m68k_output_dwarf_dtprel (FILE *file, int size, rtx x)
14901 + gcc_assert (size == 4);
14902 + fputs ("\t.long\t", file);
14903 + output_addr_const (file, x);
14904 + fputs ("@TLSLDO+0x8000", file);
14908 @@ -4019,15 +4641,8 @@ print_operand_address (FILE *file, rtx a
14911 if (address.offset)
14913 - output_addr_const (file, address.offset);
14914 - if (flag_pic && address.base == pic_offset_table_rtx)
14916 - fprintf (file, "@GOT");
14917 - if (flag_pic == 1 && TARGET_68020)
14918 - fprintf (file, ".w");
14921 + output_addr_const (file, address.offset);
14925 fputs (M68K_REGNAME (REGNO (address.base)), file);
14926 @@ -4060,19 +4675,7 @@ print_operand_address (FILE *file, rtx a
14927 fputs (M68K_REGNAME (REGNO (address.base)), file);
14928 fprintf (file, "@(");
14929 if (address.offset)
14931 - output_addr_const (file, address.offset);
14932 - if (address.base == pic_offset_table_rtx && TARGET_68020)
14933 - switch (flag_pic)
14936 - fprintf (file, ":w"); break;
14938 - fprintf (file, ":l"); break;
14943 + output_addr_const (file, address.offset);
14945 /* Print the ",index" component, if any. */
14947 @@ -4580,7 +5183,8 @@ m68k_libcall_value (enum machine_mode mo
14951 - return gen_rtx_REG (mode, D0_REG);
14953 + return gen_rtx_REG (mode, m68k_libcall_value_in_a0_p ? A0_REG : D0_REG);
14957 @@ -4846,9 +5450,8 @@ sched_attr_op_type (rtx insn, bool opx_p
14958 return OP_TYPE_IMM_L;
14961 - if (GET_CODE (op) == SYMBOL_REF)
14962 - /* ??? Just a guess. Probably we can guess better using length
14963 - attribute of the instructions. */
14964 + if (symbolic_operand (m68k_unwrap_symbol (op, false), VOIDmode))
14965 + /* Just a guess. */
14966 return OP_TYPE_IMM_W;
14968 return OP_TYPE_IMM_L;
14969 @@ -5793,3 +6396,5 @@ m68k_sched_indexed_address_bypass_p (rtx
14974 +#include "gt-m68k.h"
14975 --- a/gcc/config/m68k/m68k.h
14976 +++ b/gcc/config/m68k/m68k.h
14977 @@ -232,6 +232,7 @@ along with GCC; see the file COPYING3.
14978 #define FL_ISA_C (1 << 16)
14979 #define FL_FIDOA (1 << 17)
14980 #define FL_MMU 0 /* Used by multilib machinery. */
14981 +#define FL_UCLINUX 0 /* Used by multilib machinery. */
14983 #define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0)
14984 #define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0)
14985 @@ -501,7 +502,8 @@ enum reg_class {
14987 extern enum reg_class regno_reg_class[];
14988 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)])
14989 -#define INDEX_REG_CLASS GENERAL_REGS
14990 +#define MODE_INDEX_REG_CLASS(MODE) \
14991 + (MODE_OK_FOR_INDEX_P (MODE) ? GENERAL_REGS : NO_REGS)
14992 #define BASE_REG_CLASS ADDR_REGS
14994 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
14995 @@ -644,7 +646,7 @@ extern enum reg_class regno_reg_class[];
14996 (though the operand list is empty). */
14997 #define TRANSFER_FROM_TRAMPOLINE \
14999 -__transfer_from_trampoline () \
15000 +__transfer_from_trampoline (void) \
15002 register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME); \
15003 asm (GLOBAL_ASM_OP "___trampoline"); \
15004 @@ -675,6 +677,10 @@ __transfer_from_trampoline () \
15005 #define HAVE_POST_INCREMENT 1
15006 #define HAVE_PRE_DECREMENT 1
15008 +/* Return true if addresses of mode MODE can have an index register. */
15009 +#define MODE_OK_FOR_INDEX_P(MODE) \
15010 + (!TARGET_COLDFIRE_FPU || GET_MODE_CLASS (MODE) != MODE_FLOAT)
15012 /* Macros to check register numbers against specific register classes. */
15014 /* True for data registers, D0 through D7. */
15015 @@ -689,9 +695,10 @@ __transfer_from_trampoline () \
15016 /* True for floating point registers, FP0 through FP7. */
15017 #define FP_REGNO_P(REGNO) IN_RANGE (REGNO, 16, 23)
15019 -#define REGNO_OK_FOR_INDEX_P(REGNO) \
15020 - (INT_REGNO_P (REGNO) \
15021 - || INT_REGNO_P (reg_renumber[REGNO]))
15022 +#define REGNO_MODE_OK_FOR_INDEX_P(REGNO, MODE) \
15023 + (MODE_OK_FOR_INDEX_P (MODE) \
15024 + && (INT_REGNO_P (REGNO) \
15025 + || INT_REGNO_P (reg_renumber[REGNO])))
15027 #define REGNO_OK_FOR_BASE_P(REGNO) \
15028 (ADDRESS_REGNO_P (REGNO) \
15029 @@ -751,13 +758,14 @@ __transfer_from_trampoline () \
15031 #define LEGITIMATE_PIC_OPERAND_P(X) \
15032 (!symbolic_operand (X, VOIDmode) \
15033 - || (TARGET_PCREL && REG_STRICT_P))
15034 + || (TARGET_PCREL && REG_STRICT_P) \
15035 + || m68k_tls_reference_p (X, true))
15037 #define REG_OK_FOR_BASE_P(X) \
15038 m68k_legitimate_base_reg_p (X, REG_STRICT_P)
15040 -#define REG_OK_FOR_INDEX_P(X) \
15041 - m68k_legitimate_index_reg_p (X, REG_STRICT_P)
15042 +#define REG_MODE_OK_FOR_INDEX_P(X, MODE) \
15043 + m68k_legitimate_index_reg_p (MODE, X, REG_STRICT_P)
15045 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
15047 @@ -770,52 +778,19 @@ __transfer_from_trampoline () \
15048 /* This address is OK as it stands. */
15049 #define PIC_CASE_VECTOR_ADDRESS(index) index
15051 -/* For the 68000, we handle X+REG by loading X into a register R and
15052 - using R+REG. R will go in an address reg and indexing will be used.
15053 - However, if REG is a broken-out memory address or multiplication,
15054 - nothing needs to be done because REG can certainly go in an address reg. */
15055 -#define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
15056 -#define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
15057 -{ register int ch = (X) != (OLDX); \
15058 - if (GET_CODE (X) == PLUS) \
15059 - { int copied = 0; \
15060 - if (GET_CODE (XEXP (X, 0)) == MULT) \
15061 - { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
15062 - if (GET_CODE (XEXP (X, 1)) == MULT) \
15063 - { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
15064 - if (ch && GET_CODE (XEXP (X, 1)) == REG \
15065 - && GET_CODE (XEXP (X, 0)) == REG) \
15066 - { if (TARGET_COLDFIRE_FPU \
15067 - && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
15068 - { COPY_ONCE (X); X = force_operand (X, 0);} \
15070 - if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
15071 - if (GET_CODE (XEXP (X, 0)) == REG \
15072 - || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
15073 - && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
15074 - && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
15075 - { register rtx temp = gen_reg_rtx (Pmode); \
15076 - register rtx val = force_operand (XEXP (X, 1), 0); \
15077 - emit_move_insn (temp, val); \
15079 - XEXP (X, 1) = temp; \
15080 - if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
15081 - && GET_CODE (XEXP (X, 0)) == REG) \
15082 - X = force_operand (X, 0); \
15084 - else if (GET_CODE (XEXP (X, 1)) == REG \
15085 - || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
15086 - && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
15087 - && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
15088 - { register rtx temp = gen_reg_rtx (Pmode); \
15089 - register rtx val = force_operand (XEXP (X, 0), 0); \
15090 - emit_move_insn (temp, val); \
15092 - XEXP (X, 0) = temp; \
15093 - if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT \
15094 - && GET_CODE (XEXP (X, 1)) == REG) \
15095 - X = force_operand (X, 0); \
15097 +#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
15101 + __x = m68k_legitimize_address (X, OLDX, MODE); \
15102 + if (__x != NULL_RTX) \
15106 + if (memory_address_p (MODE, X)) \
15111 /* On the 68000, only predecrement and postincrement address depend thus
15112 (the amount of decrement or increment being the length of the operand).
15113 @@ -1028,6 +1003,9 @@ do { if (cc_prev_status.flags & CC_IN_68
15114 assemble_name ((FILE), (NAME)), \
15115 fprintf ((FILE), ",%u\n", (int)(ROUNDED)))
15117 +#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
15118 + m68k_final_prescan_insn (INSN, OPVEC, NOPERANDS)
15120 /* On the 68000, we use several CODE characters:
15121 '.' for dot needed in Motorola-style opcode names.
15122 '-' for an operand pushing on the stack:
15123 --- a/gcc/config/m68k/m68k.md
15124 +++ b/gcc/config/m68k/m68k.md
15125 @@ -116,7 +116,8 @@
15129 - (UNSPEC_GOTOFF 6)
15130 + (UNSPEC_RELOC16 6)
15131 + (UNSPEC_RELOC32 7)
15134 ;; UNSPEC_VOLATILE usage:
15135 @@ -414,7 +415,7 @@
15137 (define_insn "tst<mode>_cf"
15139 - (match_operand:FP 0 "general_operand" "f<FP:dreg><Q>U"))]
15140 + (match_operand:FP 0 "general_operand" "f<FP:dreg>m"))]
15141 "TARGET_COLDFIRE_FPU"
15143 cc_status.flags = CC_IN_68881;
15144 @@ -570,8 +571,8 @@
15146 (define_insn "*cmp<mode>_cf"
15148 - (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg><Q>U")
15149 - (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg><Q>U,f")))]
15150 + (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg>m")
15151 + (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg>m,f")))]
15152 "TARGET_COLDFIRE_FPU
15153 && (register_operand (operands[0], <MODE>mode)
15154 || register_operand (operands[1], <MODE>mode))"
15155 @@ -779,7 +780,41 @@
15157 rtx tmp, base, offset;
15159 - if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
15160 + /* Recognize the case where operand[1] is a reference to thread-local
15161 + data and load its address to a register. */
15162 + if (!TARGET_PCREL && m68k_tls_reference_p (operands[1], false))
15164 + rtx tmp = operands[1];
15165 + rtx addend = NULL;
15167 + if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
15169 + addend = XEXP (XEXP (tmp, 0), 1);
15170 + tmp = XEXP (XEXP (tmp, 0), 0);
15173 + gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
15174 + gcc_assert (SYMBOL_REF_TLS_MODEL (tmp) != 0);
15176 + tmp = m68k_legitimize_tls_address (tmp);
15180 + if (!REG_P (tmp))
15184 + reg = gen_reg_rtx (Pmode);
15185 + emit_move_insn (reg, tmp);
15189 + tmp = gen_rtx_PLUS (SImode, tmp, addend);
15192 + operands[1] = tmp;
15194 + else if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
15196 /* The source is an address which requires PIC relocation.
15197 Call legitimize_pic_address with the source, mode, and a relocation
15198 @@ -1070,10 +1105,8 @@
15199 ;; SFmode MEMs are restricted to modes 2-4 if TARGET_COLDFIRE_FPU.
15200 ;; The move instructions can handle all combinations.
15201 (define_insn "movsf_cf_hard"
15202 - [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>U, f, f,mr,f,r<Q>,f
15204 - (match_operand:SF 1 "general_operand" " f, r<Q>U,f,rm,F,F, m
15206 + [(set (match_operand:SF 0 "nonimmediate_operand" "=rm,f, f,rm,f,r<Q>,f,m")
15207 + (match_operand:SF 1 "general_operand" " f, rm,f,rm,F,F, m,f"))]
15208 "TARGET_COLDFIRE_FPU"
15210 if (which_alternative == 4 || which_alternative == 5) {
15211 @@ -1215,8 +1248,8 @@
15214 (define_insn "movdf_cf_hard"
15215 - [(set (match_operand:DF 0 "nonimmediate_operand" "=f, <Q>U,r,f,r,r,m,f")
15216 - (match_operand:DF 1 "general_operand" " f<Q>U,f, f,r,r,m,r,E"))]
15217 + [(set (match_operand:DF 0 "nonimmediate_operand" "=f, m,r,f,r,r,m,f")
15218 + (match_operand:DF 1 "general_operand" " fm,f,f,r,r,m,r,E"))]
15219 "TARGET_COLDFIRE_FPU"
15222 @@ -1857,7 +1890,7 @@
15223 (define_insn "extendsfdf2_cf"
15224 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f")
15226 - (match_operand:SF 1 "general_operand" "f,<Q>U")))]
15227 + (match_operand:SF 1 "general_operand" "f,m")))]
15228 "TARGET_COLDFIRE_FPU"
15230 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
15231 @@ -1897,9 +1930,9 @@
15234 (define_insn "truncdfsf2_cf"
15235 - [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d<Q>U")
15236 + [(set (match_operand:SF 0 "nonimmediate_operand" "=f,dm")
15238 - (match_operand:DF 1 "general_operand" "<Q>U,f")))]
15239 + (match_operand:DF 1 "general_operand" "m,f")))]
15240 "TARGET_COLDFIRE_FPU"
15243 @@ -2045,7 +2078,7 @@
15245 (define_insn "ftrunc<mode>2_cf"
15246 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
15247 - (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))]
15248 + (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
15249 "TARGET_COLDFIRE_FPU"
15251 if (FP_REG_P (operands[1]))
15252 @@ -2338,9 +2371,9 @@
15253 "* return output_addsi3 (operands);")
15255 (define_insn_and_split "*addsi3_5200"
15256 - [(set (match_operand:SI 0 "nonimmediate_operand" "=mr,mr,a,m,r, ?a, ?a,?a,?a")
15257 - (plus:SI (match_operand:SI 1 "general_operand" "%0, 0, 0,0,0, a, a, r, a")
15258 - (match_operand:SI 2 "general_src_operand" " I, L, J,d,mrKi,Cj, r, a, J")))]
15259 + [(set (match_operand:SI 0 "nonimmediate_operand" "=mr,mr,a, m,r, ?a, ?a,?a,?a")
15260 + (plus:SI (match_operand:SI 1 "general_operand" "%0, 0, 0, 0,0, a, a, r, a")
15261 + (match_operand:SI 2 "general_src_operand" " I, L, JCu,d,mrKi,Cj, r, a, JCu")))]
15264 switch (which_alternative)
15265 @@ -2382,9 +2415,9 @@
15266 (plus:SI (match_dup 0)
15269 - [(set_attr "type" "aluq_l,aluq_l,lea,alu_l,alu_l,*,lea,lea,lea")
15270 - (set_attr "opy" "2,2,*,2,2,*,*,*,*")
15271 - (set_attr "opy_type" "*,*,mem5,*,*,*,mem6,mem6,mem5")])
15272 + [(set_attr "type" "aluq_l,aluq_l,lea, alu_l,alu_l,*,lea, lea, lea")
15273 + (set_attr "opy" "2, 2, *, 2, 2, *,*, *, *")
15274 + (set_attr "opy_type" "*, *, mem5,*, *, *,mem6,mem6,mem5")])
15277 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
15278 @@ -2666,7 +2699,7 @@
15279 (define_insn "add<mode>3_cf"
15280 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
15281 (plus:FP (match_operand:FP 1 "general_operand" "%0")
15282 - (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))]
15283 + (match_operand:FP 2 "general_operand" "f<FP:dreg>m")))]
15284 "TARGET_COLDFIRE_FPU"
15286 if (FP_REG_P (operands[2]))
15287 @@ -2889,7 +2922,7 @@
15288 (define_insn "sub<mode>3_cf"
15289 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
15290 (minus:FP (match_operand:FP 1 "general_operand" "0")
15291 - (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))]
15292 + (match_operand:FP 2 "general_operand" "f<FP:dreg>m")))]
15293 "TARGET_COLDFIRE_FPU"
15295 if (FP_REG_P (operands[2]))
15296 @@ -3245,7 +3278,7 @@
15297 (define_insn "fmul<mode>3_cf"
15298 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
15299 (mult:FP (match_operand:FP 1 "general_operand" "%0")
15300 - (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))]
15301 + (match_operand:FP 2 "general_operand" "fm<FP:dreg>")))]
15302 "TARGET_COLDFIRE_FPU"
15304 if (FP_REG_P (operands[2]))
15305 @@ -3315,7 +3348,7 @@
15306 (define_insn "div<mode>3_cf"
15307 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
15308 (div:FP (match_operand:FP 1 "general_operand" "0")
15309 - (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))]
15310 + (match_operand:FP 2 "general_operand" "fm<FP:dreg>")))]
15311 "TARGET_COLDFIRE_FPU"
15313 if (FP_REG_P (operands[2]))
15314 @@ -4163,7 +4196,7 @@
15316 (define_insn "neg<mode>2_cf"
15317 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
15318 - (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))]
15319 + (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m,0")))]
15320 "TARGET_COLDFIRE_FPU"
15322 if (DATA_REG_P (operands[0]))
15323 @@ -4197,7 +4230,7 @@
15325 (define_insn "sqrt<mode>2_cf"
15326 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
15327 - (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))]
15328 + (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
15329 "TARGET_COLDFIRE_FPU"
15331 if (FP_REG_P (operands[1]))
15332 @@ -4316,7 +4349,7 @@
15334 (define_insn "abs<mode>2_cf"
15335 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
15336 - (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))]
15337 + (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m,0")))]
15338 "TARGET_COLDFIRE_FPU"
15340 if (DATA_REG_P (operands[0]))
15341 --- a/gcc/config/m68k/m68k.opt
15342 +++ b/gcc/config/m68k/m68k.opt
15343 @@ -182,3 +182,7 @@ Tune for the specified target CPU or arc
15345 Target Report Mask(XGOT)
15346 Support more than 8192 GOT entries on ColdFire
15349 +Target Report Mask(XTLS)
15350 +Support TLS segment larger than 64K
15351 --- a/gcc/config/m68k/predicates.md
15352 +++ b/gcc/config/m68k/predicates.md
15353 @@ -130,7 +130,9 @@
15354 (match_code "sign_extend,zero_extend"))
15356 ;; Returns true if OP is either a symbol reference or a sum of a
15357 -;; symbol reference and a constant.
15358 +;; symbol reference and a constant. This predicate is for "raw"
15359 +;; symbol references not yet processed by legitimize*_address,
15360 +;; hence we do not handle UNSPEC_{XGOT, TLS, XTLS} here.
15362 (define_predicate "symbolic_operand"
15363 (match_code "symbol_ref,label_ref,const")
15364 --- a/gcc/config/m68k/t-uclinux
15365 +++ b/gcc/config/m68k/t-uclinux
15367 # crti and crtn are provided by uClibc.
15368 EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o
15370 -# Only include multilibs for the 68020 and for CPUs without an MMU.
15371 -M68K_MLIB_CPU += && (MLIB == "68020" || !match(FLAGS, "FL_MMU"))
15372 +# Include multilibs for CPUs without an MMU or with FL_UCLINUX
15373 +M68K_MLIB_CPU += && (!match(FLAGS, "FL_MMU") || match(FLAGS, "FL_UCLINUX"))
15375 # Add multilibs for execute-in-place and shared-library code.
15376 M68K_MLIB_OPTIONS += msep-data/mid-shared-library
15377 --- a/gcc/config/mips/74k.md
15378 +++ b/gcc/config/mips/74k.md
15379 @@ -118,8 +118,7 @@
15381 (define_insn_reservation "r74k_int_store" 1
15382 (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
15383 - (and (eq_attr "type" "store")
15384 - (eq_attr "mode" "!unknown")))
15385 + (eq_attr "type" "store"))
15389 @@ -145,33 +144,123 @@
15390 ;; load->load base: 4 cycles
15391 ;; load->store base: 4 cycles
15392 (define_bypass 4 "r74k_int_load" "r74k_int_load")
15393 -(define_bypass 4 "r74k_int_load" "r74k_int_store" "!store_data_bypass_p")
15394 +(define_bypass 4 "r74k_int_load" "r74k_int_store" "!mips_store_data_bypass_p")
15396 ;; logical/move/slt/signext->next use : 1 cycles (Default)
15397 ;; logical/move/slt/signext->load base: 2 cycles
15398 ;; logical/move/slt/signext->store base: 2 cycles
15399 (define_bypass 2 "r74k_int_logical" "r74k_int_load")
15400 -(define_bypass 2 "r74k_int_logical" "r74k_int_store" "!store_data_bypass_p")
15401 +(define_bypass 2 "r74k_int_logical" "r74k_int_store"
15402 + "!mips_store_data_bypass_p")
15404 ;; arith->next use : 2 cycles (Default)
15405 ;; arith->load base: 3 cycles
15406 ;; arith->store base: 3 cycles
15407 (define_bypass 3 "r74k_int_arith" "r74k_int_load")
15408 -(define_bypass 3 "r74k_int_arith" "r74k_int_store" "!store_data_bypass_p")
15409 +(define_bypass 3 "r74k_int_arith" "r74k_int_store" "!mips_store_data_bypass_p")
15411 ;; cmove->next use : 4 cycles (Default)
15412 ;; cmove->load base: 5 cycles
15413 ;; cmove->store base: 5 cycles
15414 (define_bypass 5 "r74k_int_cmove" "r74k_int_load")
15415 -(define_bypass 5 "r74k_int_cmove" "r74k_int_store" "!store_data_bypass_p")
15416 +(define_bypass 5 "r74k_int_cmove" "r74k_int_store"
15417 + "!mips_store_data_bypass_p")
15419 ;; mult/madd/msub->int_mfhilo : 4 cycles (default)
15420 ;; mult->madd/msub : 1 cycles
15421 ;; madd/msub->madd/msub : 1 cycles
15422 -(define_bypass 1 "r74k_int_mult,r74k_int_mul3" "r74k_int_madd"
15423 - "mips_linked_madd_p")
15424 -(define_bypass 1 "r74k_int_madd" "r74k_int_madd"
15425 - "mips_linked_madd_p")
15426 +(define_bypass 1 "r74k_int_mult" "r74k_int_madd")
15427 +(define_bypass 1 "r74k_int_madd" "r74k_int_madd")
15429 +(define_bypass 1 "r74k_int_mul3" "r74k_int_madd"
15430 + "mips_mult_madd_chain_bypass_p")
15433 +;; --------------------------------------------------------------
15434 +;; DSP instructins
15435 +;; --------------------------------------------------------------
15437 +;; Non-saturating insn have the same latency as normal ALU operations,
15438 +(define_insn_reservation "r74k_dsp_alu" 2
15439 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
15440 + (eq_attr "type" "dspalu"))
15443 +;; Saturating insn takes an extra cycle.
15444 +(define_insn_reservation "r74k_dsp_alu_sat" 3
15445 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
15446 + (eq_attr "type" "dspalusat"))
15449 +;; dpaq_s, dpau, dpsq_s, dpsu, maq_s, mulsaq
15450 +;; - delivers result to hi/lo in 6 cycle (bypass at M4)
15451 +(define_insn_reservation "r74k_dsp_mac" 6
15452 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
15453 + (eq_attr "type" "dspmac"))
15454 + "r74k_alu+r74k_mul")
15456 +;; dpaq_sa, dpsq_sa, maq_sa
15457 +;; - delivers result to hi/lo in 7 cycle (bypass at WB)
15458 +(define_insn_reservation "r74k_dsp_mac_sat" 7
15459 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
15460 + (eq_attr "type" "dspmacsat"))
15461 + "r74k_alu+r74k_mul")
15463 +;; extp, extpdp, extpdpv, extpv, extr, extrv
15464 +;; - same latency as "mul"
15465 +(define_insn_reservation "r74k_dsp_acc_ext" 7
15466 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
15467 + (eq_attr "type" "accext"))
15468 + "r74k_alu+r74k_mul")
15470 +;; mthlip, shilo, shilov
15471 +;; - same latency as "mul"
15472 +(define_insn_reservation "r74k_dsp_acc_mod" 7
15473 + (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
15474 + (eq_attr "type" "accmod"))
15475 + "r74k_alu+r74k_mul")
15477 +;; dspalu ->load/store base
15478 +;; dspalusat->load/store base
15479 +;; - we should never see these in real life.
15481 +;; dsp_mac->dsp_mac : 1 cycles (repeat rate of 1)
15482 +;; dsp_mac->dsp_mac_sat : 1 cycles (repeat rate of 1)
15483 +(define_bypass 1 "r74k_dsp_mac" "r74k_dsp_mac")
15484 +(define_bypass 1 "r74k_dsp_mac" "r74k_dsp_mac_sat")
15486 +;; dsp_mac_sat->dsp_mac_sat : 2 cycles (repeat rate of 2)
15487 +;; dsp_mac_sat->dsp_mac : 2 cycles (repeat rate of 2)
15488 +(define_bypass 2 "r74k_dsp_mac_sat" "r74k_dsp_mac_sat")
15489 +(define_bypass 2 "r74k_dsp_mac_sat" "r74k_dsp_mac")
15491 +(define_bypass 1 "r74k_int_mult" "r74k_dsp_mac")
15492 +(define_bypass 1 "r74k_int_mult" "r74k_dsp_mac_sat")
15494 +;; Before reload, all multiplier is registered as imul3 (which has a long
15495 +;; latency). We temporary jig the latency such that the macc groups
15496 +;; are scheduled closely together during the first scheduler pass.
15497 +(define_bypass 1 "r74k_int_mul3" "r74k_dsp_mac"
15498 + "mips_mult_madd_chain_bypass_p")
15499 +(define_bypass 1 "r74k_int_mul3" "r74k_dsp_mac_sat"
15500 + "mips_mult_madd_chain_bypass_p")
15502 +;; Assuming the following is true (bypass at M4)
15503 +;; AP AF AM MB M1 M2 M3 M4 WB GR GC
15504 +;; AP AF AM MB M1 M2 M3 M4 WB GR GC
15505 +;; dsp_mac->dsp_acc_ext : 4 cycles
15506 +;; dsp_mac->dsp_acc_mod : 4 cycles
15507 +(define_bypass 4 "r74k_dsp_mac" "r74k_dsp_acc_ext")
15508 +(define_bypass 4 "r74k_dsp_mac" "r74k_dsp_acc_mod")
15510 +;; Assuming the following is true (bypass at WB)
15511 +;; AP AF AM MB M1 M2 M3 M4 WB GR GC
15512 +;; AP AF AM MB M1 M2 M3 M4 WB GR GC
15513 +;; dsp_mac_sat->dsp_acc_ext : 5 cycles
15514 +;; dsp_mac_sat->dsp_acc_mod : 5 cycles
15515 +(define_bypass 5 "r74k_dsp_mac_sat" "r74k_dsp_acc_ext")
15516 +(define_bypass 5 "r74k_dsp_mac_sat" "r74k_dsp_acc_mod")
15519 ;; --------------------------------------------------------------
15520 ;; Floating Point Instructions
15522 +++ b/gcc/config/mips/crtfastmath.c
15524 +/* Copyright (C) 2008, 2009 Free Software Foundation, Inc.
15526 + This file is part of GCC.
15528 + GCC is free software; you can redistribute it and/or modify it
15529 + under the terms of the GNU General Public License as published by
15530 + the Free Software Foundation; either version 3, or (at your option)
15531 + any later version.
15533 + GCC is distributed in the hope that it will be useful, but WITHOUT
15534 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15535 + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15536 + License for more details.
15538 + Under Section 7 of GPL version 3, you are granted additional
15539 + permissions described in the GCC Runtime Library Exception, version
15540 + 3.1, as published by the Free Software Foundation.
15542 + You should have received a copy of the GNU General Public License
15543 + and a copy of the GCC Runtime Library Exception along with this
15544 + program; see the files COPYING3 and COPYING.RUNTIME respectively.
15545 + If not, see <http://www.gnu.org/licenses/>. */
15547 +#ifdef __mips_hard_float
15549 +/* flush denormalized numbers to zero */
15550 +#define _FPU_FLUSH_TZ 0x1000000
15552 +/* rounding control */
15553 +#define _FPU_RC_NEAREST 0x0 /* RECOMMENDED */
15554 +#define _FPU_RC_ZERO 0x1
15555 +#define _FPU_RC_UP 0x2
15556 +#define _FPU_RC_DOWN 0x3
15558 +/* enable interrupts for IEEE exceptions */
15559 +#define _FPU_IEEE 0x00000F80
15561 +/* Macros for accessing the hardware control word. */
15562 +#define _FPU_GETCW(cw) __asm__ ("cfc1 %0,$31" : "=r" (cw))
15563 +#define _FPU_SETCW(cw) __asm__ ("ctc1 %0,$31" : : "r" (cw))
15565 +static void __attribute__((constructor))
15566 +set_fast_math (void)
15568 + unsigned int fcr;
15570 + /* fastmath: flush to zero, round to nearest, ieee exceptions disabled */
15571 + fcr = _FPU_FLUSH_TZ | _FPU_RC_NEAREST;
15576 +#endif /* __mips_hard_float */
15577 --- a/gcc/config/mips/linux.h
15578 +++ b/gcc/config/mips/linux.h
15579 @@ -147,3 +147,17 @@ extern const char *host_detect_local_cpu
15580 #define DRIVER_SELF_SPECS \
15581 BASE_DRIVER_SELF_SPECS, \
15582 LINUX_DRIVER_SELF_SPECS
15584 +/* Similar to standard Linux, but adding -ffast-math support. */
15585 +#undef ENDFILE_SPEC
15586 +#define ENDFILE_SPEC \
15587 + "%{ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \
15588 + %{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
15590 +#undef SUBTARGET_OVERRIDE_OPTIONS
15591 +#define SUBTARGET_OVERRIDE_OPTIONS \
15593 + /* __thread_support is not supported by uClibc. */ \
15594 + if (linux_uclibc) \
15595 + targetm.have_tls = 0; \
15597 --- a/gcc/config/mips/linux64.h
15598 +++ b/gcc/config/mips/linux64.h
15599 @@ -69,3 +69,9 @@ along with GCC; see the file COPYING3.
15600 ieee_quad_format is the default, but let's put this here to make
15601 sure nobody thinks we just forgot to set it to something else. */
15602 #define MIPS_TFMODE_FORMAT mips_quad_format
15604 +/* Similar to standard Linux, but adding -ffast-math support. */
15605 +#undef ENDFILE_SPEC
15606 +#define ENDFILE_SPEC \
15607 + "%{ffast-math|funsafe-math-optimizations:crtfastmath.o%s} \
15608 + %{shared|pie:crtendS.o%s;:crtend.o%s} crtn.o%s"
15609 --- a/gcc/config/mips/mips-dsp.md
15610 +++ b/gcc/config/mips/mips-dsp.md
15612 (match_operand:DSPV 2 "register_operand" "d")))
15613 (set (reg:CCDSP CCDSP_OU_REGNUM)
15614 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))])]
15617 "add<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
15618 - [(set_attr "type" "arith")
15619 + [(set_attr "type" "dspalu")
15620 (set_attr "mode" "SI")])
15622 (define_insn "mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>"
15625 (set (reg:CCDSP CCDSP_OU_REGNUM)
15626 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])]
15629 "add<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
15630 - [(set_attr "type" "arith")
15631 + [(set_attr "type" "dspalusat")
15632 (set_attr "mode" "SI")])
15636 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])]
15638 "sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2"
15639 - [(set_attr "type" "arith")
15640 + [(set_attr "type" "dspalu")
15641 (set_attr "mode" "SI")])
15643 (define_insn "mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>"
15645 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])]
15647 "sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2"
15648 - [(set_attr "type" "arith")
15649 + [(set_attr "type" "dspalusat")
15650 (set_attr "mode" "SI")])
15654 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])]
15657 - [(set_attr "type" "arith")
15658 + [(set_attr "type" "dspalu")
15659 (set_attr "mode" "SI")])
15662 @@ -112,7 +112,7 @@
15663 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])]
15666 - [(set_attr "type" "arith")
15667 + [(set_attr "type" "dspalu")
15668 (set_attr "mode" "SI")])
15671 @@ -123,7 +123,7 @@
15675 - [(set_attr "type" "arith")
15676 + [(set_attr "type" "dspalu")
15677 (set_attr "mode" "SI")])
15680 @@ -133,7 +133,7 @@
15681 UNSPEC_RADDU_W_QB))]
15683 "raddu.w.qb\t%0,%1"
15684 - [(set_attr "type" "arith")
15685 + [(set_attr "type" "dspalu")
15686 (set_attr "mode" "SI")])
15689 @@ -146,7 +146,7 @@
15690 (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])]
15692 "absq_s.<DSPQ:dspfmt2>\t%0,%1"
15693 - [(set_attr "type" "arith")
15694 + [(set_attr "type" "dspalusat")
15695 (set_attr "mode" "SI")])
15698 @@ -157,7 +157,7 @@
15699 UNSPEC_PRECRQ_QB_PH))]
15701 "precrq.qb.ph\t%0,%1,%2"
15702 - [(set_attr "type" "arith")
15703 + [(set_attr "type" "dspalu")
15704 (set_attr "mode" "SI")])
15706 (define_insn "mips_precrq_ph_w"
15707 @@ -167,7 +167,7 @@
15708 UNSPEC_PRECRQ_PH_W))]
15710 "precrq.ph.w\t%0,%1,%2"
15711 - [(set_attr "type" "arith")
15712 + [(set_attr "type" "dspalu")
15713 (set_attr "mode" "SI")])
15715 (define_insn "mips_precrq_rs_ph_w"
15716 @@ -181,7 +181,7 @@
15717 UNSPEC_PRECRQ_RS_PH_W))])]
15719 "precrq_rs.ph.w\t%0,%1,%2"
15720 - [(set_attr "type" "arith")
15721 + [(set_attr "type" "dspalu")
15722 (set_attr "mode" "SI")])
15725 @@ -196,7 +196,7 @@
15726 UNSPEC_PRECRQU_S_QB_PH))])]
15728 "precrqu_s.qb.ph\t%0,%1,%2"
15729 - [(set_attr "type" "arith")
15730 + [(set_attr "type" "dspalusat")
15731 (set_attr "mode" "SI")])
15734 @@ -206,7 +206,7 @@
15735 UNSPEC_PRECEQ_W_PHL))]
15737 "preceq.w.phl\t%0,%1"
15738 - [(set_attr "type" "arith")
15739 + [(set_attr "type" "dspalu")
15740 (set_attr "mode" "SI")])
15742 (define_insn "mips_preceq_w_phr"
15743 @@ -215,7 +215,7 @@
15744 UNSPEC_PRECEQ_W_PHR))]
15746 "preceq.w.phr\t%0,%1"
15747 - [(set_attr "type" "arith")
15748 + [(set_attr "type" "dspalu")
15749 (set_attr "mode" "SI")])
15752 @@ -225,7 +225,7 @@
15753 UNSPEC_PRECEQU_PH_QBL))]
15755 "precequ.ph.qbl\t%0,%1"
15756 - [(set_attr "type" "arith")
15757 + [(set_attr "type" "dspalu")
15758 (set_attr "mode" "SI")])
15760 (define_insn "mips_precequ_ph_qbr"
15761 @@ -234,7 +234,7 @@
15762 UNSPEC_PRECEQU_PH_QBR))]
15764 "precequ.ph.qbr\t%0,%1"
15765 - [(set_attr "type" "arith")
15766 + [(set_attr "type" "dspalu")
15767 (set_attr "mode" "SI")])
15769 (define_insn "mips_precequ_ph_qbla"
15770 @@ -243,7 +243,7 @@
15771 UNSPEC_PRECEQU_PH_QBLA))]
15773 "precequ.ph.qbla\t%0,%1"
15774 - [(set_attr "type" "arith")
15775 + [(set_attr "type" "dspalu")
15776 (set_attr "mode" "SI")])
15778 (define_insn "mips_precequ_ph_qbra"
15779 @@ -252,7 +252,7 @@
15780 UNSPEC_PRECEQU_PH_QBRA))]
15782 "precequ.ph.qbra\t%0,%1"
15783 - [(set_attr "type" "arith")
15784 + [(set_attr "type" "dspalu")
15785 (set_attr "mode" "SI")])
15788 @@ -262,7 +262,7 @@
15789 UNSPEC_PRECEU_PH_QBL))]
15791 "preceu.ph.qbl\t%0,%1"
15792 - [(set_attr "type" "arith")
15793 + [(set_attr "type" "dspalu")
15794 (set_attr "mode" "SI")])
15796 (define_insn "mips_preceu_ph_qbr"
15797 @@ -271,7 +271,7 @@
15798 UNSPEC_PRECEU_PH_QBR))]
15800 "preceu.ph.qbr\t%0,%1"
15801 - [(set_attr "type" "arith")
15802 + [(set_attr "type" "dspalu")
15803 (set_attr "mode" "SI")])
15805 (define_insn "mips_preceu_ph_qbla"
15806 @@ -280,7 +280,7 @@
15807 UNSPEC_PRECEU_PH_QBLA))]
15809 "preceu.ph.qbla\t%0,%1"
15810 - [(set_attr "type" "arith")
15811 + [(set_attr "type" "dspalu")
15812 (set_attr "mode" "SI")])
15814 (define_insn "mips_preceu_ph_qbra"
15815 @@ -289,7 +289,7 @@
15816 UNSPEC_PRECEU_PH_QBRA))]
15818 "preceu.ph.qbra\t%0,%1"
15819 - [(set_attr "type" "arith")
15820 + [(set_attr "type" "dspalu")
15821 (set_attr "mode" "SI")])
15823 ;; Table 2-2. MIPS DSP ASE Instructions: Shift
15824 @@ -313,7 +313,7 @@
15826 return "shllv.<DSPV:dspfmt2>\t%0,%1,%2";
15828 - [(set_attr "type" "shift")
15829 + [(set_attr "type" "dspalu")
15830 (set_attr "mode" "SI")])
15832 (define_insn "mips_shll_s_<DSPQ:dspfmt2>"
15833 @@ -335,7 +335,7 @@
15835 return "shllv_s.<DSPQ:dspfmt2>\t%0,%1,%2";
15837 - [(set_attr "type" "shift")
15838 + [(set_attr "type" "dspalusat")
15839 (set_attr "mode" "SI")])
15842 @@ -354,7 +354,7 @@
15844 return "shrlv.qb\t%0,%1,%2";
15846 - [(set_attr "type" "shift")
15847 + [(set_attr "type" "dspalu")
15848 (set_attr "mode" "SI")])
15851 @@ -373,7 +373,7 @@
15853 return "shrav.ph\t%0,%1,%2";
15855 - [(set_attr "type" "shift")
15856 + [(set_attr "type" "dspalu")
15857 (set_attr "mode" "SI")])
15859 (define_insn "mips_shra_r_<DSPQ:dspfmt2>"
15860 @@ -392,7 +392,7 @@
15862 return "shrav_r.<DSPQ:dspfmt2>\t%0,%1,%2";
15864 - [(set_attr "type" "shift")
15865 + [(set_attr "type" "dspalu")
15866 (set_attr "mode" "SI")])
15868 ;; Table 2-3. MIPS DSP ASE Instructions: Multiply
15869 @@ -478,7 +478,7 @@
15870 UNSPEC_DPAU_H_QBL))]
15871 "ISA_HAS_DSP && !TARGET_64BIT"
15872 "dpau.h.qbl\t%q0,%2,%3"
15873 - [(set_attr "type" "imadd")
15874 + [(set_attr "type" "dspmac")
15875 (set_attr "mode" "SI")])
15877 (define_insn "mips_dpau_h_qbr"
15878 @@ -489,7 +489,7 @@
15879 UNSPEC_DPAU_H_QBR))]
15880 "ISA_HAS_DSP && !TARGET_64BIT"
15881 "dpau.h.qbr\t%q0,%2,%3"
15882 - [(set_attr "type" "imadd")
15883 + [(set_attr "type" "dspmac")
15884 (set_attr "mode" "SI")])
15887 @@ -501,7 +501,7 @@
15888 UNSPEC_DPSU_H_QBL))]
15889 "ISA_HAS_DSP && !TARGET_64BIT"
15890 "dpsu.h.qbl\t%q0,%2,%3"
15891 - [(set_attr "type" "imadd")
15892 + [(set_attr "type" "dspmac")
15893 (set_attr "mode" "SI")])
15895 (define_insn "mips_dpsu_h_qbr"
15896 @@ -512,7 +512,7 @@
15897 UNSPEC_DPSU_H_QBR))]
15898 "ISA_HAS_DSP && !TARGET_64BIT"
15899 "dpsu.h.qbr\t%q0,%2,%3"
15900 - [(set_attr "type" "imadd")
15901 + [(set_attr "type" "dspmac")
15902 (set_attr "mode" "SI")])
15905 @@ -528,7 +528,7 @@
15906 UNSPEC_DPAQ_S_W_PH))])]
15907 "ISA_HAS_DSP && !TARGET_64BIT"
15908 "dpaq_s.w.ph\t%q0,%2,%3"
15909 - [(set_attr "type" "imadd")
15910 + [(set_attr "type" "dspmac")
15911 (set_attr "mode" "SI")])
15914 @@ -544,7 +544,7 @@
15915 UNSPEC_DPSQ_S_W_PH))])]
15916 "ISA_HAS_DSP && !TARGET_64BIT"
15917 "dpsq_s.w.ph\t%q0,%2,%3"
15918 - [(set_attr "type" "imadd")
15919 + [(set_attr "type" "dspmac")
15920 (set_attr "mode" "SI")])
15923 @@ -560,7 +560,7 @@
15924 UNSPEC_MULSAQ_S_W_PH))])]
15925 "ISA_HAS_DSP && !TARGET_64BIT"
15926 "mulsaq_s.w.ph\t%q0,%2,%3"
15927 - [(set_attr "type" "imadd")
15928 + [(set_attr "type" "dspmac")
15929 (set_attr "mode" "SI")])
15932 @@ -576,7 +576,7 @@
15933 UNSPEC_DPAQ_SA_L_W))])]
15934 "ISA_HAS_DSP && !TARGET_64BIT"
15935 "dpaq_sa.l.w\t%q0,%2,%3"
15936 - [(set_attr "type" "imadd")
15937 + [(set_attr "type" "dspmacsat")
15938 (set_attr "mode" "SI")])
15941 @@ -592,7 +592,7 @@
15942 UNSPEC_DPSQ_SA_L_W))])]
15943 "ISA_HAS_DSP && !TARGET_64BIT"
15944 "dpsq_sa.l.w\t%q0,%2,%3"
15945 - [(set_attr "type" "imadd")
15946 + [(set_attr "type" "dspmacsat")
15947 (set_attr "mode" "SI")])
15950 @@ -608,7 +608,7 @@
15951 UNSPEC_MAQ_S_W_PHL))])]
15952 "ISA_HAS_DSP && !TARGET_64BIT"
15953 "maq_s.w.phl\t%q0,%2,%3"
15954 - [(set_attr "type" "imadd")
15955 + [(set_attr "type" "dspmac")
15956 (set_attr "mode" "SI")])
15958 (define_insn "mips_maq_s_w_phr"
15959 @@ -623,7 +623,7 @@
15960 UNSPEC_MAQ_S_W_PHR))])]
15961 "ISA_HAS_DSP && !TARGET_64BIT"
15962 "maq_s.w.phr\t%q0,%2,%3"
15963 - [(set_attr "type" "imadd")
15964 + [(set_attr "type" "dspmac")
15965 (set_attr "mode" "SI")])
15968 @@ -639,7 +639,7 @@
15969 UNSPEC_MAQ_SA_W_PHL))])]
15970 "ISA_HAS_DSP && !TARGET_64BIT"
15971 "maq_sa.w.phl\t%q0,%2,%3"
15972 - [(set_attr "type" "imadd")
15973 + [(set_attr "type" "dspmacsat")
15974 (set_attr "mode" "SI")])
15976 (define_insn "mips_maq_sa_w_phr"
15977 @@ -654,7 +654,7 @@
15978 UNSPEC_MAQ_SA_W_PHR))])]
15979 "ISA_HAS_DSP && !TARGET_64BIT"
15980 "maq_sa.w.phr\t%q0,%2,%3"
15981 - [(set_attr "type" "imadd")
15982 + [(set_attr "type" "dspmacsat")
15983 (set_attr "mode" "SI")])
15985 ;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation
15986 @@ -665,7 +665,7 @@
15990 - [(set_attr "type" "arith")
15991 + [(set_attr "type" "dspalu")
15992 (set_attr "mode" "SI")])
15995 @@ -678,7 +678,7 @@
15999 - [(set_attr "type" "arith")
16000 + [(set_attr "type" "dspalu")
16001 (set_attr "mode" "SI")])
16004 @@ -696,7 +696,7 @@
16006 return "replv.qb\t%0,%1";
16008 - [(set_attr "type" "arith")
16009 + [(set_attr "type" "dspalu")
16010 (set_attr "mode" "SI")])
16012 (define_insn "mips_repl_ph"
16013 @@ -707,7 +707,7 @@
16017 - [(set_attr "type" "arith")
16018 + [(set_attr "type" "dspalu")
16019 (set_attr "mode" "SI")])
16021 ;; Table 2-5. MIPS DSP ASE Instructions: Compare-Pick
16022 @@ -720,7 +720,7 @@
16025 "cmp<DSPV:dspfmt1_1>.eq.<DSPV:dspfmt2>\t%0,%1"
16026 - [(set_attr "type" "arith")
16027 + [(set_attr "type" "dspalu")
16028 (set_attr "mode" "SI")])
16030 (define_insn "mips_cmp<DSPV:dspfmt1_1>_lt_<DSPV:dspfmt2>"
16031 @@ -731,7 +731,7 @@
16034 "cmp<DSPV:dspfmt1_1>.lt.<DSPV:dspfmt2>\t%0,%1"
16035 - [(set_attr "type" "arith")
16036 + [(set_attr "type" "dspalu")
16037 (set_attr "mode" "SI")])
16039 (define_insn "mips_cmp<DSPV:dspfmt1_1>_le_<DSPV:dspfmt2>"
16040 @@ -742,7 +742,7 @@
16043 "cmp<DSPV:dspfmt1_1>.le.<DSPV:dspfmt2>\t%0,%1"
16044 - [(set_attr "type" "arith")
16045 + [(set_attr "type" "dspalu")
16046 (set_attr "mode" "SI")])
16048 (define_insn "mips_cmpgu_eq_qb"
16049 @@ -752,7 +752,7 @@
16050 UNSPEC_CMPGU_EQ_QB))]
16052 "cmpgu.eq.qb\t%0,%1,%2"
16053 - [(set_attr "type" "arith")
16054 + [(set_attr "type" "dspalu")
16055 (set_attr "mode" "SI")])
16057 (define_insn "mips_cmpgu_lt_qb"
16058 @@ -762,7 +762,7 @@
16059 UNSPEC_CMPGU_LT_QB))]
16061 "cmpgu.lt.qb\t%0,%1,%2"
16062 - [(set_attr "type" "arith")
16063 + [(set_attr "type" "dspalu")
16064 (set_attr "mode" "SI")])
16066 (define_insn "mips_cmpgu_le_qb"
16067 @@ -772,7 +772,7 @@
16068 UNSPEC_CMPGU_LE_QB))]
16070 "cmpgu.le.qb\t%0,%1,%2"
16071 - [(set_attr "type" "arith")
16072 + [(set_attr "type" "dspalu")
16073 (set_attr "mode" "SI")])
16076 @@ -784,7 +784,7 @@
16079 "pick.<DSPV:dspfmt2>\t%0,%1,%2"
16080 - [(set_attr "type" "arith")
16081 + [(set_attr "type" "dspalu")
16082 (set_attr "mode" "SI")])
16085 @@ -795,7 +795,7 @@
16086 UNSPEC_PACKRL_PH))]
16088 "packrl.ph\t%0,%1,%2"
16089 - [(set_attr "type" "arith")
16090 + [(set_attr "type" "dspalu")
16091 (set_attr "mode" "SI")])
16093 ;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access
16094 @@ -818,7 +818,7 @@
16096 return "extrv.w\t%0,%q1,%2";
16098 - [(set_attr "type" "mfhilo")
16099 + [(set_attr "type" "accext")
16100 (set_attr "mode" "SI")])
16102 (define_insn "mips_extr_r_w"
16103 @@ -839,7 +839,7 @@
16105 return "extrv_r.w\t%0,%q1,%2";
16107 - [(set_attr "type" "mfhilo")
16108 + [(set_attr "type" "accext")
16109 (set_attr "mode" "SI")])
16111 (define_insn "mips_extr_rs_w"
16112 @@ -860,7 +860,7 @@
16114 return "extrv_rs.w\t%0,%q1,%2";
16116 - [(set_attr "type" "mfhilo")
16117 + [(set_attr "type" "accext")
16118 (set_attr "mode" "SI")])
16121 @@ -882,7 +882,7 @@
16123 return "extrv_s.h\t%0,%q1,%2";
16125 - [(set_attr "type" "mfhilo")
16126 + [(set_attr "type" "accext")
16127 (set_attr "mode" "SI")])
16130 @@ -905,7 +905,7 @@
16132 return "extpv\t%0,%q1,%2";
16134 - [(set_attr "type" "mfhilo")
16135 + [(set_attr "type" "accext")
16136 (set_attr "mode" "SI")])
16138 (define_insn "mips_extpdp"
16139 @@ -930,7 +930,7 @@
16141 return "extpdpv\t%0,%q1,%2";
16143 - [(set_attr "type" "mfhilo")
16144 + [(set_attr "type" "accext")
16145 (set_attr "mode" "SI")])
16148 @@ -949,7 +949,7 @@
16150 return "shilov\t%q0,%2";
16152 - [(set_attr "type" "mfhilo")
16153 + [(set_attr "type" "accmod")
16154 (set_attr "mode" "SI")])
16157 @@ -965,7 +965,7 @@
16158 (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])]
16159 "ISA_HAS_DSP && !TARGET_64BIT"
16161 - [(set_attr "type" "mfhilo")
16162 + [(set_attr "type" "accmod")
16163 (set_attr "mode" "SI")])
16166 @@ -987,7 +987,7 @@
16167 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])]
16170 - [(set_attr "type" "arith")
16171 + [(set_attr "type" "dspalu")
16172 (set_attr "mode" "SI")])
16175 @@ -1003,7 +1003,7 @@
16179 - [(set_attr "type" "arith")
16180 + [(set_attr "type" "dspalu")
16181 (set_attr "mode" "SI")])
16183 ;; Table 2-7. MIPS DSP ASE Instructions: Indexed-Load
16184 --- a/gcc/config/mips/mips-dspr2.md
16185 +++ b/gcc/config/mips/mips-dspr2.md
16187 (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])]
16189 "absq_s.qb\t%0,%z1"
16190 - [(set_attr "type" "arith")
16191 + [(set_attr "type" "dspalusat")
16192 (set_attr "mode" "SI")])
16194 (define_insn "mips_addu_ph"
16196 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])]
16198 "addu.ph\t%0,%z1,%z2"
16199 - [(set_attr "type" "arith")
16200 + [(set_attr "type" "dspalu")
16201 (set_attr "mode" "SI")])
16203 (define_insn "mips_addu_s_ph"
16205 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])]
16207 "addu_s.ph\t%0,%z1,%z2"
16208 - [(set_attr "type" "arith")
16209 + [(set_attr "type" "dspalusat")
16210 (set_attr "mode" "SI")])
16212 (define_insn "mips_adduh_qb"
16216 "adduh.qb\t%0,%z1,%z2"
16217 - [(set_attr "type" "arith")
16218 + [(set_attr "type" "dspalu")
16219 (set_attr "mode" "SI")])
16221 (define_insn "mips_adduh_r_qb"
16223 UNSPEC_ADDUH_R_QB))]
16225 "adduh_r.qb\t%0,%z1,%z2"
16226 - [(set_attr "type" "arith")
16227 + [(set_attr "type" "dspalusat")
16228 (set_attr "mode" "SI")])
16230 (define_insn "mips_append"
16232 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
16233 return "append\t%0,%z2,%3";
16235 - [(set_attr "type" "arith")
16236 + [(set_attr "type" "dspalu")
16237 (set_attr "mode" "SI")])
16239 (define_insn "mips_balign"
16241 operands[2] = GEN_INT (INTVAL (operands[2]) & 3);
16242 return "balign\t%0,%z2,%3";
16244 - [(set_attr "type" "arith")
16245 + [(set_attr "type" "dspalu")
16246 (set_attr "mode" "SI")])
16248 (define_insn "mips_cmpgdu_eq_qb"
16250 UNSPEC_CMPGDU_EQ_QB))])]
16252 "cmpgdu.eq.qb\t%0,%z1,%z2"
16253 - [(set_attr "type" "arith")
16254 + [(set_attr "type" "dspalu")
16255 (set_attr "mode" "SI")])
16257 (define_insn "mips_cmpgdu_lt_qb"
16258 @@ -114,7 +114,7 @@
16259 UNSPEC_CMPGDU_LT_QB))])]
16261 "cmpgdu.lt.qb\t%0,%z1,%z2"
16262 - [(set_attr "type" "arith")
16263 + [(set_attr "type" "dspalu")
16264 (set_attr "mode" "SI")])
16266 (define_insn "mips_cmpgdu_le_qb"
16267 @@ -129,7 +129,7 @@
16268 UNSPEC_CMPGDU_LE_QB))])]
16270 "cmpgdu.le.qb\t%0,%z1,%z2"
16271 - [(set_attr "type" "arith")
16272 + [(set_attr "type" "dspalu")
16273 (set_attr "mode" "SI")])
16275 (define_insn "mips_dpa_w_ph"
16276 @@ -140,7 +140,7 @@
16278 "ISA_HAS_DSPR2 && !TARGET_64BIT"
16279 "dpa.w.ph\t%q0,%z2,%z3"
16280 - [(set_attr "type" "imadd")
16281 + [(set_attr "type" "dspmac")
16282 (set_attr "mode" "SI")])
16284 (define_insn "mips_dps_w_ph"
16285 @@ -151,7 +151,7 @@
16287 "ISA_HAS_DSPR2 && !TARGET_64BIT"
16288 "dps.w.ph\t%q0,%z2,%z3"
16289 - [(set_attr "type" "imadd")
16290 + [(set_attr "type" "dspmac")
16291 (set_attr "mode" "SI")])
16293 (define_expand "mips_madd<u>"
16294 @@ -247,7 +247,7 @@
16295 UNSPEC_MULSA_W_PH))]
16296 "ISA_HAS_DSPR2 && !TARGET_64BIT"
16297 "mulsa.w.ph\t%q0,%z2,%z3"
16298 - [(set_attr "type" "imadd")
16299 + [(set_attr "type" "dspmac")
16300 (set_attr "mode" "SI")])
16302 (define_insn "mips_mult"
16303 @@ -277,7 +277,7 @@
16304 UNSPEC_PRECR_QB_PH))]
16306 "precr.qb.ph\t%0,%z1,%z2"
16307 - [(set_attr "type" "arith")
16308 + [(set_attr "type" "dspalu")
16309 (set_attr "mode" "SI")])
16311 (define_insn "mips_precr_sra_ph_w"
16312 @@ -292,7 +292,7 @@
16313 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
16314 return "precr_sra.ph.w\t%0,%z2,%3";
16316 - [(set_attr "type" "arith")
16317 + [(set_attr "type" "dspalu")
16318 (set_attr "mode" "SI")])
16320 (define_insn "mips_precr_sra_r_ph_w"
16321 @@ -307,7 +307,7 @@
16322 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
16323 return "precr_sra_r.ph.w\t%0,%z2,%3";
16325 - [(set_attr "type" "arith")
16326 + [(set_attr "type" "dspalu")
16327 (set_attr "mode" "SI")])
16329 (define_insn "mips_prepend"
16330 @@ -322,7 +322,7 @@
16331 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
16332 return "prepend\t%0,%z2,%3";
16334 - [(set_attr "type" "arith")
16335 + [(set_attr "type" "dspalu")
16336 (set_attr "mode" "SI")])
16338 (define_insn "mips_shra_qb"
16339 @@ -340,7 +340,7 @@
16341 return "shrav.qb\t%0,%z1,%2";
16343 - [(set_attr "type" "shift")
16344 + [(set_attr "type" "dspalu")
16345 (set_attr "mode" "SI")])
16348 @@ -359,7 +359,7 @@
16350 return "shrav_r.qb\t%0,%z1,%2";
16352 - [(set_attr "type" "shift")
16353 + [(set_attr "type" "dspalu")
16354 (set_attr "mode" "SI")])
16356 (define_insn "mips_shrl_ph"
16357 @@ -377,7 +377,7 @@
16359 return "shrlv.ph\t%0,%z1,%2";
16361 - [(set_attr "type" "shift")
16362 + [(set_attr "type" "dspalu")
16363 (set_attr "mode" "SI")])
16365 (define_insn "mips_subu_ph"
16366 @@ -390,7 +390,7 @@
16367 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])]
16369 "subu.ph\t%0,%z1,%z2"
16370 - [(set_attr "type" "arith")
16371 + [(set_attr "type" "dspalu")
16372 (set_attr "mode" "SI")])
16374 (define_insn "mips_subu_s_ph"
16375 @@ -403,7 +403,7 @@
16376 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])]
16378 "subu_s.ph\t%0,%z1,%z2"
16379 - [(set_attr "type" "arith")
16380 + [(set_attr "type" "dspalusat")
16381 (set_attr "mode" "SI")])
16383 (define_insn "mips_subuh_qb"
16384 @@ -413,7 +413,7 @@
16387 "subuh.qb\t%0,%z1,%z2"
16388 - [(set_attr "type" "arith")
16389 + [(set_attr "type" "dspalu")
16390 (set_attr "mode" "SI")])
16392 (define_insn "mips_subuh_r_qb"
16393 @@ -423,7 +423,7 @@
16394 UNSPEC_SUBUH_R_QB))]
16396 "subuh_r.qb\t%0,%z1,%z2"
16397 - [(set_attr "type" "arith")
16398 + [(set_attr "type" "dspalu")
16399 (set_attr "mode" "SI")])
16401 (define_insn "mips_addqh_ph"
16402 @@ -433,7 +433,7 @@
16405 "addqh.ph\t%0,%z1,%z2"
16406 - [(set_attr "type" "arith")
16407 + [(set_attr "type" "dspalu")
16408 (set_attr "mode" "SI")])
16410 (define_insn "mips_addqh_r_ph"
16411 @@ -443,7 +443,7 @@
16412 UNSPEC_ADDQH_R_PH))]
16414 "addqh_r.ph\t%0,%z1,%z2"
16415 - [(set_attr "type" "arith")
16416 + [(set_attr "type" "dspalu")
16417 (set_attr "mode" "SI")])
16419 (define_insn "mips_addqh_w"
16420 @@ -453,7 +453,7 @@
16423 "addqh.w\t%0,%z1,%z2"
16424 - [(set_attr "type" "arith")
16425 + [(set_attr "type" "dspalu")
16426 (set_attr "mode" "SI")])
16428 (define_insn "mips_addqh_r_w"
16429 @@ -463,7 +463,7 @@
16430 UNSPEC_ADDQH_R_W))]
16432 "addqh_r.w\t%0,%z1,%z2"
16433 - [(set_attr "type" "arith")
16434 + [(set_attr "type" "dspalu")
16435 (set_attr "mode" "SI")])
16437 (define_insn "mips_subqh_ph"
16438 @@ -473,7 +473,7 @@
16441 "subqh.ph\t%0,%z1,%z2"
16442 - [(set_attr "type" "arith")
16443 + [(set_attr "type" "dspalu")
16444 (set_attr "mode" "SI")])
16446 (define_insn "mips_subqh_r_ph"
16447 @@ -483,7 +483,7 @@
16448 UNSPEC_SUBQH_R_PH))]
16450 "subqh_r.ph\t%0,%z1,%z2"
16451 - [(set_attr "type" "arith")
16452 + [(set_attr "type" "dspalu")
16453 (set_attr "mode" "SI")])
16455 (define_insn "mips_subqh_w"
16456 @@ -493,7 +493,7 @@
16459 "subqh.w\t%0,%z1,%z2"
16460 - [(set_attr "type" "arith")
16461 + [(set_attr "type" "dspalu")
16462 (set_attr "mode" "SI")])
16464 (define_insn "mips_subqh_r_w"
16465 @@ -503,7 +503,7 @@
16466 UNSPEC_SUBQH_R_W))]
16468 "subqh_r.w\t%0,%z1,%z2"
16469 - [(set_attr "type" "arith")
16470 + [(set_attr "type" "dspalu")
16471 (set_attr "mode" "SI")])
16473 (define_insn "mips_dpax_w_ph"
16474 @@ -514,7 +514,7 @@
16475 UNSPEC_DPAX_W_PH))]
16476 "ISA_HAS_DSPR2 && !TARGET_64BIT"
16477 "dpax.w.ph\t%q0,%z2,%z3"
16478 - [(set_attr "type" "imadd")
16479 + [(set_attr "type" "dspmac")
16480 (set_attr "mode" "SI")])
16482 (define_insn "mips_dpsx_w_ph"
16483 @@ -525,7 +525,7 @@
16484 UNSPEC_DPSX_W_PH))]
16485 "ISA_HAS_DSPR2 && !TARGET_64BIT"
16486 "dpsx.w.ph\t%q0,%z2,%z3"
16487 - [(set_attr "type" "imadd")
16488 + [(set_attr "type" "dspmac")
16489 (set_attr "mode" "SI")])
16491 (define_insn "mips_dpaqx_s_w_ph"
16492 @@ -540,7 +540,7 @@
16493 UNSPEC_DPAQX_S_W_PH))])]
16494 "ISA_HAS_DSPR2 && !TARGET_64BIT"
16495 "dpaqx_s.w.ph\t%q0,%z2,%z3"
16496 - [(set_attr "type" "imadd")
16497 + [(set_attr "type" "dspmac")
16498 (set_attr "mode" "SI")])
16500 (define_insn "mips_dpaqx_sa_w_ph"
16501 @@ -555,7 +555,7 @@
16502 UNSPEC_DPAQX_SA_W_PH))])]
16503 "ISA_HAS_DSPR2 && !TARGET_64BIT"
16504 "dpaqx_sa.w.ph\t%q0,%z2,%z3"
16505 - [(set_attr "type" "imadd")
16506 + [(set_attr "type" "dspmacsat")
16507 (set_attr "mode" "SI")])
16509 (define_insn "mips_dpsqx_s_w_ph"
16510 @@ -570,7 +570,7 @@
16511 UNSPEC_DPSQX_S_W_PH))])]
16512 "ISA_HAS_DSPR2 && !TARGET_64BIT"
16513 "dpsqx_s.w.ph\t%q0,%z2,%z3"
16514 - [(set_attr "type" "imadd")
16515 + [(set_attr "type" "dspmac")
16516 (set_attr "mode" "SI")])
16518 (define_insn "mips_dpsqx_sa_w_ph"
16519 @@ -585,5 +585,43 @@
16520 UNSPEC_DPSQX_SA_W_PH))])]
16521 "ISA_HAS_DSPR2 && !TARGET_64BIT"
16522 "dpsqx_sa.w.ph\t%q0,%z2,%z3"
16523 - [(set_attr "type" "imadd")
16524 + [(set_attr "type" "dspmacsat")
16525 + (set_attr "mode" "SI")])
16527 +;; Convert mtlo $ac[1-3],$0 => mult $ac[1-3],$0,$0
16528 +;; mthi $ac[1-3],$0
16530 + [(set (match_operand:SI 0 "register_operand" "")
16532 + (set (match_operand:SI 1 "register_operand" "")
16535 + && !TARGET_MIPS16
16537 + && (((true_regnum (operands[0]) == AC1LO_REGNUM
16538 + && true_regnum (operands[1]) == AC1HI_REGNUM)
16539 + || (true_regnum (operands[0]) == AC1HI_REGNUM
16540 + && true_regnum (operands[1]) == AC1LO_REGNUM))
16541 + || ((true_regnum (operands[0]) == AC2LO_REGNUM
16542 + && true_regnum (operands[1]) == AC2HI_REGNUM)
16543 + || (true_regnum (operands[0]) == AC2HI_REGNUM
16544 + && true_regnum (operands[1]) == AC2LO_REGNUM))
16545 + || ((true_regnum (operands[0]) == AC3LO_REGNUM
16546 + && true_regnum (operands[1]) == AC3HI_REGNUM)
16547 + || (true_regnum (operands[0]) == AC3HI_REGNUM
16548 + && true_regnum (operands[1]) == AC3LO_REGNUM)))"
16549 + [(parallel [(set (match_dup 0) (const_int 0))
16550 + (set (match_dup 1) (const_int 0))])]
16553 +(define_insn "*mips_acc_init"
16554 + [(parallel [(set (match_operand:SI 0 "register_operand" "=a")
16556 + (set (match_operand:SI 1 "register_operand" "=a")
16557 + (const_int 0))])]
16559 + && !TARGET_MIPS16
16560 + && !TARGET_64BIT"
16561 + "mult\t%q0,$0,$0\t\t# Clear ACC HI/LO"
16562 + [(set_attr "type" "imul")
16563 (set_attr "mode" "SI")])
16564 --- a/gcc/config/mips/mips-protos.h
16565 +++ b/gcc/config/mips/mips-protos.h
16566 @@ -261,6 +261,8 @@ extern void mips_print_operand_address (
16567 extern void mips_output_external (FILE *, tree, const char *);
16568 extern void mips_output_filename (FILE *, const char *);
16569 extern void mips_output_ascii (FILE *, const char *, size_t);
16570 +extern void octeon_output_shared_variable (FILE *, tree, const char *,
16571 + unsigned HOST_WIDE_INT, int);
16572 extern void mips_output_aligned_decl_common (FILE *, tree, const char *,
16573 unsigned HOST_WIDE_INT,
16575 @@ -307,6 +309,8 @@ extern unsigned int mips_hard_regno_nreg
16576 extern bool mips_linked_madd_p (rtx, rtx);
16577 extern bool mips_store_data_bypass_p (rtx, rtx);
16578 extern rtx mips_prefetch_cookie (rtx, rtx);
16579 +extern int mips_mult_madd_chain_bypass_p (rtx, rtx);
16580 +extern int mips_dspalu_bypass_p (rtx, rtx);
16582 extern void irix_asm_output_align (FILE *, unsigned);
16583 extern const char *current_section_name (void);
16584 @@ -332,4 +336,6 @@ extern void mips_expand_atomic_qihi (uni
16586 extern void mips_expand_vector_init (rtx, rtx);
16588 +extern bool mips_epilogue_uses (unsigned int);
16590 #endif /* ! GCC_MIPS_PROTOS_H */
16591 --- a/gcc/config/mips/mips.c
16592 +++ b/gcc/config/mips/mips.c
16593 @@ -261,18 +261,29 @@ struct mips_frame_info GTY(()) {
16594 /* Likewise FPR X. */
16595 unsigned int fmask;
16597 - /* The number of GPRs and FPRs saved. */
16598 + /* Likewise doubleword accumulator X ($acX). */
16599 + unsigned int acc_mask;
16601 + /* The number of GPRs, FPRs, doubleword accumulators and COP0
16602 + registers saved. */
16603 unsigned int num_gp;
16604 unsigned int num_fp;
16605 + unsigned int num_acc;
16606 + unsigned int num_cop0_regs;
16608 - /* The offset of the topmost GPR and FPR save slots from the top of
16609 - the frame, or zero if no such slots are needed. */
16610 + /* The offset of the topmost GPR, FPR, accumulator and COP0-register
16611 + save slots from the top of the frame, or zero if no such slots are
16613 HOST_WIDE_INT gp_save_offset;
16614 HOST_WIDE_INT fp_save_offset;
16615 + HOST_WIDE_INT acc_save_offset;
16616 + HOST_WIDE_INT cop0_save_offset;
16618 /* Likewise, but giving offsets from the bottom of the frame. */
16619 HOST_WIDE_INT gp_sp_offset;
16620 HOST_WIDE_INT fp_sp_offset;
16621 + HOST_WIDE_INT acc_sp_offset;
16622 + HOST_WIDE_INT cop0_sp_offset;
16624 /* The offset of arg_pointer_rtx from frame_pointer_rtx. */
16625 HOST_WIDE_INT arg_pointer_offset;
16626 @@ -310,6 +321,20 @@ struct machine_function GTY(()) {
16627 /* True if we have emitted an instruction to initialize
16628 mips16_gp_pseudo_rtx. */
16629 bool initialized_mips16_gp_pseudo_p;
16631 + /* True if this is an interrupt handler. */
16632 + bool interrupt_handler_p;
16634 + /* True if this is an interrupt handler that uses shadow registers. */
16635 + bool use_shadow_register_set_p;
16637 + /* True if this is an interrupt handler that should keep interrupts
16639 + bool keep_interrupts_masked_p;
16641 + /* True if this is an interrupt handler that should use DERET
16642 + instead of ERET. */
16643 + bool use_debug_exception_return_p;
16646 /* Information about a single argument. */
16647 @@ -542,9 +567,16 @@ const enum reg_class mips_regno_to_class
16648 ALL_REGS, ALL_REGS, ALL_REGS, ALL_REGS
16651 +#ifdef CVMX_SHARED_BSS_FLAGS
16652 +static tree octeon_handle_cvmx_shared_attribute (tree *, tree, tree, int, bool *);
16655 /* The value of TARGET_ATTRIBUTE_TABLE. */
16656 const struct attribute_spec mips_attribute_table[] = {
16657 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
16658 +#ifdef CVMX_SHARED_BSS_FLAGS
16659 + { "cvmx_shared", 0, 0, true, false, false, octeon_handle_cvmx_shared_attribute },
16661 { "long_call", 0, 0, false, true, true, NULL },
16662 { "far", 0, 0, false, true, true, NULL },
16663 { "near", 0, 0, false, true, true, NULL },
16664 @@ -554,6 +586,11 @@ const struct attribute_spec mips_attribu
16665 code generation but don't carry other semantics. */
16666 { "mips16", 0, 0, true, false, false, NULL },
16667 { "nomips16", 0, 0, true, false, false, NULL },
16668 + /* Allow functions to be specified as interrupt handlers */
16669 + { "interrupt", 0, 0, false, true, true, NULL },
16670 + { "use_shadow_register_set", 0, 0, false, true, true, NULL },
16671 + { "keep_interrupts_masked", 0, 0, false, true, true, NULL },
16672 + { "use_debug_exception_return", 0, 0, false, true, true, NULL },
16673 { NULL, 0, 0, false, false, false, NULL }
16676 @@ -659,6 +696,11 @@ static const struct mips_cpu_info mips_c
16677 { "74kx", PROCESSOR_74KF1_1, 33, 0 },
16678 { "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
16680 + { "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */
16681 + { "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 },
16682 + { "1004kf", PROCESSOR_24KF2_1, 33, 0 },
16683 + { "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 },
16685 /* MIPS64 processors. */
16686 { "5kc", PROCESSOR_5KC, 64, 0 },
16687 { "5kf", PROCESSOR_5KF, 64, 0 },
16688 @@ -1064,13 +1106,7 @@ static const struct mips_rtx_cost_data m
16692 - /* Need to replace first five with the costs of calling the appropriate
16693 - libgcc routine. */
16694 - COSTS_N_INSNS (256), /* fp_add */
16695 - COSTS_N_INSNS (256), /* fp_mult_sf */
16696 - COSTS_N_INSNS (256), /* fp_mult_df */
16697 - COSTS_N_INSNS (256), /* fp_div_sf */
16698 - COSTS_N_INSNS (256), /* fp_div_df */
16700 COSTS_N_INSNS (8), /* int_mult_si */
16701 COSTS_N_INSNS (8), /* int_mult_di */
16702 COSTS_N_INSNS (72), /* int_div_si */
16703 @@ -1172,6 +1208,42 @@ mips_nomips16_decl_p (const_tree decl)
16704 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl)) != NULL;
16707 +/* Check if the interrupt attribute is set for a function. */
16710 +mips_interrupt_type_p (tree type)
16712 + return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL;
16715 +/* Check if the attribute to use shadow register set is set for a function. */
16718 +mips_use_shadow_register_set_p (tree type)
16720 + return lookup_attribute ("use_shadow_register_set",
16721 + TYPE_ATTRIBUTES (type)) != NULL;
16724 +/* Check if the attribute to keep interrupts masked is set for a function. */
16727 +mips_keep_interrupts_masked_p (tree type)
16729 + return lookup_attribute ("keep_interrupts_masked",
16730 + TYPE_ATTRIBUTES (type)) != NULL;
16733 +/* Check if the attribute to use debug exception return is set for
16737 +mips_use_debug_exception_return_p (tree type)
16739 + return lookup_attribute ("use_debug_exception_return",
16740 + TYPE_ATTRIBUTES (type)) != NULL;
16743 /* Return true if function DECL is a MIPS16 function. Return the ambient
16744 setting if DECL is null. */
16746 @@ -2817,7 +2889,7 @@ bool
16747 mips_legitimize_address (rtx *xloc, enum machine_mode mode)
16750 - HOST_WIDE_INT offset;
16751 + HOST_WIDE_INT intval, high, offset;
16753 if (mips_tls_symbol_p (*xloc))
16755 @@ -2842,6 +2914,32 @@ mips_legitimize_address (rtx *xloc, enum
16756 *xloc = mips_force_address (addr, mode);
16760 + /* Handle references to constant addresses by loading the high part
16761 + into a register and using an offset for the low part. */
16762 + if (GET_CODE (base) == CONST_INT)
16764 + intval = INTVAL (base);
16765 + high = trunc_int_for_mode (CONST_HIGH_PART (intval), Pmode);
16766 + offset = CONST_LOW_PART (intval);
16767 + /* Ignore cases in which a positive address would be accessed by a
16768 + negative offset from a negative address. The required wraparound
16769 + does not occur for 32-bit addresses on 64-bit targets, and it is
16770 + very unlikely that such an access would occur in real code anyway.
16772 + If the low offset is not legitimate for MODE, prefer to load
16773 + the constant normally, instead of using mips_force_address on
16774 + the legitimized address. The latter option would cause us to
16775 + use (D)ADDIU unconditionally, but LUI/ORI is more efficient
16776 + than LUI/ADDIU on some targets. */
16777 + if ((intval < 0 || high > 0)
16778 + && mips_valid_offset_p (GEN_INT (offset), mode))
16780 + base = mips_force_temporary (NULL, GEN_INT (high));
16781 + *xloc = plus_constant (base, offset);
16788 @@ -6210,6 +6308,11 @@ mips_function_ok_for_sibcall (tree decl,
16789 if (!TARGET_SIBCALLS)
16792 + /* Interrupt handlers need special epilogue code and therefore can't
16794 + if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
16797 /* We can't do a sibcall if the called function is a MIPS16 function
16798 because there is no direct "jx" instruction equivalent to "jalx" to
16799 switch the ISA mode. We only care about cases where the sibling
16800 @@ -6655,6 +6758,15 @@ mips_expand_ext_as_unaligned_load (rtx d
16801 if (!mips_get_unaligned_mem (&src, width, bitpos, &left, &right))
16804 + if (ISA_HAS_UL_US)
16806 + if (GET_MODE (dest) == DImode)
16807 + emit_insn (gen_mov_uld (dest, src, left));
16809 + emit_insn (gen_mov_ulw (dest, src, left));
16813 temp = gen_reg_rtx (GET_MODE (dest));
16814 if (GET_MODE (dest) == DImode)
16816 @@ -6689,6 +6801,16 @@ mips_expand_ins_as_unaligned_store (rtx
16818 mode = mode_for_size (width, MODE_INT, 0);
16819 src = gen_lowpart (mode, src);
16821 + if (ISA_HAS_UL_US)
16823 + if (GET_MODE (src) == DImode)
16824 + emit_insn (gen_mov_usd (dest, src, left));
16826 + emit_insn (gen_mov_usw (dest, src, left));
16830 if (mode == DImode)
16832 emit_insn (gen_mov_sdl (dest, src, left));
16833 @@ -7276,7 +7398,11 @@ mips_print_operand (FILE *file, rtx op,
16834 || (letter == 'L' && TARGET_BIG_ENDIAN)
16837 - fprintf (file, "%s", reg_names[regno]);
16838 + /* We need to print $0 .. $31 for COP0 registers. */
16839 + if (COP0_REG_P (regno))
16840 + fprintf (file, "$%s", ®_names[regno][4]);
16842 + fprintf (file, "%s", reg_names[regno]);
16846 @@ -7416,6 +7542,12 @@ mips_in_small_data_p (const_tree decl)
16847 if (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
16850 +#ifdef CVMX_SHARED_BSS_FLAGS
16851 + if (TARGET_OCTEON && TREE_CODE (decl) == VAR_DECL
16852 + && lookup_attribute ("cvmx_shared", DECL_ATTRIBUTES (decl)))
16856 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl) != 0)
16859 @@ -7642,6 +7774,37 @@ mips_dwarf_register_span (rtx reg)
16863 +/* DSP ALU can bypass data with no delays for the following pairs. */
16864 +enum insn_code dspalu_bypass_table[][2] =
16866 + {CODE_FOR_mips_addsc, CODE_FOR_mips_addwc},
16867 + {CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_pick_qb},
16868 + {CODE_FOR_mips_cmpu_lt_qb, CODE_FOR_mips_pick_qb},
16869 + {CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_pick_qb},
16870 + {CODE_FOR_mips_cmp_eq_ph, CODE_FOR_mips_pick_ph},
16871 + {CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_pick_ph},
16872 + {CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_ph},
16873 + {CODE_FOR_mips_wrdsp, CODE_FOR_mips_insv}
16877 +mips_dspalu_bypass_p (rtx out_insn, rtx in_insn)
16880 + int num_bypass = (sizeof (dspalu_bypass_table)
16881 + / (2 * sizeof (enum insn_code)));
16882 + enum insn_code out_icode = INSN_CODE (out_insn);
16883 + enum insn_code in_icode = INSN_CODE (in_insn);
16885 + for (i = 0; i < num_bypass; i++)
16887 + if (out_icode == dspalu_bypass_table[i][0]
16888 + && in_icode == dspalu_bypass_table[i][1])
16894 /* Implement ASM_OUTPUT_ASCII. */
16897 @@ -7866,11 +8029,19 @@ mips_file_start (void)
16898 "\t.previous\n", TARGET_LONG64 ? 64 : 32);
16900 #ifdef HAVE_AS_GNU_ATTRIBUTE
16901 +#ifdef TARGET_MIPS_SDEMTK
16902 + fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
16903 + (!TARGET_NO_FLOAT
16904 + ? (TARGET_HARD_FLOAT
16905 + ? (TARGET_DOUBLE_FLOAT
16906 + ? ((!TARGET_64BIT && TARGET_FLOAT64) ? 4 : 1) : 2) : 3) : 0));
16908 fprintf (asm_out_file, "\t.gnu_attribute 4, %d\n",
16909 (TARGET_HARD_FLOAT_ABI
16910 ? (TARGET_DOUBLE_FLOAT
16911 ? ((!TARGET_64BIT && TARGET_FLOAT64) ? 4 : 1) : 2) : 3));
16916 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
16917 @@ -8483,12 +8654,53 @@ mips_global_pointer (void)
16918 return GLOBAL_POINTER_REGNUM;
16921 +/* Return true if REGNO is a register that is ordinarily call-clobbered
16922 + but must nevertheless be preserved by an interrupt handler. */
16925 +mips_interrupt_extra_call_saved_reg_p (unsigned int regno)
16927 + if (MD_REG_P (regno))
16930 + if (TARGET_DSP && DSP_ACC_REG_P (regno))
16933 + if (GP_REG_P (regno) && !cfun->machine->use_shadow_register_set_p)
16935 + /* $0 is hard-wired. */
16936 + if (regno == GP_REG_FIRST)
16939 + /* The interrupt handler can treat kernel registers as
16940 + scratch registers. */
16941 + if (KERNEL_REG_P (regno))
16944 + /* The function will return the stack pointer to its original value
16946 + if (regno == STACK_POINTER_REGNUM)
16949 + /* Otherwise, return true for registers that aren't ordinarily
16950 + call-clobbered. */
16951 + return call_really_used_regs[regno];
16957 /* Return true if the current function should treat register REGNO
16961 mips_cfun_call_saved_reg_p (unsigned int regno)
16963 + /* Interrupt handlers need to save extra registers. */
16964 + if (cfun->machine->interrupt_handler_p
16965 + && mips_interrupt_extra_call_saved_reg_p (regno))
16968 /* call_insns preserve $28 unless they explicitly say otherwise,
16969 so call_really_used_regs[] treats $28 as call-saved. However,
16970 we want the ABI property rather than the default call_insn
16971 @@ -8537,6 +8749,13 @@ mips_cfun_might_clobber_call_saved_reg_p
16972 if (regno == GP_REG_FIRST + 31 && mips16_cfun_returns_in_fpr_p ())
16975 + /* If REGNO is ordinarily call-clobbered, we must assume that any
16976 + called function could modify it. */
16977 + if (cfun->machine->interrupt_handler_p
16978 + && !current_function_is_leaf
16979 + && mips_interrupt_extra_call_saved_reg_p (regno))
16985 @@ -8592,6 +8811,14 @@ mips_save_reg_p (unsigned int regno)
16986 C | callee-allocated save area |
16987 | for register varargs |
16989 + +-------------------------------+ <-- frame_pointer_rtx
16990 + | | + cop0_sp_offset
16991 + | COP0 reg save area | + UNITS_PER_WORD
16993 + +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
16994 + | | + UNITS_PER_WORD
16995 + | accumulator save area |
16997 +-------------------------------+ <-- frame_pointer_rtx + fp_sp_offset
16998 | | + UNITS_PER_HWFPVALUE
17000 @@ -8635,6 +8862,28 @@ mips_compute_frame_info (void)
17001 HOST_WIDE_INT offset, size;
17002 unsigned int regno, i;
17004 + /* Set this function's interrupt properties. */
17005 + if (mips_interrupt_type_p (TREE_TYPE (current_function_decl)))
17007 + if (!ISA_MIPS32R2)
17008 + error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
17009 + else if (TARGET_HARD_FLOAT)
17010 + error ("the %<interrupt%> attribute requires %<-msoft-float%>");
17011 + else if (TARGET_MIPS16)
17012 + error ("interrupt handlers cannot be MIPS16 functions");
17015 + cfun->machine->interrupt_handler_p = true;
17016 + cfun->machine->use_shadow_register_set_p =
17017 + mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl));
17018 + cfun->machine->keep_interrupts_masked_p =
17019 + mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl));
17020 + cfun->machine->use_debug_exception_return_p =
17021 + mips_use_debug_exception_return_p (TREE_TYPE
17022 + (current_function_decl));
17026 frame = &cfun->machine->frame;
17027 memset (frame, 0, sizeof (*frame));
17028 size = get_frame_size ();
17029 @@ -8704,7 +8953,7 @@ mips_compute_frame_info (void)
17032 /* Find out which FPRs we need to save. This loop must iterate over
17033 - the same space as its companion in mips_for_each_saved_reg. */
17034 + the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
17035 if (TARGET_HARD_FLOAT)
17036 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += MAX_FPRS_PER_FMT)
17037 if (mips_save_reg_p (regno))
17038 @@ -8720,6 +8969,47 @@ mips_compute_frame_info (void)
17039 frame->fp_sp_offset = offset - UNITS_PER_HWFPVALUE;
17042 + /* Add in space for the interrupt context information. */
17043 + if (cfun->machine->interrupt_handler_p)
17045 + /* Check HI/LO. */
17046 + if (mips_save_reg_p (LO_REGNUM) || mips_save_reg_p (HI_REGNUM))
17048 + frame->num_acc++;
17049 + frame->acc_mask |= (1 << 0);
17052 + /* Check accumulators 1, 2, 3. */
17053 + for (i = DSP_ACC_REG_FIRST; i <= DSP_ACC_REG_LAST; i += 2)
17054 + if (mips_save_reg_p (i) || mips_save_reg_p (i + 1))
17056 + frame->num_acc++;
17057 + frame->acc_mask |= 1 << (((i - DSP_ACC_REG_FIRST) / 2) + 1);
17060 + /* All interrupt context functions need space to preserve STATUS. */
17061 + frame->num_cop0_regs++;
17063 + /* If we don't keep interrupts masked, we need to save EPC. */
17064 + if (!cfun->machine->keep_interrupts_masked_p)
17065 + frame->num_cop0_regs++;
17068 + /* Move above the accumulator save area. */
17069 + if (frame->num_acc > 0)
17071 + /* Each accumulator needs 2 words. */
17072 + offset += frame->num_acc * 2 * UNITS_PER_WORD;
17073 + frame->acc_sp_offset = offset - UNITS_PER_WORD;
17076 + /* Move above the COP0 register save area. */
17077 + if (frame->num_cop0_regs > 0)
17079 + offset += frame->num_cop0_regs * UNITS_PER_WORD;
17080 + frame->cop0_sp_offset = offset - UNITS_PER_WORD;
17083 /* Move above the callee-allocated varargs save area. */
17084 offset += MIPS_STACK_ALIGN (cfun->machine->varargs_size);
17085 frame->arg_pointer_offset = offset;
17086 @@ -8733,6 +9023,10 @@ mips_compute_frame_info (void)
17087 frame->gp_save_offset = frame->gp_sp_offset - offset;
17088 if (frame->fp_sp_offset > 0)
17089 frame->fp_save_offset = frame->fp_sp_offset - offset;
17090 + if (frame->acc_sp_offset > 0)
17091 + frame->acc_save_offset = frame->acc_sp_offset - offset;
17092 + if (frame->num_cop0_regs > 0)
17093 + frame->cop0_save_offset = frame->cop0_sp_offset - offset;
17095 /* MIPS16 code offsets the frame pointer by the size of the outgoing
17096 arguments. This tends to increase the chances of using unextended
17097 @@ -8929,12 +9223,41 @@ mips_save_restore_reg (enum machine_mode
17098 fn (gen_rtx_REG (mode, regno), mem);
17101 +/* Call FN for each accumlator that is saved by the current function.
17102 + SP_OFFSET is the offset of the current stack pointer from the start
17106 +mips_for_each_saved_acc (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
17108 + HOST_WIDE_INT offset;
17111 + offset = cfun->machine->frame.acc_sp_offset - sp_offset;
17112 + if (BITSET_P (cfun->machine->frame.acc_mask, 0))
17114 + mips_save_restore_reg (word_mode, LO_REGNUM, offset, fn);
17115 + offset -= UNITS_PER_WORD;
17116 + mips_save_restore_reg (word_mode, HI_REGNUM, offset, fn);
17117 + offset -= UNITS_PER_WORD;
17120 + for (regno = DSP_ACC_REG_FIRST; regno <= DSP_ACC_REG_LAST; regno++)
17121 + if (BITSET_P (cfun->machine->frame.acc_mask,
17122 + ((regno - DSP_ACC_REG_FIRST) / 2) + 1))
17124 + mips_save_restore_reg (word_mode, regno, offset, fn);
17125 + offset -= UNITS_PER_WORD;
17129 /* Call FN for each register that is saved by the current function.
17130 SP_OFFSET is the offset of the current stack pointer from the start
17134 -mips_for_each_saved_reg (HOST_WIDE_INT sp_offset, mips_save_restore_fn fn)
17135 +mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset,
17136 + mips_save_restore_fn fn)
17138 enum machine_mode fpr_mode;
17139 HOST_WIDE_INT offset;
17140 @@ -9122,13 +9445,24 @@ mips_save_reg (rtx reg, rtx mem)
17144 - if (TARGET_MIPS16
17145 - && REGNO (reg) != GP_REG_FIRST + 31
17146 - && !M16_REG_P (REGNO (reg)))
17148 - /* Save a non-MIPS16 register by moving it through a temporary.
17149 - We don't need to do this for $31 since there's a special
17150 - instruction for it. */
17151 + if (REGNO (reg) == HI_REGNUM)
17153 + if (TARGET_64BIT)
17154 + emit_insn (gen_mfhidi_ti (MIPS_PROLOGUE_TEMP (DImode),
17155 + gen_rtx_REG (TImode, MD_REG_FIRST)));
17157 + emit_insn (gen_mfhisi_di (MIPS_PROLOGUE_TEMP (SImode),
17158 + gen_rtx_REG (DImode, MD_REG_FIRST)));
17159 + mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
17161 + else if ((TARGET_MIPS16
17162 + && REGNO (reg) != GP_REG_FIRST + 31
17163 + && !M16_REG_P (REGNO (reg)))
17164 + || ACC_REG_P (REGNO (reg)))
17166 + /* If the register has no direct store instruction, move it
17167 + through a temporary. Note that there's a special MIPS16
17168 + instruction to save $31. */
17169 mips_emit_move (MIPS_PROLOGUE_TEMP (GET_MODE (reg)), reg);
17170 mips_emit_move (mem, MIPS_PROLOGUE_TEMP (GET_MODE (reg)));
17172 @@ -9200,6 +9534,14 @@ mips_emit_loadgp (void)
17173 emit_insn (gen_loadgp_blockage ());
17176 +/* A for_each_rtx callback. Stop the search if *X is a kernel register. */
17179 +mips_kernel_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
17181 + return GET_CODE (*x) == REG && KERNEL_REG_P (REGNO (*x));
17184 /* Expand the "prologue" pattern. */
17187 @@ -9219,7 +9561,8 @@ mips_expand_prologue (void)
17188 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
17189 bytes beforehand; this is enough to cover the register save area
17190 without going out of range. */
17191 - if ((frame->mask | frame->fmask) != 0)
17192 + if (((frame->mask | frame->fmask | frame->acc_mask) != 0)
17193 + || frame->num_cop0_regs > 0)
17195 HOST_WIDE_INT step1;
17197 @@ -9250,12 +9593,97 @@ mips_expand_prologue (void)
17201 - insn = gen_add3_insn (stack_pointer_rtx,
17202 - stack_pointer_rtx,
17203 - GEN_INT (-step1));
17204 - RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
17206 - mips_for_each_saved_reg (size, mips_save_reg);
17207 + if (cfun->machine->interrupt_handler_p)
17209 + HOST_WIDE_INT offset;
17212 + /* If this interrupt is using a shadow register set, we need to
17213 + get the stack pointer from the previous register set. */
17214 + if (cfun->machine->use_shadow_register_set_p)
17215 + emit_insn (gen_mips_rdpgpr (stack_pointer_rtx,
17216 + stack_pointer_rtx));
17218 + if (!cfun->machine->keep_interrupts_masked_p)
17220 + /* Move from COP0 Cause to K0. */
17221 + emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K0_REG_NUM),
17222 + gen_rtx_REG (SImode,
17223 + COP0_CAUSE_REG_NUM)));
17224 + /* Move from COP0 EPC to K1. */
17225 + emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
17226 + gen_rtx_REG (SImode,
17227 + COP0_EPC_REG_NUM)));
17230 + /* Allocate the first part of the frame. */
17231 + insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx,
17232 + GEN_INT (-step1));
17233 + RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
17236 + /* Start at the uppermost location for saving. */
17237 + offset = frame->cop0_sp_offset - size;
17238 + if (!cfun->machine->keep_interrupts_masked_p)
17240 + /* Push EPC into its stack slot. */
17241 + mem = gen_frame_mem (word_mode,
17242 + plus_constant (stack_pointer_rtx,
17244 + mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
17245 + offset -= UNITS_PER_WORD;
17248 + /* Move from COP0 Status to K1. */
17249 + emit_insn (gen_cop0_move (gen_rtx_REG (SImode, K1_REG_NUM),
17250 + gen_rtx_REG (SImode,
17251 + COP0_STATUS_REG_NUM)));
17253 + /* Right justify the RIPL in k0. */
17254 + if (!cfun->machine->keep_interrupts_masked_p)
17255 + emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode, K0_REG_NUM),
17256 + gen_rtx_REG (SImode, K0_REG_NUM),
17257 + GEN_INT (CAUSE_IPL)));
17259 + /* Push Status into its stack slot. */
17260 + mem = gen_frame_mem (word_mode,
17261 + plus_constant (stack_pointer_rtx, offset));
17262 + mips_emit_move (mem, gen_rtx_REG (word_mode, K1_REG_NUM));
17263 + offset -= UNITS_PER_WORD;
17265 + /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
17266 + if (!cfun->machine->keep_interrupts_masked_p)
17267 + emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
17269 + GEN_INT (SR_IPL),
17270 + gen_rtx_REG (SImode, K0_REG_NUM)));
17272 + if (!cfun->machine->keep_interrupts_masked_p)
17273 + /* Enable interrupts by clearing the KSU ERL and EXL bits.
17274 + IE is already the correct value, so we don't have to do
17275 + anything explicit. */
17276 + emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
17278 + GEN_INT (SR_EXL),
17279 + gen_rtx_REG (SImode, GP_REG_FIRST)));
17281 + /* Disable interrupts by clearing the KSU, ERL, EXL,
17283 + emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
17286 + gen_rtx_REG (SImode, GP_REG_FIRST)));
17290 + insn = gen_add3_insn (stack_pointer_rtx,
17291 + stack_pointer_rtx,
17292 + GEN_INT (-step1));
17293 + RTX_FRAME_RELATED_P (emit_insn (insn)) = 1;
17296 + mips_for_each_saved_acc (size, mips_save_reg);
17297 + mips_for_each_saved_gpr_and_fpr (size, mips_save_reg);
17301 @@ -9340,6 +9768,20 @@ mips_expand_prologue (void)
17302 pic_offset_table_rtx);
17305 + /* We need to search back to the last use of K0 or K1. */
17306 + if (cfun->machine->interrupt_handler_p)
17308 + for (insn = get_last_insn (); insn != NULL_RTX; insn = PREV_INSN (insn))
17309 + if (INSN_P (insn)
17310 + && for_each_rtx (&PATTERN (insn), mips_kernel_reg_p, NULL))
17312 + /* Emit a move from K1 to COP0 Status after insn. */
17313 + gcc_assert (insn != NULL_RTX);
17314 + emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
17315 + gen_rtx_REG (SImode, K1_REG_NUM)),
17319 /* If we are profiling, make sure no instructions are scheduled before
17320 the call to mcount. */
17322 @@ -9356,7 +9798,20 @@ mips_restore_reg (rtx reg, rtx mem)
17323 if (TARGET_MIPS16 && REGNO (reg) == GP_REG_FIRST + 31)
17324 reg = gen_rtx_REG (GET_MODE (reg), GP_REG_FIRST + 7);
17326 - if (TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
17327 + if (REGNO (reg) == HI_REGNUM)
17329 + mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
17330 + if (TARGET_64BIT)
17331 + emit_insn (gen_mthisi_di (gen_rtx_REG (TImode, MD_REG_FIRST),
17332 + MIPS_EPILOGUE_TEMP (DImode),
17333 + gen_rtx_REG (DImode, LO_REGNUM)));
17335 + emit_insn (gen_mthisi_di (gen_rtx_REG (DImode, MD_REG_FIRST),
17336 + MIPS_EPILOGUE_TEMP (SImode),
17337 + gen_rtx_REG (SImode, LO_REGNUM)));
17339 + else if ((TARGET_MIPS16 && !M16_REG_P (REGNO (reg)))
17340 + || ACC_REG_P (REGNO (reg)))
17342 /* Can't restore directly; move through a temporary. */
17343 mips_emit_move (MIPS_EPILOGUE_TEMP (GET_MODE (reg)), mem);
17344 @@ -9392,7 +9847,7 @@ mips_expand_epilogue (bool sibcall_p)
17346 const struct mips_frame_info *frame;
17347 HOST_WIDE_INT step1, step2;
17348 - rtx base, target;
17349 + rtx base, target, insn;
17351 if (!sibcall_p && mips_can_use_return_insn ())
17353 @@ -9425,7 +9880,8 @@ mips_expand_epilogue (bool sibcall_p)
17355 /* If we need to restore registers, deallocate as much stack as
17356 possible in the second step without going out of range. */
17357 - if ((frame->mask | frame->fmask) != 0)
17358 + if ((frame->mask | frame->fmask | frame->acc_mask) != 0
17359 + || frame->num_cop0_regs > 0)
17361 step2 = MIN (step1, MIPS_MAX_FIRST_STACK_STEP);
17363 @@ -9487,13 +9943,53 @@ mips_expand_epilogue (bool sibcall_p)
17366 /* Restore the registers. */
17367 - mips_for_each_saved_reg (frame->total_size - step2, mips_restore_reg);
17368 + mips_for_each_saved_acc (frame->total_size - step2, mips_restore_reg);
17369 + mips_for_each_saved_gpr_and_fpr (frame->total_size - step2,
17370 + mips_restore_reg);
17372 - /* Deallocate the final bit of the frame. */
17374 - emit_insn (gen_add3_insn (stack_pointer_rtx,
17375 - stack_pointer_rtx,
17376 - GEN_INT (step2)));
17377 + if (cfun->machine->interrupt_handler_p)
17379 + HOST_WIDE_INT offset;
17382 + offset = frame->cop0_sp_offset - (frame->total_size - step2);
17383 + if (!cfun->machine->keep_interrupts_masked_p)
17385 + /* Restore the original EPC. */
17386 + mem = gen_frame_mem (word_mode,
17387 + plus_constant (stack_pointer_rtx, offset));
17388 + mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
17389 + offset -= UNITS_PER_WORD;
17391 + /* Move to COP0 EPC. */
17392 + emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_EPC_REG_NUM),
17393 + gen_rtx_REG (SImode, K0_REG_NUM)));
17396 + /* Restore the original Status. */
17397 + mem = gen_frame_mem (word_mode,
17398 + plus_constant (stack_pointer_rtx, offset));
17399 + mips_emit_move (gen_rtx_REG (word_mode, K0_REG_NUM), mem);
17400 + offset -= UNITS_PER_WORD;
17402 + /* If we don't use shoadow register set, we need to update SP. */
17403 + if (!cfun->machine->use_shadow_register_set_p && step2 > 0)
17404 + emit_insn (gen_add3_insn (stack_pointer_rtx,
17405 + stack_pointer_rtx,
17406 + GEN_INT (step2)));
17408 + /* Move to COP0 Status. */
17409 + emit_insn (gen_cop0_move (gen_rtx_REG (SImode, COP0_STATUS_REG_NUM),
17410 + gen_rtx_REG (SImode, K0_REG_NUM)));
17414 + /* Deallocate the final bit of the frame. */
17416 + emit_insn (gen_add3_insn (stack_pointer_rtx,
17417 + stack_pointer_rtx,
17418 + GEN_INT (step2)));
17422 /* Add in the __builtin_eh_return stack adjustment. We need to
17423 @@ -9516,18 +10012,44 @@ mips_expand_epilogue (bool sibcall_p)
17427 - unsigned int regno;
17429 - /* When generating MIPS16 code, the normal mips_for_each_saved_reg
17430 - path will restore the return address into $7 rather than $31. */
17431 - if (TARGET_MIPS16
17432 - && !GENERATE_MIPS16E_SAVE_RESTORE
17433 - && BITSET_P (frame->mask, 31))
17434 - regno = GP_REG_FIRST + 7;
17436 - regno = GP_REG_FIRST + 31;
17437 mips_expand_before_return ();
17438 - emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
17439 + if (cfun->machine->interrupt_handler_p)
17441 + /* Interrupt handlers generate eret or deret. */
17442 + if (cfun->machine->use_debug_exception_return_p)
17443 + emit_jump_insn (gen_mips_deret ());
17445 + emit_jump_insn (gen_mips_eret ());
17449 + unsigned int regno;
17451 + /* When generating MIPS16 code, the normal
17452 + mips_for_each_saved_gpr_and_fpr path will restore the return
17453 + address into $7 rather than $31. */
17454 + if (TARGET_MIPS16
17455 + && !GENERATE_MIPS16E_SAVE_RESTORE
17456 + && BITSET_P (frame->mask, 31))
17457 + regno = GP_REG_FIRST + 7;
17459 + regno = GP_REG_FIRST + 31;
17460 + emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode, regno)));
17464 + /* Search from the beginning to the first use of K0 or K1. */
17465 + if (cfun->machine->interrupt_handler_p
17466 + && !cfun->machine->keep_interrupts_masked_p)
17468 + for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
17469 + if (INSN_P (insn)
17470 + && for_each_rtx (&PATTERN(insn), mips_kernel_reg_p, NULL))
17472 + gcc_assert (insn != NULL_RTX);
17473 + /* Insert disable interrupts before the first use of K0 or K1. */
17474 + emit_insn_before (gen_mips_di (), insn);
17475 + emit_insn_before (gen_mips_ehb (), insn);
17479 @@ -9538,6 +10060,10 @@ mips_expand_epilogue (bool sibcall_p)
17481 mips_can_use_return_insn (void)
17483 + /* Interrupt handlers need to go through the epilogue. */
17484 + if (cfun->machine->interrupt_handler_p)
17487 if (!reload_completed)
17490 @@ -10469,10 +10995,15 @@ mips_output_division (const char *divisi
17491 s = "bnez\t%2,1f\n\tbreak\t7\n1:";
17493 else if (GENERATE_DIVIDE_TRAPS)
17495 - output_asm_insn (s, operands);
17496 - s = "teq\t%2,%.,7";
17500 + output_asm_insn ("teq\t%2,%.,7", operands);
17503 + output_asm_insn (s, operands);
17504 + s = "teq\t%2,%.,7";
17509 output_asm_insn ("%(bne\t%2,%.,1f", operands);
17510 @@ -10784,7 +11315,17 @@ mips_maybe_swap_ready (rtx *ready, int p
17511 ready[pos2] = temp;
17517 +mips_mult_madd_chain_bypass_p (rtx out_insn ATTRIBUTE_UNUSED,
17518 + rtx in_insn ATTRIBUTE_UNUSED)
17520 + if (reload_completed)
17526 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
17527 that may clobber hi or lo. */
17528 static rtx mips_macc_chains_last_hilo;
17529 @@ -13957,6 +14498,14 @@ mips_override_options (void)
17530 long as any indirect jumps use $25. */
17533 + /* For SDE, switch on ABICALLS mode if -fpic or -fpie were used, and the
17534 + user hasn't explicitly disabled these modes. */
17535 + if (TARGET_MIPS_SDE
17536 + && (flag_pic || flag_pie) && !TARGET_ABICALLS
17537 + && !((target_flags_explicit & MASK_ABICALLS))
17538 + && mips_abi != ABI_EABI)
17539 + target_flags |= MASK_ABICALLS;
17541 /* -mvr4130-align is a "speed over size" optimization: it usually produces
17542 faster code, but at the expense of more nops. Enable it at -O3 and
17544 @@ -14309,6 +14858,178 @@ mips_order_regs_for_local_alloc (void)
17545 reg_alloc_order[24] = 0;
17549 +/* Implement EPILOGUE_USES. */
17552 +mips_epilogue_uses (unsigned int regno)
17554 + /* Say that the epilogue uses the return address register. Note that
17555 + in the case of sibcalls, the values "used by the epilogue" are
17556 + considered live at the start of the called function. */
17560 + /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17561 + See the comment above load_call<mode> for details. */
17562 + if (TARGET_USE_GOT && (regno) == GOT_VERSION_REGNUM)
17565 + /* An interrupt handler must preserve some registers that are
17566 + ordinarily call-clobbered. */
17567 + if (cfun->machine->interrupt_handler_p
17568 + && mips_interrupt_extra_call_saved_reg_p (regno))
17574 +#ifdef CVMX_SHARED_BSS_FLAGS
17575 +/* Handle a "cvmx_shared" attribute; arguments as in
17576 + struct attribute_spec.handler. */
17579 +octeon_handle_cvmx_shared_attribute (tree *node, tree name,
17580 + tree args ATTRIBUTE_UNUSED,
17581 + int flags ATTRIBUTE_UNUSED,
17582 + bool *no_add_attrs)
17584 + if (TREE_CODE (*node) != VAR_DECL)
17586 + warning (OPT_Wattributes, "%qs attribute only applies to variables",
17587 + IDENTIFIER_POINTER (name));
17588 + *no_add_attrs = true;
17591 + return NULL_TREE;
17594 +/* Switch to the appropriate section for output of DECL.
17595 + DECL is either a `VAR_DECL' node or a constant of some sort.
17596 + RELOC indicates whether forming the initial value of DECL requires
17597 + link-time relocations. */
17600 +octeon_select_section (tree decl, int reloc, unsigned HOST_WIDE_INT align)
17602 + if (decl && TREE_CODE (decl) == VAR_DECL
17603 + && lookup_attribute ("cvmx_shared", DECL_ATTRIBUTES (decl)))
17605 + const char *sname = NULL;
17606 + unsigned int flags = SECTION_WRITE;
17608 + switch (categorize_decl_for_section (decl, reloc))
17610 + case SECCAT_DATA:
17611 + case SECCAT_SDATA:
17612 + case SECCAT_RODATA:
17613 + case SECCAT_SRODATA:
17614 + case SECCAT_RODATA_MERGE_STR:
17615 + case SECCAT_RODATA_MERGE_STR_INIT:
17616 + case SECCAT_RODATA_MERGE_CONST:
17617 + case SECCAT_DATA_REL:
17618 + case SECCAT_DATA_REL_LOCAL:
17619 + case SECCAT_DATA_REL_RO:
17620 + case SECCAT_DATA_REL_RO_LOCAL:
17621 + sname = ".cvmx_shared";
17624 + case SECCAT_SBSS:
17625 + sname = ".cvmx_shared_bss";
17626 + flags |= SECTION_BSS;
17628 + case SECCAT_TEXT:
17629 + case SECCAT_TDATA:
17630 + case SECCAT_TBSS:
17635 + return get_section (sname, flags, decl);
17638 + return default_elf_select_section (decl, reloc, align);
17641 +/* Build up a unique section name, expressed as a
17642 + STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17643 + RELOC indicates whether the initial value of EXP requires
17644 + link-time relocations. */
17647 +octeon_unique_section (tree decl, int reloc)
17649 + if (decl && TREE_CODE (decl) == VAR_DECL
17650 + && lookup_attribute ("cvmx_shared", DECL_ATTRIBUTES (decl)))
17652 + const char *sname = NULL;
17654 + if (! DECL_ONE_ONLY (decl))
17657 + sect = octeon_select_section (decl, reloc, DECL_ALIGN (decl));
17658 + DECL_SECTION_NAME (decl) = build_string (strlen (sect->named.name),
17659 + sect->named.name);
17663 + switch (categorize_decl_for_section (decl, reloc))
17666 + case SECCAT_SBSS:
17667 + sname = ".cvmx_shared_bss.linkonce.";
17669 + case SECCAT_SDATA:
17670 + case SECCAT_DATA:
17671 + case SECCAT_DATA_REL:
17672 + case SECCAT_DATA_REL_LOCAL:
17673 + case SECCAT_DATA_REL_RO:
17674 + case SECCAT_DATA_REL_RO_LOCAL:
17675 + case SECCAT_RODATA:
17676 + case SECCAT_SRODATA:
17677 + case SECCAT_RODATA_MERGE_STR:
17678 + case SECCAT_RODATA_MERGE_STR_INIT:
17679 + case SECCAT_RODATA_MERGE_CONST:
17680 + sname = ".cvmx_shared.linkonce.";
17682 + case SECCAT_TEXT:
17683 + case SECCAT_TDATA:
17684 + case SECCAT_TBSS:
17689 + const char *name;
17690 + size_t plen, nlen;
17692 + plen = strlen (sname);
17694 + name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
17695 + name = targetm.strip_name_encoding (name);
17696 + nlen = strlen (name);
17698 + string = alloca (plen + nlen + 1);
17699 + memcpy (string, sname, plen);
17700 + memcpy (string + plen, name, nlen + 1);
17701 + DECL_SECTION_NAME (decl) = build_string (nlen + plen, string);
17705 + default_unique_section (decl, reloc);
17708 +/* Emit an uninitialized cvmx_shared variable. */
17710 +octeon_output_shared_variable (FILE *stream, tree decl, const char *name,
17711 + unsigned HOST_WIDE_INT size, int align)
17713 + switch_to_section (get_section (".cvmx_shared_bss", CVMX_SHARED_BSS_FLAGS,
17715 + ASM_OUTPUT_ALIGN (stream, floor_log2 (align / BITS_PER_UNIT));
17716 + ASM_DECLARE_OBJECT_NAME (stream, name, decl);
17717 + ASM_OUTPUT_SKIP (stream, size != 0 ? size : 1);
17721 /* Initialize the GCC target structure. */
17722 #undef TARGET_ASM_ALIGNED_HI_OP
17723 --- a/gcc/config/mips/mips.h
17724 +++ b/gcc/config/mips/mips.h
17725 @@ -342,6 +342,9 @@ enum mips_code_readable_setting {
17726 #define TARGET_IRIX 0
17727 #define TARGET_IRIX6 0
17729 +/* SDE specific stuff. */
17730 +#define TARGET_MIPS_SDE 0
17732 /* Define preprocessor macros for the -march and -mtune options.
17733 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
17734 processor. If INFO's canonical name is "foo", define PREFIX to
17735 @@ -708,8 +711,9 @@ enum mips_code_readable_setting {
17736 |march=r10000|march=r12000|march=r14000|march=r16000:-mips4} \
17737 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
17738 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
17739 - |march=34k*|march=74k*: -mips32r2} \
17740 - %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
17741 + |march=34k*|march=74k*|march=1004k*: -mips32r2} \
17742 + %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000 \
17743 + |march=xlr: -mips64} \
17744 %{march=mips64r2|march=octeon: -mips64r2} \
17745 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
17747 @@ -720,7 +724,8 @@ enum mips_code_readable_setting {
17748 #define MIPS_ARCH_FLOAT_SPEC \
17749 "%{mhard-float|msoft-float|march=mips*:; \
17750 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
17751 - |march=34kc|march=74kc|march=5kc|march=octeon: -msoft-float; \
17752 + |march=34kc|march=74kc|march=1004kc|march=5kc \
17753 + |march=octeon|march=xlr: -msoft-float; \
17754 march=*: -mhard-float}"
17756 /* A spec condition that matches 32-bit options. It only works if
17757 @@ -731,8 +736,9 @@ enum mips_code_readable_setting {
17759 /* Support for a compile-time default CPU, et cetera. The rules are:
17760 --with-arch is ignored if -march is specified or a -mips is specified
17761 - (other than -mips16).
17762 - --with-tune is ignored if -mtune is specified.
17763 + (other than -mips16); likewise --with-arch-32 and --with-arch-64.
17764 + --with-tune is ignored if -mtune is specified; likewise
17765 + --with-tune-32 and --with-tune-64.
17766 --with-abi is ignored if -mabi is specified.
17767 --with-float is ignored if -mhard-float or -msoft-float are
17769 @@ -740,7 +746,11 @@ enum mips_code_readable_setting {
17771 #define OPTION_DEFAULT_SPECS \
17772 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
17773 + {"arch_32", "%{!mabi=*|mabi=32:%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
17774 + {"arch_64", "%{mabi=n32|mabi=64:%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}}" }, \
17775 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
17776 + {"tune_32", "%{!mabi=*|mabi=32:%{!mtune=*:-mtune=%(VALUE)}}" }, \
17777 + {"tune_64", "%{mabi=n32|mabi=64:%{!mtune=*:-mtune=%(VALUE)}}" }, \
17778 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
17779 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
17780 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
17781 @@ -750,7 +760,7 @@ enum mips_code_readable_setting {
17783 /* A spec that infers the -mdsp setting from an -march argument. */
17784 #define BASE_DRIVER_SELF_SPECS \
17785 - "%{!mno-dsp:%{march=24ke*|march=34k*|march=74k*: -mdsp}}"
17786 + "%{!mno-dsp:%{march=24ke*|march=34k*|march=74k*|march=1004k*: -mdsp}}"
17788 #define DRIVER_SELF_SPECS BASE_DRIVER_SELF_SPECS
17790 @@ -1038,6 +1048,11 @@ enum mips_code_readable_setting {
17791 /* ISA includes the bbit* instructions. */
17792 #define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16)
17794 +/* ISA has single-instruction unaligned load/store support. */
17795 +#define ISA_HAS_UL_US (TARGET_OCTEON \
17796 + && TARGET_OCTEON_UNALIGNED \
17797 + && !TARGET_MIPS16)
17799 /* ISA includes the cins instruction. */
17800 #define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16)
17802 @@ -1055,6 +1070,7 @@ enum mips_code_readable_setting {
17804 /* The CACHE instruction is available. */
17805 #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16)
17808 /* Add -G xx support. */
17810 @@ -1152,6 +1168,7 @@ enum mips_code_readable_setting {
17811 %{mshared} %{mno-shared} \
17812 %{msym32} %{mno-sym32} \
17814 +%{mocteon-useun} %{mno-octeon-useun} \
17815 %(subtarget_asm_spec)"
17817 /* Extra switches sometimes passed to the linker. */
17818 @@ -1622,6 +1639,9 @@ enum mips_code_readable_setting {
17819 #define GP_REG_LAST 31
17820 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
17821 #define GP_DBX_FIRST 0
17822 +#define K0_REG_NUM (GP_REG_FIRST + 26)
17823 +#define K1_REG_NUM (GP_REG_FIRST + 27)
17824 +#define KERNEL_REG_P(REGNO) (IN_RANGE (REGNO, K0_REG_NUM, K1_REG_NUM))
17826 #define FP_REG_FIRST 32
17827 #define FP_REG_LAST 63
17828 @@ -1649,6 +1669,10 @@ enum mips_code_readable_setting {
17829 #define COP0_REG_LAST 111
17830 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
17832 +#define COP0_STATUS_REG_NUM (COP0_REG_FIRST + 12)
17833 +#define COP0_CAUSE_REG_NUM (COP0_REG_FIRST + 13)
17834 +#define COP0_EPC_REG_NUM (COP0_REG_FIRST + 14)
17836 #define COP2_REG_FIRST 112
17837 #define COP2_REG_LAST 143
17838 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
17839 @@ -1666,6 +1690,29 @@ enum mips_code_readable_setting {
17840 #define AT_REGNUM (GP_REG_FIRST + 1)
17841 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
17842 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
17843 +#define AC1HI_REGNUM (TARGET_BIG_ENDIAN \
17844 + ? DSP_ACC_REG_FIRST : DSP_ACC_REG_FIRST + 1)
17845 +#define AC1LO_REGNUM (TARGET_BIG_ENDIAN \
17846 + ? DSP_ACC_REG_FIRST + 1 : DSP_ACC_REG_FIRST)
17847 +#define AC2HI_REGNUM (TARGET_BIG_ENDIAN \
17848 + ? DSP_ACC_REG_FIRST + 2 : DSP_ACC_REG_FIRST + 3)
17849 +#define AC2LO_REGNUM (TARGET_BIG_ENDIAN \
17850 + ? DSP_ACC_REG_FIRST + 3 : DSP_ACC_REG_FIRST + 2)
17851 +#define AC3HI_REGNUM (TARGET_BIG_ENDIAN \
17852 + ? DSP_ACC_REG_FIRST + 4 : DSP_ACC_REG_FIRST + 5)
17853 +#define AC3LO_REGNUM (TARGET_BIG_ENDIAN \
17854 + ? DSP_ACC_REG_FIRST + 5 : DSP_ACC_REG_FIRST + 4)
17856 +/* A few bitfield locations for the coprocessor registers. */
17857 +/* Request Interrupt Priority Level is from bit 10 to bit 15 of
17858 + the cause register for the EIC interrupt mode. */
17859 +#define CAUSE_IPL 10
17860 +/* Interrupt Priority Level is from bit 10 to bit 15 of the status register. */
17862 +/* Exception Level is at bit 1 of the status register. */
17864 +/* Interrupt Enable is at bit 0 of the status register. */
17867 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
17868 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
17869 @@ -1754,11 +1801,18 @@ enum mips_code_readable_setting {
17870 incoming arguments, the static chain pointer, or the frame pointer.
17871 The epilogue temporary mustn't conflict with the return registers,
17872 the PIC call register ($25), the frame pointer, the EH stack adjustment,
17873 - or the EH data registers. */
17874 + or the EH data registers.
17876 + If we're generating interrupt handlers, we use K0 as a temporary register
17877 + in prologue/epilogue code. */
17879 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
17880 -#define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
17881 -#define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
17882 +#define MIPS_PROLOGUE_TEMP_REGNUM \
17883 + (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 3)
17884 +#define MIPS_EPILOGUE_TEMP_REGNUM \
17885 + (cfun->machine->interrupt_handler_p \
17887 + : GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
17889 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
17890 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
17891 @@ -2284,14 +2338,7 @@ typedef struct mips_args {
17892 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
17895 -/* Say that the epilogue uses the return address register. Note that
17896 - in the case of sibcalls, the values "used by the epilogue" are
17897 - considered live at the start of the called function.
17899 - If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
17900 - See the comment above load_call<mode> for details. */
17901 -#define EPILOGUE_USES(REGNO) \
17902 - ((REGNO) == 31 || (TARGET_USE_GOT && (REGNO) == GOT_VERSION_REGNUM))
17903 +#define EPILOGUE_USES(REGNO) mips_epilogue_uses (REGNO)
17905 /* Treat LOC as a byte offset from the stack pointer and round it up
17906 to the next fully-aligned offset. */
17907 --- a/gcc/config/mips/mips.md
17908 +++ b/gcc/config/mips/mips.md
17910 (UNSPEC_SET_GOT_VERSION 46)
17911 (UNSPEC_UPDATE_GOT_VERSION 47)
17914 + (UNSPEC_DERET 50)
17917 + (UNSPEC_RDPGPR 53)
17920 + (UNSPEC_UNALIGNED_LOAD 60)
17921 + (UNSPEC_UNALIGNED_STORE 61)
17923 (UNSPEC_ADDRESS_FIRST 100)
17925 (TLS_GET_TP_REGNUM 3)
17926 @@ -372,6 +381,12 @@
17927 ;; frsqrt floating point reciprocal square root
17928 ;; frsqrt1 floating point reciprocal square root step1
17929 ;; frsqrt2 floating point reciprocal square root step2
17930 +;; dspmac DSP MAC instructions not saturating the accumulator
17931 +;; dspmacsat DSP MAC instructions that saturate the accumulator
17932 +;; accext DSP accumulator extract instructions
17933 +;; accmod DSP accumulator modify instructions
17934 +;; dspalu DSP ALU instructions not saturating the result
17935 +;; dspalusat DSP ALU instructions that saturate the result
17936 ;; multi multiword sequence (or user asm statements)
17937 ;; nop no operation
17938 ;; ghost an instruction that produces no real code
17939 @@ -380,7 +395,7 @@
17940 prefetch,prefetchx,condmove,mtc,mfc,mthilo,mfhilo,const,arith,logical,
17941 shift,slt,signext,clz,pop,trap,imul,imul3,imul3nc,imadd,idiv,idiv3,move,
17942 fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,
17943 - frsqrt,frsqrt1,frsqrt2,multi,nop,ghost"
17944 + frsqrt,frsqrt1,frsqrt2,dspmac,dspmacsat,accext,accmod,dspalu,dspalusat,multi,nop,ghost"
17945 (cond [(eq_attr "jal" "!unset") (const_string "call")
17946 (eq_attr "got" "load") (const_string "load")
17948 @@ -3565,7 +3580,9 @@
17949 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
17950 (match_operand:QI 2 "memory_operand" "m")]
17951 UNSPEC_LOAD_LEFT))]
17952 - "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
17954 + && !ISA_HAS_UL_US
17955 + && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
17957 [(set_attr "move_type" "load")
17958 (set_attr "mode" "<MODE>")])
17959 @@ -3576,7 +3593,9 @@
17960 (match_operand:QI 2 "memory_operand" "m")
17961 (match_operand:GPR 3 "register_operand" "0")]
17962 UNSPEC_LOAD_RIGHT))]
17963 - "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
17965 + && !ISA_HAS_UL_US
17966 + && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
17968 [(set_attr "move_type" "load")
17969 (set_attr "mode" "<MODE>")])
17970 @@ -3586,7 +3605,9 @@
17971 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
17972 (match_operand:QI 2 "memory_operand" "m")]
17973 UNSPEC_STORE_LEFT))]
17974 - "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
17976 + && !ISA_HAS_UL_US
17977 + && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
17979 [(set_attr "move_type" "store")
17980 (set_attr "mode" "<MODE>")])
17981 @@ -3602,6 +3623,28 @@
17982 [(set_attr "move_type" "store")
17983 (set_attr "mode" "<MODE>")])
17985 +;; Unaligned load and store patterns.
17987 +(define_insn "mov_u<load>"
17988 + [(set (match_operand:GPR 0 "register_operand" "=d")
17989 + (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
17990 + (match_operand:QI 2 "memory_operand" "m")]
17991 + UNSPEC_UNALIGNED_LOAD))]
17992 + "ISA_HAS_UL_US && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
17994 + [(set_attr "type" "load")
17995 + (set_attr "mode" "<MODE>")])
17997 +(define_insn "mov_u<store>"
17998 + [(set (match_operand:BLK 0 "memory_operand" "=m")
17999 + (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
18000 + (match_operand:QI 2 "memory_operand" "m")]
18001 + UNSPEC_UNALIGNED_STORE))]
18002 + "ISA_HAS_UL_US && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
18003 + "u<store>\t%z1,%2"
18004 + [(set_attr "type" "store")
18005 + (set_attr "mode" "<MODE>")])
18007 ;; An instruction to calculate the high part of a 64-bit SYMBOL_ABSOLUTE.
18008 ;; The required value is:
18010 @@ -5472,6 +5515,26 @@
18011 return "%*b\t%l0%/";
18014 + if (final_sequence && (mips_abi == ABI_32 || mips_abi == ABI_O64))
18016 + /* If the delay slot contains a $gp restore, we need to
18017 + do that first, because we need it for the load
18018 + label. Other ABIs do not have caller-save $gp. */
18019 + rtx next = NEXT_INSN (insn);
18020 + if (INSN_P (next) && !INSN_DELETED_P (next))
18022 + rtx pat = PATTERN (next);
18023 + if (GET_CODE (pat) == SET
18024 + && REG_P (SET_DEST (pat))
18025 + && REGNO (SET_DEST (pat)) == PIC_OFFSET_TABLE_REGNUM)
18028 + ops[0] = SET_DEST (pat);
18029 + ops[1] = SET_SRC (pat);
18030 + output_asm_insn (mips_output_move (ops[0], ops[1]), ops);
18034 output_asm_insn (mips_output_load_label (), operands);
18035 return "%*jr\t%@%/%]";
18037 @@ -5490,7 +5553,13 @@
18038 (lt (abs (minus (match_dup 0)
18039 (plus (pc) (const_int 4))))
18040 (const_int 131072)))
18041 - (const_int 4) (const_int 16)))])
18044 + ;; for these two ABIs we may need to move a restore of $gp
18045 + (ior (eq (symbol_ref "mips_abi") (symbol_ref "ABI_32"))
18046 + (eq (symbol_ref "mips_abi") (symbol_ref "ABI_O64")))
18048 + (const_int 16))))])
18050 ;; We need a different insn for the mips16, because a mips16 branch
18051 ;; does not have a delay slot.
18052 @@ -5679,6 +5748,60 @@
18053 [(set_attr "type" "jump")
18054 (set_attr "mode" "none")])
18056 +;; Exception return.
18057 +(define_insn "mips_eret"
18059 + (unspec_volatile [(const_int 0)] UNSPEC_ERET)]
18062 + [(set_attr "type" "trap")
18063 + (set_attr "mode" "none")])
18065 +;; Debug exception return.
18066 +(define_insn "mips_deret"
18068 + (unspec_volatile [(const_int 0)] UNSPEC_DERET)]
18071 + [(set_attr "type" "trap")
18072 + (set_attr "mode" "none")])
18074 +;; Disable interrupts.
18075 +(define_insn "mips_di"
18076 + [(unspec_volatile [(const_int 0)] UNSPEC_DI)]
18079 + [(set_attr "type" "trap")
18080 + (set_attr "mode" "none")])
18082 +;; Execution hazard barrier.
18083 +(define_insn "mips_ehb"
18084 + [(unspec_volatile [(const_int 0)] UNSPEC_EHB)]
18087 + [(set_attr "type" "trap")
18088 + (set_attr "mode" "none")])
18090 +;; Read GPR from previous shadow register set.
18091 +(define_insn "mips_rdpgpr"
18092 + [(set (match_operand:SI 0 "register_operand" "=d")
18093 + (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d")]
18097 + [(set_attr "type" "move")
18098 + (set_attr "mode" "SI")])
18100 +;; Move involving COP0 registers.
18101 +(define_insn "cop0_move"
18102 + [(set (match_operand:SI 0 "register_operand" "=B,d")
18103 + (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "d,B")]
18106 +{ return mips_output_move (operands[0], operands[1]); }
18107 + [(set_attr "type" "mtc,mfc")
18108 + (set_attr "mode" "SI")])
18110 ;; This is used in compiling the unwind routines.
18111 (define_expand "eh_return"
18112 [(use (match_operand 0 "general_operand"))]
18113 --- a/gcc/config/mips/mips.opt
18114 +++ b/gcc/config/mips/mips.opt
18115 @@ -184,6 +184,10 @@ mips16
18116 Target Report RejectNegative Mask(MIPS16)
18117 Generate MIPS16 code
18120 +Target Report RejectNegative Mask(MIPS16) MaskExists
18121 +Deprecated; alias for -mips16
18124 Target Report RejectNegative Mask(MIPS3D)
18125 Use MIPS-3D instructions
18126 @@ -236,6 +240,10 @@ mno-mips3d
18127 Target Report RejectNegative InverseMask(MIPS3D)
18128 Do not use MIPS-3D instructions
18131 +Target Report Mask(OCTEON_UNALIGNED)
18132 +Use Octeon-specific unaligned loads/stores for 32/64-bit data
18135 Target Report Mask(PAIRED_SINGLE_FLOAT)
18136 Use paired-single floating-point instructions
18138 +++ b/gcc/config/mips/octeon-elf-unwind.h
18140 +/* Stack unwinding support through the first exception frame.
18141 + Copyright (C) 2007 Cavium Networks.
18143 +This file is part of GCC.
18145 +GCC is free software; you can redistribute it and/or modify
18146 +it under the terms of the GNU General Public License as published by
18147 +the Free Software Foundation; either version 2, or (at your option)
18148 +any later version.
18150 +GCC is distributed in the hope that it will be useful,
18151 +but WITHOUT ANY WARRANTY; without even the implied warranty of
18152 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18153 +GNU General Public License for more details.
18155 +You should have received a copy of the GNU General Public License
18156 +along with GCC; see the file COPYING. If not, write to
18157 +the Free Software Foundation, 51 Franklin Street, Fifth Floor,
18158 +Boston, MA 02110-1301, USA. */
18160 +#define MD_FALLBACK_FRAME_STATE_FOR octeon_elf_fallback_frame_state
18162 +/* Check whether this is the cvmx_interrupt_stage2 frame. If the
18163 + function call was dispatched via k0 assume we are in
18164 + cvmx_interrupt_stage2. In this case the sp in point to the saved
18165 + register array. */
18167 +static _Unwind_Reason_Code
18168 +octeon_elf_fallback_frame_state (struct _Unwind_Context *context,
18169 + _Unwind_FrameState *fs)
18172 + unsigned *pc = context->ra;
18174 + /* Look for "jalr k0". */
18175 + if (pc[-2] != 0x0340f809)
18176 + return _URC_END_OF_STACK;
18178 + for (i = 0; i < 32; i++)
18180 + fs->regs.reg[i].how = REG_SAVED_OFFSET;
18181 + fs->regs.reg[i].loc.offset = 8 * i;
18184 + /* Keep the next frame's sp. This way we have a CFA that points
18185 + exactly to the register array. */
18186 + fs->regs.cfa_how = CFA_REG_OFFSET;
18187 + fs->regs.cfa_reg = STACK_POINTER_REGNUM;
18188 + fs->regs.cfa_offset = 0;
18190 + /* DEPC is saved as the 35. register. */
18191 + fs->regs.reg[DWARF_ALT_FRAME_RETURN_COLUMN].how = REG_SAVED_OFFSET;
18192 + fs->regs.reg[DWARF_ALT_FRAME_RETURN_COLUMN].loc.offset = 8 * 35;
18193 + fs->retaddr_column = DWARF_ALT_FRAME_RETURN_COLUMN;
18195 + return _URC_NO_REASON;
18198 +++ b/gcc/config/mips/octeon-elf.h
18200 +/* Macros for mips*-octeon-elf target.
18201 + Copyright (C) 2004, 2005, 2006 Cavium Networks.
18203 +This file is part of GCC.
18205 +GCC is free software; you can redistribute it and/or modify
18206 +it under the terms of the GNU General Public License as published by
18207 +the Free Software Foundation; either version 2, or (at your option)
18208 +any later version.
18210 +GCC is distributed in the hope that it will be useful,
18211 +but WITHOUT ANY WARRANTY; without even the implied warranty of
18212 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18213 +GNU General Public License for more details.
18215 +You should have received a copy of the GNU General Public License
18216 +along with GCC; see the file COPYING. If not, write to
18217 +the Free Software Foundation, 51 Franklin Street, Fifth Floor,
18218 +Boston, MA 02110-1301, USA. */
18220 +/* Add MASK_SOFT_FLOAT and MASK_OCTEON_UNALIGNED. */
18222 +#undef TARGET_DEFAULT
18223 +#define TARGET_DEFAULT (MASK_SOFT_FLOAT_ABI | MASK_OCTEON_UNALIGNED)
18225 +/* Forward -m*octeon-useun. */
18227 +#undef SUBTARGET_ASM_SPEC
18228 +#define SUBTARGET_ASM_SPEC "%{mno-octeon-useun} %{!mno-octeon-useun:-mocteon-useun}"
18230 +/* Enable backtrace including on machine exceptions by default. */
18232 +#undef SUBTARGET_CC1_SPEC
18233 +#define SUBTARGET_CC1_SPEC "%{!fno-asynchronous-unwind-tables:-fasynchronous-unwind-tables}"
18235 +/* Without ASM_PREFERRED_EH_DATA_FORMAT, output_call_frame_info emits
18236 + pointer-sized addresses for FDE addresses. For 64-bit targets, it does
18237 + it without properly "switching over" to 64-bit as described in the DWARF3
18238 + spec. GDB can fall back on .eh_frames and misinterpret FDE addresses.
18239 + Instead let's be explicit and use augmentation to describe the encoding if
18240 + pointer size is 64. */
18242 +#undef ASM_PREFERRED_EH_DATA_FORMAT
18243 +#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
18244 + ((CODE) == 1 && POINTER_SIZE == 64 \
18245 + ? (ABI_HAS_64BIT_SYMBOLS ? DW_EH_PE_udata8 : DW_EH_PE_udata4) \
18246 + : DW_EH_PE_absptr)
18248 +/* Link to libc library. */
18251 +#define LIB_SPEC "-lc"
18253 +/* Link to startup file. */
18255 +#undef STARTFILE_SPEC
18256 +#define STARTFILE_SPEC "crti%O%s crtbegin%O%s crt0%O%s"
18258 +/* Default our test-only n64 configuration to -G0 since that is what
18259 + the kernel uses. */
18261 +#undef SUBTARGET_SELF_SPECS
18262 +#define SUBTARGET_SELF_SPECS \
18263 +"%{mabi=64:%{!G*: -G0}}"
18265 +/* Pass linker emulation mode for N32. */
18268 +#define LINK_SPEC "\
18270 +%{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
18271 +%{mips64r2} %{bestGnum} %{shared} %{non_shared} \
18272 +%{mabi=n32:-melf32e%{!EL:b}%{EL:l}octeonn32} \
18273 +%{mabi=64:-melf64e%{!EL:b}%{EL:l}octeon}"
18275 +/* Override because of N32. */
18277 +#undef LOCAL_LABEL_PREFIX
18278 +#define LOCAL_LABEL_PREFIX ((mips_abi == ABI_N32) ? "." : "$")
18280 +/* Append the core number to the GCOV filename FN. */
18282 +#define GCOV_TARGET_SUFFIX_LENGTH 2
18283 +#define ADD_GCOV_TARGET_SUFFIX(FN) \
18290 + asm ("rdhwr %0, $0" : "=r"(core)); \
18291 + sprintf (s, "%d", core); \
18292 + strcat (fn, s); \
18296 +/* Code to unwind through the exception frame. */
18297 +#define MD_UNWIND_SUPPORT "config/mips/octeon-elf-unwind.h"
18299 +++ b/gcc/config/mips/octeon.h
18301 +/* Macros for mips*-octeon-* target.
18302 + Copyright (C) 2004, 2005, 2006 Cavium Networks.
18304 +This file is part of GCC.
18306 +GCC is free software; you can redistribute it and/or modify
18307 +it under the terms of the GNU General Public License as published by
18308 +the Free Software Foundation; either version 2, or (at your option)
18309 +any later version.
18311 +GCC is distributed in the hope that it will be useful,
18312 +but WITHOUT ANY WARRANTY; without even the implied warranty of
18313 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18314 +GNU General Public License for more details.
18316 +You should have received a copy of the GNU General Public License
18317 +along with GCC; see the file COPYING. If not, write to
18318 +the Free Software Foundation, 51 Franklin Street, Fifth Floor,
18319 +Boston, MA 02110-1301, USA. */
18321 +#define CVMX_SHARED_BSS_FLAGS (SECTION_WRITE | SECTION_BSS)
18323 +#undef TARGET_ASM_SELECT_SECTION
18324 +#define TARGET_ASM_SELECT_SECTION octeon_select_section
18326 +#undef TARGET_ASM_UNIQUE_SECTION
18327 +#define TARGET_ASM_UNIQUE_SECTION octeon_unique_section
18329 +/* Implement ASM_OUTPUT_ALIGNED_DECL_LOCAL. This differs from the
18330 + generic version only in the use of cvmx_shared attribute. */
18332 +#undef ASM_OUTPUT_ALIGNED_DECL_LOCAL
18333 +#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGN) \
18336 + if ((DECL) && TREE_CODE ((DECL)) == VAR_DECL \
18337 + && lookup_attribute ("cvmx_shared", DECL_ATTRIBUTES (DECL))) \
18339 + fprintf ((STREAM), "%s", LOCAL_ASM_OP); \
18340 + assemble_name ((STREAM), (NAME)); \
18341 + fprintf ((STREAM), "\n"); \
18342 + octeon_output_shared_variable ((STREAM), (DECL), (NAME), \
18343 + (SIZE), (ALIGN)); \
18346 + ASM_OUTPUT_ALIGNED_LOCAL (STREAM, NAME, SIZE, ALIGN); \
18351 +/* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This differs from the mips
18352 + version only in the use of cvmx_shared attribute. */
18354 +#undef ASM_OUTPUT_ALIGNED_DECL_COMMON
18355 +#define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
18357 + if (TREE_CODE ((DECL)) == VAR_DECL \
18358 + && lookup_attribute ("cvmx_shared", DECL_ATTRIBUTES ((DECL)))) \
18360 + if (TREE_PUBLIC ((DECL)) && DECL_NAME ((DECL))) \
18361 + targetm.asm_out.globalize_label (asm_out_file, (NAME)); \
18362 + octeon_output_shared_variable ((STREAM), (DECL), (NAME), \
18363 + (SIZE), (ALIGN)); \
18366 + mips_output_aligned_decl_common ((STREAM), (DECL), (NAME), (SIZE), \
18369 --- a/gcc/config/mips/predicates.md
18370 +++ b/gcc/config/mips/predicates.md
18371 @@ -211,6 +211,20 @@
18375 +(define_predicate "mask_low_and_shift_operator"
18376 + (and (match_code "and")
18377 + (match_test "GET_CODE (XEXP (op, 0)) == ASHIFT
18378 + && GET_CODE (XEXP (op, 1)) == CONST_INT
18379 + && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT"))
18383 + len = mask_low_and_shift_len (GET_MODE (op),
18384 + INTVAL (XEXP (XEXP (op, 0), 1)),
18385 + INTVAL (XEXP (op, 1)));
18386 + return 0 < len && len <= 32;
18389 (define_predicate "consttable_operand"
18390 (match_test "CONSTANT_P (op)"))
18392 --- a/gcc/config/mips/sde.h
18393 +++ b/gcc/config/mips/sde.h
18394 @@ -19,6 +19,9 @@ You should have received a copy of the G
18395 along with GCC; see the file COPYING3. If not see
18396 <http://www.gnu.org/licenses/>. */
18398 +#undef TARGET_MIPS_SDE
18399 +#define TARGET_MIPS_SDE 1
18401 #undef DRIVER_SELF_SPECS
18402 #define DRIVER_SELF_SPECS \
18403 /* Make sure a -mips option is present. This helps us to pick \
18404 @@ -90,7 +93,8 @@ along with GCC; see the file COPYING3.
18406 /* Use $5 as a temporary for both MIPS16 and non-MIPS16. */
18407 #undef MIPS_EPILOGUE_TEMP_REGNUM
18408 -#define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + 5)
18409 +#define MIPS_EPILOGUE_TEMP_REGNUM \
18410 + (cfun->machine->interrupt_handler_p ? K0_REG_NUM : GP_REG_FIRST + 5)
18412 /* Using long will always be right for size_t and ptrdiff_t, since
18413 sizeof(long) must equal sizeof(void *), following from the setting
18414 --- a/gcc/config/mips/sdemtk.h
18415 +++ b/gcc/config/mips/sdemtk.h
18416 @@ -19,6 +19,8 @@ You should have received a copy of the G
18417 along with GCC; see the file COPYING3. If not see
18418 <http://www.gnu.org/licenses/>. */
18420 +#define TARGET_MIPS_SDEMTK 1
18422 #define TARGET_OS_CPP_BUILTINS() \
18425 @@ -113,3 +115,12 @@ extern void mips_sync_icache (void *beg,
18426 /* ...nor does the call sequence preserve $31. */
18427 #undef MIPS_SAVE_REG_FOR_PROFILING_P
18428 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) ((REGNO) == GP_REG_FIRST + 31)
18430 +/* From mips.h, with mno-float option added. */
18432 +#undef MIPS_ARCH_FLOAT_SPEC
18433 +#define MIPS_ARCH_FLOAT_SPEC \
18434 + "%{mhard-float|msoft-float|mno-float|march=mips*:; \
18435 + march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
18436 + |march=34kc|march=74kc|march=1004kc|march=5kc|march=octeon|march=xlr: -msoft-float; \
18437 + march=*: -mhard-float}"
18439 +++ b/gcc/config/mips/t-crtfm
18442 +EXTRA_MULTILIB_PARTS += crtfastmath.o
18444 +EXTRA_PARTS += crtfastmath.o
18446 +$(T)crtfastmath.o: $(srcdir)/config/mips/crtfastmath.c $(GCC_PASSES)
18447 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
18448 + -c -o $(T)crtfastmath.o $(srcdir)/config/mips/crtfastmath.c
18451 +++ b/gcc/config/mips/t-octeon-elf
18453 +# Don't let CTOR_LIST end up in sdata section.
18455 +CRTSTUFF_T_CFLAGS = -G 0 -fno-asynchronous-unwind-tables
18457 +# Assemble startup files.
18459 +$(T)crti.o: $(srcdir)/config/mips/crti.asm $(GCC_PASSES)
18460 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
18461 + -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/mips/crti.asm
18463 +$(T)crtn.o: $(srcdir)/config/mips/crtn.asm $(GCC_PASSES)
18464 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
18465 + -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/mips/crtn.asm
18467 +# N32 uses TFmode for long double.
18471 +tp-bit.c: $(srcdir)/config/fp-bit.c
18472 + echo '#ifdef __MIPSEL__' > tp-bit.c
18473 + echo '# define FLOAT_BIT_ORDER_MISMATCH' >> tp-bit.c
18474 + echo '#endif' >> tp-bit.c
18475 + echo '#if __LDBL_MANT_DIG__ == 113' >> tp-bit.c
18476 + echo '#define QUIET_NAN_NEGATED' >> tp-bit.c
18477 + echo '# define TFLOAT' >> tp-bit.c
18478 + cat $(srcdir)/config/fp-bit.c >> tp-bit.c
18479 + echo '#endif' >> tp-bit.c
18481 +# We must build libgcc2.a with -G 0, in case the user wants to link
18482 +# without the $gp register.
18484 +TARGET_LIBGCC2_CFLAGS = -G 0
18486 +# Build both ABIs.
18488 +MULTILIB_OPTIONS = mabi=n32/mabi=eabi/mabi=64
18489 +MULTILIB_DIRNAMES = n32 eabi n64
18490 +EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o
18492 +LIBGCC = stmp-multilib
18493 +INSTALL_LIBGCC = install-multilib
18494 --- a/gcc/config/mips/xlr.md
18495 +++ b/gcc/config/mips/xlr.md
18497 ;; DFA-based pipeline description for the XLR.
18498 -;; Copyright (C) 2008 Free Software Foundation, Inc.
18499 +;; Copyright (C) 2008, 2009 Free Software Foundation, Inc.
18501 ;; xlr.md Machine Description for the RMI XLR Microprocessor
18502 ;; This file is part of GCC.
18504 ;; Integer arithmetic instructions.
18505 (define_insn_reservation "ir_xlr_alu" 1
18506 (and (eq_attr "cpu" "xlr")
18507 - (eq_attr "type" "arith,shift,clz,const,unknown,multi,nop,trap"))
18508 + (eq_attr "type" "move,arith,shift,clz,logical,signext,const,unknown,multi,nop,trap"))
18511 ;; Integer arithmetic instructions.
18513 +++ b/gcc/config/rs6000/e500mc.h
18515 +/* Core target definitions for GNU compiler
18516 + for IBM RS/6000 PowerPC targeted to embedded ELF systems.
18517 + Copyright (C) 1995, 1996, 2000, 2003, 2004, 2007 Free Software Foundation, Inc.
18518 + Contributed by Cygnus Support.
18520 + This file is part of GCC.
18522 + GCC is free software; you can redistribute it and/or modify it
18523 + under the terms of the GNU General Public License as published
18524 + by the Free Software Foundation; either version 3, or (at your
18525 + option) any later version.
18527 + GCC is distributed in the hope that it will be useful, but WITHOUT
18528 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18529 + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18530 + License for more details.
18532 + You should have received a copy of the GNU General Public License
18533 + along with GCC; see the file COPYING3. If not see
18534 + <http://www.gnu.org/licenses/>. */
18536 +/* Add -meabi to target flags. */
18537 +#undef TARGET_DEFAULT
18538 +#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_EABI)
18540 +#undef TARGET_VERSION
18541 +#define TARGET_VERSION fprintf (stderr, " (PowerPC Embedded)");
18543 +#undef TARGET_OS_CPP_BUILTINS
18544 +#define TARGET_OS_CPP_BUILTINS() \
18547 + builtin_define_std ("PPC"); \
18548 + builtin_define ("__embedded__"); \
18549 + builtin_assert ("system=embedded"); \
18550 + builtin_assert ("cpu=powerpc"); \
18551 + builtin_assert ("machine=powerpc"); \
18552 + TARGET_OS_SYSV_CPP_BUILTINS (); \
18556 +#undef CC1_EXTRA_SPEC
18557 +#define CC1_EXTRA_SPEC "-maix-struct-return"
18559 +#undef ASM_DEFAULT_SPEC
18560 +#define ASM_DEFAULT_SPEC "-mppc%{m64:64} -me500mc"
18561 --- a/gcc/config/rs6000/eabi-ci.asm
18562 +++ b/gcc/config/rs6000/eabi-ci.asm
18563 @@ -98,6 +98,7 @@ __EH_FRAME_BEGIN__:
18564 /* Head of __init function used for static constructors. */
18565 .section ".init","ax"
18571 @@ -106,6 +107,7 @@ FUNC_START(__init)
18572 /* Head of __fini function used for static destructors. */
18573 .section ".fini","ax"
18579 --- a/gcc/config/rs6000/eabi.asm
18580 +++ b/gcc/config/rs6000/eabi.asm
18581 @@ -230,7 +230,7 @@ FUNC_END(__eabi)
18582 r11 has the address of .LCTOC1 in it.
18583 r12 has the value to add to each pointer
18584 r13 .. r31 are unchanged */
18586 +#ifdef _RELOCATABLE
18587 FUNC_START(__eabi_convert)
18588 cmplw 1,3,4 /* any pointers to convert? */
18589 subf 5,3,4 /* calculate number of words to convert */
18590 @@ -285,5 +285,5 @@ FUNC_START(__eabi_uconvert)
18593 FUNC_END(__eabi_uconvert)
18597 --- a/gcc/config/rs6000/eabi.h
18598 +++ b/gcc/config/rs6000/eabi.h
18600 #undef TARGET_DEFAULT
18601 #define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_EABI)
18603 -/* Invoke an initializer function to set up the GOT. */
18604 -#define NAME__MAIN "__eabi"
18605 -#define INVOKE__main
18607 #undef TARGET_VERSION
18608 #define TARGET_VERSION fprintf (stderr, " (PowerPC Embedded)");
18611 TARGET_OS_SYSV_CPP_BUILTINS (); \
18615 +/* Add -te500v1 and -te500v2 options for convenience in generating
18617 +#undef CC1_EXTRA_SPEC
18618 +#define CC1_EXTRA_SPEC \
18619 + "%{te500v1: -mcpu=8540 -mfloat-gprs=single -mspe=yes -mabi=spe} " \
18620 + "%{te500v2: -mcpu=8548 -mfloat-gprs=double -mspe=yes -mabi=spe} " \
18621 + "%{te600: -mcpu=7400 -maltivec -mabi=altivec}" \
18622 + "%{te500mc: -mcpu=e500mc -maix-struct-return}"
18624 +#undef ASM_DEFAULT_SPEC
18625 +#define ASM_DEFAULT_SPEC \
18626 + "%{te500v1:-mppc -mspe -me500 ; \
18627 + te500v2:-mppc -mspe -me500 ; \
18628 + te600:-mppc -maltivec ; \
18629 + te500mc:-mppc -me500mc ; \
18630 + :-mppc%{m64:64}}"
18631 --- a/gcc/config/rs6000/linux.h
18632 +++ b/gcc/config/rs6000/linux.h
18633 @@ -128,3 +128,29 @@
18634 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
18635 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 128
18638 +/* Add -te500v1 and -te500v2 options for convenience in generating
18640 +#undef CC1_EXTRA_SPEC
18641 +#define CC1_EXTRA_SPEC \
18642 + "%{te500v1: -mcpu=8540 -mfloat-gprs=single -mspe=yes -mabi=spe} " \
18643 + "%{te500v2: -mcpu=8548 -mfloat-gprs=double -mspe=yes -mabi=spe} " \
18644 + "%{te600: -mcpu=7400 -maltivec -mabi=altivec}" \
18645 + "%{te500mc: -mcpu=e500mc}"
18647 +#undef ASM_DEFAULT_SPEC
18648 +#define ASM_DEFAULT_SPEC \
18649 + "%{te500v1:-mppc -mspe -me500 ; \
18650 + te500v2:-mppc -mspe -me500 ; \
18651 + te600:-mppc -maltivec ; \
18652 + te500mc:-me500mc ; \
18653 + :-mppc%{m64:64}}"
18655 +/* The various C libraries each have their own subdirectory. */
18656 +#undef SYSROOT_SUFFIX_SPEC
18657 +#define SYSROOT_SUFFIX_SPEC \
18658 + "%{msoft-float:/nof ; \
18660 + te500v1:/te500v1 ; \
18661 + te500v2:/te500v2 ; \
18662 + te500mc:/te500mc}"
18664 +++ b/gcc/config/rs6000/option-defaults.h
18666 +/* Definitions of default options for config/rs6000 configurations.
18667 + Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
18668 + 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
18669 + Free Software Foundation, Inc.
18671 + This file is part of GCC.
18673 + GCC is free software; you can redistribute it and/or modify it
18674 + under the terms of the GNU General Public License as published
18675 + by the Free Software Foundation; either version 3, or (at your
18676 + option) any later version.
18678 + GCC is distributed in the hope that it will be useful, but WITHOUT
18679 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
18680 + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18681 + License for more details.
18683 + Under Section 7 of GPL version 3, you are granted additional
18684 + permissions described in the GCC Runtime Library Exception, version
18685 + 3.1, as published by the Free Software Foundation.
18687 + You should have received a copy of the GNU General Public License and
18688 + a copy of the GCC Runtime Library Exception along with this program;
18689 + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
18690 + <http://www.gnu.org/licenses/>. */
18692 +/* This header needs to be included after any other headers affecting
18693 + TARGET_DEFAULT. */
18696 +#define OPT_64 "maix64"
18697 +#define OPT_32 "maix32"
18699 +#define OPT_64 "m64"
18700 +#define OPT_32 "m32"
18703 +#ifndef MASK_64BIT
18704 +#define MASK_64BIT 0
18707 +#if TARGET_DEFAULT & MASK_64BIT
18708 +#define OPT_ARCH64 "!"OPT_32
18709 +#define OPT_ARCH32 OPT_32
18711 +#define OPT_ARCH64 OPT_64
18712 +#define OPT_ARCH32 "!"OPT_64
18715 +/* Support for a compile-time default CPU, et cetera. The rules are:
18716 + --with-cpu is ignored if -mcpu is specified; likewise --with-cpu-32
18717 + and --with-cpu-64.
18718 + --with-tune is ignored if -mtune is specified; likewise --with-tune-32
18719 + and --with-tune-64.
18720 + --with-float is ignored if -mhard-float or -msoft-float are
18722 +#define OPTION_DEFAULT_SPECS \
18723 + {"cpu", "%{mcpu=*|te500mc|te500v1|te500v2|te600:;:-mcpu=%(VALUE)}" }, \
18724 + {"cpu_32", "%{" OPT_ARCH32 ":%{mcpu=*|te500mc|te500v1|te500v2|te600:;:-mcpu=%(VALUE)}}" }, \
18725 + {"cpu_64", "%{" OPT_ARCH64 ":%{mcpu=*|te500mc|te500v1|te500v2|te600:;:-mcpu=%(VALUE)}}" }, \
18726 + {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
18727 + {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
18728 + {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:-mtune=%(VALUE)}}" }, \
18729 + {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
18730 --- a/gcc/config/rs6000/paired.md
18731 +++ b/gcc/config/rs6000/paired.md
18733 (UNSPEC_EXTODD_V2SF 333)
18736 -(define_insn "negv2sf2"
18737 +(define_insn "paired_negv2sf2"
18738 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
18739 (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
18740 "TARGET_PAIRED_FLOAT"
18743 [(set_attr "type" "fp")])
18745 -(define_insn "absv2sf2"
18746 +(define_insn "paired_absv2sf2"
18747 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
18748 (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")))]
18749 "TARGET_PAIRED_FLOAT"
18752 [(set_attr "type" "fp")])
18754 -(define_insn "addv2sf3"
18755 +(define_insn "paired_addv2sf3"
18756 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
18757 (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f")
18758 (match_operand:V2SF 2 "gpc_reg_operand" "f")))]
18761 [(set_attr "type" "fp")])
18763 -(define_insn "subv2sf3"
18764 +(define_insn "paired_subv2sf3"
18765 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
18766 (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
18767 (match_operand:V2SF 2 "gpc_reg_operand" "f")))]
18770 [(set_attr "type" "fp")])
18772 -(define_insn "mulv2sf3"
18773 +(define_insn "paired_mulv2sf3"
18774 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
18775 (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "%f")
18776 (match_operand:V2SF 2 "gpc_reg_operand" "f")))]
18779 [(set_attr "type" "fp")])
18781 -(define_insn "divv2sf3"
18782 +(define_insn "paired_divv2sf3"
18783 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=f")
18784 (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "f")
18785 (match_operand:V2SF 2 "gpc_reg_operand" "f")))]
18786 --- a/gcc/config/rs6000/rs6000.c
18787 +++ b/gcc/config/rs6000/rs6000.c
18788 @@ -919,6 +919,7 @@ int easy_vector_constant (rtx, enum mach
18789 static bool rs6000_is_opaque_type (const_tree);
18790 static rtx rs6000_dwarf_register_span (rtx);
18791 static void rs6000_init_dwarf_reg_sizes_extra (tree);
18792 +static int rs6000_commutative_operand_precedence (const_rtx, int);
18793 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
18794 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
18795 static rtx rs6000_tls_get_addr (void);
18796 @@ -1194,6 +1195,10 @@ static const char alt_reg_names[][8] =
18797 #undef TARGET_VECTOR_OPAQUE_P
18798 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
18800 +#undef TARGET_COMMUTATIVE_OPERAND_PRECEDENCE
18801 +#define TARGET_COMMUTATIVE_OPERAND_PRECEDENCE \
18802 + rs6000_commutative_operand_precedence
18804 #undef TARGET_DWARF_REGISTER_SPAN
18805 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
18807 @@ -4708,16 +4713,19 @@ rs6000_conditional_register_usage (void)
18808 if (TARGET_ALTIVEC)
18809 global_regs[VSCR_REGNO] = 1;
18811 - if (TARGET_ALTIVEC_ABI)
18813 - for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
18814 - call_used_regs[i] = call_really_used_regs[i] = 1;
18815 + /* If we are not using the AltiVec ABI, pretend that the normally
18816 + call-saved registers are also call-used. We could use them
18817 + normally if we saved and restored them in the prologue; that
18818 + would require using the alignment padding around the register
18819 + save area, and some care with unwinding information. */
18820 + if (! TARGET_ALTIVEC_ABI)
18821 + for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
18822 + call_used_regs[i] = call_really_used_regs[i] = 1;
18824 - /* AIX reserves VR20:31 in non-extended ABI mode. */
18825 - if (TARGET_XCOFF)
18826 - for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
18827 - fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
18829 + if (TARGET_ALTIVEC_ABI && TARGET_XCOFF)
18830 + /* AIX reserves VR20:31 in non-extended ABI mode. */
18831 + for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
18832 + fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
18835 /* Try to output insns to set TARGET equal to the constant C if it can
18836 @@ -7533,10 +7541,10 @@ static struct builtin_description bdesc_
18837 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
18838 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
18840 - { 0, CODE_FOR_divv2sf3, "__builtin_paired_divv2sf3", PAIRED_BUILTIN_DIVV2SF3 },
18841 - { 0, CODE_FOR_addv2sf3, "__builtin_paired_addv2sf3", PAIRED_BUILTIN_ADDV2SF3 },
18842 - { 0, CODE_FOR_subv2sf3, "__builtin_paired_subv2sf3", PAIRED_BUILTIN_SUBV2SF3 },
18843 - { 0, CODE_FOR_mulv2sf3, "__builtin_paired_mulv2sf3", PAIRED_BUILTIN_MULV2SF3 },
18844 + { 0, CODE_FOR_paired_divv2sf3, "__builtin_paired_divv2sf3", PAIRED_BUILTIN_DIVV2SF3 },
18845 + { 0, CODE_FOR_paired_addv2sf3, "__builtin_paired_addv2sf3", PAIRED_BUILTIN_ADDV2SF3 },
18846 + { 0, CODE_FOR_paired_subv2sf3, "__builtin_paired_subv2sf3", PAIRED_BUILTIN_SUBV2SF3 },
18847 + { 0, CODE_FOR_paired_mulv2sf3, "__builtin_paired_mulv2sf3", PAIRED_BUILTIN_MULV2SF3 },
18848 { 0, CODE_FOR_paired_muls0, "__builtin_paired_muls0", PAIRED_BUILTIN_MULS0 },
18849 { 0, CODE_FOR_paired_muls1, "__builtin_paired_muls1", PAIRED_BUILTIN_MULS1 },
18850 { 0, CODE_FOR_paired_merge00, "__builtin_paired_merge00", PAIRED_BUILTIN_MERGE00 },
18851 @@ -7545,10 +7553,10 @@ static struct builtin_description bdesc_
18852 { 0, CODE_FOR_paired_merge11, "__builtin_paired_merge11", PAIRED_BUILTIN_MERGE11 },
18854 /* Place holder, leave as first spe builtin. */
18855 - { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
18856 - { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
18857 + { 0, CODE_FOR_addv2si3, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
18858 + { 0, CODE_FOR_andv2si3, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
18859 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
18860 - { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
18861 + { 0, CODE_FOR_divv2si3, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
18862 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
18863 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
18864 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
18865 @@ -7824,7 +7832,7 @@ static struct builtin_description bdesc_
18867 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
18868 end with SPE_BUILTIN_EVSUBFUSIAAW. */
18869 - { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
18870 + { 0, CODE_FOR_absv2si2, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
18871 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
18872 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
18873 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
18874 @@ -7856,9 +7864,9 @@ static struct builtin_description bdesc_
18875 /* Place-holder. Leave as last unary SPE builtin. */
18876 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
18878 - { 0, CODE_FOR_absv2sf2, "__builtin_paired_absv2sf2", PAIRED_BUILTIN_ABSV2SF2 },
18879 + { 0, CODE_FOR_paired_absv2sf2, "__builtin_paired_absv2sf2", PAIRED_BUILTIN_ABSV2SF2 },
18880 { 0, CODE_FOR_nabsv2sf2, "__builtin_paired_nabsv2sf2", PAIRED_BUILTIN_NABSV2SF2 },
18881 - { 0, CODE_FOR_negv2sf2, "__builtin_paired_negv2sf2", PAIRED_BUILTIN_NEGV2SF2 },
18882 + { 0, CODE_FOR_paired_negv2sf2, "__builtin_paired_negv2sf2", PAIRED_BUILTIN_NEGV2SF2 },
18883 { 0, CODE_FOR_sqrtv2sf2, "__builtin_paired_sqrtv2sf2", PAIRED_BUILTIN_SQRTV2SF2 },
18884 { 0, CODE_FOR_resv2sf2, "__builtin_paired_resv2sf2", PAIRED_BUILTIN_RESV2SF2 }
18886 @@ -9396,6 +9404,8 @@ build_opaque_vector_type (tree node, int
18888 rs6000_init_builtins (void)
18892 V2SI_type_node = build_vector_type (intSI_type_node, 2);
18893 V2SF_type_node = build_vector_type (float_type_node, 2);
18894 V4HI_type_node = build_vector_type (intHI_type_node, 4);
18895 @@ -9433,60 +9443,75 @@ rs6000_init_builtins (void)
18896 float_type_internal_node = float_type_node;
18897 void_type_internal_node = void_type_node;
18899 - (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
18900 - get_identifier ("__bool char"),
18901 - bool_char_type_node));
18902 - (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
18903 - get_identifier ("__bool short"),
18904 - bool_short_type_node));
18905 - (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
18906 - get_identifier ("__bool int"),
18907 - bool_int_type_node));
18908 - (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
18909 - get_identifier ("__pixel"),
18910 - pixel_type_node));
18911 + tdecl = build_decl (TYPE_DECL, get_identifier ("__bool char"),
18912 + bool_char_type_node);
18913 + TYPE_NAME (bool_char_type_node) = tdecl;
18914 + (*lang_hooks.decls.pushdecl) (tdecl);
18915 + tdecl = build_decl (TYPE_DECL, get_identifier ("__bool short"),
18916 + bool_short_type_node);
18917 + TYPE_NAME (bool_short_type_node) = tdecl;
18918 + (*lang_hooks.decls.pushdecl) (tdecl);
18919 + tdecl = build_decl (TYPE_DECL, get_identifier ("__bool int"),
18920 + bool_int_type_node);
18921 + TYPE_NAME (bool_int_type_node) = tdecl;
18922 + (*lang_hooks.decls.pushdecl) (tdecl);
18923 + tdecl = build_decl (TYPE_DECL, get_identifier ("__pixel"),
18924 + pixel_type_node);
18925 + TYPE_NAME (pixel_type_node) = tdecl;
18926 + (*lang_hooks.decls.pushdecl) (tdecl);
18928 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
18929 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
18930 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
18931 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
18933 - (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
18934 - get_identifier ("__vector unsigned char"),
18935 - unsigned_V16QI_type_node));
18936 - (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
18937 - get_identifier ("__vector signed char"),
18938 - V16QI_type_node));
18939 - (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
18940 - get_identifier ("__vector __bool char"),
18941 - bool_V16QI_type_node));
18943 - (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
18944 - get_identifier ("__vector unsigned short"),
18945 - unsigned_V8HI_type_node));
18946 - (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
18947 - get_identifier ("__vector signed short"),
18948 - V8HI_type_node));
18949 - (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
18950 - get_identifier ("__vector __bool short"),
18951 - bool_V8HI_type_node));
18953 - (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
18954 - get_identifier ("__vector unsigned int"),
18955 - unsigned_V4SI_type_node));
18956 - (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
18957 - get_identifier ("__vector signed int"),
18958 - V4SI_type_node));
18959 - (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
18960 - get_identifier ("__vector __bool int"),
18961 - bool_V4SI_type_node));
18963 - (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
18964 - get_identifier ("__vector float"),
18965 - V4SF_type_node));
18966 - (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
18967 - get_identifier ("__vector __pixel"),
18968 - pixel_V8HI_type_node));
18969 + tdecl = build_decl (TYPE_DECL, get_identifier ("__vector unsigned char"),
18970 + unsigned_V16QI_type_node);
18971 + TYPE_NAME (unsigned_V16QI_type_node) = tdecl;
18972 + (*lang_hooks.decls.pushdecl) (tdecl);
18973 + tdecl = build_decl (TYPE_DECL, get_identifier ("__vector signed char"),
18974 + V16QI_type_node);
18975 + TYPE_NAME (V16QI_type_node) = tdecl;
18976 + (*lang_hooks.decls.pushdecl) (tdecl);
18977 + tdecl = build_decl (TYPE_DECL, get_identifier ("__vector __bool char"),
18978 + bool_V16QI_type_node);
18979 + TYPE_NAME ( bool_V16QI_type_node) = tdecl;
18980 + (*lang_hooks.decls.pushdecl) (tdecl);
18982 + tdecl = build_decl (TYPE_DECL, get_identifier ("__vector unsigned short"),
18983 + unsigned_V8HI_type_node);
18984 + TYPE_NAME (unsigned_V8HI_type_node) = tdecl;
18985 + (*lang_hooks.decls.pushdecl) (tdecl);
18986 + tdecl = build_decl (TYPE_DECL, get_identifier ("__vector signed short"),
18988 + TYPE_NAME (V8HI_type_node) = tdecl;
18989 + (*lang_hooks.decls.pushdecl) (tdecl);
18990 + tdecl = build_decl (TYPE_DECL, get_identifier ("__vector __bool short"),
18991 + bool_V8HI_type_node);
18992 + TYPE_NAME (bool_V8HI_type_node) = tdecl;
18993 + (*lang_hooks.decls.pushdecl) (tdecl);
18995 + tdecl = build_decl (TYPE_DECL, get_identifier ("__vector unsigned int"),
18996 + unsigned_V4SI_type_node);
18997 + TYPE_NAME (unsigned_V4SI_type_node) = tdecl;
18998 + (*lang_hooks.decls.pushdecl) (tdecl);
18999 + tdecl = build_decl (TYPE_DECL, get_identifier ("__vector signed int"),
19001 + TYPE_NAME (V4SI_type_node) = tdecl;
19002 + (*lang_hooks.decls.pushdecl) (tdecl);
19003 + tdecl = build_decl (TYPE_DECL, get_identifier ("__vector __bool int"),
19004 + bool_V4SI_type_node);
19005 + TYPE_NAME (bool_V4SI_type_node) = tdecl;
19006 + (*lang_hooks.decls.pushdecl) (tdecl);
19008 + tdecl = build_decl (TYPE_DECL, get_identifier ("__vector float"),
19010 + TYPE_NAME (V4SF_type_node) = tdecl;
19011 + (*lang_hooks.decls.pushdecl) (tdecl);
19012 + tdecl = build_decl (TYPE_DECL, get_identifier ("__vector __pixel"),
19013 + pixel_V8HI_type_node);
19014 + TYPE_NAME (pixel_V8HI_type_node) = tdecl;
19015 + (*lang_hooks.decls.pushdecl) (tdecl);
19017 if (TARGET_PAIRED_FLOAT)
19018 paired_init_builtins ();
19019 @@ -15869,7 +15894,7 @@ static bool
19020 no_global_regs_above (int first, bool gpr)
19023 - for (i = first; i < gpr ? 32 : 64 ; i++)
19024 + for (i = first; i < (gpr ? 32 : 64); i++)
19025 if (global_regs[i])
19028 @@ -15895,11 +15920,11 @@ rs6000_savres_routine_sym (rs6000_stack_
19029 int regno = gpr ? info->first_gp_reg_save : (info->first_fp_reg_save - 32);
19031 int select = ((savep ? 1 : 0) << 2
19033 + | (TARGET_SPE_ABI
19034 /* On the SPE, we never have any FPRs, but we do have
19035 32/64-bit versions of the routines. */
19036 - ? (TARGET_SPE_ABI && info->spe_64bit_regs_used ? 1 : 0)
19038 + ? (info->spe_64bit_regs_used ? 1 : 0)
19039 + : (gpr ? 1 : 0)) << 1
19042 /* Don't generate bogus routine names. */
19043 @@ -15934,6 +15959,7 @@ rs6000_savres_routine_sym (rs6000_stack_
19045 sym = savres_routine_syms[regno-FIRST_SAVRES_REGISTER][select]
19046 = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name));
19047 + SYMBOL_REF_FLAGS (sym) |= SYMBOL_FLAG_FUNCTION;
19051 @@ -16124,6 +16150,14 @@ rs6000_savres_strategy (rs6000_stack_t *
19052 savres_gprs_inline = savres_gprs_inline || using_multiple_p;
19055 + /* Code intended for use in shared libraries cannot be reliably linked
19056 + with out-of-line prologues and epilogues. */
19059 + savres_gprs_inline = 1;
19060 + savres_fprs_inline = 1;
19063 return (using_multiple_p
19064 | (savres_fprs_inline << 1)
19065 | (savres_gprs_inline << 2));
19066 @@ -16148,7 +16182,7 @@ rs6000_emit_prologue (void)
19067 int using_store_multiple;
19068 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
19069 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
19070 - && !call_used_regs[STATIC_CHAIN_REGNUM]);
19071 + && call_used_regs[STATIC_CHAIN_REGNUM]);
19072 HOST_WIDE_INT sp_offset = 0;
19074 if (TARGET_FIX_AND_CONTINUE)
19075 @@ -16956,8 +16990,9 @@ rs6000_emit_epilogue (int sibcall)
19076 || (cfun->calls_alloca
19077 && !frame_pointer_needed));
19078 restore_lr = (info->lr_save_p
19079 - && restoring_GPRs_inline
19080 - && restoring_FPRs_inline);
19081 + && (restoring_GPRs_inline
19082 + || (restoring_FPRs_inline
19083 + && info->first_fp_reg_save < 64)));
19085 if (WORLD_SAVE_P (info))
19087 @@ -17229,7 +17264,7 @@ rs6000_emit_epilogue (int sibcall)
19089 /* Get the old lr if we saved it. If we are restoring registers
19090 out-of-line, then the out-of-line routines can do this for us. */
19092 + if (restore_lr && restoring_GPRs_inline)
19094 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
19095 info->lr_save_offset + sp_offset);
19096 @@ -17248,7 +17283,7 @@ rs6000_emit_epilogue (int sibcall)
19099 /* Set LR here to try to overlap restores below. */
19101 + if (restore_lr && restoring_GPRs_inline)
19102 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
19103 gen_rtx_REG (Pmode, 0));
19105 @@ -17428,6 +17463,18 @@ rs6000_emit_epilogue (int sibcall)
19109 + if (restore_lr && !restoring_GPRs_inline)
19111 + rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
19112 + info->lr_save_offset + sp_offset);
19114 + emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
19117 + if (restore_lr && !restoring_GPRs_inline)
19118 + emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
19119 + gen_rtx_REG (Pmode, 0));
19121 /* Restore fpr's if we need to do it without calling a function. */
19122 if (restoring_FPRs_inline)
19123 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
19124 @@ -22195,6 +22242,30 @@ rs6000_memory_move_cost (enum machine_mo
19125 return 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);
19128 +/* Return a value indicating whether OP, an operand of a commutative
19129 + operation, is preferred as the first or second operand. The higher
19130 + the value, the stronger the preference for being the first operand.
19131 + We use negative values to indicate a preference for the first operand
19132 + and positive values for the second operand.
19133 + VALUE is the default precedence for OP; see rtlanal.c:
19134 + commutative_operand_precendece. */
19137 +rs6000_commutative_operand_precedence (const_rtx op, int value)
19139 + /* Prefer pointer objects over non pointer objects.
19140 + For rationale see PR28690. */
19141 + if (GET_RTX_CLASS (GET_CODE (op)) == RTX_OBJ
19142 + && ((REG_P (op) && REG_POINTER (op))
19143 + || (MEM_P (op) && MEM_POINTER (op))))
19144 + /* value = -1 */;
19152 /* Returns a code for a target-specific builtin that implements
19153 reciprocal of the function, or NULL_TREE if not available. */
19155 @@ -22718,12 +22789,16 @@ rs6000_is_opaque_type (const_tree type)
19157 rs6000_dwarf_register_span (rtx reg)
19162 + unsigned regno = REGNO (reg);
19163 + enum machine_mode mode = GET_MODE (reg);
19167 && (SPE_VECTOR_MODE (GET_MODE (reg))
19168 - || (TARGET_E500_DOUBLE
19169 - && (GET_MODE (reg) == DFmode || GET_MODE (reg) == DDmode))))
19170 + || (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode)
19171 + && mode != SFmode && mode != SDmode && mode != SCmode)))
19175 @@ -22733,15 +22808,23 @@ rs6000_dwarf_register_span (rtx reg)
19176 /* The duality of the SPE register size wreaks all kinds of havoc.
19177 This is a way of distinguishing r0 in 32-bits from r0 in
19180 - gen_rtx_PARALLEL (VOIDmode,
19183 - gen_rtx_REG (SImode, regno + 1200),
19184 - gen_rtx_REG (SImode, regno))
19186 - gen_rtx_REG (SImode, regno),
19187 - gen_rtx_REG (SImode, regno + 1200)));
19188 + words = (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
19189 + gcc_assert (words <= 4);
19190 + for (i = 0; i < words; i++, regno++)
19192 + if (BYTES_BIG_ENDIAN)
19194 + parts[2 * i] = gen_rtx_REG (SImode, regno + 1200);
19195 + parts[2 * i + 1] = gen_rtx_REG (SImode, regno);
19199 + parts[2 * i] = gen_rtx_REG (SImode, regno);
19200 + parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200);
19204 + return gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (words * 2, parts));
19207 /* Fill in sizes for SPE register high parts in table used by unwinder. */
19208 --- a/gcc/config/rs6000/rs6000.h
19209 +++ b/gcc/config/rs6000/rs6000.h
19210 @@ -368,16 +368,6 @@ enum group_termination
19214 -/* Support for a compile-time default CPU, et cetera. The rules are:
19215 - --with-cpu is ignored if -mcpu is specified.
19216 - --with-tune is ignored if -mtune is specified.
19217 - --with-float is ignored if -mhard-float or -msoft-float are
19219 -#define OPTION_DEFAULT_SPECS \
19220 - {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \
19221 - {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
19222 - {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }
19224 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
19225 struct rs6000_cpu_select
19227 @@ -794,8 +784,8 @@ extern int rs6000_xilinx_fpu;
19228 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
19229 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
19230 /* AltiVec registers. */ \
19231 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
19232 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
19233 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
19234 + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
19238 @@ -813,8 +803,8 @@ extern int rs6000_xilinx_fpu;
19239 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
19240 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
19241 /* AltiVec registers. */ \
19242 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
19243 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
19244 + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
19245 + 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
19249 --- a/gcc/config/rs6000/rs6000.md
19250 +++ b/gcc/config/rs6000/rs6000.md
19251 @@ -14703,9 +14703,9 @@
19252 [(match_parallel 0 "any_parallel_operand"
19253 [(clobber (reg:P 65))
19254 (use (match_operand:P 1 "symbol_ref_operand" "s"))
19255 - (use (match_operand:P 2 "gpc_reg_operand" "r"))
19256 - (set (match_operand:P 3 "memory_operand" "=m")
19257 - (match_operand:P 4 "gpc_reg_operand" "r"))])]
19259 + (set (match_operand:P 2 "memory_operand" "=m")
19260 + (match_operand:P 3 "gpc_reg_operand" "r"))])]
19263 [(set_attr "type" "branch")
19264 @@ -14715,9 +14715,9 @@
19265 [(match_parallel 0 "any_parallel_operand"
19266 [(clobber (reg:P 65))
19267 (use (match_operand:P 1 "symbol_ref_operand" "s"))
19268 - (use (match_operand:P 2 "gpc_reg_operand" "r"))
19269 - (set (match_operand:DF 3 "memory_operand" "=m")
19270 - (match_operand:DF 4 "gpc_reg_operand" "f"))])]
19272 + (set (match_operand:DF 2 "memory_operand" "=m")
19273 + (match_operand:DF 3 "gpc_reg_operand" "f"))])]
19276 [(set_attr "type" "branch")
19277 @@ -14810,9 +14810,9 @@
19278 [(match_parallel 0 "any_parallel_operand"
19279 [(clobber (match_operand:P 1 "register_operand" "=l"))
19280 (use (match_operand:P 2 "symbol_ref_operand" "s"))
19281 - (use (match_operand:P 3 "gpc_reg_operand" "r"))
19282 - (set (match_operand:P 4 "gpc_reg_operand" "=r")
19283 - (match_operand:P 5 "memory_operand" "m"))])]
19285 + (set (match_operand:P 3 "gpc_reg_operand" "=r")
19286 + (match_operand:P 4 "memory_operand" "m"))])]
19289 [(set_attr "type" "branch")
19290 @@ -14823,9 +14823,9 @@
19292 (clobber (match_operand:P 1 "register_operand" "=l"))
19293 (use (match_operand:P 2 "symbol_ref_operand" "s"))
19294 - (use (match_operand:P 3 "gpc_reg_operand" "r"))
19295 - (set (match_operand:P 4 "gpc_reg_operand" "=r")
19296 - (match_operand:P 5 "memory_operand" "m"))])]
19298 + (set (match_operand:P 3 "gpc_reg_operand" "=r")
19299 + (match_operand:P 4 "memory_operand" "m"))])]
19302 [(set_attr "type" "branch")
19303 @@ -14836,9 +14836,9 @@
19305 (clobber (match_operand:P 1 "register_operand" "=l"))
19306 (use (match_operand:P 2 "symbol_ref_operand" "s"))
19307 - (use (match_operand:P 3 "gpc_reg_operand" "r"))
19308 - (set (match_operand:DF 4 "gpc_reg_operand" "=f")
19309 - (match_operand:DF 5 "memory_operand" "m"))])]
19311 + (set (match_operand:DF 3 "gpc_reg_operand" "=f")
19312 + (match_operand:DF 4 "memory_operand" "m"))])]
19315 [(set_attr "type" "branch")
19316 @@ -14889,6 +14889,120 @@
19318 [(set_attr "type" "load")])
19320 +;;; Expanders for vector insn patterns shared between the SPE and TARGET_PAIRED systems.
19322 +(define_expand "absv2sf2"
19323 + [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
19324 + (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
19325 + "TARGET_PAIRED_FLOAT || TARGET_SPE"
19330 + /* We need to make a note that we clobber SPEFSCR. */
19331 + emit_insn (gen_rtx_SET (VOIDmode, operands[0],
19332 + gen_rtx_ABS (V2SFmode, operands[1])));
19333 + emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO)));
19338 +(define_expand "negv2sf2"
19339 + [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
19340 + (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")))]
19341 + "TARGET_PAIRED_FLOAT || TARGET_SPE"
19346 + /* We need to make a note that we clobber SPEFSCR. */
19347 + emit_insn (gen_rtx_SET (VOIDmode, operands[0],
19348 + gen_rtx_NEG (V2SFmode, operands[1])));
19349 + emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO)));
19354 +(define_expand "addv2sf3"
19355 + [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
19356 + (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
19357 + (match_operand:V2SF 2 "gpc_reg_operand" "")))]
19358 + "TARGET_PAIRED_FLOAT || TARGET_SPE"
19363 + /* We need to make a note that we clobber SPEFSCR. */
19364 + rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
19366 + XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
19367 + gen_rtx_PLUS (V2SFmode, operands[1], operands[2]));
19368 + XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
19374 +(define_expand "subv2sf3"
19375 + [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
19376 + (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
19377 + (match_operand:V2SF 2 "gpc_reg_operand" "")))]
19378 + "TARGET_PAIRED_FLOAT || TARGET_SPE"
19383 + /* We need to make a note that we clobber SPEFSCR. */
19384 + rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
19386 + XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
19387 + gen_rtx_MINUS (V2SFmode, operands[1], operands[2]));
19388 + XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
19394 +(define_expand "mulv2sf3"
19395 + [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
19396 + (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
19397 + (match_operand:V2SF 2 "gpc_reg_operand" "")))]
19398 + "TARGET_PAIRED_FLOAT || TARGET_SPE"
19403 + /* We need to make a note that we clobber SPEFSCR. */
19404 + rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
19406 + XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
19407 + gen_rtx_MULT (V2SFmode, operands[1], operands[2]));
19408 + XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
19414 +(define_expand "divv2sf3"
19415 + [(set (match_operand:V2SF 0 "gpc_reg_operand" "")
19416 + (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "")
19417 + (match_operand:V2SF 2 "gpc_reg_operand" "")))]
19418 + "TARGET_PAIRED_FLOAT || TARGET_SPE"
19423 + /* We need to make a note that we clobber SPEFSCR. */
19424 + rtx par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (2));
19426 + XVECEXP (par, 0, 0) = gen_rtx_SET (VOIDmode, operands[0],
19427 + gen_rtx_DIV (V2SFmode, operands[1], operands[2]));
19428 + XVECEXP (par, 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, SPEFSCR_REGNO));
19435 (include "sync.md")
19436 (include "altivec.md")
19437 --- a/gcc/config/rs6000/spe.md
19438 +++ b/gcc/config/rs6000/spe.md
19439 @@ -164,7 +164,7 @@
19441 ;; SPE SIMD instructions
19443 -(define_insn "spe_evabs"
19444 +(define_insn "absv2si2"
19445 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
19446 (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
19448 @@ -181,7 +181,7 @@
19449 [(set_attr "type" "vecsimple")
19450 (set_attr "length" "4")])
19452 -(define_insn "spe_evand"
19453 +(define_insn "andv2si3"
19454 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
19455 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
19456 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
19457 @@ -1898,7 +1898,7 @@
19458 [(set_attr "type" "veccomplex")
19459 (set_attr "length" "4")])
19461 -(define_insn "spe_evaddw"
19462 +(define_insn "addv2si3"
19463 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
19464 (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
19465 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
19466 @@ -2028,7 +2028,7 @@
19467 [(set_attr "type" "veccomplex")
19468 (set_attr "length" "4")])
19470 -(define_insn "spe_evdivws"
19471 +(define_insn "divv2si3"
19472 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
19473 (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
19474 (match_operand:V2SI 2 "gpc_reg_operand" "r")))
19475 @@ -3156,9 +3156,9 @@
19476 [(match_parallel 0 "any_parallel_operand"
19477 [(clobber (reg:P 65))
19478 (use (match_operand:P 1 "symbol_ref_operand" "s"))
19479 - (use (match_operand:P 2 "gpc_reg_operand" "r"))
19480 - (set (match_operand:V2SI 3 "memory_operand" "=m")
19481 - (match_operand:V2SI 4 "gpc_reg_operand" "r"))])]
19483 + (set (match_operand:V2SI 2 "memory_operand" "=m")
19484 + (match_operand:V2SI 3 "gpc_reg_operand" "r"))])]
19487 [(set_attr "type" "branch")
19488 @@ -3168,9 +3168,9 @@
19489 [(match_parallel 0 "any_parallel_operand"
19490 [(clobber (reg:P 65))
19491 (use (match_operand:P 1 "symbol_ref_operand" "s"))
19492 - (use (match_operand:P 2 "gpc_reg_operand" "r"))
19493 - (set (match_operand:V2SI 3 "gpc_reg_operand" "=r")
19494 - (match_operand:V2SI 4 "memory_operand" "m"))])]
19496 + (set (match_operand:V2SI 2 "gpc_reg_operand" "=r")
19497 + (match_operand:V2SI 3 "memory_operand" "m"))])]
19500 [(set_attr "type" "branch")
19501 @@ -3181,9 +3181,9 @@
19503 (clobber (reg:P 65))
19504 (use (match_operand:P 1 "symbol_ref_operand" "s"))
19505 - (use (match_operand:P 2 "gpc_reg_operand" "r"))
19506 - (set (match_operand:V2SI 3 "gpc_reg_operand" "=r")
19507 - (match_operand:V2SI 4 "memory_operand" "m"))])]
19509 + (set (match_operand:V2SI 2 "gpc_reg_operand" "=r")
19510 + (match_operand:V2SI 3 "memory_operand" "m"))])]
19513 [(set_attr "type" "branch")
19514 --- a/gcc/config/rs6000/sysv4.h
19515 +++ b/gcc/config/rs6000/sysv4.h
19516 @@ -619,6 +619,9 @@ SVR4_ASM_SPEC \
19517 #define CC1_SECURE_PLT_DEFAULT_SPEC ""
19520 +#undef CC1_EXTRA_SPEC
19521 +#define CC1_EXTRA_SPEC ""
19523 /* Pass -G xxx to the compiler and set correct endian mode. */
19524 #define CC1_SPEC "%{G*} %(cc1_cpu) \
19525 %{mlittle|mlittle-endian: %(cc1_endian_little); \
19526 @@ -643,7 +646,7 @@ SVR4_ASM_SPEC \
19527 %{msdata: -msdata=default} \
19528 %{mno-sdata: -msdata=none} \
19529 %{!mbss-plt: %{!msecure-plt: %(cc1_secure_plt_default)}} \
19531 +%{profile: -p}" CC1_EXTRA_SPEC
19533 /* Don't put -Y P,<path> for cross compilers. */
19534 #ifndef CROSS_DIRECTORY_STRUCTURE
19535 @@ -843,15 +846,15 @@ SVR4_ASM_SPEC \
19536 #define CPP_OS_MVME_SPEC ""
19538 /* PowerPC simulator based on netbsd system calls support. */
19539 -#define LIB_SIM_SPEC "--start-group -lsim -lc --end-group"
19540 +#define LIB_SIM_SPEC LIB_DEFAULT_SPEC
19542 -#define STARTFILE_SIM_SPEC "ecrti.o%s sim-crt0.o%s crtbegin.o%s"
19543 +#define STARTFILE_SIM_SPEC "ecrti.o%s crtbegin.o%s"
19545 -#define ENDFILE_SIM_SPEC "crtend.o%s ecrtn.o%s"
19546 +#define ENDFILE_SIM_SPEC "crtend.o%s ecrtn.o%s -Tsim-hosted.ld"
19548 #define LINK_START_SIM_SPEC ""
19550 -#define LINK_OS_SIM_SPEC "-m elf32ppcsim"
19551 +#define LINK_OS_SIM_SPEC ""
19553 #define CPP_OS_SIM_SPEC ""
19556 +++ b/gcc/config/rs6000/t-ppc-e500mc
19558 +# Multilibs for powerpc embedded ELF targets.
19560 +MULTILIB_OPTIONS =
19562 +MULTILIB_DIRNAMES =
19564 +MULTILIB_EXCEPTIONS =
19566 +MULTILIB_EXTRA_OPTS = mno-eabi mstrict-align
19568 +MULTILIB_MATCHES = ${MULTILIB_MATCHES_FLOAT} \
19569 + ${MULTILIB_MATCHES_ENDIAN}
19570 --- a/gcc/config/rs6000/t-ppccomm
19571 +++ b/gcc/config/rs6000/t-ppccomm
19573 LIB2FUNCS_EXTRA += tramp.S $(srcdir)/config/rs6000/darwin-ldouble.c
19575 # These can't end up in shared libgcc
19576 -LIB2FUNCS_STATIC_EXTRA = eabi.S
19578 -eabi.S: $(srcdir)/config/rs6000/eabi.asm
19579 - cat $(srcdir)/config/rs6000/eabi.asm > eabi.S
19580 +LIB2FUNCS_STATIC_EXTRA = \
19581 + crtsavfpr.S crtresfpr.S \
19582 + crtsavgpr.S crtresgpr.S \
19583 + crtresxfpr.S crtresxgpr.S \
19584 + e500crtres32gpr.S \
19585 + e500crtres64gpr.S \
19586 + e500crtres64gprctr.S \
19587 + e500crtrest32gpr.S \
19588 + e500crtrest64gpr.S \
19589 + e500crtresx32gpr.S \
19590 + e500crtresx64gpr.S \
19591 + e500crtsav32gpr.S \
19592 + e500crtsav64gpr.S \
19593 + e500crtsav64gprctr.S \
19594 + e500crtsavg32gpr.S \
19595 + e500crtsavg64gpr.S \
19596 + e500crtsavg64gprctr.S
19598 tramp.S: $(srcdir)/config/rs6000/tramp.asm
19599 cat $(srcdir)/config/rs6000/tramp.asm > tramp.S
19600 @@ -36,6 +49,63 @@ ncrti.S: $(srcdir)/config/rs6000/sol-ci.
19601 ncrtn.S: $(srcdir)/config/rs6000/sol-cn.asm
19602 cat $(srcdir)/config/rs6000/sol-cn.asm >ncrtn.S
19604 +crtsavfpr.S: $(srcdir)/config/rs6000/crtsavfpr.asm
19605 + cat $(srcdir)/config/rs6000/crtsavfpr.asm >crtsavfpr.S
19607 +crtresfpr.S: $(srcdir)/config/rs6000/crtresfpr.asm
19608 + cat $(srcdir)/config/rs6000/crtresfpr.asm >crtresfpr.S
19610 +crtsavgpr.S: $(srcdir)/config/rs6000/crtsavgpr.asm
19611 + cat $(srcdir)/config/rs6000/crtsavgpr.asm >crtsavgpr.S
19613 +crtresgpr.S: $(srcdir)/config/rs6000/crtresgpr.asm
19614 + cat $(srcdir)/config/rs6000/crtresgpr.asm >crtresgpr.S
19616 +crtresxfpr.S: $(srcdir)/config/rs6000/crtresxfpr.asm
19617 + cat $(srcdir)/config/rs6000/crtresxfpr.asm >crtresxfpr.S
19619 +crtresxgpr.S: $(srcdir)/config/rs6000/crtresxgpr.asm
19620 + cat $(srcdir)/config/rs6000/crtresxgpr.asm >crtresxgpr.S
19622 +e500crtres32gpr.S: $(srcdir)/config/rs6000/e500crtres32gpr.asm
19623 + cat $(srcdir)/config/rs6000/e500crtres32gpr.asm >e500crtres32gpr.S
19625 +e500crtres64gpr.S: $(srcdir)/config/rs6000/e500crtres64gpr.asm
19626 + cat $(srcdir)/config/rs6000/e500crtres64gpr.asm >e500crtres64gpr.S
19628 +e500crtres64gprctr.S: $(srcdir)/config/rs6000/e500crtres64gprctr.asm
19629 + cat $(srcdir)/config/rs6000/e500crtres64gprctr.asm >e500crtres64gprctr.S
19631 +e500crtrest32gpr.S: $(srcdir)/config/rs6000/e500crtrest32gpr.asm
19632 + cat $(srcdir)/config/rs6000/e500crtrest32gpr.asm >e500crtrest32gpr.S
19634 +e500crtrest64gpr.S: $(srcdir)/config/rs6000/e500crtrest64gpr.asm
19635 + cat $(srcdir)/config/rs6000/e500crtrest64gpr.asm >e500crtrest64gpr.S
19637 +e500crtresx32gpr.S: $(srcdir)/config/rs6000/e500crtresx32gpr.asm
19638 + cat $(srcdir)/config/rs6000/e500crtresx32gpr.asm >e500crtresx32gpr.S
19640 +e500crtresx64gpr.S: $(srcdir)/config/rs6000/e500crtresx64gpr.asm
19641 + cat $(srcdir)/config/rs6000/e500crtresx64gpr.asm >e500crtresx64gpr.S
19643 +e500crtsav32gpr.S: $(srcdir)/config/rs6000/e500crtsav32gpr.asm
19644 + cat $(srcdir)/config/rs6000/e500crtsav32gpr.asm >e500crtsav32gpr.S
19646 +e500crtsav64gpr.S: $(srcdir)/config/rs6000/e500crtsav64gpr.asm
19647 + cat $(srcdir)/config/rs6000/e500crtsav64gpr.asm >e500crtsav64gpr.S
19649 +e500crtsav64gprctr.S: $(srcdir)/config/rs6000/e500crtsav64gprctr.asm
19650 + cat $(srcdir)/config/rs6000/e500crtsav64gprctr.asm >e500crtsav64gprctr.S
19652 +e500crtsavg32gpr.S: $(srcdir)/config/rs6000/e500crtsavg32gpr.asm
19653 + cat $(srcdir)/config/rs6000/e500crtsavg32gpr.asm >e500crtsavg32gpr.S
19655 +e500crtsavg64gpr.S: $(srcdir)/config/rs6000/e500crtsavg64gpr.asm
19656 + cat $(srcdir)/config/rs6000/e500crtsavg64gpr.asm >e500crtsavg64gpr.S
19658 +e500crtsavg64gprctr.S: $(srcdir)/config/rs6000/e500crtsavg64gprctr.asm
19659 + cat $(srcdir)/config/rs6000/e500crtsavg64gprctr.asm >e500crtsavg64gprctr.S
19661 # Build multiple copies of ?crt{i,n}.o, one for each target switch.
19662 $(T)ecrti$(objext): ecrti.S
19663 $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c ecrti.S -o $(T)ecrti$(objext)
19664 @@ -49,6 +119,63 @@ $(T)ncrti$(objext): ncrti.S
19665 $(T)ncrtn$(objext): ncrtn.S
19666 $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c ncrtn.S -o $(T)ncrtn$(objext)
19668 +$(T)crtsavfpr$(objext): crtsavfpr.S
19669 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c crtsavfpr.S -o $(T)crtsavfpr$(objext)
19671 +$(T)crtresfpr$(objext): crtresfpr.S
19672 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c crtresfpr.S -o $(T)crtresfpr$(objext)
19674 +$(T)crtsavgpr$(objext): crtsavgpr.S
19675 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c crtsavgpr.S -o $(T)crtsavgpr$(objext)
19677 +$(T)crtresgpr$(objext): crtresgpr.S
19678 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c crtresgpr.S -o $(T)crtresgpr$(objext)
19680 +$(T)crtresxfpr$(objext): crtresxfpr.S
19681 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c crtresxfpr.S -o $(T)crtresxfpr$(objext)
19683 +$(T)crtresxgpr$(objext): crtresxgpr.S
19684 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c crtresxgpr.S -o $(T)crtresxgpr$(objext)
19686 +$(T)e500crtres32gpr$(objext): e500crtres32gpr.S
19687 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c e500crtres32gpr.S -o $(T)e500crtres32gpr$(objext)
19689 +$(T)e500crtres64gpr$(objext): e500crtres64gpr.S
19690 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c e500crtres64gpr.S -o $(T)e500crtres64gpr$(objext)
19692 +$(T)e500crtres64gprctr$(objext): e500crtres64gprctr.S
19693 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c e500crtres64gprctr.S -o $(T)e500crtres64gprctr$(objext)
19695 +$(T)e500crtrest32gpr$(objext): e500crtrest32gpr.S
19696 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c e500crtrest32gpr.S -o $(T)e500crtrest32gpr$(objext)
19698 +$(T)e500crtrest64gpr$(objext): e500crtrest64gpr.S
19699 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c e500crtrest64gpr.S -o $(T)e500crtrest64gpr$(objext)
19701 +$(T)e500crtresx32gpr$(objext): e500crtresx32gpr.S
19702 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c e500crtresx32gpr.S -o $(T)e500crtresx32gpr$(objext)
19704 +$(T)e500crtresx64gpr$(objext): e500crtresx64gpr.S
19705 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c e500crtresx64gpr.S -o $(T)e500crtresx64gpr$(objext)
19707 +$(T)e500crtsav32gpr$(objext): e500crtsav32gpr.S
19708 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c e500crtsav32gpr.S -o $(T)e500crtsav32gpr$(objext)
19710 +$(T)e500crtsav64gpr$(objext): e500crtsav64gpr.S
19711 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c e500crtsav64gpr.S -o $(T)e500crtsav64gpr$(objext)
19713 +$(T)e500crtsav64gprctr$(objext): e500crtsav64gprctr.S
19714 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c e500crtsav64gprctr.S -o $(T)e500crtsav64gprctr$(objext)
19716 +$(T)e500crtsavg32gpr$(objext): e500crtsavg32gpr.S
19717 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c e500crtsavg32gpr.S -o $(T)e500crtsavg32gpr$(objext)
19719 +$(T)e500crtsavg64gpr$(objext): e500crtsavg64gpr.S
19720 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c e500crtsavg64gpr.S -o $(T)e500crtsavg64gpr$(objext)
19722 +$(T)e500crtsavg64gprctr$(objext): e500crtsavg64gprctr.S
19723 + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) $(MULTILIB_CFLAGS) -c e500crtsavg64gprctr.S -o $(T)e500crtsavg64gprctr$(objext)
19725 # It is important that crtbegin.o, etc., aren't surprised by stuff in .sdata.
19726 CRTSTUFF_T_CFLAGS = -msdata=none
19727 # Make sure crt*.o are built with -fPIC even if configured with
19728 --- a/gcc/config/sh/lib1funcs.asm
19729 +++ b/gcc/config/sh/lib1funcs.asm
19730 @@ -2080,8 +2080,9 @@ GLOBAL(ic_invalidate):
19731 GLOBAL(ic_invalidate):
19738 ENDFUNC(GLOBAL(ic_invalidate))
19739 #elif defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) || (defined(__SH4_NOFPU__) && !defined(__SH5__))
19740 /* For system code, we use ic_invalidate_line_i, but user code
19741 @@ -2147,8 +2148,10 @@ GLOBAL(ic_invalidate):
19742 GLOBAL(ic_invalidate_array):
19751 ENDFUNC(GLOBAL(ic_invalidate_array))
19752 #elif defined(__SH4_SINGLE__) || defined(__SH4__) || defined(__SH4_SINGLE_ONLY__) || (defined(__SH4_NOFPU__) && !defined(__SH5__))
19753 --- a/gcc/config/sh/linux-unwind.h
19754 +++ b/gcc/config/sh/linux-unwind.h
19755 @@ -24,7 +24,10 @@ see the files COPYING3 and COPYING.RUNTI
19758 /* Do code reading to identify a signal frame, and set the frame
19759 - state data appropriately. See unwind-dw2.c for the structs. */
19760 + state data appropriately. See unwind-dw2.c for the structs.
19761 + Don't use this at all if inhibit_libc is used. */
19763 +#ifndef inhibit_libc
19765 #include <signal.h>
19766 #include <sys/ucontext.h>
19767 @@ -248,3 +251,5 @@ sh_fallback_frame_state (struct _Unwind_
19768 return _URC_NO_REASON;
19770 #endif /* defined (__SH5__) */
19772 +#endif /* inhibit_libc */
19773 --- a/gcc/config/sh/sh.h
19774 +++ b/gcc/config/sh/sh.h
19775 @@ -712,8 +712,9 @@ do { \
19776 /* Never run scheduling before reload, since that can \
19777 break global alloc, and generates slower code anyway due \
19778 to the pressure on R0. */ \
19779 - /* Enable sched1 for SH4; ready queue will be reordered by \
19780 - the target hooks when pressure is high. We can not do this for \
19781 + /* Enable sched1 for SH4 if the user explicitly requests. \
19782 + When sched1 is enabled, the ready queue will be reordered by \
19783 + the target hooks if pressure is high. We can not do this for \
19784 PIC, SH3 and lower as they give spill failures for R0. */ \
19785 if (!TARGET_HARD_SH4 || flag_pic) \
19786 flag_schedule_insns = 0; \
19787 @@ -728,6 +729,8 @@ do { \
19788 warning (0, "ignoring -fschedule-insns because of exception handling bug"); \
19789 flag_schedule_insns = 0; \
19791 + else if (flag_schedule_insns == 2) \
19792 + flag_schedule_insns = 0; \
19795 if (align_loops == 0) \
19796 --- a/gcc/config/sh/t-1e
19800 --- a/gcc/config/sh/t-linux
19801 +++ b/gcc/config/sh/t-linux
19802 @@ -4,6 +4,5 @@ LIB2FUNCS_EXTRA= $(srcdir)/config/sh/lin
19806 -MULTILIB_EXCEPTIONS=
19808 EXTRA_MULTILIB_PARTS= crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o
19809 --- a/gcc/config/sh/t-mlib-sh1
19813 --- a/gcc/config/sh/t-mlib-sh2
19817 --- a/gcc/config/sh/t-mlib-sh2a
19821 --- a/gcc/config/sh/t-mlib-sh2a-nofpu
19824 -ML_sh2a_nofpu=m2a-nofpu/
19825 --- a/gcc/config/sh/t-mlib-sh2a-single
19828 -ML_sh2a_single=m2a-single/
19829 --- a/gcc/config/sh/t-mlib-sh2a-single-only
19832 -ML_sh2a_single_only=m2a-single-only/
19833 --- a/gcc/config/sh/t-mlib-sh2e
19837 --- a/gcc/config/sh/t-mlib-sh3
19841 --- a/gcc/config/sh/t-mlib-sh3e
19845 --- a/gcc/config/sh/t-mlib-sh4
19849 --- a/gcc/config/sh/t-mlib-sh4-nofpu
19852 -ML_sh4_nofpu=m4-nofpu/
19853 --- a/gcc/config/sh/t-mlib-sh4-single
19856 -ML_sh4_single=m4-single/
19857 --- a/gcc/config/sh/t-mlib-sh4-single-only
19860 -ML_sh4_single_only=m4-single-only/
19861 --- a/gcc/config/sh/t-mlib-sh4a
19865 --- a/gcc/config/sh/t-mlib-sh4a-nofpu
19868 -ML_sh4a_nofpu=m4a-nofpu/
19869 --- a/gcc/config/sh/t-mlib-sh4a-single
19872 -ML_sh4a_single=m4a-single/
19873 --- a/gcc/config/sh/t-mlib-sh4a-single-only
19876 -ML_sh4a_single_only=m4a-single-only/
19877 --- a/gcc/config/sh/t-mlib-sh4al
19881 --- a/gcc/config/sh/t-mlib-sh5-32media
19884 -ML_sh5_32media=m5-32media/
19885 --- a/gcc/config/sh/t-mlib-sh5-32media-nofpu
19888 -ML_sh5_32media_nofpu=m5-32media-nofpu/
19889 --- a/gcc/config/sh/t-mlib-sh5-64media
19892 -ML_sh5_64media=m5-64media/
19893 --- a/gcc/config/sh/t-mlib-sh5-64media-nofpu
19896 -ML_sh5_64media_nofpu=m5-64media-nofpu/
19897 --- a/gcc/config/sh/t-mlib-sh5-compact
19900 -ML_sh5_compact=m5-compact/
19901 --- a/gcc/config/sh/t-mlib-sh5-compact-nofpu
19904 -ML_sh5_compact_nofpu=m5-compact-nofpu/
19905 --- a/gcc/config/sh/t-sh
19906 +++ b/gcc/config/sh/t-sh
19907 @@ -27,10 +27,10 @@ fp-bit.c: $(srcdir)/config/fp-bit.c
19908 echo '#endif' >> fp-bit.c
19909 cat $(srcdir)/config/fp-bit.c >> fp-bit.c
19911 -MULTILIB_ENDIAN = ml/mb
19912 -MULTILIB_CPUS= $(ML_sh1)$(ML_sh2a)$(ML_sh2a_nofpu)$(ML_sh2a_single_only)$(ML_sh2a_single)$(ML_sh2e)$(ML_sh2)$(ML_sh3e)$(ML_sh3)$(ML_sh4_nofpu)$(ML_sh4_single_only)$(ML_sh4_single)$(ML_sh4)$(ML_sh4a_nofpu)$(ML_sh4a_single_only)$(ML_sh4a_single)$(ML_sh4a)$(ML_sh5_32media)$(ML_sh5_32media_nofpu)$(ML_sh5_compact)$(ML_sh5_compact_nofpu)$(ML_sh5_64media)$(ML_sh5_64media_nofpu)
19913 +DEFAULT_ENDIAN = $(word 1,$(TM_ENDIAN_CONFIG))
19914 +OTHER_ENDIAN = $(word 2,$(TM_ENDIAN_CONFIG))
19916 -MULTILIB_OPTIONS= $(MULTILIB_ENDIAN) $(MULTILIB_CPUS:/=)
19917 +MULTILIB_OPTIONS= $(OTHER_ENDIAN) $(TM_MULTILIB_CONFIG)
19920 # The separate entries for m2a-nofpu and m2a-single-only with
19921 @@ -58,7 +58,34 @@ MULTILIB_MATCHES = $(shell \
19924 # SH1 only supports big endian.
19925 -MULTILIB_EXCEPTIONS = ml/m1 ml/m2a*
19926 +MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
19928 +MULTILIB_OSDIRNAMES = \
19929 + $(OTHER_ENDIAN)=!$(OTHER_ENDIAN) \
19930 + m1=!m1 $(OTHER_ENDIAN)/m1=!$(OTHER_ENDIAN)/m1 \
19931 + m2a=!m2a $(OTHER_ENDIAN)/m2a=!$(OTHER_ENDIAN)/m2a \
19932 + m2a-nofpu=!m2a-nofpu $(OTHER_ENDIAN)/m2a-nofpu=!$(OTHER_ENDIAN)/m2a-nofpu \
19933 + m2a-single-only=!m2a-single-only $(OTHER_ENDIAN)/m2a-single-only=!$(OTHER_ENDIAN)/m2a-single-only \
19934 + m2a-single=!m2a-single $(OTHER_ENDIAN)/m2a-single=!$(OTHER_ENDIAN)/m2a-single \
19935 + m2e=!m2e $(OTHER_ENDIAN)/m2e=!$(OTHER_ENDIAN)/m2e \
19936 + m2=!m2 $(OTHER_ENDIAN)/m2=!$(OTHER_ENDIAN)/m2 \
19937 + m3e=!m3e $(OTHER_ENDIAN)/m3e=!$(OTHER_ENDIAN)/m3e \
19938 + m3=!m3 $(OTHER_ENDIAN)/m3=!$(OTHER_ENDIAN)/m3 \
19939 + m4-nofpu=!m4-nofpu $(OTHER_ENDIAN)/m4-nofpu=!$(OTHER_ENDIAN)/m4-nofpu \
19940 + m4-single-only=!m4-single-only $(OTHER_ENDIAN)/m4-single-only=!$(OTHER_ENDIAN)/m4-single-only \
19941 + m4-single=!m4-single $(OTHER_ENDIAN)/m4-single=!$(OTHER_ENDIAN)/m4-single \
19942 + m4=!m4 $(OTHER_ENDIAN)/m4=!$(OTHER_ENDIAN)/m4 \
19943 + m4a-nofpu=!m4a-nofpu $(OTHER_ENDIAN)/m4a-nofpu=!$(OTHER_ENDIAN)/m4a-nofpu \
19944 + m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \
19945 + m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \
19946 + m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \
19947 + m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \
19948 + m5-32media=!m5-32media $(OTHER_ENDIAN)/m5-32media=!$(OTHER_ENDIAN)/m5-32media \
19949 + m5-32media-nofpu=!m5-32media-nofpu $(OTHER_ENDIAN)/m5-32media-nofpu=!$(OTHER_ENDIAN)/m5-32media-nofpu \
19950 + m5-compact=!m5-compact $(OTHER_ENDIAN)/m5-compact=!$(OTHER_ENDIAN)/m5-compact \
19951 + m5-compact-nofpu=!m5-compact-nofpu $(OTHER_ENDIAN)/m5-compact-nofpu=!$(OTHER_ENDIAN)/m5-compact-nofpu \
19952 + m5-64media=!m5-64media $(OTHER_ENDIAN)/m5-64media=!$(OTHER_ENDIAN)/m5-64media \
19953 + m5-64media-nofpu=!m5-64media-nofpu $(OTHER_ENDIAN)/m5-64media-nofpu=!$(OTHER_ENDIAN)/m5-64media-nofpu
19955 LIBGCC = stmp-multilib
19956 INSTALL_LIBGCC = install-multilib
19957 --- a/gcc/config/sol2.h
19958 +++ b/gcc/config/sol2.h
19959 @@ -123,12 +123,12 @@ along with GCC; see the file COPYING3.
19963 - %{!YP,*:%{p|pg:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
19964 - %{!p:%{!pg:-Y P,/usr/ucblib:/usr/ccs/lib:/usr/lib}}} \
19965 - -R /usr/ucblib} \
19966 + %{!YP,*:%{p|pg:-Y P,%R/usr/ucblib:%R/usr/ccs/lib/libp:%R/usr/lib/libp:%R/usr/ccs/lib:%R/usr/lib} \
19967 + %{!p:%{!pg:-Y P,%R/usr/ucblib:%R/usr/ccs/lib:%R/usr/lib}}} \
19968 + -R %R/usr/ucblib} \
19970 - %{!YP,*:%{p|pg:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \
19971 - %{!p:%{!pg:-Y P,/usr/ccs/lib:/usr/lib}}}}"
19972 + %{!YP,*:%{p|pg:-Y P,%R/usr/ccs/lib/libp:%R/usr/lib/libp:%R/usr/ccs/lib:%R/usr/lib} \
19973 + %{!p:%{!pg:-Y P,%R/usr/ccs/lib:%R/usr/lib}}}}"
19975 #undef LINK_ARCH32_SPEC
19976 #define LINK_ARCH32_SPEC LINK_ARCH32_SPEC_BASE
19977 --- a/gcc/config/sparc/linux64.h
19978 +++ b/gcc/config/sparc/linux64.h
19979 @@ -40,10 +40,15 @@ along with GCC; see the file COPYING3.
19980 in a Medium/Low code model environment. */
19982 #undef TARGET_DEFAULT
19983 +#ifdef BIARCH_32BIT_DEFAULT
19984 +#define TARGET_DEFAULT \
19985 + (MASK_APP_REGS + MASK_FPU)
19987 #define TARGET_DEFAULT \
19988 (MASK_V9 + MASK_PTR64 + MASK_64BIT /* + MASK_HARD_QUAD */ \
19989 + MASK_STACK_BIAS + MASK_APP_REGS + MASK_FPU + MASK_LONG_DOUBLE_128)
19993 /* This must be v9a not just v9 because by default we enable
19995 --- a/gcc/config/sparc/sol2-bi.h
19996 +++ b/gcc/config/sparc/sol2-bi.h
19997 @@ -172,12 +172,12 @@
20001 - %{!YP,*:%{p|pg:-Y P,/usr/ucblib/sparcv9:/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \
20002 - %{!p:%{!pg:-Y P,/usr/ucblib/sparcv9:/usr/lib/sparcv9}}} \
20003 - -R /usr/ucblib/sparcv9} \
20004 + %{!YP,*:%{p|pg:-Y P,%R/usr/ucblib/sparcv9:%R/usr/lib/libp/sparcv9:%R/usr/lib/sparcv9} \
20005 + %{!p:%{!pg:-Y P,%R/usr/ucblib/sparcv9:%R/usr/lib/sparcv9}}} \
20006 + -R %R/usr/ucblib/sparcv9} \
20008 - %{!YP,*:%{p|pg:-Y P,/usr/lib/libp/sparcv9:/usr/lib/sparcv9} \
20009 - %{!p:%{!pg:-Y P,/usr/lib/sparcv9}}}}"
20010 + %{!YP,*:%{p|pg:-Y P,%R/usr/lib/libp/sparcv9:%R/usr/lib/sparcv9} \
20011 + %{!p:%{!pg:-Y P,%R/usr/lib/sparcv9}}}}"
20013 #define LINK_ARCH64_SPEC LINK_ARCH64_SPEC_BASE
20015 --- a/gcc/config/sparc/sparc.c
20016 +++ b/gcc/config/sparc/sparc.c
20017 @@ -6104,7 +6104,7 @@ enum rtx_code
20018 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
20020 const char *qpfunc;
20021 - rtx slot0, slot1, result, tem, tem2;
20022 + rtx slot0, slot1, result, tem, tem2, libfunc;
20023 enum machine_mode mode;
20024 enum rtx_code new_comparison;
20026 @@ -6167,7 +6167,8 @@ sparc_emit_float_lib_cmp (rtx x, rtx y,
20027 emit_move_insn (slot1, y);
20030 - emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
20031 + libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
20032 + emit_library_call (libfunc, LCT_NORMAL,
20034 XEXP (slot0, 0), Pmode,
20035 XEXP (slot1, 0), Pmode);
20036 @@ -6175,7 +6176,8 @@ sparc_emit_float_lib_cmp (rtx x, rtx y,
20040 - emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
20041 + libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc);
20042 + emit_library_call (libfunc, LCT_NORMAL,
20044 x, TFmode, y, TFmode);
20046 @@ -6186,7 +6188,7 @@ sparc_emit_float_lib_cmp (rtx x, rtx y,
20047 register so reload doesn't clobber the value if it needs
20048 the return register for a spill reg. */
20049 result = gen_reg_rtx (mode);
20050 - emit_move_insn (result, hard_libcall_value (mode));
20051 + emit_move_insn (result, hard_libcall_value (mode, libfunc));
20053 switch (comparison)
20055 --- a/gcc/config/spu/spu.h
20056 +++ b/gcc/config/spu/spu.h
20057 @@ -270,7 +270,8 @@ targetm.resolve_overloaded_builtin = spu
20059 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
20061 -#define ARG_POINTER_CFA_OFFSET(FNDECL) (-STACK_POINTER_OFFSET)
20062 +#define ARG_POINTER_CFA_OFFSET(FNDECL) \
20063 + (crtl->args.pretend_args_size - STACK_POINTER_OFFSET)
20066 /* Stack Checking */
20068 +++ b/gcc/config/t-eglibc
20070 +# multilibs -*- mode:Makefile -*-
20072 +MULTILIB_EXCEPTIONS :=
20073 +MULTILIB_MATCHES :=
20074 +MULTILIB_ALIASES :=
20076 +# For all items in EGLIBC_CONFIGS except for the last one
20077 +# do $1. For the last one do $2. The items are separated with ",".
20078 +EGLIBC_AWK = $(shell echo $(EGLIBC_CONFIGS) | $(AWK) \
20080 + N=split ($$0, configs, ","); \
20081 + for (i = 1; i < N; ++i) $1; \
20085 +MULTILIB_OPTIONS := $(call EGLIBC_AWK, \
20086 + printf ("feglibc=%s/", configs[i]), \
20087 + printf ("feglibc=%s\n", configs[i]))
20088 +MULTILIB_DIRNAMES := $(call EGLIBC_AWK, \
20089 + printf ("%s ", configs[i]), \
20090 + printf ("%s\n", configs[i]))
20091 +MULTILIB_OSDIRNAMES := $(call EGLIBC_AWK, \
20092 + printf ("feglibc.%s=!%s ", configs[i], configs[i]), \
20093 + printf ("feglibc.%s=!%s\n", configs[i], configs[i]))
20095 --- a/gcc/configure
20096 +++ b/gcc/configure
20097 @@ -458,7 +458,7 @@ ac_includes_default="\
20098 # include <unistd.h>
20101 -ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os target_noncanonical build_libsubdir build_subdir host_subdir target_subdir GENINSRC CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT GNATBIND ac_ct_GNATBIND GNATMAKE ac_ct_GNATMAKE NO_MINUS_C_MINUS_O OUTPUT_OPTION CPP EGREP loose_warn strict_warn warn_cflags nocommon_flag TREEBROWSER valgrind_path valgrind_path_defines valgrind_command coverage_flags enable_multilib enable_decimal_float enable_fixed_point enable_shared TARGET_SYSTEM_ROOT TARGET_SYSTEM_ROOT_DEFINE CROSS_SYSTEM_HEADER_DIR onestep PKGVERSION REPORT_BUGS_TO REPORT_BUGS_TEXI datarootdir docdir htmldir SET_MAKE AWK LN_S LN RANLIB ac_ct_RANLIB ranlib_flags INSTALL INSTALL_PROGRAM INSTALL_DATA make_compare_target have_mktemp_command MAKEINFO BUILD_INFO GENERATED_MANPAGES FLEX BISON NM AR COLLECT2_LIBS GNAT_LIBEXC LDEXP_LIB TARGET_GETGROUPS_T LIBICONV LTLIBICONV LIBICONV_DEP manext objext gthread_flags extra_modes_file extra_opt_files USE_NLS LIBINTL LIBINTL_DEP INCINTL XGETTEXT GMSGFMT POSUB CATALOGS DATADIRNAME INSTOBJEXT GENCAT CATOBJEXT CROSS ALL SYSTEM_HEADER_DIR inhibit_libc CC_FOR_BUILD BUILD_CFLAGS BUILD_LDFLAGS STMP_FIXINC STMP_FIXPROTO collect2 LIBTOOL SED FGREP GREP LD DUMPBIN ac_ct_DUMPBIN OBJDUMP ac_ct_OBJDUMP ac_ct_AR STRIP ac_ct_STRIP lt_ECHO DSYMUTIL ac_ct_DSYMUTIL NMEDIT ac_ct_NMEDIT LIPO ac_ct_LIPO OTOOL ac_ct_OTOOL OTOOL64 ac_ct_OTOOL64 objdir enable_fast_install gcc_cv_as ORIGINAL_AS_FOR_TARGET gcc_cv_ld ORIGINAL_LD_FOR_TARGET gcc_cv_nm ORIGINAL_NM_FOR_TARGET gcc_cv_objdump gcc_cv_readelf libgcc_visibility GGC zlibdir zlibinc MAINT gcc_tooldir dollar slibdir subdirs srcdir all_compilers all_gtfiles all_lang_makefrags all_lang_makefiles all_languages all_selected_languages build_exeext build_install_headers_dir build_xm_file_list build_xm_include_list build_xm_defines build_file_translate check_languages cpp_install_dir xmake_file tmake_file extra_gcc_objs extra_headers_list extra_objs extra_parts extra_passes extra_programs float_h_file gcc_config_arguments gcc_gxx_include_dir host_exeext host_xm_file_list host_xm_include_list host_xm_defines out_host_hook_obj install lang_opt_files lang_specs_files lang_tree_files local_prefix md_file objc_boehm_gc out_file out_object_file thread_file tm_file_list tm_include_list tm_defines tm_p_file_list tm_p_include_list xm_file_list xm_include_list xm_defines c_target_objs cxx_target_objs fortran_target_objs target_cpu_default GMPLIBS GMPINC PPLLIBS PPLINC CLOOGLIBS CLOOGINC LIBOBJS LTLIBOBJS'
20102 +ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os target_noncanonical build_libsubdir build_subdir host_subdir target_subdir GENINSRC CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT GNATBIND ac_ct_GNATBIND GNATMAKE ac_ct_GNATMAKE NO_MINUS_C_MINUS_O OUTPUT_OPTION CPP EGREP loose_warn strict_warn warn_cflags nocommon_flag TREEBROWSER valgrind_path valgrind_path_defines valgrind_command coverage_flags enable_multilib enable_decimal_float enable_fixed_point enable_shared TARGET_SYSTEM_ROOT TARGET_SYSTEM_ROOT_DEFINE CROSS_SYSTEM_HEADER_DIR EGLIBC_CONFIGS CONFIGURE_SPECS onestep PKGVERSION REPORT_BUGS_TO REPORT_BUGS_TEXI datarootdir docdir htmldir SET_MAKE AWK LN_S LN RANLIB ac_ct_RANLIB ranlib_flags INSTALL INSTALL_PROGRAM INSTALL_DATA make_compare_target have_mktemp_command MAKEINFO BUILD_INFO GENERATED_MANPAGES FLEX BISON NM AR COLLECT2_LIBS GNAT_LIBEXC LDEXP_LIB TARGET_GETGROUPS_T LIBICONV LTLIBICONV LIBICONV_DEP manext objext gthread_flags extra_modes_file extra_opt_files USE_NLS LIBINTL LIBINTL_DEP INCINTL XGETTEXT GMSGFMT POSUB CATALOGS DATADIRNAME INSTOBJEXT GENCAT CATOBJEXT CROSS ALL SYSTEM_HEADER_DIR inhibit_libc CC_FOR_BUILD BUILD_CFLAGS BUILD_LDFLAGS STMP_FIXINC STMP_FIXPROTO collect2 LIBTOOL SED FGREP GREP LD DUMPBIN ac_ct_DUMPBIN OBJDUMP ac_ct_OBJDUMP ac_ct_AR STRIP ac_ct_STRIP lt_ECHO DSYMUTIL ac_ct_DSYMUTIL NMEDIT ac_ct_NMEDIT LIPO ac_ct_LIPO OTOOL ac_ct_OTOOL OTOOL64 ac_ct_OTOOL64 objdir enable_fast_install gcc_cv_as ORIGINAL_AS_FOR_TARGET gcc_cv_ld ORIGINAL_LD_FOR_TARGET gcc_cv_nm ORIGINAL_NM_FOR_TARGET gcc_cv_objdump gcc_cv_readelf libgcc_visibility GGC zlibdir zlibinc MAINT gcc_tooldir dollar slibdir subdirs srcdir all_compilers all_gtfiles all_lang_makefrags all_lang_makefiles all_languages all_selected_languages build_exeext build_install_headers_dir build_xm_file_list build_xm_include_list build_xm_defines build_file_translate check_languages cpp_install_dir xmake_file tmake_file TM_ENDIAN_CONFIG TM_MULTILIB_CONFIG TM_MULTILIB_EXCEPTIONS_CONFIG extra_gcc_objs extra_headers_list extra_objs extra_parts extra_passes extra_programs float_h_file gcc_config_arguments gcc_gxx_include_dir host_exeext host_xm_file_list host_xm_include_list host_xm_defines out_host_hook_obj install lang_opt_files lang_specs_files lang_tree_files local_prefix md_file objc_boehm_gc out_file out_object_file thread_file tm_file_list tm_include_list tm_defines tm_p_file_list tm_p_include_list xm_file_list xm_include_list xm_defines c_target_objs cxx_target_objs fortran_target_objs target_cpu_default GMPLIBS GMPINC PPLLIBS PPLINC CLOOGLIBS CLOOGINC LIBOBJS LTLIBOBJS'
20103 ac_subst_files='language_hooks'
20106 @@ -1084,6 +1084,8 @@ Optional Features:
20107 --enable-version-specific-runtime-libs
20108 specify that runtime libraries should be
20109 installed in a compiler-specific directory
20110 + --enable-poison-system-directories
20111 + warn for use of native system header directories
20114 --with-PACKAGE[=ARG] use PACKAGE [ARG=yes]
20115 @@ -1105,8 +1107,12 @@ Optional Packages:
20116 --with-build-sysroot=sysroot
20117 use sysroot as the system root during the build
20118 --with-sysroot=DIR Search for usr/lib, usr/include, et al, within DIR.
20119 + --with-eglibc-configs=CONFIGS
20120 + build multilibs for these EGLIBC configurations
20121 + --with-specs=SPECS add SPECS to driver command-line processing
20122 --with-pkgversion=PKG Use PKG in the version string in place of "GCC"
20123 --with-bugurl=URL Direct users to URL to report a bug
20124 + --with-multilib-list Select multilibs (SH only)
20125 --with-gnu-ld assume the C compiler uses GNU ld default=no
20126 --with-libiconv-prefix[=DIR] search for libiconv in DIR/include and DIR/lib
20127 --without-libiconv-prefix don't search for libiconv in includedir and libdir
20128 @@ -8042,6 +8048,28 @@ fi;
20133 +# Check whether --with-eglibc-configs or --without-eglibc-configs was given.
20134 +if test "${with_eglibc_configs+set}" = set; then
20135 + withval="$with_eglibc_configs"
20136 + EGLIBC_CONFIGS=$withval
20144 +# Check whether --with-specs or --without-specs was given.
20145 +if test "${with_specs+set}" = set; then
20146 + withval="$with_specs"
20147 + CONFIGURE_SPECS=$withval
20154 # Build with intermodule optimisations
20155 # Check whether --enable-intermodule or --disable-intermodule was given.
20156 if test "${enable_intermodule+set}" = set; then
20157 @@ -8137,6 +8165,15 @@ fi;
20162 +# Check whether --with-multilib-list or --without-multilib-list was given.
20163 +if test "${with_multilib_list+set}" = set; then
20164 + withval="$with_multilib_list"
20167 + with_multilib_list=default
20170 # -------------------------
20171 # Checks for other programs
20172 # -------------------------
20173 @@ -14509,13 +14546,13 @@ if test "${lt_cv_nm_interface+set}" = se
20175 lt_cv_nm_interface="BSD nm"
20176 echo "int some_variable = 0;" > conftest.$ac_ext
20177 - (eval echo "\"\$as_me:14512: $ac_compile\"" >&5)
20178 + (eval echo "\"\$as_me:14621: $ac_compile\"" >&5)
20179 (eval "$ac_compile" 2>conftest.err)
20180 cat conftest.err >&5
20181 - (eval echo "\"\$as_me:14515: $NM \\\"conftest.$ac_objext\\\"\"" >&5)
20182 + (eval echo "\"\$as_me:14624: $NM \\\"conftest.$ac_objext\\\"\"" >&5)
20183 (eval "$NM \"conftest.$ac_objext\"" 2>conftest.err > conftest.out)
20184 cat conftest.err >&5
20185 - (eval echo "\"\$as_me:14518: output\"" >&5)
20186 + (eval echo "\"\$as_me:14627: output\"" >&5)
20187 cat conftest.out >&5
20188 if $GREP 'External.*some_variable' conftest.out > /dev/null; then
20189 lt_cv_nm_interface="MS dumpbin"
20190 @@ -15672,7 +15709,7 @@ ia64-*-hpux*)
20193 # Find out which ABI we are using.
20194 - echo '#line 15675 "configure"' > conftest.$ac_ext
20195 + echo '#line 15784 "configure"' > conftest.$ac_ext
20196 if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
20197 (eval $ac_compile) 2>&5
20199 @@ -16971,11 +17008,11 @@ else
20200 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
20201 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
20202 -e 's:$: $lt_compiler_flag:'`
20203 - (eval echo "\"\$as_me:16974: $lt_compile\"" >&5)
20204 + (eval echo "\"\$as_me:17083: $lt_compile\"" >&5)
20205 (eval "$lt_compile" 2>conftest.err)
20207 cat conftest.err >&5
20208 - echo "$as_me:16978: \$? = $ac_status" >&5
20209 + echo "$as_me:17087: \$? = $ac_status" >&5
20210 if (exit $ac_status) && test -s "$ac_outfile"; then
20211 # The compiler can only warn and ignore the option if not recognized
20212 # So say no if there are warnings other than the usual output.
20213 @@ -17310,11 +17347,11 @@ else
20214 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
20215 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
20216 -e 's:$: $lt_compiler_flag:'`
20217 - (eval echo "\"\$as_me:17313: $lt_compile\"" >&5)
20218 + (eval echo "\"\$as_me:17422: $lt_compile\"" >&5)
20219 (eval "$lt_compile" 2>conftest.err)
20221 cat conftest.err >&5
20222 - echo "$as_me:17317: \$? = $ac_status" >&5
20223 + echo "$as_me:17426: \$? = $ac_status" >&5
20224 if (exit $ac_status) && test -s "$ac_outfile"; then
20225 # The compiler can only warn and ignore the option if not recognized
20226 # So say no if there are warnings other than the usual output.
20227 @@ -17415,11 +17452,11 @@ else
20228 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
20229 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
20230 -e 's:$: $lt_compiler_flag:'`
20231 - (eval echo "\"\$as_me:17418: $lt_compile\"" >&5)
20232 + (eval echo "\"\$as_me:17527: $lt_compile\"" >&5)
20233 (eval "$lt_compile" 2>out/conftest.err)
20235 cat out/conftest.err >&5
20236 - echo "$as_me:17422: \$? = $ac_status" >&5
20237 + echo "$as_me:17531: \$? = $ac_status" >&5
20238 if (exit $ac_status) && test -s out/conftest2.$ac_objext
20240 # The compiler can only warn and ignore the option if not recognized
20241 @@ -17470,11 +17507,11 @@ else
20242 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
20243 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
20244 -e 's:$: $lt_compiler_flag:'`
20245 - (eval echo "\"\$as_me:17473: $lt_compile\"" >&5)
20246 + (eval echo "\"\$as_me:17582: $lt_compile\"" >&5)
20247 (eval "$lt_compile" 2>out/conftest.err)
20249 cat out/conftest.err >&5
20250 - echo "$as_me:17477: \$? = $ac_status" >&5
20251 + echo "$as_me:17586: \$? = $ac_status" >&5
20252 if (exit $ac_status) && test -s out/conftest2.$ac_objext
20254 # The compiler can only warn and ignore the option if not recognized
20255 @@ -20282,7 +20319,7 @@ else
20256 lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
20257 lt_status=$lt_dlunknown
20258 cat > conftest.$ac_ext <<_LT_EOF
20259 -#line 20285 "configure"
20260 +#line 20394 "configure"
20261 #include "confdefs.h"
20264 @@ -20378,7 +20415,7 @@ else
20265 lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
20266 lt_status=$lt_dlunknown
20267 cat > conftest.$ac_ext <<_LT_EOF
20268 -#line 20381 "configure"
20269 +#line 20490 "configure"
20270 #include "confdefs.h"
20273 @@ -22144,6 +22181,22 @@ x:
20275 tls_as_opt='-32 --fatal-warnings'
20279 + .section .tdata,"awT",@progbits
20284 + move.l x@TLSGD(%a5),%a0
20285 + move.l x@TLSLDM(%a5),%a0
20286 + move.l x@TLSLDO(%a5),%a0
20287 + move.l x@TLSIE(%a5),%a0
20288 + move.l x@TLSLE(%a5),%a0'
20289 + tls_first_major=2
20290 + tls_first_minor=19
20291 + tls_as_opt='--fatal-warnings'
20295 .section ".tdata","awT",@progbits
20296 @@ -22775,6 +22828,44 @@ fi
20297 i[34567]86-*-* | x86_64-*-*)
20299 cygwin* | pe | mingw32*)
20300 + # Recent binutils allows the three-operand form of ".comm" on PE. This
20301 + # definition is used unconditionally to initialise the default state of
20302 + # the target option variable that governs usage of the feature.
20303 + echo "$as_me:$LINENO: checking assembler for .comm with alignment" >&5
20304 +echo $ECHO_N "checking assembler for .comm with alignment... $ECHO_C" >&6
20305 +if test "${gcc_cv_as_comm_has_align+set}" = set; then
20306 + echo $ECHO_N "(cached) $ECHO_C" >&6
20308 + gcc_cv_as_comm_has_align=no
20309 + if test $in_tree_gas = yes; then
20310 + if test $gcc_cv_gas_vers -ge `expr \( \( 2 \* 1000 \) + 19 \) \* 1000 + 52`
20311 + then gcc_cv_as_comm_has_align=yes
20313 + elif test x$gcc_cv_as != x; then
20314 + echo '.comm foo,1,32' > conftest.s
20315 + if { ac_try='$gcc_cv_as -o conftest.o conftest.s >&5'
20316 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
20317 + (eval $ac_try) 2>&5
20319 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
20320 + (exit $ac_status); }; }
20322 + gcc_cv_as_comm_has_align=yes
20324 + echo "configure: failed program was" >&5
20325 + cat conftest.s >&5
20327 + rm -f conftest.o conftest.s
20330 +echo "$as_me:$LINENO: result: $gcc_cv_as_comm_has_align" >&5
20331 +echo "${ECHO_T}$gcc_cv_as_comm_has_align" >&6
20334 +cat >>confdefs.h <<_ACEOF
20335 +#define HAVE_GAS_ALIGNED_COMM `if test $gcc_cv_as_comm_has_align = yes; then echo 1; else echo 0; fi`
20338 # Used for DWARF 2 in PE
20339 echo "$as_me:$LINENO: checking assembler for .secrel32 relocs" >&5
20340 echo $ECHO_N "checking assembler for .secrel32 relocs... $ECHO_C" >&6
20341 @@ -24747,6 +24838,21 @@ else
20345 +# Check whether --enable-poison-system-directories or --disable-poison-system-directories was given.
20346 +if test "${enable_poison_system_directories+set}" = set; then
20347 + enableval="$enable_poison_system_directories"
20350 + enable_poison_system_directories=no
20352 +if test "x${enable_poison_system_directories}" = "xyes"; then
20354 +cat >>confdefs.h <<\_ACEOF
20355 +#define ENABLE_POISON_SYSTEM_DIRECTORIES 1
20360 # Substitute configuration variables
20363 @@ -25523,6 +25629,8 @@ s,@enable_shared@,$enable_shared,;t t
20364 s,@TARGET_SYSTEM_ROOT@,$TARGET_SYSTEM_ROOT,;t t
20365 s,@TARGET_SYSTEM_ROOT_DEFINE@,$TARGET_SYSTEM_ROOT_DEFINE,;t t
20366 s,@CROSS_SYSTEM_HEADER_DIR@,$CROSS_SYSTEM_HEADER_DIR,;t t
20367 +s,@EGLIBC_CONFIGS@,$EGLIBC_CONFIGS,;t t
20368 +s,@CONFIGURE_SPECS@,$CONFIGURE_SPECS,;t t
20369 s,@onestep@,$onestep,;t t
20370 s,@PKGVERSION@,$PKGVERSION,;t t
20371 s,@REPORT_BUGS_TO@,$REPORT_BUGS_TO,;t t
20372 @@ -25642,6 +25750,9 @@ s,@check_languages@,$check_languages,;t
20373 s,@cpp_install_dir@,$cpp_install_dir,;t t
20374 s,@xmake_file@,$xmake_file,;t t
20375 s,@tmake_file@,$tmake_file,;t t
20376 +s,@TM_ENDIAN_CONFIG@,$TM_ENDIAN_CONFIG,;t t
20377 +s,@TM_MULTILIB_CONFIG@,$TM_MULTILIB_CONFIG,;t t
20378 +s,@TM_MULTILIB_EXCEPTIONS_CONFIG@,$TM_MULTILIB_EXCEPTIONS_CONFIG,;t t
20379 s,@extra_gcc_objs@,$extra_gcc_objs,;t t
20380 s,@extra_headers_list@,$extra_headers_list,;t t
20381 s,@extra_objs@,$extra_objs,;t t
20382 --- a/gcc/configure.ac
20383 +++ b/gcc/configure.ac
20384 @@ -770,6 +770,22 @@ AC_SUBST(TARGET_SYSTEM_ROOT)
20385 AC_SUBST(TARGET_SYSTEM_ROOT_DEFINE)
20386 AC_SUBST(CROSS_SYSTEM_HEADER_DIR)
20388 +AC_ARG_WITH(eglibc-configs,
20389 + [AS_HELP_STRING([--with-eglibc-configs=CONFIGS],
20390 + [build multilibs for these EGLIBC configurations])],
20391 + [EGLIBC_CONFIGS=$withval],
20392 + [EGLIBC_CONFIGS=]
20394 +AC_SUBST(EGLIBC_CONFIGS)
20396 +AC_ARG_WITH(specs,
20397 + [AS_HELP_STRING([--with-specs=SPECS],
20398 + [add SPECS to driver command-line processing])],
20399 + [CONFIGURE_SPECS=$withval],
20400 + [CONFIGURE_SPECS=]
20402 +AC_SUBST(CONFIGURE_SPECS)
20404 # Build with intermodule optimisations
20405 AC_ARG_ENABLE(intermodule,
20406 [ --enable-intermodule build the compiler in one step],
20407 @@ -810,6 +826,11 @@ AC_SUBST(datarootdir)
20411 +AC_ARG_WITH(multilib-list,
20412 +[ --with-multilib-list Select multilibs (SH only)],
20414 +with_multilib_list=default)
20416 # -------------------------
20417 # Checks for other programs
20418 # -------------------------
20419 @@ -2587,6 +2608,22 @@ x:
20421 tls_as_opt='-32 --fatal-warnings'
20425 + .section .tdata,"awT",@progbits
20430 + move.l x@TLSGD(%a5),%a0
20431 + move.l x@TLSLDM(%a5),%a0
20432 + move.l x@TLSLDO(%a5),%a0
20433 + move.l x@TLSIE(%a5),%a0
20434 + move.l x@TLSLE(%a5),%a0'
20435 + tls_first_major=2
20436 + tls_first_minor=19
20437 + tls_as_opt='--fatal-warnings'
20441 .section ".tdata","awT",@progbits
20442 @@ -2955,6 +2992,15 @@ changequote(,)dnl
20443 changequote([,])dnl
20445 cygwin* | pe | mingw32*)
20446 + # Recent binutils allows the three-operand form of ".comm" on PE. This
20447 + # definition is used unconditionally to initialise the default state of
20448 + # the target option variable that governs usage of the feature.
20449 + gcc_GAS_CHECK_FEATURE([.comm with alignment], gcc_cv_as_comm_has_align,
20450 + [2,19,52],,[.comm foo,1,32])
20451 + AC_DEFINE_UNQUOTED(HAVE_GAS_ALIGNED_COMM,
20452 + [`if test $gcc_cv_as_comm_has_align = yes; then echo 1; else echo 0; fi`],
20453 + [Define if your assembler supports specifying the alignment
20454 + of objects allocated using the GAS .comm command.])
20455 # Used for DWARF 2 in PE
20456 gcc_GAS_CHECK_FEATURE([.secrel32 relocs],
20457 gcc_cv_as_ix86_pe_secrel32,
20458 @@ -3902,6 +3948,16 @@ htmldir="\${prefix}/$with_htmldir",
20459 htmldir='$(docdir)')
20462 +AC_ARG_ENABLE([poison-system-directories],
20463 + AS_HELP_STRING([--enable-poison-system-directories],
20464 + [warn for use of native system header directories]),,
20465 + [enable_poison_system_directories=no])
20466 +if test "x${enable_poison_system_directories}" = "xyes"; then
20467 + AC_DEFINE([ENABLE_POISON_SYSTEM_DIRECTORIES],
20469 + [Define to warn for use of native system header directories])
20472 # Substitute configuration variables
20475 @@ -3921,6 +3977,9 @@ AC_SUBST(check_languages)
20476 AC_SUBST(cpp_install_dir)
20477 AC_SUBST(xmake_file)
20478 AC_SUBST(tmake_file)
20479 +AC_SUBST(TM_ENDIAN_CONFIG)
20480 +AC_SUBST(TM_MULTILIB_CONFIG)
20481 +AC_SUBST(TM_MULTILIB_EXCEPTIONS_CONFIG)
20482 AC_SUBST(extra_gcc_objs)
20483 AC_SUBST(extra_headers_list)
20484 AC_SUBST(extra_objs)
20485 --- a/gcc/cp/class.c
20486 +++ b/gcc/cp/class.c
20487 @@ -6136,7 +6136,7 @@ resolve_address_of_overloaded_function (
20488 if (flags & tf_error)
20490 error ("no matches converting function %qD to type %q#T",
20491 - DECL_NAME (OVL_FUNCTION (overload)),
20492 + DECL_NAME (OVL_CURRENT (overload)),
20495 /* print_candidates expects a chain with the functions in
20496 @@ -6299,13 +6299,8 @@ instantiate_type (tree lhstype, tree rhs
20497 dependent on overload resolution. */
20498 gcc_assert (TREE_CODE (rhs) == ADDR_EXPR
20499 || TREE_CODE (rhs) == COMPONENT_REF
20500 - || TREE_CODE (rhs) == COMPOUND_EXPR
20501 - || really_overloaded_fn (rhs));
20503 - /* We don't overwrite rhs if it is an overloaded function.
20504 - Copying it would destroy the tree link. */
20505 - if (TREE_CODE (rhs) != OVERLOAD)
20506 - rhs = copy_node (rhs);
20507 + || really_overloaded_fn (rhs)
20508 + || (flag_ms_extensions && TREE_CODE (rhs) == FUNCTION_DECL));
20510 /* This should really only be used when attempting to distinguish
20511 what sort of a pointer to function we have. For now, any
20512 @@ -6357,19 +6352,6 @@ instantiate_type (tree lhstype, tree rhs
20513 /*explicit_targs=*/NULL_TREE,
20516 - case COMPOUND_EXPR:
20517 - TREE_OPERAND (rhs, 0)
20518 - = instantiate_type (lhstype, TREE_OPERAND (rhs, 0), flags);
20519 - if (TREE_OPERAND (rhs, 0) == error_mark_node)
20520 - return error_mark_node;
20521 - TREE_OPERAND (rhs, 1)
20522 - = instantiate_type (lhstype, TREE_OPERAND (rhs, 1), flags);
20523 - if (TREE_OPERAND (rhs, 1) == error_mark_node)
20524 - return error_mark_node;
20526 - TREE_TYPE (rhs) = lhstype;
20531 if (PTRMEM_OK_P (rhs))
20532 --- a/gcc/cp/cp-tree.h
20533 +++ b/gcc/cp/cp-tree.h
20534 @@ -43,9 +43,6 @@ along with GCC; see the file COPYING3.
20536 #define ATTRIBUTE_GCC_CXXDIAG(m, n) ATTRIBUTE_NONNULL(m)
20538 -extern void cp_cpp_error (cpp_reader *, int,
20539 - const char *, va_list *)
20540 - ATTRIBUTE_GCC_CXXDIAG(3,0);
20541 #ifdef GCC_TOPLEV_H
20543 In order for the format checking to accept the C++ front end diagnostic \
20546 @@ -581,6 +581,7 @@ ocp_convert (tree type, tree expr, int c
20548 enum tree_code code = TREE_CODE (type);
20549 const char *invalid_conv_diag;
20552 if (error_operand_p (e) || type == error_mark_node)
20553 return error_mark_node;
20554 @@ -629,6 +630,10 @@ ocp_convert (tree type, tree expr, int c
20558 + e1 = targetm.convert_to_type (type, e);
20562 if (code == VOID_TYPE && (convtype & CONV_STATIC))
20564 e = convert_to_void (e, /*implicit=*/NULL, tf_warning_or_error);
20565 @@ -1231,11 +1236,18 @@ build_expr_type_conversion (int desires,
20567 type_promotes_to (tree type)
20569 + tree promoted_type;
20571 if (type == error_mark_node)
20572 return error_mark_node;
20574 type = TYPE_MAIN_VARIANT (type);
20576 + /* Check for promotions of target-defined types first. */
20577 + promoted_type = targetm.promoted_type (type);
20578 + if (promoted_type)
20579 + return promoted_type;
20581 /* bool always promotes to int (not unsigned), even if it's the same
20583 if (type == boolean_type_node)
20584 --- a/gcc/cp/decl.c
20585 +++ b/gcc/cp/decl.c
20586 @@ -4508,7 +4508,7 @@ maybe_deduce_size_from_array_init (tree
20588 cp_apply_type_quals_to_decl (cp_type_quals (TREE_TYPE (decl)), decl);
20590 - layout_decl (decl, 0);
20591 + relayout_decl (decl);
20595 @@ -7622,6 +7622,7 @@ grokdeclarator (const cp_declarator *dec
20596 bool type_was_error_mark_node = false;
20597 bool parameter_pack_p = declarator? declarator->parameter_pack_p : false;
20598 bool template_type_arg = false;
20599 + const char *errmsg;
20601 signed_p = declspecs->specs[(int)ds_signed];
20602 unsigned_p = declspecs->specs[(int)ds_unsigned];
20603 @@ -8300,6 +8301,12 @@ grokdeclarator (const cp_declarator *dec
20604 decl, but to its return type. */
20605 type_quals = TYPE_UNQUALIFIED;
20607 + errmsg = targetm.invalid_return_type (type);
20611 + type = integer_type_node;
20614 /* Error about some types functions can't return. */
20616 @@ -8842,8 +8849,13 @@ grokdeclarator (const cp_declarator *dec
20618 /* Replace the anonymous name with the real name everywhere. */
20619 for (t = TYPE_MAIN_VARIANT (type); t; t = TYPE_NEXT_VARIANT (t))
20620 - if (TYPE_NAME (t) == oldname)
20621 - TYPE_NAME (t) = decl;
20623 + if (ANON_AGGRNAME_P (TYPE_IDENTIFIER (t)))
20625 + debug_hooks->set_name (t, decl);
20626 + TYPE_NAME (t) = decl;
20630 if (TYPE_LANG_SPECIFIC (type))
20631 TYPE_WAS_ANONYMOUS (type) = 1;
20632 @@ -9679,6 +9691,7 @@ grokparms (tree parmlist, tree *parms)
20633 tree type = NULL_TREE;
20634 tree init = TREE_PURPOSE (parm);
20635 tree decl = TREE_VALUE (parm);
20636 + const char *errmsg;
20638 if (parm == void_list_node)
20640 @@ -9712,6 +9725,14 @@ grokparms (tree parmlist, tree *parms)
20644 + if (type != error_mark_node
20645 + && (errmsg = targetm.invalid_parameter_type (type)))
20648 + type = error_mark_node;
20649 + TREE_TYPE (decl) = error_mark_node;
20652 if (type != error_mark_node)
20654 if (deprecated_state != DEPRECATED_SUPPRESS)
20655 --- a/gcc/cp/decl2.c
20656 +++ b/gcc/cp/decl2.c
20657 @@ -1724,6 +1724,10 @@ decl_needed_p (tree decl)
20658 || (DECL_ASSEMBLER_NAME_SET_P (decl)
20659 && TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl))))
20661 + /* Functions marked "dllexport" must be emitted so that they are
20662 + visible to other DLLs. */
20663 + if (lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl)))
20665 /* Otherwise, DECL does not need to be emitted -- yet. A subsequent
20666 reference to DECL might cause it to be emitted later. */
20668 @@ -3810,6 +3814,15 @@ mark_used (tree decl)
20671 TREE_USED (decl) = 1;
20672 + if (current_function_decl != NULL_TREE
20673 + && (TREE_CODE (decl) == VAR_DECL
20674 + || TREE_CODE (decl) == PARM_DECL
20675 + || TREE_CODE (decl) == FUNCTION_DECL))
20677 + tree context = decl_function_context (decl);
20678 + if (context != NULL_TREE && context != current_function_decl)
20679 + DECL_NONLOCAL (decl) = 1;
20681 if (DECL_CLONED_FUNCTION_P (decl))
20682 TREE_USED (DECL_CLONED_FUNCTION (decl)) = 1;
20683 if (TREE_CODE (decl) == FUNCTION_DECL
20684 --- a/gcc/cp/error.c
20685 +++ b/gcc/cp/error.c
20686 @@ -2670,39 +2670,6 @@ cp_printer (pretty_printer *pp, text_inf
20690 -/* Callback from cpp_error for PFILE to print diagnostics arising from
20691 - interpreting strings. The diagnostic is of type LEVEL; MSG is the
20692 - translated message and AP the arguments. */
20695 -cp_cpp_error (cpp_reader *pfile ATTRIBUTE_UNUSED, int level,
20696 - const char *msg, va_list *ap)
20698 - diagnostic_info diagnostic;
20699 - diagnostic_t dlevel;
20702 - case CPP_DL_WARNING:
20703 - case CPP_DL_WARNING_SYSHDR:
20704 - dlevel = DK_WARNING;
20706 - case CPP_DL_PEDWARN:
20707 - dlevel = DK_PEDWARN;
20709 - case CPP_DL_ERROR:
20710 - dlevel = DK_ERROR;
20716 - gcc_unreachable ();
20718 - diagnostic_set_info_translated (&diagnostic, msg, ap,
20719 - input_location, dlevel);
20720 - report_diagnostic (&diagnostic);
20723 /* Warn about the use of C++0x features when appropriate. */
20725 maybe_warn_cpp0x (const char* str)
20726 --- a/gcc/cp/except.c
20727 +++ b/gcc/cp/except.c
20728 @@ -146,14 +146,26 @@ eh_type_info (tree type)
20730 build_eh_type_type (tree type)
20732 - tree exp = eh_type_info (type);
20733 + bool is_ref = TREE_CODE (type) == REFERENCE_TYPE;
20737 + type = TREE_TYPE (type);
20739 + exp = eh_type_info (type);
20746 - return convert (ptr_type_node, build_address (exp));
20747 + exp = build_address (exp);
20750 + exp = targetm.cxx.ttype_ref_encode (exp);
20752 + exp = convert (ptr_type_node, exp);
20757 @@ -495,6 +507,16 @@ expand_start_catch_block (tree decl)
20758 initialize_handler_parm (decl, exp);
20761 + /* Preserve the reference type on the exception, as this affects
20762 + derived-to-base conversions in catch matching. Only do this when
20763 + the ABI supports it, as originally this case was (incorrectly)
20764 + treated just as catching a pointer-to-class by value. */
20765 + if (targetm.cxx.ttype_ref_encode
20766 + && decl && TREE_CODE (type) == POINTER_TYPE
20767 + && CLASS_TYPE_P (TREE_TYPE (type))
20768 + && TREE_CODE (TREE_TYPE (decl)) == REFERENCE_TYPE)
20769 + type = build_reference_type (type);
20774 @@ -538,10 +560,20 @@ finish_eh_spec_block (tree raw_raises, t
20775 raw_raises && TREE_VALUE (raw_raises);
20776 raw_raises = TREE_CHAIN (raw_raises))
20778 - tree type = prepare_eh_type (TREE_VALUE (raw_raises));
20779 + tree orig_type = TREE_VALUE (raw_raises);
20780 + tree type = prepare_eh_type (orig_type);
20781 tree tinfo = eh_type_info (type);
20784 + /* Preserve the reference type on the exception, as this affects
20785 + derived-to-base conversions in catch matching. Only do this when
20786 + the ABI supports it, as originally this case was (incorrectly)
20787 + treated just as catching a pointer-to-class by value. */
20788 + if (targetm.cxx.ttype_ref_encode
20789 + && TREE_CODE (orig_type) == REFERENCE_TYPE
20790 + && TREE_CODE (type) == POINTER_TYPE
20791 + && CLASS_TYPE_P (TREE_TYPE (type)))
20792 + type = build_reference_type (type);
20793 raises = tree_cons (NULL_TREE, type, raises);
20796 @@ -956,24 +988,40 @@ nothrow_libfn_p (const_tree fn)
20798 can_convert_eh (tree to, tree from)
20800 - to = non_reference (to);
20801 - from = non_reference (from);
20802 + bool to_ref = TREE_CODE (to) == REFERENCE_TYPE;
20803 + int depth = to_ref;
20804 + bool outer_const = true;
20806 - if (TREE_CODE (to) == POINTER_TYPE && TREE_CODE (from) == POINTER_TYPE)
20808 + to = TREE_TYPE (to);
20809 + from = non_reference (from);
20811 + while (TREE_CODE (to) == POINTER_TYPE && TREE_CODE (from) == POINTER_TYPE)
20813 + unsigned to_quals, from_quals;
20817 to = TREE_TYPE (to);
20818 from = TREE_TYPE (from);
20819 + to_quals = TYPE_QUALS (to);
20820 + from_quals = TYPE_QUALS (from);
20822 - if (! at_least_as_qualified_p (to, from))
20823 + if ((from_quals & ~to_quals)
20824 + || (!outer_const && to_quals & ~from_quals))
20827 - if (TREE_CODE (to) == VOID_TYPE)
20830 - /* Else fall through. */
20832 + if (!(to_quals & TYPE_QUAL_CONST))
20833 + outer_const = false;
20836 - if (CLASS_TYPE_P (to) && CLASS_TYPE_P (from)
20837 + if (same_type_ignoring_top_level_qualifiers_p (from, to))
20840 + if (depth == to_ref + 1 && TREE_CODE (to) == VOID_TYPE)
20843 + if (depth < 2 && CLASS_TYPE_P (to) && CLASS_TYPE_P (from)
20844 && PUBLICLY_UNIQUELY_DERIVED_P (to, from))
20847 --- a/gcc/cp/parser.c
20848 +++ b/gcc/cp/parser.c
20849 @@ -309,8 +309,7 @@ cp_lexer_new_main (void)
20851 /* Subsequent preprocessor diagnostics should use compiler
20852 diagnostic functions to get the compiler source location. */
20853 - cpp_get_options (parse_in)->client_diagnostic = true;
20854 - cpp_get_callbacks (parse_in)->error = cp_cpp_error;
20855 + done_lexing = true;
20857 gcc_assert (lexer->next_token->type != CPP_PURGED);
20859 --- a/gcc/cp/rtti.c
20860 +++ b/gcc/cp/rtti.c
20861 @@ -393,6 +393,7 @@ get_tinfo_decl (tree type)
20865 + gcc_assert (TREE_CODE (type) != REFERENCE_TYPE);
20866 name = mangle_typeinfo_for_type (type);
20868 d = IDENTIFIER_GLOBAL_VALUE (name);
20869 --- a/gcc/cp/semantics.c
20870 +++ b/gcc/cp/semantics.c
20871 @@ -1120,7 +1120,11 @@ finish_handler_parms (tree decl, tree ha
20872 type = expand_start_catch_block (decl);
20873 HANDLER_TYPE (handler) = type;
20874 if (!processing_template_decl && type)
20875 - mark_used (eh_type_info (type));
20877 + if (TREE_CODE (type) == REFERENCE_TYPE)
20878 + type = TREE_TYPE (type);
20879 + mark_used (eh_type_info (type));
20883 /* Finish a handler, which may be given by HANDLER. The BLOCKs are
20884 @@ -3242,8 +3246,10 @@ expand_or_defer_fn (tree fn)
20886 /* If the user wants us to keep all inline functions, then mark
20887 this function as needed so that finish_file will make sure to
20888 - output it later. */
20889 - if (flag_keep_inline_functions && DECL_DECLARED_INLINE_P (fn))
20890 + output it later. Similarly, all dllexport'd functions must
20891 + be emitted; there may be callers in other DLLs. */
20892 + if ((flag_keep_inline_functions && DECL_DECLARED_INLINE_P (fn))
20893 + || lookup_attribute ("dllexport", DECL_ATTRIBUTES (fn)))
20897 --- a/gcc/cp/typeck.c
20898 +++ b/gcc/cp/typeck.c
20899 @@ -1707,10 +1707,14 @@ decay_conversion (tree exp)
20901 default_conversion (tree exp)
20903 + /* Check for target-specific promotions. */
20904 + tree promoted_type = targetm.promoted_type (TREE_TYPE (exp));
20905 + if (promoted_type)
20906 + exp = cp_convert (promoted_type, exp);
20907 /* Perform the integral promotions first so that bitfield
20908 expressions (which may promote to "int", even if the bitfield is
20909 declared "unsigned") are promoted correctly. */
20910 - if (INTEGRAL_OR_UNSCOPED_ENUMERATION_TYPE_P (TREE_TYPE (exp)))
20911 + else if (INTEGRAL_OR_UNSCOPED_ENUMERATION_TYPE_P (TREE_TYPE (exp)))
20912 exp = perform_integral_promotions (exp);
20913 /* Perform the other conversions. */
20914 exp = decay_conversion (exp);
20915 @@ -3389,6 +3393,25 @@ cp_build_binary_op (location_t location,
20916 return error_mark_node;
20919 + /* Issue warnings about peculiar, but valid, uses of NULL. */
20920 + if ((orig_op0 == null_node || orig_op1 == null_node)
20921 + /* It's reasonable to use pointer values as operands of &&
20922 + and ||, so NULL is no exception. */
20923 + && code != TRUTH_ANDIF_EXPR && code != TRUTH_ORIF_EXPR
20924 + && ( /* Both are NULL (or 0) and the operation was not a
20925 + comparison or a pointer subtraction. */
20926 + (null_ptr_cst_p (orig_op0) && null_ptr_cst_p (orig_op1)
20927 + && code != EQ_EXPR && code != NE_EXPR && code != MINUS_EXPR)
20928 + /* Or if one of OP0 or OP1 is neither a pointer nor NULL. */
20929 + || (!null_ptr_cst_p (orig_op0)
20930 + && !TYPE_PTR_P (type0) && !TYPE_PTR_TO_MEMBER_P (type0))
20931 + || (!null_ptr_cst_p (orig_op1)
20932 + && !TYPE_PTR_P (type1) && !TYPE_PTR_TO_MEMBER_P (type1)))
20933 + && (complain & tf_warning))
20934 + /* Some sort of arithmetic operation involving NULL was
20936 + warning (OPT_Wpointer_arith, "NULL used in arithmetic");
20941 @@ -3979,25 +4002,6 @@ cp_build_binary_op (location_t location,
20945 - /* Issue warnings about peculiar, but valid, uses of NULL. */
20946 - if ((orig_op0 == null_node || orig_op1 == null_node)
20947 - /* It's reasonable to use pointer values as operands of &&
20948 - and ||, so NULL is no exception. */
20949 - && code != TRUTH_ANDIF_EXPR && code != TRUTH_ORIF_EXPR
20950 - && ( /* Both are NULL (or 0) and the operation was not a comparison. */
20951 - (null_ptr_cst_p (orig_op0) && null_ptr_cst_p (orig_op1)
20952 - && code != EQ_EXPR && code != NE_EXPR)
20953 - /* Or if one of OP0 or OP1 is neither a pointer nor NULL. */
20954 - || (!null_ptr_cst_p (orig_op0) && TREE_CODE (TREE_TYPE (op0)) != POINTER_TYPE)
20955 - || (!null_ptr_cst_p (orig_op1) && TREE_CODE (TREE_TYPE (op1)) != POINTER_TYPE))
20956 - && (complain & tf_warning))
20957 - /* Some sort of arithmetic operation involving NULL was
20958 - performed. Note that pointer-difference and pointer-addition
20959 - have already been handled above, and so we don't end up here in
20961 - warning (OPT_Wpointer_arith, "NULL used in arithmetic");
20964 /* If CONVERTED is zero, both args will be converted to type RESULT_TYPE.
20965 Then the expression will be built.
20966 It will be given type FINAL_TYPE if that is nonzero;
20967 @@ -5024,6 +5028,12 @@ cp_build_compound_expr (tree lhs, tree r
20971 + if (type_unknown_p (rhs))
20973 + error ("no context to resolve type of %qE", rhs);
20974 + return error_mark_node;
20977 return build2 (COMPOUND_EXPR, TREE_TYPE (rhs), lhs, rhs);
20982 @@ -5754,6 +5754,11 @@ cse_process_notes_1 (rtx x, rtx object,
20983 validate_change (object, &XEXP (x, i),
20984 cse_process_notes (XEXP (x, i), object, changed), 0);
20986 + /* Rebuild a PLUS expression in canonical form if the first operand
20987 + ends up as a constant. */
20988 + if (code == PLUS && GET_CODE (XEXP (x, 0)) == CONST_INT)
20989 + return plus_constant (XEXP(x, 1), INTVAL (XEXP (x, 0)));
20996 @@ -377,6 +377,7 @@ const struct gcc_debug_hooks dbx_debug_h
20997 dbxout_handle_pch, /* handle_pch */
20998 debug_nothing_rtx, /* var_location */
20999 debug_nothing_void, /* switch_text_section */
21000 + debug_nothing_tree_tree, /* set_name */
21001 0 /* start_end_main_source_file */
21003 #endif /* DBX_DEBUGGING_INFO */
21004 @@ -410,6 +411,7 @@ const struct gcc_debug_hooks xcoff_debug
21005 dbxout_handle_pch, /* handle_pch */
21006 debug_nothing_rtx, /* var_location */
21007 debug_nothing_void, /* switch_text_section */
21008 + debug_nothing_tree_tree, /* set_name */
21009 0 /* start_end_main_source_file */
21011 #endif /* XCOFF_DEBUGGING_INFO */
21014 @@ -51,6 +51,7 @@ const struct gcc_debug_hooks do_nothing_
21015 debug_nothing_int, /* handle_pch */
21016 debug_nothing_rtx, /* var_location */
21017 debug_nothing_void, /* switch_text_section */
21018 + debug_nothing_tree_tree, /* set_name */
21019 0 /* start_end_main_source_file */
21022 @@ -68,6 +69,12 @@ debug_nothing_tree (tree decl ATTRIBUTE_
21026 +debug_nothing_tree_tree (tree t1 ATTRIBUTE_UNUSED,
21027 + tree t2 ATTRIBUTE_UNUSED)
21032 debug_nothing_tree_tree_tree_bool (tree t1 ATTRIBUTE_UNUSED,
21033 tree t2 ATTRIBUTE_UNUSED,
21034 tree t3 ATTRIBUTE_UNUSED,
21037 @@ -130,6 +130,10 @@ struct gcc_debug_hooks
21039 void (* switch_text_section) (void);
21041 + /* Called from grokdeclarator. Replaces the anonymous name with the
21043 + void (* set_name) (tree, tree);
21045 /* This is 1 if the debug writer wants to see start and end commands for the
21046 main source files, and 0 otherwise. */
21047 int start_end_main_source_file;
21048 @@ -144,6 +148,7 @@ extern void debug_nothing_int_charstar (
21049 extern void debug_nothing_int (unsigned int);
21050 extern void debug_nothing_int_int (unsigned int, unsigned int);
21051 extern void debug_nothing_tree (tree);
21052 +extern void debug_nothing_tree_tree (tree, tree);
21053 extern void debug_nothing_tree_int (tree, int);
21054 extern void debug_nothing_tree_tree_tree_bool (tree, tree, tree, bool);
21055 extern bool debug_true_const_tree (const_tree);
21056 --- a/gcc/defaults.h
21057 +++ b/gcc/defaults.h
21058 @@ -902,7 +902,8 @@ see the files COPYING3 and COPYING.RUNTI
21060 /* On most machines, the CFA coincides with the first incoming parm. */
21061 #ifndef ARG_POINTER_CFA_OFFSET
21062 -#define ARG_POINTER_CFA_OFFSET(FNDECL) FIRST_PARM_OFFSET (FNDECL)
21063 +#define ARG_POINTER_CFA_OFFSET(FNDECL) \
21064 + (FIRST_PARM_OFFSET (FNDECL) + crtl->args.pretend_args_size)
21067 /* On most machines, we use the CFA as DW_AT_frame_base. */
21068 --- a/gcc/diagnostic.c
21069 +++ b/gcc/diagnostic.c
21070 @@ -126,6 +126,7 @@ diagnostic_set_info_translated (diagnost
21071 diagnostic->message.args_ptr = args;
21072 diagnostic->message.format_spec = msg;
21073 diagnostic->location = location;
21074 + diagnostic->override_column = 0;
21075 diagnostic->kind = kind;
21076 diagnostic->option_index = 0;
21078 @@ -153,6 +154,8 @@ diagnostic_build_prefix (diagnostic_info
21080 const char *text = _(diagnostic_kind_text[diagnostic->kind]);
21081 expanded_location s = expand_location (diagnostic->location);
21082 + if (diagnostic->override_column)
21083 + s.column = diagnostic->override_column;
21084 gcc_assert (diagnostic->kind < DK_LAST_DIAGNOSTIC_KIND);
21087 --- a/gcc/diagnostic.h
21088 +++ b/gcc/diagnostic.h
21089 @@ -41,6 +41,7 @@ typedef struct diagnostic_info
21092 location_t location;
21093 + unsigned int override_column;
21094 /* TREE_BLOCK if the diagnostic is to be reported in some inline
21095 function inlined into other function, otherwise NULL. */
21096 tree abstract_origin;
21097 @@ -185,6 +186,10 @@ extern diagnostic_context *global_dc;
21099 #define report_diagnostic(D) diagnostic_report_diagnostic (global_dc, D)
21101 +/* Override the column number to be used for reporting a
21103 +#define diagnostic_override_column(DI, COL) (DI)->override_column = (COL)
21105 /* Diagnostic related functions. */
21106 extern void diagnostic_initialize (diagnostic_context *);
21107 extern void diagnostic_report_current_module (diagnostic_context *);
21108 --- a/gcc/dwarf2out.c
21109 +++ b/gcc/dwarf2out.c
21110 @@ -2486,6 +2486,12 @@ dwarf2out_frame_debug (rtx insn, bool af
21111 insn = PATTERN (insn);
21113 dwarf2out_frame_debug_expr (insn, label);
21115 + /* Check again. A parallel can save and update the same register.
21116 + We could probably check just once, here, but this is safer than
21117 + removing the check above. */
21118 + if (clobbers_queued_reg_save (insn))
21119 + flush_queued_reg_saves ();
21123 @@ -4611,6 +4617,7 @@ static void dwarf2out_imported_module_or
21124 static void dwarf2out_abstract_function (tree);
21125 static void dwarf2out_var_location (rtx);
21126 static void dwarf2out_begin_function (tree);
21127 +static void dwarf2out_set_name (tree, tree);
21129 /* The debug hooks structure. */
21131 @@ -4645,6 +4652,7 @@ const struct gcc_debug_hooks dwarf2_debu
21132 debug_nothing_int, /* handle_pch */
21133 dwarf2out_var_location,
21134 dwarf2out_switch_text_section,
21135 + dwarf2out_set_name,
21136 1 /* start_end_main_source_file */
21139 @@ -5989,12 +5997,9 @@ debug_str_eq (const void *x1, const void
21140 (const char *)x2) == 0;
21143 -/* Add a string attribute value to a DIE. */
21145 -static inline void
21146 -add_AT_string (dw_die_ref die, enum dwarf_attribute attr_kind, const char *str)
21147 +static struct indirect_string_node *
21148 +find_AT_string (const char *str)
21150 - dw_attr_node attr;
21151 struct indirect_string_node *node;
21154 @@ -6015,6 +6020,18 @@ add_AT_string (dw_die_ref die, enum dwar
21155 node = (struct indirect_string_node *) *slot;
21161 +/* Add a string attribute value to a DIE. */
21163 +static inline void
21164 +add_AT_string (dw_die_ref die, enum dwarf_attribute attr_kind, const char *str)
21166 + dw_attr_node attr;
21167 + struct indirect_string_node *node;
21169 + node = find_AT_string (str);
21171 attr.dw_attr = attr_kind;
21172 attr.dw_attr_val.val_class = dw_val_class_str;
21173 @@ -6651,6 +6668,8 @@ decl_loc_table_eq (const void *x, const
21174 static inline var_loc_list *
21175 lookup_decl_loc (const_tree decl)
21177 + if (!decl_loc_table)
21179 return (var_loc_list *)
21180 htab_find_with_hash (decl_loc_table, decl, DECL_UID (decl));
21182 @@ -13502,6 +13521,7 @@ dwarf2out_abstract_function (tree decl)
21185 int was_abstract = DECL_ABSTRACT (decl);
21186 + htab_t old_decl_loc_table;
21188 /* Make sure we have the actual abstract inline, not a clone. */
21189 decl = DECL_ORIGIN (decl);
21190 @@ -13511,6 +13531,12 @@ dwarf2out_abstract_function (tree decl)
21191 /* We've already generated the abstract instance. */
21194 + /* We can be called while recursively when seeing block defining inlined subroutine
21195 + DIE. Be sure to not clobber the outer location table nor use it or we would
21196 + get locations in abstract instantces. */
21197 + old_decl_loc_table = decl_loc_table;
21198 + decl_loc_table = NULL;
21200 /* Be sure we've emitted the in-class declaration DIE (if any) first, so
21201 we don't get confused by DECL_ABSTRACT. */
21202 if (debug_info_level > DINFO_LEVEL_TERSE)
21203 @@ -13532,6 +13558,7 @@ dwarf2out_abstract_function (tree decl)
21204 set_decl_abstract_flags (decl, 0);
21206 current_function_decl = save_fn;
21207 + decl_loc_table = old_decl_loc_table;
21211 @@ -15881,6 +15908,31 @@ maybe_emit_file (struct dwarf_file_data
21212 return fd->emitted_number;
21215 +/* Replace DW_AT_name for the decl with name. */
21218 +dwarf2out_set_name (tree decl, tree name)
21221 + dw_attr_ref attr;
21223 + die = TYPE_SYMTAB_DIE (decl);
21227 + attr = get_AT (die, DW_AT_name);
21230 + struct indirect_string_node *node;
21232 + node = find_AT_string (dwarf2_name (name, 0));
21233 + /* replace the string. */
21234 + attr->dw_attr_val.v.val_str = node;
21238 + add_name_attribute (die, dwarf2_name (name, 0));
21240 /* Called by the final INSN scan whenever we see a var location. We
21241 use it to drop labels in the right places, and throw the location in
21242 our lookup table. */
21245 @@ -3567,6 +3567,12 @@ output_ttype (tree type, int tt_format,
21246 paths below go through assemble_integer, which would take
21247 care of this for us. */
21249 + if (TREE_CODE (type) == POINTER_PLUS_EXPR)
21251 + gcc_assert (TREE_CODE (TREE_OPERAND (type, 1)) == INTEGER_CST);
21252 + type = TREE_OPERAND (type, 0);
21253 + STRIP_NOPS (type);
21255 if (TREE_CODE (type) == ADDR_EXPR)
21257 type = TREE_OPERAND (type, 0);
21260 @@ -1491,9 +1491,9 @@ hard_function_value (const_tree valtype,
21261 in which a scalar value of mode MODE was returned by a library call. */
21264 -hard_libcall_value (enum machine_mode mode)
21265 +hard_libcall_value (enum machine_mode mode, rtx fun)
21267 - return LIBCALL_VALUE (mode);
21268 + return targetm.calls.libcall_value (mode, fun);
21271 /* Look up the tree code for a given rtx code
21274 @@ -103,7 +103,8 @@ static int add_cost[2][NUM_MACHINE_MODES
21275 static int neg_cost[2][NUM_MACHINE_MODES];
21276 static int shift_cost[2][NUM_MACHINE_MODES][MAX_BITS_PER_WORD];
21277 static int shiftadd_cost[2][NUM_MACHINE_MODES][MAX_BITS_PER_WORD];
21278 -static int shiftsub_cost[2][NUM_MACHINE_MODES][MAX_BITS_PER_WORD];
21279 +static int shiftsub0_cost[2][NUM_MACHINE_MODES][MAX_BITS_PER_WORD];
21280 +static int shiftsub1_cost[2][NUM_MACHINE_MODES][MAX_BITS_PER_WORD];
21281 static int mul_cost[2][NUM_MACHINE_MODES];
21282 static int sdiv_cost[2][NUM_MACHINE_MODES];
21283 static int udiv_cost[2][NUM_MACHINE_MODES];
21284 @@ -130,7 +131,8 @@ init_expmed (void)
21285 struct rtx_def shift; rtunion shift_fld1;
21286 struct rtx_def shift_mult; rtunion shift_mult_fld1;
21287 struct rtx_def shift_add; rtunion shift_add_fld1;
21288 - struct rtx_def shift_sub; rtunion shift_sub_fld1;
21289 + struct rtx_def shift_sub0; rtunion shift_sub0_fld1;
21290 + struct rtx_def shift_sub1; rtunion shift_sub1_fld1;
21293 rtx pow2[MAX_BITS_PER_WORD];
21294 @@ -201,9 +203,13 @@ init_expmed (void)
21295 XEXP (&all.shift_add, 0) = &all.shift_mult;
21296 XEXP (&all.shift_add, 1) = &all.reg;
21298 - PUT_CODE (&all.shift_sub, MINUS);
21299 - XEXP (&all.shift_sub, 0) = &all.shift_mult;
21300 - XEXP (&all.shift_sub, 1) = &all.reg;
21301 + PUT_CODE (&all.shift_sub0, MINUS);
21302 + XEXP (&all.shift_sub0, 0) = &all.shift_mult;
21303 + XEXP (&all.shift_sub0, 1) = &all.reg;
21305 + PUT_CODE (&all.shift_sub1, MINUS);
21306 + XEXP (&all.shift_sub1, 0) = &all.reg;
21307 + XEXP (&all.shift_sub1, 1) = &all.shift_mult;
21309 for (speed = 0; speed < 2; speed++)
21311 @@ -226,7 +232,8 @@ init_expmed (void)
21312 PUT_MODE (&all.shift, mode);
21313 PUT_MODE (&all.shift_mult, mode);
21314 PUT_MODE (&all.shift_add, mode);
21315 - PUT_MODE (&all.shift_sub, mode);
21316 + PUT_MODE (&all.shift_sub0, mode);
21317 + PUT_MODE (&all.shift_sub1, mode);
21319 add_cost[speed][mode] = rtx_cost (&all.plus, SET, speed);
21320 neg_cost[speed][mode] = rtx_cost (&all.neg, SET, speed);
21321 @@ -254,8 +261,8 @@ init_expmed (void)
21324 shift_cost[speed][mode][0] = 0;
21325 - shiftadd_cost[speed][mode][0] = shiftsub_cost[speed][mode][0]
21326 - = add_cost[speed][mode];
21327 + shiftadd_cost[speed][mode][0] = shiftsub0_cost[speed][mode][0]
21328 + = shiftsub1_cost[speed][mode][0] = add_cost[speed][mode];
21330 n = MIN (MAX_BITS_PER_WORD, GET_MODE_BITSIZE (mode));
21331 for (m = 1; m < n; m++)
21332 @@ -265,7 +272,8 @@ init_expmed (void)
21334 shift_cost[speed][mode][m] = rtx_cost (&all.shift, SET, speed);
21335 shiftadd_cost[speed][mode][m] = rtx_cost (&all.shift_add, SET, speed);
21336 - shiftsub_cost[speed][mode][m] = rtx_cost (&all.shift_sub, SET, speed);
21337 + shiftsub0_cost[speed][mode][m] = rtx_cost (&all.shift_sub0, SET, speed);
21338 + shiftsub1_cost[speed][mode][m] = rtx_cost (&all.shift_sub1, SET, speed);
21342 @@ -2397,6 +2405,7 @@ synth_mult (struct algorithm *alg_out, u
21343 struct mult_cost best_cost;
21344 struct mult_cost new_limit;
21345 int op_cost, op_latency;
21346 + unsigned HOST_WIDE_INT orig_t = t;
21347 unsigned HOST_WIDE_INT q;
21348 int maxm = MIN (BITS_PER_WORD, GET_MODE_BITSIZE (mode));
21350 @@ -2542,6 +2551,38 @@ synth_mult (struct algorithm *alg_out, u
21351 best_alg->log[best_alg->ops] = m;
21352 best_alg->op[best_alg->ops] = alg_shift;
21355 + /* See if treating ORIG_T as a signed number yields a better
21356 + sequence. Try this sequence only for a negative ORIG_T
21357 + as it would be useless for a non-negative ORIG_T. */
21358 + if ((HOST_WIDE_INT) orig_t < 0)
21360 + /* Shift ORIG_T as follows because a right shift of a
21361 + negative-valued signed type is implementation
21363 + q = ~(~orig_t >> m);
21364 + /* The function expand_shift will choose between a shift
21365 + and a sequence of additions, so the observed cost is
21366 + given as MIN (m * add_cost[speed][mode],
21367 + shift_cost[speed][mode][m]). */
21368 + op_cost = m * add_cost[speed][mode];
21369 + if (shift_cost[speed][mode][m] < op_cost)
21370 + op_cost = shift_cost[speed][mode][m];
21371 + new_limit.cost = best_cost.cost - op_cost;
21372 + new_limit.latency = best_cost.latency - op_cost;
21373 + synth_mult (alg_in, q, &new_limit, mode);
21375 + alg_in->cost.cost += op_cost;
21376 + alg_in->cost.latency += op_cost;
21377 + if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
21379 + struct algorithm *x;
21380 + best_cost = alg_in->cost;
21381 + x = alg_in, alg_in = best_alg, best_alg = x;
21382 + best_alg->log[best_alg->ops] = m;
21383 + best_alg->op[best_alg->ops] = alg_shift;
21389 @@ -2604,6 +2645,29 @@ synth_mult (struct algorithm *alg_out, u
21390 best_alg->op[best_alg->ops] = alg_add_t_m2;
21394 + /* We may be able to calculate a * -7, a * -15, a * -31, etc
21395 + quickly with a - a * n for some appropriate constant n. */
21396 + m = exact_log2 (-orig_t + 1);
21397 + if (m >= 0 && m < maxm)
21399 + op_cost = shiftsub1_cost[speed][mode][m];
21400 + new_limit.cost = best_cost.cost - op_cost;
21401 + new_limit.latency = best_cost.latency - op_cost;
21402 + synth_mult (alg_in, (unsigned HOST_WIDE_INT) (-orig_t + 1) >> m, &new_limit, mode);
21404 + alg_in->cost.cost += op_cost;
21405 + alg_in->cost.latency += op_cost;
21406 + if (CHEAPER_MULT_COST (&alg_in->cost, &best_cost))
21408 + struct algorithm *x;
21409 + best_cost = alg_in->cost;
21410 + x = alg_in, alg_in = best_alg, best_alg = x;
21411 + best_alg->log[best_alg->ops] = m;
21412 + best_alg->op[best_alg->ops] = alg_sub_t_m2;
21419 @@ -2673,9 +2737,9 @@ synth_mult (struct algorithm *alg_out, u
21420 hardware the shift may be executed concurrently with the
21421 earlier steps in the algorithm. */
21422 op_cost = add_cost[speed][mode] + shift_cost[speed][mode][m];
21423 - if (shiftsub_cost[speed][mode][m] < op_cost)
21424 + if (shiftsub0_cost[speed][mode][m] < op_cost)
21426 - op_cost = shiftsub_cost[speed][mode][m];
21427 + op_cost = shiftsub0_cost[speed][mode][m];
21428 op_latency = op_cost;
21431 @@ -2738,7 +2802,7 @@ synth_mult (struct algorithm *alg_out, u
21432 m = exact_log2 (q);
21433 if (m >= 0 && m < maxm)
21435 - op_cost = shiftsub_cost[speed][mode][m];
21436 + op_cost = shiftsub0_cost[speed][mode][m];
21437 new_limit.cost = best_cost.cost - op_cost;
21438 new_limit.latency = best_cost.latency - op_cost;
21439 synth_mult (alg_in, (t + 1) >> m, &new_limit, mode);
21442 @@ -4391,6 +4391,29 @@ expand_assignment (tree to, tree from, b
21444 /* Compute FROM and store the value in the rtx we got. */
21446 + if (TREE_CODE (to) == MISALIGNED_INDIRECT_REF)
21450 + enum insn_code icode;
21451 + enum machine_mode mode = GET_MODE (to_rtx);
21453 + icode = optab_handler (movmisalign_optab, mode)->insn_code;
21454 + gcc_assert (icode != CODE_FOR_nothing);
21456 + from_rtx = expand_expr (from, NULL_RTX, mode, EXPAND_NORMAL);
21457 + insn = GEN_FCN (icode) (to_rtx, from_rtx);
21458 + /* If that failed then force the source into a reg and try again. */
21461 + from_rtx = copy_to_mode_reg(mode, from_rtx);
21462 + insn = GEN_FCN (icode) (to_rtx, from_rtx);
21463 + gcc_assert(insn);
21465 + emit_insn (insn);
21469 push_temp_slots ();
21470 result = store_expr (from, to_rtx, 0, nontemporal);
21471 preserve_temp_slots (result);
21472 @@ -7291,6 +7314,19 @@ expand_expr_real_1 (tree exp, rtx target
21473 decl_rtl = DECL_RTL (exp);
21474 gcc_assert (decl_rtl);
21475 decl_rtl = copy_rtx (decl_rtl);
21476 + /* Record writes to register variables. */
21477 + if (modifier == EXPAND_WRITE && REG_P(decl_rtl)
21478 + && REGNO(decl_rtl) < FIRST_PSEUDO_REGISTER)
21480 + int i = REGNO(decl_rtl);
21481 + int nregs = hard_regno_nregs[i][GET_MODE(decl_rtl)];
21484 + SET_HARD_REG_BIT(crtl->asm_clobbers, i);
21490 /* Ensure variable marked as used even if it doesn't go through
21491 a parser. If it hasn't be used yet, write out an external
21492 @@ -7538,14 +7574,15 @@ expand_expr_real_1 (tree exp, rtx target
21494 /* Resolve the misalignment now, so that we don't have to remember
21495 to resolve it later. Of course, this only works for reads. */
21496 - /* ??? When we get around to supporting writes, we'll have to handle
21497 - this in store_expr directly. The vectorizer isn't generating
21498 - those yet, however. */
21499 if (code == MISALIGNED_INDIRECT_REF)
21504 + /* For writes produce a MEM, and expand_assignment will DTRT. */
21505 + if (modifier == EXPAND_WRITE)
21508 gcc_assert (modifier == EXPAND_NORMAL
21509 || modifier == EXPAND_STACK_PARM);
21513 @@ -757,7 +757,7 @@ extern void probe_stack_range (HOST_WIDE
21515 /* Return an rtx that refers to the value returned by a library call
21516 in its original home. This becomes invalid if any more code is emitted. */
21517 -extern rtx hard_libcall_value (enum machine_mode);
21518 +extern rtx hard_libcall_value (enum machine_mode, rtx);
21520 /* Return the mode desired by operand N of a particular bitfield
21521 insert/extract insn, or MAX_MACHINE_MODE if no such insn is
21524 @@ -891,6 +891,7 @@ shorten_branches (rtx first ATTRIBUTE_UN
21525 if (LABEL_P (insn))
21528 + bool next_is_jumptable;
21530 /* Merge in alignments computed by compute_alignments. */
21531 log = LABEL_TO_ALIGNMENT (insn);
21532 @@ -900,31 +901,30 @@ shorten_branches (rtx first ATTRIBUTE_UN
21533 max_skip = LABEL_TO_MAX_SKIP (insn);
21536 - log = LABEL_ALIGN (insn);
21537 - if (max_log < log)
21538 + next = next_nonnote_insn (insn);
21539 + next_is_jumptable = next && JUMP_TABLE_DATA_P (next);
21540 + if (!next_is_jumptable)
21543 - max_skip = LABEL_ALIGN_MAX_SKIP;
21544 + log = LABEL_ALIGN (insn);
21545 + if (max_log < log)
21548 + max_skip = LABEL_ALIGN_MAX_SKIP;
21551 - next = next_nonnote_insn (insn);
21552 /* ADDR_VECs only take room if read-only data goes into the text
21554 - if (JUMP_TABLES_IN_TEXT_SECTION
21555 - || readonly_data_section == text_section)
21556 - if (next && JUMP_P (next))
21558 - rtx nextbody = PATTERN (next);
21559 - if (GET_CODE (nextbody) == ADDR_VEC
21560 - || GET_CODE (nextbody) == ADDR_DIFF_VEC)
21562 - log = ADDR_VEC_ALIGN (next);
21563 - if (max_log < log)
21566 - max_skip = LABEL_ALIGN_MAX_SKIP;
21570 + if ((JUMP_TABLES_IN_TEXT_SECTION
21571 + || readonly_data_section == text_section)
21572 + && next_is_jumptable)
21574 + log = ADDR_VEC_ALIGN (next);
21575 + if (max_log < log)
21578 + max_skip = LABEL_ALIGN_MAX_SKIP;
21581 LABEL_TO_ALIGNMENT (insn) = max_log;
21582 LABEL_TO_MAX_SKIP (insn) = max_skip;
21584 @@ -2013,48 +2013,41 @@ final_scan_insn (rtx insn, FILE *file, i
21587 next = next_nonnote_insn (insn);
21588 - if (next != 0 && JUMP_P (next))
21589 + /* If this label is followed by a jump-table, make sure we put
21590 + the label in the read-only section. Also possibly write the
21591 + label and jump table together. */
21592 + if (next != 0 && JUMP_TABLE_DATA_P (next))
21594 - rtx nextbody = PATTERN (next);
21596 - /* If this label is followed by a jump-table,
21597 - make sure we put the label in the read-only section. Also
21598 - possibly write the label and jump table together. */
21600 - if (GET_CODE (nextbody) == ADDR_VEC
21601 - || GET_CODE (nextbody) == ADDR_DIFF_VEC)
21603 #if defined(ASM_OUTPUT_ADDR_VEC) || defined(ASM_OUTPUT_ADDR_DIFF_VEC)
21604 - /* In this case, the case vector is being moved by the
21605 - target, so don't output the label at all. Leave that
21606 - to the back end macros. */
21607 + /* In this case, the case vector is being moved by the
21608 + target, so don't output the label at all. Leave that
21609 + to the back end macros. */
21611 - if (! JUMP_TABLES_IN_TEXT_SECTION)
21614 + if (! JUMP_TABLES_IN_TEXT_SECTION)
21618 - switch_to_section (targetm.asm_out.function_rodata_section
21619 - (current_function_decl));
21620 + switch_to_section (targetm.asm_out.function_rodata_section
21621 + (current_function_decl));
21623 #ifdef ADDR_VEC_ALIGN
21624 - log_align = ADDR_VEC_ALIGN (next);
21625 + log_align = ADDR_VEC_ALIGN (next);
21627 - log_align = exact_log2 (BIGGEST_ALIGNMENT / BITS_PER_UNIT);
21628 + log_align = exact_log2 (BIGGEST_ALIGNMENT / BITS_PER_UNIT);
21630 - ASM_OUTPUT_ALIGN (file, log_align);
21633 - switch_to_section (current_function_section ());
21634 + ASM_OUTPUT_ALIGN (file, log_align);
21637 + switch_to_section (current_function_section ());
21639 #ifdef ASM_OUTPUT_CASE_LABEL
21640 - ASM_OUTPUT_CASE_LABEL (file, "L", CODE_LABEL_NUMBER (insn),
21642 + ASM_OUTPUT_CASE_LABEL (file, "L", CODE_LABEL_NUMBER (insn),
21645 - targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (insn));
21646 + targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (insn));
21653 if (LABEL_ALT_ENTRY_P (insn))
21654 output_alternate_entry_point (file, insn);
21655 --- a/gcc/fold-const.c
21656 +++ b/gcc/fold-const.c
21657 @@ -2293,7 +2293,24 @@ fold_convert_const_real_from_real (tree
21658 real_convert (&value, TYPE_MODE (type), &TREE_REAL_CST (arg1));
21659 t = build_real (type, value);
21661 - TREE_OVERFLOW (t) = TREE_OVERFLOW (arg1);
21662 + /* If converting an infinity or NAN to a representation that doesn't
21663 + have one, set the overflow bit so that we can produce some kind of
21664 + error message at the appropriate point if necessary. It's not the
21665 + most user-friendly message, but it's better than nothing. */
21666 + if (REAL_VALUE_ISINF (TREE_REAL_CST (arg1))
21667 + && !MODE_HAS_INFINITIES (TYPE_MODE (type)))
21668 + TREE_OVERFLOW (t) = 1;
21669 + else if (REAL_VALUE_ISNAN (TREE_REAL_CST (arg1))
21670 + && !MODE_HAS_NANS (TYPE_MODE (type)))
21671 + TREE_OVERFLOW (t) = 1;
21672 + /* Regular overflow, conversion produced an infinity in a mode that
21673 + can't represent them. */
21674 + else if (!MODE_HAS_INFINITIES (TYPE_MODE (type))
21675 + && REAL_VALUE_ISINF (value)
21676 + && !REAL_VALUE_ISINF (TREE_REAL_CST (arg1)))
21677 + TREE_OVERFLOW (t) = 1;
21679 + TREE_OVERFLOW (t) = TREE_OVERFLOW (arg1);
21683 --- a/gcc/fortran/cpp.c
21684 +++ b/gcc/fortran/cpp.c
21685 @@ -137,6 +137,9 @@ static void cb_include (cpp_reader *, so
21686 static void cb_ident (cpp_reader *, source_location, const cpp_string *);
21687 static void cb_used_define (cpp_reader *, source_location, cpp_hashnode *);
21688 static void cb_used_undef (cpp_reader *, source_location, cpp_hashnode *);
21689 +static bool cb_cpp_error (cpp_reader *, int, location_t, unsigned int,
21690 + const char *, va_list *)
21691 + ATTRIBUTE_GCC_DIAG(5,0);
21692 void pp_dir_change (cpp_reader *, const char *);
21694 static int dump_macro (cpp_reader *, cpp_hashnode *, void *);
21695 @@ -452,7 +455,6 @@ gfc_cpp_post_options (void)
21696 cpp_option->cplusplus_comments = 0;
21698 cpp_option->pedantic = pedantic;
21699 - cpp_option->inhibit_warnings = inhibit_warnings;
21701 cpp_option->dollars_in_ident = gfc_option.flag_dollar_ok;
21702 cpp_option->discard_comments = gfc_cpp_option.discard_comments;
21703 @@ -465,9 +467,6 @@ gfc_cpp_post_options (void)
21705 cpp_post_options (cpp_in);
21707 - /* If an error has occurred in cpplib, note it so we fail immediately. */
21708 - errorcount += cpp_errors (cpp_in);
21710 gfc_cpp_register_include_paths ();
21713 @@ -482,6 +481,7 @@ gfc_cpp_init_0 (void)
21714 cb->line_change = cb_line_change;
21715 cb->ident = cb_ident;
21716 cb->def_pragma = cb_def_pragma;
21717 + cb->error = cb_cpp_error;
21719 if (gfc_cpp_option.dump_includes)
21720 cb->include = cb_include;
21721 @@ -961,6 +961,57 @@ cb_used_define (cpp_reader *pfile, sourc
21722 cpp_define_queue = q;
21725 +/* Callback from cpp_error for PFILE to print diagnostics from the
21726 + preprocessor. The diagnostic is of type LEVEL, at location
21727 + LOCATION, with column number possibly overridden by COLUMN_OVERRIDE
21728 + if not zero; MSG is the translated message and AP the arguments.
21729 + Returns true if a diagnostic was emitted, false otherwise. */
21732 +cb_cpp_error (cpp_reader *pfile ATTRIBUTE_UNUSED, int level,
21733 + location_t location, unsigned int column_override,
21734 + const char *msg, va_list *ap)
21736 + diagnostic_info diagnostic;
21737 + diagnostic_t dlevel;
21738 + int save_warn_system_headers = warn_system_headers;
21743 + case CPP_DL_WARNING_SYSHDR:
21744 + warn_system_headers = 1;
21745 + /* Fall through. */
21746 + case CPP_DL_WARNING:
21747 + dlevel = DK_WARNING;
21749 + case CPP_DL_PEDWARN:
21750 + dlevel = DK_PEDWARN;
21752 + case CPP_DL_ERROR:
21753 + dlevel = DK_ERROR;
21758 + case CPP_DL_NOTE:
21759 + dlevel = DK_NOTE;
21761 + case CPP_DL_FATAL:
21762 + dlevel = DK_FATAL;
21765 + gcc_unreachable ();
21767 + diagnostic_set_info_translated (&diagnostic, msg, ap,
21768 + location, dlevel);
21769 + if (column_override)
21770 + diagnostic_override_column (&diagnostic, column_override);
21771 + ret = report_diagnostic (&diagnostic);
21772 + if (level == CPP_DL_WARNING_SYSHDR)
21773 + warn_system_headers = save_warn_system_headers;
21777 /* Callback called when -fworking-director and -E to emit working
21778 directory in cpp output file. */
21779 --- a/gcc/function.c
21780 +++ b/gcc/function.c
21781 @@ -276,7 +276,10 @@ get_stack_local_alignment (tree type, en
21783 type = lang_hooks.types.type_for_mode (mode, 0);
21785 - return STACK_SLOT_ALIGNMENT (type, mode, alignment);
21786 + return alignment_for_aligned_arrays (type,
21787 + STACK_SLOT_ALIGNMENT (type,
21792 /* Allocate a stack slot of SIZE bytes and return a MEM rtx for it
21793 @@ -5355,6 +5358,57 @@ current_function_assembler_name (void)
21795 return IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (cfun->decl));
21798 +/* This function adjusts alignments as appropriate according to the
21799 + setting of -falign-arrays. If that is specified then the minimum
21800 + alignment for array variables is set to be the largest power of two
21801 + less than or equal to their total storage size, or the biggest
21802 + alignment used on the machine, whichever is smaller. */
21805 +alignment_for_aligned_arrays (tree ty, unsigned int existing_alignment)
21807 + unsigned int min_alignment;
21810 + /* Return the existing alignment if not using -falign-arrays or if
21811 + the type is not an array type. */
21812 + if (!flag_align_arrays || !ty || TREE_CODE (ty) != ARRAY_TYPE)
21813 + return existing_alignment;
21815 + /* Extract the total storage size of the array in bits. */
21816 + size = TYPE_SIZE (ty);
21817 + gcc_assert (size);
21819 + /* At least for variable-length arrays, TREE_CODE (size) might not be an
21820 + integer constant; check it now. If it is not, give the array at
21821 + least BIGGEST_ALIGNMENT just to be safe. Furthermore, we assume that
21822 + alignments always fit into a host integer. So if we can't fit the
21823 + size of the array in bits into a host integer, it must also be large
21824 + enough to deserve at least BIGGEST_ALIGNMENT (see below). */
21825 + if (TREE_CODE (size) != INTEGER_CST || !host_integerp (size, 1))
21826 + min_alignment = BIGGEST_ALIGNMENT;
21829 + unsigned HOST_WIDE_INT bits = TREE_INT_CST_LOW (size);
21830 + bits = (bits ? bits : 1);
21832 + /* An array with size greater than BIGGEST_ALIGNMENT is assigned
21833 + at least that alignment. In all other cases the minimum
21834 + alignment of the array is set to be the largest power of two
21835 + less than or equal to the total storage size of the array.
21836 + We assume that BIGGEST_ALIGNMENT fits in "unsigned int"; thus,
21837 + the shift below will not overflow. */
21838 + if (bits >= BIGGEST_ALIGNMENT)
21839 + min_alignment = BIGGEST_ALIGNMENT;
21841 + min_alignment = 1 << (floor_log2 (bits));
21844 + /* Having computed the minimum permissible alignment, enlarge it
21845 + if EXISTING_ALIGNMENT is greater. */
21846 + return MAX (min_alignment, existing_alignment);
21850 static unsigned int
21851 --- a/gcc/function.h
21852 +++ b/gcc/function.h
21853 @@ -25,6 +25,7 @@ along with GCC; see the file COPYING3.
21855 #include "hashtab.h"
21856 #include "varray.h"
21857 +#include "hard-reg-set.h"
21859 /* Stack of pending (incomplete) sequences saved by `start_sequence'.
21860 Each element describes one pending sequence.
21861 @@ -441,6 +442,8 @@ struct rtl_data GTY(())
21863 /* True if dbr_schedule has already been called for this function. */
21864 bool dbr_scheduled_p;
21866 + HARD_REG_SET asm_clobbers;
21869 #define return_label (crtl->x_return_label)
21870 @@ -709,4 +712,7 @@ extern bool reference_callee_copied (CUM
21871 extern void used_types_insert (tree);
21873 extern int get_next_funcdef_no (void);
21875 +extern unsigned int alignment_for_aligned_arrays (tree, unsigned int);
21877 #endif /* GCC_FUNCTION_H */
21880 @@ -229,6 +229,16 @@ static int combine_flag = 0;
21882 static int use_pipes;
21884 +/* Nonzero means that libgcc is being linked automatically by the
21885 + compiler from its normal installed location; that is, neither -B,
21886 + -nostdlib nor -nodefaultlibs was passed. */
21888 +static int using_libgcc = 1;
21890 +/* Nonzero means that the current spec is executing the linker. */
21892 +static int executing_linker = 0;
21894 /* The compiler version. */
21896 static const char *compiler_version;
21897 @@ -651,8 +661,32 @@ proper position among the other output f
21899 /* config.h can define SWITCHES_NEED_SPACES to control which options
21900 require spaces between the option and the argument. */
21901 +/* GCC Bugzilla PR11810 indicates that GCC does not correctly handle
21902 + "-ofoo.o", in that it records "-ofoo.o" as a temporary file to
21903 + delete, rather than "foo.o".
21905 + Unfortunately, Eclipse's makefile generators use the "-ofoo.o"
21906 + form. See also CS Issue #3433. So, although most users probably
21907 + use "-o foo.o", the "-ofoo.o" form is used in practice.
21909 + See this email thread for additional information:
21911 + http://gcc.gnu.org/ml/gcc/2008-07/msg00395.html
21913 + Therefore, we define SWITCHES_NEED_SPACES to include "o" by
21914 + default. This causes "-ofoo.o" to be split into "-o foo.o" during
21915 + the initial processing of the command-line, before being seen by
21916 + the specs machinery.
21918 + A risk of this change is that tools which *require* the "-ofoo.o"
21919 + form will no longer work. However, we know of no such tools, and
21920 + they would not have worked with the "-o foo.o" form anyhow.
21922 + If this general strategy is acceptable upstream, the best approach
21923 + might be simply to eliminate this macro, since the only definitions
21924 + in target files are also to the value "o". */
21925 #ifndef SWITCHES_NEED_SPACES
21926 -#define SWITCHES_NEED_SPACES ""
21927 +#define SWITCHES_NEED_SPACES "o"
21930 /* config.h can define ENDFILE_SPEC to override the default crtn files. */
21931 @@ -728,6 +762,8 @@ proper position among the other output f
21932 %{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S:\
21933 %(linker) %l " LINK_PIE_SPEC "%X %{o*} %{A} %{d} %{e*} %{m} %{N} %{n} %{r}\
21934 %{s} %{t} %{u*} %{x} %{z} %{Z} %{!A:%{!nostdlib:%{!nostartfiles:%S}}}\
21935 + %{Wno-poison-system-directories:--no-poison-system-directories}\
21936 + %{Werror=poison-system-directories:--error-poison-system-directories}\
21937 %{static:} %{L*} %(mfwrap) %(link_libgcc) %o\
21938 %{fopenmp|ftree-parallelize-loops=*:%:include(libgomp.spec)%(link_gomp)} %(mflib)\
21939 %{fprofile-arcs|fprofile-generate|coverage:-lgcov}\
21940 @@ -882,7 +918,7 @@ static const char *const multilib_defaul
21943 static const char *const driver_self_specs[] = {
21944 - DRIVER_SELF_SPECS, GOMP_SELF_SPECS
21945 + DRIVER_SELF_SPECS, CONFIGURE_SPECS, GOMP_SELF_SPECS
21948 #ifndef OPTION_DEFAULT_SPECS
21949 @@ -2853,6 +2889,29 @@ execute (void)
21951 gcc_assert (!processing_spec_function);
21953 + if (executing_linker && using_libgcc)
21955 + const char *libgcc_a_filename;
21957 + /* Verify that the multilib being used is actually installed. */
21958 + libgcc_a_filename = (gcc_exec_prefix
21959 + ? gcc_exec_prefix
21960 + : concat (standard_exec_prefix,
21961 + machine_suffix, NULL));
21962 + if (multilib_dir && strcmp (multilib_dir, ".") != 0)
21963 + libgcc_a_filename = concat (libgcc_a_filename, multilib_dir,
21964 + dir_separator_str, NULL);
21965 + libgcc_a_filename = concat (libgcc_a_filename, "libgcc.a", NULL);
21966 + if (access (libgcc_a_filename, R_OK) != 0)
21968 + if (errno == ENOENT)
21969 + fatal ("selected multilib '%s' not installed",
21970 + multilib_dir ? multilib_dir : ".");
21972 + pfatal_with_name (libgcc_a_filename);
21976 if (wrapper_string)
21978 string = find_a_file (&exec_prefixes, argbuf[0], X_OK, false);
21979 @@ -3688,6 +3747,16 @@ warranty; not even for MERCHANTABILITY o
21980 add_assembler_option ("--target-help", 13);
21981 add_linker_option ("--target-help", 13);
21983 + else if (! strcmp (argv[i], "-nodefaultlibs"))
21985 + using_libgcc = 0;
21988 + else if (! strcmp (argv[i], "-nostdlib"))
21990 + using_libgcc = 0;
21993 else if (! strcmp (argv[i], "-pass-exit-codes"))
21995 pass_exit_codes = 1;
21996 @@ -3905,6 +3974,7 @@ warranty; not even for MERCHANTABILITY o
21997 PREFIX_PRIORITY_B_OPT, 0, 0);
21998 add_prefix (&include_prefixes, value, NULL,
21999 PREFIX_PRIORITY_B_OPT, 0, 0);
22000 + using_libgcc = 0;
22004 @@ -4616,27 +4686,53 @@ do_self_spec (const char *spec)
22006 if (argbuf_index > 0)
22011 first = n_switches;
22012 - n_switches += argbuf_index;
22013 - switches = XRESIZEVEC (struct switchstr, switches, n_switches + 1);
22014 + n = n_switches + argbuf_index;
22015 + switches = XRESIZEVEC (struct switchstr, switches, n + 1);
22016 + switches[n] = switches[first];
22018 switches[n_switches] = switches[first];
22019 for (i = 0; i < argbuf_index; i++)
22021 struct switchstr *sw;
22022 + const char *p = &argbuf[i][1];
22025 /* Each switch should start with '-'. */
22026 if (argbuf[i][0] != '-')
22027 fatal ("switch '%s' does not start with '-'", argbuf[i]);
22029 - sw = &switches[i + first];
22030 + sw = &switches[n_switches];
22031 sw->part1 = &argbuf[i][1];
22037 + /* Deal with option arguments in separate argv elements. */
22038 + if ((SWITCH_TAKES_ARG (c) > (p[1] != 0))
22039 + || WORD_SWITCH_TAKES_ARG (p))
22042 + int n_args = WORD_SWITCH_TAKES_ARG (p);
22046 + /* Count only the option arguments in separate argv elements. */
22047 + n_args = SWITCH_TAKES_ARG (c) - (p[1] != 0);
22049 + if (i + n_args >= argbuf_index)
22050 + fatal ("argument to '-%s' is missing", p);
22051 + switches[n_switches].args
22052 + = XNEWVEC (const char *, n_args + 1);
22053 + while (j < n_args)
22054 + switches[n_switches].args[j++] = argbuf[++i];
22055 + /* Null-terminate the vector. */
22056 + switches[n_switches].args[j] = 0;
22062 @@ -6873,7 +6969,9 @@ main (int argc, char **argv)
22063 " to the linker.\n\n"));
22066 + executing_linker = 1;
22067 value = do_spec (link_command_spec);
22068 + executing_linker = 0;
22071 linker_was_run = (tmp != execution_count);
22074 @@ -172,6 +172,7 @@ along with GCC; see the file COPYING3.
22075 #include "hashtab.h"
22077 #include "dbgcnt.h"
22078 +#include "target.h"
22080 /* Propagate flow information through back edges and thus enable PRE's
22081 moving loop invariant calculations out of loops.
22082 @@ -1744,7 +1745,9 @@ hash_scan_set (rtx pat, rtx insn, struct
22083 REG_EQUIV notes and if the argument slot is used somewhere
22084 explicitly, it means address of parameter has been taken,
22085 so we should not extend the lifetime of the pseudo. */
22086 - && (note == NULL_RTX || ! MEM_P (XEXP (note, 0))))
22087 + && (note == NULL_RTX || ! MEM_P (XEXP (note, 0)))
22088 + && ! (targetm.cannot_copy_insn_p && INSN_P (insn)
22089 + && targetm.cannot_copy_insn_p (insn)))
22091 /* An expression is not anticipatable if its operands are
22092 modified before this insn or if this is not the only SET in
22093 --- a/gcc/genautomata.c
22094 +++ b/gcc/genautomata.c
22096 /* Pipeline hazard description translator.
22097 - Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
22098 + Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009
22099 Free Software Foundation, Inc.
22101 Written by Vladimir Makarov <vmakarov@redhat.com>
22102 @@ -22,21 +22,25 @@ along with GCC; see the file COPYING3.
22106 - 1. Detecting pipeline structural hazards quickly. T. Proebsting,
22107 + 1. The finite state automaton based pipeline hazard recognizer and
22108 + instruction scheduler in GCC. V. Makarov. Proceedings of GCC
22111 + 2. Detecting pipeline structural hazards quickly. T. Proebsting,
22112 C. Fraser. Proceedings of ACM SIGPLAN-SIGACT Symposium on
22113 Principles of Programming Languages, pages 280--286, 1994.
22115 This article is a good start point to understand usage of finite
22116 state automata for pipeline hazard recognizers. But I'd
22117 - recommend the 2nd article for more deep understanding.
22118 + recommend the 1st and 3rd article for more deep understanding.
22120 - 2. Efficient Instruction Scheduling Using Finite State Automata:
22121 + 3. Efficient Instruction Scheduling Using Finite State Automata:
22122 V. Bala and N. Rubin, Proceedings of MICRO-28. This is the best
22123 article about usage of finite state automata for pipeline hazard
22126 - The current implementation is different from the 2nd article in the
22128 + The current implementation is described in the 1st article and it
22129 + is different from the 3rd article in the following:
22131 1. New operator `|' (alternative) is permitted in functional unit
22132 reservation which can be treated deterministically and
22133 @@ -463,7 +467,10 @@ struct insn_reserv_decl
22136 /* The following field value is list of bypasses in which given insn
22137 - is output insn. */
22138 + is output insn. Bypasses with the same input insn stay one after
22139 + another in the list in the same order as their occurrences in the
22140 + description but the bypass without a guard stays always the last
22141 + in a row of bypasses with the same input insn. */
22142 struct bypass_decl *bypass_list;
22144 /* The following fields are defined by automaton generator. */
22145 @@ -2367,18 +2374,67 @@ add_presence_absence (unit_set_el_t dest
22149 -/* The function searches for bypass with given IN_INSN_RESERV in given
22151 -static struct bypass_decl *
22152 -find_bypass (struct bypass_decl *bypass_list,
22153 - struct insn_reserv_decl *in_insn_reserv)
22155 - struct bypass_decl *bypass;
22157 - for (bypass = bypass_list; bypass != NULL; bypass = bypass->next)
22158 - if (bypass->in_insn_reserv == in_insn_reserv)
22161 +/* The function inserts BYPASS in the list of bypasses of the
22162 + corresponding output insn. The order of bypasses in the list is
22163 + decribed in a comment for member `bypass_list' (see above). If
22164 + there is already the same bypass in the list the function reports
22165 + this and does nothing. */
22167 +insert_bypass (struct bypass_decl *bypass)
22169 + struct bypass_decl *curr, *last;
22170 + struct insn_reserv_decl *out_insn_reserv = bypass->out_insn_reserv;
22171 + struct insn_reserv_decl *in_insn_reserv = bypass->in_insn_reserv;
22173 + for (curr = out_insn_reserv->bypass_list, last = NULL;
22175 + last = curr, curr = curr->next)
22176 + if (curr->in_insn_reserv == in_insn_reserv)
22178 + if ((bypass->bypass_guard_name != NULL
22179 + && curr->bypass_guard_name != NULL
22180 + && ! strcmp (bypass->bypass_guard_name, curr->bypass_guard_name))
22181 + || bypass->bypass_guard_name == curr->bypass_guard_name)
22183 + if (bypass->bypass_guard_name == NULL)
22186 + error ("the same bypass `%s - %s' is already defined",
22187 + bypass->out_insn_name, bypass->in_insn_name);
22189 + warning (0, "the same bypass `%s - %s' is already defined",
22190 + bypass->out_insn_name, bypass->in_insn_name);
22192 + else if (!w_flag)
22193 + error ("the same bypass `%s - %s' (guard %s) is already defined",
22194 + bypass->out_insn_name, bypass->in_insn_name,
22195 + bypass->bypass_guard_name);
22198 + (0, "the same bypass `%s - %s' (guard %s) is already defined",
22199 + bypass->out_insn_name, bypass->in_insn_name,
22200 + bypass->bypass_guard_name);
22203 + if (curr->bypass_guard_name == NULL)
22205 + if (curr->next == NULL || curr->next->in_insn_reserv != in_insn_reserv)
22212 + if (last == NULL)
22214 + bypass->next = out_insn_reserv->bypass_list;
22215 + out_insn_reserv->bypass_list = bypass;
22219 + bypass->next = last->next;
22220 + last->next = bypass;
22224 /* The function processes pipeline description declarations, checks
22225 @@ -2391,7 +2447,6 @@ process_decls (void)
22226 decl_t decl_in_table;
22227 decl_t out_insn_reserv;
22228 decl_t in_insn_reserv;
22229 - struct bypass_decl *bypass;
22230 int automaton_presence;
22233 @@ -2514,36 +2569,7 @@ process_decls (void)
22234 = DECL_INSN_RESERV (out_insn_reserv);
22235 DECL_BYPASS (decl)->in_insn_reserv
22236 = DECL_INSN_RESERV (in_insn_reserv);
22238 - = find_bypass (DECL_INSN_RESERV (out_insn_reserv)->bypass_list,
22239 - DECL_BYPASS (decl)->in_insn_reserv);
22240 - if (bypass != NULL)
22242 - if (DECL_BYPASS (decl)->latency == bypass->latency)
22246 - ("the same bypass `%s - %s' is already defined",
22247 - DECL_BYPASS (decl)->out_insn_name,
22248 - DECL_BYPASS (decl)->in_insn_name);
22251 - (0, "the same bypass `%s - %s' is already defined",
22252 - DECL_BYPASS (decl)->out_insn_name,
22253 - DECL_BYPASS (decl)->in_insn_name);
22256 - error ("bypass `%s - %s' is already defined",
22257 - DECL_BYPASS (decl)->out_insn_name,
22258 - DECL_BYPASS (decl)->in_insn_name);
22262 - DECL_BYPASS (decl)->next
22263 - = DECL_INSN_RESERV (out_insn_reserv)->bypass_list;
22264 - DECL_INSN_RESERV (out_insn_reserv)->bypass_list
22265 - = DECL_BYPASS (decl);
22267 + insert_bypass (DECL_BYPASS (decl));
22271 @@ -8159,19 +8185,32 @@ output_internal_insn_latency_func (void)
22272 (advance_cycle_insn_decl)->insn_num));
22273 fprintf (output_file, " case %d:\n",
22274 bypass->in_insn_reserv->insn_num);
22275 - if (bypass->bypass_guard_name == NULL)
22276 - fprintf (output_file, " return %d;\n",
22277 - bypass->latency);
22281 - fprintf (output_file,
22282 - " if (%s (%s, %s))\n",
22283 - bypass->bypass_guard_name, INSN_PARAMETER_NAME,
22284 - INSN2_PARAMETER_NAME);
22285 - fprintf (output_file,
22286 - " return %d;\n break;\n",
22287 - bypass->latency);
22288 + if (bypass->bypass_guard_name == NULL)
22290 + gcc_assert (bypass->next == NULL
22291 + || (bypass->in_insn_reserv
22292 + != bypass->next->in_insn_reserv));
22293 + fprintf (output_file, " return %d;\n",
22294 + bypass->latency);
22298 + fprintf (output_file,
22299 + " if (%s (%s, %s))\n",
22300 + bypass->bypass_guard_name, INSN_PARAMETER_NAME,
22301 + INSN2_PARAMETER_NAME);
22302 + fprintf (output_file, " return %d;\n",
22303 + bypass->latency);
22305 + if (bypass->next == NULL
22306 + || bypass->in_insn_reserv != bypass->next->in_insn_reserv)
22308 + bypass = bypass->next;
22310 + if (bypass->bypass_guard_name != NULL)
22311 + fprintf (output_file, " break;\n");
22313 fputs (" }\n break;\n", output_file);
22315 --- a/gcc/gengtype-lex.l
22316 +++ b/gcc/gengtype-lex.l
22317 @@ -48,7 +48,7 @@ update_lineno (const char *l, size_t len
22318 ID [[:alpha:]_][[:alnum:]_]*
22321 -IWORD short|long|(un)?signed|char|int|HOST_WIDE_INT|HOST_WIDEST_INT|bool|size_t|BOOL_BITFIELD|CPPCHAR_SIGNED_T|ino_t|dev_t
22322 +IWORD short|long|(un)?signed|char|int|HOST_WIDE_INT|HOST_WIDEST_INT|bool|size_t|BOOL_BITFIELD|CPPCHAR_SIGNED_T|ino_t|dev_t|HARD_REG_SET
22323 ITYPE {IWORD}({WS}{IWORD})*
22326 --- a/gcc/genmultilib
22327 +++ b/gcc/genmultilib
22329 # the os directory names are used exclusively. Use the mapping when
22330 # there is no one-to-one equivalence between GCC levels and the OS.
22332 +# The optional eighth option is a list of multilib aliases. This takes the
22333 +# same form as the third argument. It specifies that the second multilib is
22334 +# a synonym for the first. This allows a suitable multilib to be selected
22335 +# for all option combinations while only building a subset of all possible
22338 +# genmultilib "mbig-endian mthumb" "eb thumb" "" "" "" "" "" \
22339 +# "mbig-endian=mbig-endian/mthumb" yes
22341 +# ". !mbig-endian !mthumb;",
22342 +# "be mbig-endian !mthumb;",
22343 +# "be mbig-endian mthumb;",
22344 +# "thumb !mbig-endian mthumb;",
22346 # The last option should be "yes" if multilibs are enabled. If it is not
22347 # "yes", all GCC multilib dir names will be ".".
22349 @@ -121,7 +135,8 @@ exceptions=$4
22353 -enable_multilib=$8
22355 +enable_multilib=$9
22357 echo "static const char *const multilib_raw[] = {"
22359 @@ -129,6 +144,23 @@ mkdir tmpmultilib.$$ || exit 1
22360 # Use cd ./foo to avoid CDPATH output.
22361 cd ./tmpmultilib.$$ || exit 1
22364 +cat >tmpmultilib3 <<\EOF
22366 +# Output a list of aliases (including the original name) for a multilib.
22370 +for a in ${aliases}; do
22371 + l=`echo $a | sed -e 's/=.*$//' -e 's/?/=/g'`
22372 + r=`echo $a | sed -e 's/^.*=//' -e 's/?/=/g'`
22373 + echo "[ \$1 == /$l/ ] && echo /$r/" >>tmpmultilib3
22375 + # Also add the alias to the exclusion list
22376 + exceptions="${exceptions} $r"
22378 +chmod +x tmpmultilib3
22380 # What we want to do is select all combinations of the sets in
22381 # options. Each combination which includes a set of mutually
22382 # exclusive options must then be output multiple times, once for each
22383 @@ -195,6 +227,21 @@ EOF
22384 combinations=`./tmpmultilib2 ${combinations}`
22387 +# Check that all the aliases actually exist
22388 +for a in ${aliases}; do
22389 + l=`echo $a | sed -e 's/=.*$//' -e 's/?/=/g'`
22390 + for c in ${combinations}; do
22391 + if [ "/$l/" = "$c" ]; then
22396 + if [ -n "$l" ] ;then
22397 + echo "Missing multilib $l for alias $a" 1>&2
22402 # Construct a sed pattern which will convert option names to directory
22405 @@ -343,23 +390,25 @@ for combo in ${combinations}; do
22409 - # Look through the options. We must output each option that is
22410 - # present, and negate each option that is not present.
22412 - for set in ${options}; do
22413 - setopts=`echo ${set} | sed -e 's_[/|]_ _g'`
22414 - for opt in ${setopts}; do
22415 - if expr "${combo} " : ".*/${opt}/.*" > /dev/null; then
22416 - optout="${optout} ${opt}"
22418 - optout="${optout} !${opt}"
22420 + for optcombo in `./tmpmultilib3 ${combo}`; do
22421 + # Look through the options. We must output each option that is
22422 + # present, and negate each option that is not present.
22424 + for set in ${options}; do
22425 + setopts=`echo ${set} | sed -e 's_[/|]_ _g'`
22426 + for opt in ${setopts}; do
22427 + if expr "${optcombo} " : ".*/${opt}/.*" > /dev/null; then
22428 + optout="${optout} ${opt}"
22430 + optout="${optout} !${opt}"
22435 - optout=`echo ${optout} | sed -e 's/^ //'`
22436 + optout=`echo ${optout} | sed -e 's/^ //'`
22438 - # Output the line with all appropriate matches.
22439 - dirout="${dirout}" optout="${optout}" ./tmpmultilib2
22440 + # Output the line with all appropriate matches.
22441 + dirout="${dirout}" optout="${optout}" ./tmpmultilib2
22445 # Terminate the list of string.
22446 --- a/gcc/haifa-sched.c
22447 +++ b/gcc/haifa-sched.c
22448 @@ -1990,6 +1990,23 @@ move_insn (rtx insn, rtx last, rtx nt)
22449 SCHED_GROUP_P (insn) = 0;
22452 +/* Return true if scheduling INSN will finish current clock cycle. */
22454 +insn_finishes_cycle_p (rtx insn)
22456 + if (SCHED_GROUP_P (insn))
22457 + /* After issuing INSN, rest of the sched_group will be forced to issue
22458 + in order. Don't make any plans for the rest of cycle. */
22461 + /* Finishing the block will, apparently, finish the cycle. */
22462 + if (current_sched_info->insn_finishes_block_p
22463 + && current_sched_info->insn_finishes_block_p (insn))
22469 /* The following structure describe an entry of the stack of choices. */
22470 struct choice_entry
22472 @@ -2168,7 +2185,10 @@ max_issue (struct ready_list *ready, int
22473 delay = state_transition (state, insn);
22476 - if (state_dead_lock_p (state))
22477 + if (state_dead_lock_p (state)
22478 + || insn_finishes_cycle_p (insn))
22479 + /* We won't issue any more instructions in the next
22486 @@ -335,3 +335,10 @@ hook_constcharptr_int_const_tree_const_t
22491 +/* Generic hook that takes a const_tree and returns NULL_TREE. */
22493 +hook_tree_const_tree_null (const_tree t ATTRIBUTE_UNUSED)
22499 @@ -64,6 +64,8 @@ extern int hook_int_rtx_bool_0 (rtx, boo
22500 extern int hook_int_size_t_constcharptr_int_0 (size_t, const char *, int);
22501 extern int hook_int_void_no_regs (void);
22503 +extern tree hook_tree_const_tree_null (const_tree);
22505 extern tree hook_tree_tree_tree_null (tree, tree);
22506 extern tree hook_tree_tree_tree_tree_null (tree, tree, tree);
22507 extern tree hook_tree_tree_tree_tree_3rd_identity (tree, tree, tree);
22508 --- a/gcc/incpath.c
22509 +++ b/gcc/incpath.c
22512 #include "incpath.h"
22513 #include "cppdefault.h"
22514 +#include "flags.h"
22515 +#include "toplev.h"
22517 /* Microsoft Windows does not natively support inodes.
22518 VMS has non-numeric inodes. */
22519 @@ -353,6 +355,24 @@ merge_include_chains (const char *sysroo
22521 fprintf (stderr, _("End of search list.\n"));
22524 +#ifdef ENABLE_POISON_SYSTEM_DIRECTORIES
22525 + if (flag_poison_system_directories)
22527 + struct cpp_dir *p;
22529 + for (p = heads[QUOTE]; p; p = p->next)
22531 + if ((!strncmp (p->name, "/usr/include", 12))
22532 + || (!strncmp (p->name, "/usr/local/include", 18))
22533 + || (!strncmp (p->name, "/usr/X11R6/include", 18)))
22534 + warning (OPT_Wpoison_system_directories,
22535 + "include location \"%s\" is unsafe for "
22536 + "cross-compilation",
22543 /* Use given -I paths for #include "..." but not #include <...>, and
22544 --- a/gcc/ira-costs.c
22545 +++ b/gcc/ira-costs.c
22546 @@ -706,11 +706,11 @@ record_reg_classes (int n_alts, int n_op
22548 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
22550 -ok_for_index_p_nonstrict (rtx reg)
22551 +ok_for_index_p_nonstrict (rtx reg, enum machine_mode mode)
22553 unsigned regno = REGNO (reg);
22555 - return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno);
22556 + return regno >= FIRST_PSEUDO_REGISTER || ok_for_index_p_1 (regno, mode);
22559 /* A version of regno_ok_for_base_p for use here, when all
22560 @@ -748,7 +748,7 @@ record_address_regs (enum machine_mode m
22561 enum reg_class rclass;
22564 - rclass = INDEX_REG_CLASS;
22565 + rclass = index_reg_class (mode);
22567 rclass = base_reg_class (mode, outer_code, index_code);
22569 @@ -795,7 +795,8 @@ record_address_regs (enum machine_mode m
22570 just record registers in any non-constant operands. We
22571 assume here, as well as in the tests below, that all
22572 addresses are in canonical form. */
22573 - else if (INDEX_REG_CLASS == base_reg_class (VOIDmode, PLUS, SCRATCH))
22574 + else if (index_reg_class (mode)
22575 + == base_reg_class (mode, PLUS, SCRATCH))
22577 record_address_regs (mode, arg0, context, PLUS, code1, scale);
22578 if (! CONSTANT_P (arg1))
22579 @@ -816,7 +817,7 @@ record_address_regs (enum machine_mode m
22580 else if (code0 == REG && code1 == REG
22581 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
22582 && (ok_for_base_p_nonstrict (arg0, mode, PLUS, REG)
22583 - || ok_for_index_p_nonstrict (arg0)))
22584 + || ok_for_index_p_nonstrict (arg0, mode)))
22585 record_address_regs (mode, arg1,
22586 ok_for_base_p_nonstrict (arg0, mode, PLUS, REG)
22588 @@ -824,7 +825,7 @@ record_address_regs (enum machine_mode m
22589 else if (code0 == REG && code1 == REG
22590 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
22591 && (ok_for_base_p_nonstrict (arg1, mode, PLUS, REG)
22592 - || ok_for_index_p_nonstrict (arg1)))
22593 + || ok_for_index_p_nonstrict (arg1, mode)))
22594 record_address_regs (mode, arg0,
22595 ok_for_base_p_nonstrict (arg1, mode, PLUS, REG)
22599 @@ -1349,14 +1349,12 @@ insn_contains_asm (rtx insn)
22600 return for_each_rtx (&insn, insn_contains_asm_1, NULL);
22603 -/* Set up regs_asm_clobbered. */
22604 +/* Add register clobbers from asm statements. */
22606 -compute_regs_asm_clobbered (char *regs_asm_clobbered)
22607 +compute_regs_asm_clobbered (void)
22611 - memset (regs_asm_clobbered, 0, sizeof (char) * FIRST_PSEUDO_REGISTER);
22616 @@ -1377,7 +1375,7 @@ compute_regs_asm_clobbered (char *regs_a
22617 + hard_regno_nregs[dregno][mode] - 1;
22619 for (i = dregno; i <= end; ++i)
22620 - regs_asm_clobbered[i] = 1;
22621 + SET_HARD_REG_BIT(crtl->asm_clobbers, i);
22625 @@ -1415,7 +1413,8 @@ setup_eliminable_regset (void)
22626 COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs);
22627 CLEAR_HARD_REG_SET (eliminable_regset);
22629 - compute_regs_asm_clobbered (regs_asm_clobbered);
22630 + compute_regs_asm_clobbered ();
22632 /* Build the regset of all eliminable registers and show we can't
22633 use those that we already know won't be eliminated. */
22634 #ifdef ELIMINABLE_REGS
22635 @@ -1425,7 +1424,7 @@ setup_eliminable_regset (void)
22636 = (! CAN_ELIMINATE (eliminables[i].from, eliminables[i].to)
22637 || (eliminables[i].to == STACK_POINTER_REGNUM && need_fp));
22639 - if (! regs_asm_clobbered[eliminables[i].from])
22640 + if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, eliminables[i].from))
22642 SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from);
22644 @@ -1439,7 +1438,7 @@ setup_eliminable_regset (void)
22645 df_set_regs_ever_live (eliminables[i].from, true);
22647 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
22648 - if (! regs_asm_clobbered[HARD_FRAME_POINTER_REGNUM])
22649 + if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM))
22651 SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM);
22653 @@ -1453,7 +1452,7 @@ setup_eliminable_regset (void)
22657 - if (! regs_asm_clobbered[FRAME_POINTER_REGNUM])
22658 + if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM))
22660 SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM);
22662 --- a/gcc/modulo-sched.c
22663 +++ b/gcc/modulo-sched.c
22664 @@ -270,6 +270,7 @@ static struct haifa_sched_info sms_sched
22668 + NULL, /* insn_finishes_block_p */
22674 @@ -3300,7 +3300,8 @@ expand_unop (enum machine_mode mode, opt
22675 if (unoptab == ffs_optab || unoptab == clz_optab || unoptab == ctz_optab
22676 || unoptab == popcount_optab || unoptab == parity_optab)
22678 - = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node)));
22679 + = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node),
22680 + optab_libfunc (unoptab, mode)));
22684 @@ -4357,10 +4358,12 @@ prepare_float_lib_cmp (rtx *px, rtx *py,
22686 mode = GET_MODE_WIDER_MODE (mode))
22688 - if ((libfunc = optab_libfunc (code_to_optab[comparison], mode)))
22689 + if (code_to_optab[comparison]
22690 + && (libfunc = optab_libfunc (code_to_optab[comparison], mode)))
22693 - if ((libfunc = optab_libfunc (code_to_optab[swapped] , mode)))
22694 + if (code_to_optab[swapped]
22695 + && (libfunc = optab_libfunc (code_to_optab[swapped], mode)))
22698 tmp = x; x = y; y = tmp;
22699 @@ -4368,7 +4371,8 @@ prepare_float_lib_cmp (rtx *px, rtx *py,
22703 - if ((libfunc = optab_libfunc (code_to_optab[reversed], mode))
22704 + if (code_to_optab[reversed]
22705 + && (libfunc = optab_libfunc (code_to_optab[reversed], mode))
22706 && FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, reversed))
22708 comparison = reversed;
22711 @@ -906,7 +906,7 @@ decode_options (unsigned int argc, const
22712 flag_tree_vrp = opt2;
22713 flag_tree_builtin_call_dce = opt2;
22714 flag_tree_pre = opt2;
22715 - flag_tree_switch_conversion = 1;
22716 + flag_tree_switch_conversion = opt2;
22717 flag_ipa_cp = opt2;
22719 /* Allow more virtual operators to increase alias precision. */
22720 @@ -930,6 +930,7 @@ decode_options (unsigned int argc, const
22721 flag_gcse_after_reload = opt3;
22722 flag_tree_vectorize = opt3;
22723 flag_ipa_cp_clone = opt3;
22724 + flag_tree_pre_partial_partial = opt3;
22725 if (flag_ipa_cp_clone)
22728 @@ -953,10 +954,13 @@ decode_options (unsigned int argc, const
22729 being declared inline. */
22730 flag_inline_functions = 1;
22732 - /* Basic optimization options. */
22733 - optimize_size = 1;
22734 + /* Basic optimization options at -Os are almost the same as -O2. The
22735 + only difference is that we disable PRE, because it sometimes still
22736 + increases code size. If the user want to run PRE with -Os, he/she
22737 + will have to indicate so explicitly. */
22740 + flag_tree_pre = 0;
22742 /* We want to crossjump as much as possible. */
22743 set_param_value ("min-crossjump-insns", 1);
22744 @@ -2062,6 +2066,10 @@ common_handle_option (size_t scode, cons
22745 /* These are no-ops, preserved for backward compatibility. */
22748 + case OPT_feglibc_:
22749 + /* This is a no-op at the moment. */
22753 /* If the flag was handled in a standard way, assume the lack of
22754 processing here is intentional. */
22757 @@ -591,6 +591,7 @@ init_optimization_passes (void)
22758 NEXT_PASS (pass_rename_ssa_copies);
22759 NEXT_PASS (pass_complete_unrolli);
22760 NEXT_PASS (pass_ccp);
22761 + NEXT_PASS (pass_promote_indices);
22762 NEXT_PASS (pass_forwprop);
22763 /* Ideally the function call conditional
22764 dead code elimination phase can be delayed
22765 @@ -605,6 +606,7 @@ init_optimization_passes (void)
22766 alias information also rewrites no longer addressed
22767 locals into SSA form if possible. */
22768 NEXT_PASS (pass_build_alias);
22769 + NEXT_PASS (pass_remove_local_statics);
22770 NEXT_PASS (pass_return_slot);
22771 NEXT_PASS (pass_phiprop);
22772 NEXT_PASS (pass_fre);
22773 --- a/gcc/pointer-set.c
22774 +++ b/gcc/pointer-set.c
22775 @@ -181,6 +181,23 @@ void pointer_set_traverse (const struct
22779 +/* Return the number of elements in PSET. */
22782 +pointer_set_n_elements (struct pointer_set_t *pset)
22784 + return pset->n_elements;
22787 +/* Remove all entries from PSET. */
22790 +pointer_set_clear (struct pointer_set_t *pset)
22792 + pset->n_elements = 0;
22793 + memset (pset->slots, 0, sizeof (pset->slots[0]) * pset->n_slots);
22797 /* A pointer map is represented the same way as a pointer_set, so
22798 the hash code is based on the address of the key, rather than
22799 @@ -301,3 +318,20 @@ void pointer_map_traverse (const struct
22800 if (pmap->keys[i] && !fn (pmap->keys[i], &pmap->values[i], data))
22804 +/* Return the number of elements in PMAP. */
22807 +pointer_map_n_elements (struct pointer_map_t *pmap)
22809 + return pmap->n_elements;
22812 +/* Remove all entries from PMAP. */
22814 +void pointer_map_clear (struct pointer_map_t *pmap)
22816 + pmap->n_elements = 0;
22817 + memset (pmap->keys, 0, sizeof (pmap->keys[0]) * pmap->n_slots);
22818 + memset (pmap->values, 0, sizeof (pmap->values[0]) * pmap->n_slots);
22820 --- a/gcc/pointer-set.h
22821 +++ b/gcc/pointer-set.h
22822 @@ -29,6 +29,8 @@ int pointer_set_insert (struct pointer_s
22823 void pointer_set_traverse (const struct pointer_set_t *,
22824 bool (*) (const void *, void *),
22826 +size_t pointer_set_n_elements (struct pointer_set_t *);
22827 +void pointer_set_clear (struct pointer_set_t *);
22829 struct pointer_map_t;
22830 struct pointer_map_t *pointer_map_create (void);
22831 @@ -38,5 +40,7 @@ void **pointer_map_contains (const struc
22832 void **pointer_map_insert (struct pointer_map_t *pmap, const void *p);
22833 void pointer_map_traverse (const struct pointer_map_t *,
22834 bool (*) (const void *, void **, void *), void *);
22835 +size_t pointer_map_n_elements (struct pointer_map_t *);
22836 +void pointer_map_clear (struct pointer_map_t *);
22838 #endif /* POINTER_SET_H */
22839 --- a/gcc/postreload.c
22840 +++ b/gcc/postreload.c
22841 @@ -46,6 +46,7 @@ along with GCC; see the file COPYING3.
22843 #include "timevar.h"
22844 #include "tree-pass.h"
22845 +#include "addresses.h"
22847 #include "dbgcnt.h"
22849 @@ -708,17 +709,19 @@ reload_combine (void)
22850 int last_label_ruid;
22851 int min_labelno, n_labels;
22852 HARD_REG_SET ever_live_at_start, *label_live;
22853 + enum reg_class index_regs;
22855 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
22856 reload has already used it where appropriate, so there is no use in
22857 trying to generate it now. */
22858 - if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
22859 + index_regs = index_reg_class (VOIDmode);
22860 + if (double_reg_address_ok && index_regs != NO_REGS)
22863 /* To avoid wasting too much time later searching for an index register,
22864 determine the minimum and maximum index register numbers. */
22865 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
22866 - if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
22867 + if (TEST_HARD_REG_BIT (reg_class_contents[index_regs], r))
22869 if (first_index_reg == -1)
22870 first_index_reg = r;
22871 @@ -826,8 +829,8 @@ reload_combine (void)
22872 substitute uses of REG (typically in MEMs) with.
22873 First check REG and BASE for being index registers;
22874 we can use them even if they are not dead. */
22875 - if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
22876 - || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
22877 + if (TEST_HARD_REG_BIT (reg_class_contents[index_regs], regno)
22878 + || TEST_HARD_REG_BIT (reg_class_contents[index_regs],
22882 @@ -841,8 +844,7 @@ reload_combine (void)
22884 for (i = first_index_reg; i <= last_index_reg; i++)
22886 - if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
22888 + if (TEST_HARD_REG_BIT (reg_class_contents[index_regs], i)
22889 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
22890 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
22891 && hard_regno_nregs[i][GET_MODE (reg)] == 1)
22894 @@ -4576,6 +4576,167 @@ const struct real_format decimal_quad_fo
22898 +/* Encode half-precision floats. This routine is used both for the IEEE
22899 + ARM alternative encodings. */
22901 +encode_ieee_half (const struct real_format *fmt, long *buf,
22902 + const REAL_VALUE_TYPE *r)
22904 + unsigned long image, sig, exp;
22905 + unsigned long sign = r->sign;
22906 + bool denormal = (r->sig[SIGSZ-1] & SIG_MSB) == 0;
22908 + image = sign << 15;
22909 + sig = (r->sig[SIGSZ-1] >> (HOST_BITS_PER_LONG - 11)) & 0x3ff;
22917 + if (fmt->has_inf)
22918 + image |= 31 << 10;
22924 + if (fmt->has_nans)
22926 + if (r->canonical)
22927 + sig = (fmt->canonical_nan_lsbs_set ? (1 << 9) - 1 : 0);
22928 + if (r->signalling == fmt->qnan_msb_set)
22929 + sig &= ~(1 << 9);
22935 + image |= 31 << 10;
22943 + /* Recall that IEEE numbers are interpreted as 1.F x 2**exp,
22944 + whereas the intermediate representation is 0.F x 2**exp.
22945 + Which means we're off by one. */
22949 + exp = REAL_EXP (r) + 15 - 1;
22950 + image |= exp << 10;
22955 + gcc_unreachable ();
22961 +/* Decode half-precision floats. This routine is used both for the IEEE
22962 + ARM alternative encodings. */
22964 +decode_ieee_half (const struct real_format *fmt, REAL_VALUE_TYPE *r,
22967 + unsigned long image = buf[0] & 0xffff;
22968 + bool sign = (image >> 15) & 1;
22969 + int exp = (image >> 10) & 0x1f;
22971 + memset (r, 0, sizeof (*r));
22972 + image <<= HOST_BITS_PER_LONG - 11;
22973 + image &= ~SIG_MSB;
22977 + if (image && fmt->has_denorm)
22979 + r->cl = rvc_normal;
22981 + SET_REAL_EXP (r, -14);
22982 + r->sig[SIGSZ-1] = image << 1;
22985 + else if (fmt->has_signed_zero)
22988 + else if (exp == 31 && (fmt->has_nans || fmt->has_inf))
22994 + r->signalling = (((image >> (HOST_BITS_PER_LONG - 2)) & 1)
22995 + ^ fmt->qnan_msb_set);
22996 + r->sig[SIGSZ-1] = image;
23006 + r->cl = rvc_normal;
23008 + SET_REAL_EXP (r, exp - 15 + 1);
23009 + r->sig[SIGSZ-1] = image | SIG_MSB;
23013 +/* Half-precision format, as specified in IEEE 754R. */
23014 +const struct real_format ieee_half_format =
23016 + encode_ieee_half,
23017 + decode_ieee_half,
23035 +/* ARM's alternative half-precision format, similar to IEEE but with
23036 + no reserved exponent value for NaNs and infinities; rather, it just
23037 + extends the range of exponents by one. */
23038 +const struct real_format arm_half_format =
23040 + encode_ieee_half,
23041 + decode_ieee_half,
23059 /* A synthetic "format" for internal arithmetic. It's the size of the
23060 internal significand minus the two bits needed for proper rounding.
23061 The encode and decode routines exist only to satisfy our paranoia
23064 @@ -304,6 +304,8 @@ extern const struct real_format real_int
23065 extern const struct real_format decimal_single_format;
23066 extern const struct real_format decimal_double_format;
23067 extern const struct real_format decimal_quad_format;
23068 +extern const struct real_format ieee_half_format;
23069 +extern const struct real_format arm_half_format;
23072 /* ====================================================================== */
23073 --- a/gcc/regrename.c
23074 +++ b/gcc/regrename.c
23075 @@ -567,14 +567,14 @@ scan_rtx_address (rtx insn, rtx *loc, en
23077 unsigned regno0 = REGNO (op0), regno1 = REGNO (op1);
23079 - if (REGNO_OK_FOR_INDEX_P (regno1)
23080 + if (regno_ok_for_index_p (regno1, mode)
23081 && regno_ok_for_base_p (regno0, mode, PLUS, REG))
23083 - else if (REGNO_OK_FOR_INDEX_P (regno0)
23084 + else if (regno_ok_for_index_p (regno0, mode)
23085 && regno_ok_for_base_p (regno1, mode, PLUS, REG))
23087 else if (regno_ok_for_base_p (regno0, mode, PLUS, REG)
23088 - || REGNO_OK_FOR_INDEX_P (regno1))
23089 + || regno_ok_for_index_p (regno1, mode))
23091 else if (regno_ok_for_base_p (regno1, mode, PLUS, REG))
23093 @@ -599,7 +599,7 @@ scan_rtx_address (rtx insn, rtx *loc, en
23097 - scan_rtx_address (insn, locI, INDEX_REG_CLASS, action, mode);
23098 + scan_rtx_address (insn, locI, index_reg_class (mode), action, mode);
23100 scan_rtx_address (insn, locB, base_reg_class (mode, PLUS, index_code),
23102 @@ -1488,14 +1488,14 @@ replace_oldest_value_addr (rtx *loc, enu
23104 unsigned regno0 = REGNO (op0), regno1 = REGNO (op1);
23106 - if (REGNO_OK_FOR_INDEX_P (regno1)
23107 + if (regno_ok_for_index_p (regno1, mode)
23108 && regno_ok_for_base_p (regno0, mode, PLUS, REG))
23110 - else if (REGNO_OK_FOR_INDEX_P (regno0)
23111 + else if (regno_ok_for_index_p (regno0, mode)
23112 && regno_ok_for_base_p (regno1, mode, PLUS, REG))
23114 else if (regno_ok_for_base_p (regno0, mode, PLUS, REG)
23115 - || REGNO_OK_FOR_INDEX_P (regno1))
23116 + || regno_ok_for_index_p (regno1, mode))
23118 else if (regno_ok_for_base_p (regno1, mode, PLUS, REG))
23120 @@ -1520,8 +1520,8 @@ replace_oldest_value_addr (rtx *loc, enu
23124 - changed |= replace_oldest_value_addr (locI, INDEX_REG_CLASS, mode,
23126 + changed |= replace_oldest_value_addr (locI, index_reg_class (mode),
23129 changed |= replace_oldest_value_addr (locB,
23130 base_reg_class (mode, PLUS,
23133 @@ -5046,7 +5046,7 @@ find_reloads_address (enum machine_mode
23134 loc = &XEXP (*loc, 0);
23137 - if (double_reg_address_ok)
23138 + if (double_reg_address_ok && index_reg_class (mode) != NO_REGS)
23140 /* Unshare the sum as well. */
23141 *loc = ad = copy_rtx (ad);
23142 @@ -5054,8 +5054,8 @@ find_reloads_address (enum machine_mode
23143 /* Reload the displacement into an index reg.
23144 We assume the frame pointer or arg pointer is a base reg. */
23145 find_reloads_address_part (XEXP (ad, 1), &XEXP (ad, 1),
23146 - INDEX_REG_CLASS, GET_MODE (ad), opnum,
23147 - type, ind_levels);
23148 + index_reg_class (mode), GET_MODE (ad),
23149 + opnum, type, ind_levels);
23153 @@ -5448,13 +5448,13 @@ find_reloads_address_1 (enum machine_mod
23154 #define REG_OK_FOR_CONTEXT(CONTEXT, REGNO, MODE, OUTER, INDEX) \
23156 ? regno_ok_for_base_p (REGNO, MODE, OUTER, INDEX) \
23157 - : REGNO_OK_FOR_INDEX_P (REGNO))
23158 + : regno_ok_for_index_p (REGNO, MODE))
23160 enum reg_class context_reg_class;
23161 RTX_CODE code = GET_CODE (x);
23164 - context_reg_class = INDEX_REG_CLASS;
23165 + context_reg_class = index_reg_class (mode);
23167 context_reg_class = base_reg_class (mode, outer_code, index_code);
23169 @@ -5546,17 +5546,17 @@ find_reloads_address_1 (enum machine_mod
23171 else if (code0 == REG && code1 == REG)
23173 - if (REGNO_OK_FOR_INDEX_P (REGNO (op1))
23174 + if (regno_ok_for_index_p (REGNO (op1), mode)
23175 && regno_ok_for_base_p (REGNO (op0), mode, PLUS, REG))
23177 - else if (REGNO_OK_FOR_INDEX_P (REGNO (op0))
23178 + else if (regno_ok_for_index_p (REGNO (op0), mode)
23179 && regno_ok_for_base_p (REGNO (op1), mode, PLUS, REG))
23181 else if (regno_ok_for_base_p (REGNO (op0), mode, PLUS, REG))
23182 find_reloads_address_1 (mode, orig_op1, 1, PLUS, SCRATCH,
23183 &XEXP (x, 1), opnum, type, ind_levels,
23185 - else if (REGNO_OK_FOR_INDEX_P (REGNO (op1)))
23186 + else if (regno_ok_for_index_p (REGNO (op1), mode))
23187 find_reloads_address_1 (mode, orig_op0, 0, PLUS, REG,
23188 &XEXP (x, 0), opnum, type, ind_levels,
23190 @@ -5564,7 +5564,7 @@ find_reloads_address_1 (enum machine_mod
23191 find_reloads_address_1 (mode, orig_op0, 1, PLUS, SCRATCH,
23192 &XEXP (x, 0), opnum, type, ind_levels,
23194 - else if (REGNO_OK_FOR_INDEX_P (REGNO (op0)))
23195 + else if (regno_ok_for_index_p (REGNO (op0), mode))
23196 find_reloads_address_1 (mode, orig_op1, 0, PLUS, REG,
23197 &XEXP (x, 1), opnum, type, ind_levels,
23199 @@ -5634,7 +5634,7 @@ find_reloads_address_1 (enum machine_mod
23200 need to live longer than a TYPE reload normally would, so be
23201 conservative and class it as RELOAD_OTHER. */
23202 if ((REG_P (XEXP (op1, 1))
23203 - && !REGNO_OK_FOR_INDEX_P (REGNO (XEXP (op1, 1))))
23204 + && !regno_ok_for_index_p (REGNO (XEXP (op1, 1)), mode))
23205 || GET_CODE (XEXP (op1, 1)) == PLUS)
23206 find_reloads_address_1 (mode, XEXP (op1, 1), 1, code, SCRATCH,
23207 &XEXP (op1, 1), opnum, RELOAD_OTHER,
23208 @@ -6131,18 +6131,26 @@ find_reloads_subreg_address (rtx x, int
23209 /* For some processors an address may be valid in the
23210 original mode but not in a smaller mode. For
23211 example, ARM accepts a scaled index register in
23212 - SImode but not in HImode. Similarly, the address may
23213 - have been valid before the subreg offset was added,
23214 - but not afterwards. find_reloads_address
23215 - assumes that we pass it a valid address, and doesn't
23216 - force a reload. This will probably be fine if
23217 - find_reloads_address finds some reloads. But if it
23218 - doesn't find any, then we may have just converted a
23219 - valid address into an invalid one. Check for that
23221 + SImode but not in HImode. Note that this is only
23222 + a problem if the address in reg_equiv_mem is already
23223 + invalid in the new mode; other cases would be fixed
23224 + by find_reloads_address as usual.
23226 + ??? We attempt to handle such cases here by doing an
23227 + additional reload of the full address after the
23228 + usual processing by find_reloads_address. Note that
23229 + this may not work in the general case, but it seems
23230 + to cover the cases where this situation currently
23231 + occurs. A more general fix might be to reload the
23232 + *value* instead of the address, but this would not
23233 + be expected by the callers of this routine as-is.
23235 + If find_reloads_address already completed replaced
23236 + the address, there is nothing further to do. */
23238 - && !strict_memory_address_p (GET_MODE (tem),
23240 + && reg_equiv_mem[regno] != 0
23241 + && !strict_memory_address_p (GET_MODE (x),
23242 + XEXP (reg_equiv_mem[regno], 0)))
23243 push_reload (XEXP (tem, 0), NULL_RTX, &XEXP (tem, 0), (rtx*) 0,
23244 base_reg_class (GET_MODE (tem), MEM, SCRATCH),
23245 GET_MODE (XEXP (tem, 0)), VOIDmode, 0, 0,
23248 @@ -1088,7 +1088,11 @@ DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_a
23249 guard for the bypass. The function will get the two insns as
23250 parameters. If the function returns zero the bypass will be
23251 ignored for this case. Additional guard is necessary to recognize
23252 - complicated bypasses, e.g. when consumer is load address. */
23253 + complicated bypasses, e.g. when consumer is load address. If there
23254 + are more one bypass with the same output and input insns, the
23255 + chosen bypass is the first bypass with a guard in description whose
23256 + guard function returns nonzero. If there is no such bypass, then
23257 + bypass without the guard function is chosen. */
23258 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
23260 /* (define_automaton string) describes names of automata generated and
23261 --- a/gcc/rtlanal.c
23262 +++ b/gcc/rtlanal.c
23263 @@ -2913,62 +2913,78 @@ int
23264 commutative_operand_precedence (rtx op)
23266 enum rtx_code code = GET_CODE (op);
23269 /* Constants always come the second operand. Prefer "nice" constants. */
23270 if (code == CONST_INT)
23272 - if (code == CONST_DOUBLE)
23274 - if (code == CONST_FIXED)
23276 - op = avoid_constant_pool_reference (op);
23277 - code = GET_CODE (op);
23279 - switch (GET_RTX_CLASS (code))
23281 - case RTX_CONST_OBJ:
23282 - if (code == CONST_INT)
23284 - if (code == CONST_DOUBLE)
23286 - if (code == CONST_FIXED)
23291 - /* SUBREGs of objects should come second. */
23292 - if (code == SUBREG && OBJECT_P (SUBREG_REG (op)))
23296 + else if (code == CONST_DOUBLE)
23298 + else if (code == CONST_FIXED)
23302 + op = avoid_constant_pool_reference (op);
23303 + code = GET_CODE (op);
23305 + switch (GET_RTX_CLASS (code))
23307 + case RTX_CONST_OBJ:
23308 + if (code == CONST_INT)
23310 + else if (code == CONST_DOUBLE)
23312 + else if (code == CONST_FIXED)
23319 + /* SUBREGs of objects should come second. */
23320 + if (code == SUBREG && OBJECT_P (SUBREG_REG (op)))
23327 + /* Complex expressions should be the first, so decrease priority
23333 - /* Complex expressions should be the first, so decrease priority
23334 - of objects. Prefer pointer objects over non pointer objects. */
23335 - if ((REG_P (op) && REG_POINTER (op))
23336 - || (MEM_P (op) && MEM_POINTER (op)))
23340 - case RTX_COMM_ARITH:
23341 - /* Prefer operands that are themselves commutative to be first.
23342 - This helps to make things linear. In particular,
23343 - (and (and (reg) (reg)) (not (reg))) is canonical. */
23346 - case RTX_BIN_ARITH:
23347 - /* If only one operand is a binary expression, it will be the first
23348 - operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
23349 - is canonical, although it will usually be further simplified. */
23351 + case RTX_COMM_ARITH:
23352 + /* Prefer operands that are themselves commutative to be first.
23353 + This helps to make things linear. In particular,
23354 + (and (and (reg) (reg)) (not (reg))) is canonical. */
23358 + case RTX_BIN_ARITH:
23359 + /* If only one operand is a binary expression, it will be the first
23360 + operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
23361 + is canonical, although it will usually be further simplified. */
23366 - /* Then prefer NEG and NOT. */
23367 - if (code == NEG || code == NOT)
23370 + /* Then prefer NEG and NOT. */
23371 + if (code == NEG || code == NOT)
23384 + if (targetm.commutative_operand_precedence)
23385 + value = targetm.commutative_operand_precedence (op, value);
23390 /* Return 1 iff it is necessary to swap operands of commutative operation
23391 --- a/gcc/sched-ebb.c
23392 +++ b/gcc/sched-ebb.c
23393 @@ -286,6 +286,7 @@ static struct haifa_sched_info ebb_sched
23396 ebb_contributes_to_priority,
23397 + NULL, /* insn_finishes_block_p */
23401 --- a/gcc/sched-int.h
23402 +++ b/gcc/sched-int.h
23403 @@ -558,6 +558,10 @@ struct haifa_sched_info
23405 int (*contributes_to_priority) (rtx, rtx);
23407 + /* Return true if scheduling insn (passed as the parameter) will trigger
23408 + finish of scheduling current block. */
23409 + bool (*insn_finishes_block_p) (rtx);
23411 /* The boundaries of the set of insns to be scheduled. */
23412 rtx prev_head, next_tail;
23414 --- a/gcc/sched-rgn.c
23415 +++ b/gcc/sched-rgn.c
23416 @@ -2338,6 +2338,19 @@ static const struct sched_deps_info_def
23420 +/* Return true if scheduling INSN will trigger finish of scheduling
23421 + current block. */
23423 +rgn_insn_finishes_block_p (rtx insn)
23425 + if (INSN_BB (insn) == target_bb
23426 + && sched_target_n_insns + 1 == target_n_insns)
23427 + /* INSN is the last not-scheduled instruction in the current block. */
23433 /* Used in schedule_insns to initialize current_sched_info for scheduling
23434 regions (or single basic blocks). */
23436 @@ -2350,6 +2363,7 @@ static const struct haifa_sched_info rgn
23439 contributes_to_priority,
23440 + rgn_insn_finishes_block_p,
23446 @@ -338,6 +338,7 @@ const struct gcc_debug_hooks sdb_debug_h
23447 debug_nothing_int, /* handle_pch */
23448 debug_nothing_rtx, /* var_location */
23449 debug_nothing_void, /* switch_text_section */
23450 + debug_nothing_tree_tree, /* set_name */
23451 0 /* start_end_main_source_file */
23454 --- a/gcc/sel-sched-ir.c
23455 +++ b/gcc/sel-sched-ir.c
23456 @@ -5431,6 +5431,7 @@ static struct haifa_sched_info sched_sel
23457 NULL, /* rgn_rank */
23458 sel_print_insn, /* rgn_print_insn */
23459 contributes_to_priority,
23460 + NULL, /* insn_finishes_block_p */
23464 --- a/gcc/target-def.h
23465 +++ b/gcc/target-def.h
23467 #define TARGET_ASM_INTERNAL_LABEL default_internal_label
23470 -#ifndef TARGET_ARM_TTYPE
23471 +#ifndef TARGET_ASM_TTYPE
23472 #define TARGET_ASM_TTYPE hook_bool_rtx_false
23475 @@ -208,6 +208,10 @@
23476 #define TARGET_EXTRA_LIVE_ON_ENTRY hook_void_bitmap
23479 +#ifndef TARGET_WARN_FUNC_RESULT
23480 +#define TARGET_WARN_FUNC_RESULT hook_bool_void_true
23483 #ifndef TARGET_ASM_FILE_START_APP_OFF
23484 #define TARGET_ASM_FILE_START_APP_OFF false
23486 @@ -383,6 +387,9 @@
23487 #define TARGET_VECTOR_ALIGNMENT_REACHABLE \
23488 default_builtin_vector_alignment_reachable
23489 #define TARGET_VECTORIZE_BUILTIN_VEC_PERM 0
23490 +#define TARGET_VECTOR_MIN_ALIGNMENT \
23491 + default_vector_min_alignment
23492 +#define TARGET_VECTOR_ALWAYS_MISALIGN hook_bool_const_tree_false
23494 #define TARGET_VECTORIZE \
23496 @@ -393,7 +400,9 @@
23497 TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD, \
23498 TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST, \
23499 TARGET_VECTOR_ALIGNMENT_REACHABLE, \
23500 - TARGET_VECTORIZE_BUILTIN_VEC_PERM \
23501 + TARGET_VECTORIZE_BUILTIN_VEC_PERM, \
23502 + TARGET_VECTOR_MIN_ALIGNMENT, \
23503 + TARGET_VECTOR_ALWAYS_MISALIGN, \
23506 #define TARGET_DEFAULT_TARGET_FLAGS 0
23507 @@ -504,6 +513,7 @@
23508 #define TARGET_ALLOCATE_INITIAL_VALUE NULL
23510 #define TARGET_UNSPEC_MAY_TRAP_P default_unspec_may_trap_p
23511 +#define TARGET_COMMUTATIVE_OPERAND_PRECEDENCE NULL
23513 #ifndef TARGET_SET_CURRENT_FUNCTION
23514 #define TARGET_SET_CURRENT_FUNCTION hook_void_tree
23515 @@ -532,6 +542,10 @@
23516 #define TARGET_INVALID_CONVERSION hook_constcharptr_const_tree_const_tree_null
23517 #define TARGET_INVALID_UNARY_OP hook_constcharptr_int_const_tree_null
23518 #define TARGET_INVALID_BINARY_OP hook_constcharptr_int_const_tree_const_tree_null
23519 +#define TARGET_INVALID_PARAMETER_TYPE hook_constcharptr_const_tree_null
23520 +#define TARGET_INVALID_RETURN_TYPE hook_constcharptr_const_tree_null
23521 +#define TARGET_PROMOTED_TYPE hook_tree_const_tree_null
23522 +#define TARGET_CONVERT_TO_TYPE hook_tree_tree_tree_null
23524 #define TARGET_FIXED_CONDITION_CODE_REGS hook_bool_uintp_uintp_false
23526 @@ -590,6 +604,7 @@
23527 #define TARGET_ARG_PARTIAL_BYTES hook_int_CUMULATIVE_ARGS_mode_tree_bool_0
23529 #define TARGET_FUNCTION_VALUE default_function_value
23530 +#define TARGET_LIBCALL_VALUE default_libcall_value
23531 #define TARGET_INTERNAL_ARG_POINTER default_internal_arg_pointer
23532 #define TARGET_UPDATE_STACK_BOUNDARY NULL
23533 #define TARGET_GET_DRAP_RTX NULL
23534 @@ -613,6 +628,7 @@
23535 TARGET_ARG_PARTIAL_BYTES, \
23536 TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN, \
23537 TARGET_FUNCTION_VALUE, \
23538 + TARGET_LIBCALL_VALUE, \
23539 TARGET_INTERNAL_ARG_POINTER, \
23540 TARGET_UPDATE_STACK_BOUNDARY, \
23541 TARGET_GET_DRAP_RTX, \
23542 @@ -716,6 +732,11 @@
23543 #define TARGET_CXX_ADJUST_CLASS_AT_DEFINITION hook_void_tree
23547 +#ifndef TARGET_CXX_TTYPE_REF_ENCODE
23548 +#define TARGET_CXX_TTYPE_REF_ENCODE NULL
23551 #define TARGET_CXX \
23553 TARGET_CXX_GUARD_TYPE, \
23554 @@ -730,7 +751,8 @@
23555 TARGET_CXX_LIBRARY_RTTI_COMDAT, \
23556 TARGET_CXX_USE_AEABI_ATEXIT, \
23557 TARGET_CXX_USE_ATEXIT_FOR_CXA_ATEXIT, \
23558 - TARGET_CXX_ADJUST_CLASS_AT_DEFINITION \
23559 + TARGET_CXX_ADJUST_CLASS_AT_DEFINITION, \
23560 + TARGET_CXX_TTYPE_REF_ENCODE \
23563 /* EMUTLS specific */
23564 @@ -886,6 +908,7 @@
23565 TARGET_ADDRESS_COST, \
23566 TARGET_ALLOCATE_INITIAL_VALUE, \
23567 TARGET_UNSPEC_MAY_TRAP_P, \
23568 + TARGET_COMMUTATIVE_OPERAND_PRECEDENCE, \
23569 TARGET_DWARF_REGISTER_SPAN, \
23570 TARGET_INIT_DWARF_REG_SIZES_EXTRA, \
23571 TARGET_FIXED_CONDITION_CODE_REGS, \
23572 @@ -913,6 +936,10 @@
23573 TARGET_INVALID_CONVERSION, \
23574 TARGET_INVALID_UNARY_OP, \
23575 TARGET_INVALID_BINARY_OP, \
23576 + TARGET_INVALID_PARAMETER_TYPE, \
23577 + TARGET_INVALID_RETURN_TYPE, \
23578 + TARGET_PROMOTED_TYPE, \
23579 + TARGET_CONVERT_TO_TYPE, \
23580 TARGET_IRA_COVER_CLASSES, \
23581 TARGET_SECONDARY_RELOAD, \
23582 TARGET_EXPAND_TO_RTL_HOOK, \
23583 @@ -923,6 +950,7 @@
23585 TARGET_OPTION_HOOKS, \
23586 TARGET_EXTRA_LIVE_ON_ENTRY, \
23587 + TARGET_WARN_FUNC_RESULT, \
23588 TARGET_UNWIND_TABLES_DEFAULT, \
23589 TARGET_HAVE_NAMED_SECTIONS, \
23590 TARGET_HAVE_SWITCHABLE_BSS_SECTIONS, \
23593 @@ -473,7 +473,16 @@ struct gcc_target
23595 /* Target builtin that implements vector permute. */
23596 tree (* builtin_vec_perm) (tree, tree*);
23599 + /* Return the minimum alignment required to load or store a
23600 + vector of the given type, which may be less than the
23601 + natural alignment of the type. */
23602 + int (* vector_min_alignment) (const_tree);
23604 + /* Return true if "movmisalign" patterns should be used for all
23605 + loads/stores from data arrays. */
23606 + bool (* always_misalign) (const_tree);
23609 /* The initial value of target_flags. */
23610 int default_target_flags;
23611 @@ -694,6 +703,10 @@ struct gcc_target
23612 FLAGS has the same meaning as in rtlanal.c: may_trap_p_1. */
23613 int (* unspec_may_trap_p) (const_rtx x, unsigned flags);
23615 + /* Return a value indicating whether an operand of a commutative
23616 + operation is preferred as the first or second operand. */
23617 + int (* commutative_operand_precedence) (const_rtx, int);
23619 /* Given a register, this hook should return a parallel of registers
23620 to represent where to find the register pieces. Define this hook
23621 if the register and its mode are represented in Dwarf in
23622 @@ -870,6 +883,10 @@ struct gcc_target
23623 rtx (*function_value) (const_tree ret_type, const_tree fn_decl_or_type,
23626 + /* Return the rtx for the result of a libcall of mode MODE,
23627 + calling the function FN_NAME. */
23628 + rtx (*libcall_value) (enum machine_mode, rtx);
23630 /* Return an rtx for the argument pointer incoming to the
23631 current function. */
23632 rtx (*internal_arg_pointer) (void);
23633 @@ -899,6 +916,24 @@ struct gcc_target
23634 is not permitted on TYPE1 and TYPE2, NULL otherwise. */
23635 const char *(*invalid_binary_op) (int op, const_tree type1, const_tree type2);
23637 + /* Return the diagnostic message string if TYPE is not valid as a
23638 + function parameter type, NULL otherwise. */
23639 + const char *(*invalid_parameter_type) (const_tree type);
23641 + /* Return the diagnostic message string if TYPE is not valid as a
23642 + function return type, NULL otherwise. */
23643 + const char *(*invalid_return_type) (const_tree type);
23645 + /* If values of TYPE are promoted to some other type when used in
23646 + expressions (analogous to the integer promotions), return that type,
23647 + or NULL_TREE otherwise. */
23648 + tree (*promoted_type) (const_tree type);
23650 + /* Convert EXPR to TYPE, if target-specific types with special conversion
23651 + rules are involved. Return the converted expression, or NULL to apply
23652 + the standard conversion rules. */
23653 + tree (*convert_to_type) (tree type, tree expr);
23655 /* Return the array of IRA cover classes for the current target. */
23656 const enum reg_class *(*ira_cover_classes) (void);
23658 @@ -977,6 +1012,11 @@ struct gcc_target
23659 class (eg, tweak visibility or perform any other required
23660 target modifications). */
23661 void (*adjust_class_at_definition) (tree type);
23662 + /* Encode a reference type info, used for catching pointer
23663 + references. The provided expression will be the address of the
23664 + type info object of the type to which a reference is being
23666 + tree (* ttype_ref_encode) (tree);
23669 /* Functions and data for emulated TLS support. */
23670 @@ -1040,6 +1080,10 @@ struct gcc_target
23671 bits in the bitmap passed in. */
23672 void (*live_on_entry) (bitmap);
23674 + /* Return false if warnings about missing return statements or suspect
23675 + noreturn attributes should be suppressed for the current function. */
23676 + bool (*warn_func_result) (void);
23678 /* True if unwinding tables should be generated by default. */
23679 bool unwind_tables_default;
23681 --- a/gcc/targhooks.c
23682 +++ b/gcc/targhooks.c
23683 @@ -441,6 +441,15 @@ hook_invalid_arg_for_unprototyped_fn (
23688 +hook_cxx_ttype_ref_in_bit0 (tree exp)
23690 + exp = convert (build_pointer_type (char_type_node), exp);
23691 + exp = pointer_int_sum (PLUS_EXPR, exp, integer_one_node);
23696 /* Initialize the stack protection decls. */
23698 /* Stack protection related decls living in libgcc. */
23699 @@ -561,6 +570,12 @@ default_function_value (const_tree ret_t
23703 +default_libcall_value (enum machine_mode mode, rtx fun ATTRIBUTE_UNUSED)
23705 + return LIBCALL_VALUE (mode);
23709 default_internal_arg_pointer (void)
23711 /* If the reg that the virtual arg pointer will be translated into is
23712 @@ -712,6 +727,12 @@ default_builtin_vector_alignment_reachab
23717 +default_vector_min_alignment (const_tree type)
23719 + return TYPE_ALIGN_UNIT (type);
23723 default_hard_regno_scratch_ok (unsigned int regno ATTRIBUTE_UNUSED)
23725 --- a/gcc/targhooks.h
23726 +++ b/gcc/targhooks.h
23727 @@ -48,6 +48,7 @@ extern enum machine_mode default_mode_fo
23729 extern tree default_cxx_guard_type (void);
23730 extern tree default_cxx_get_cookie_size (tree);
23731 +extern tree hook_cxx_ttype_ref_in_bit0 (tree);
23733 extern bool hook_pass_by_reference_must_pass_in_stack
23734 (CUMULATIVE_ARGS *, enum machine_mode mode, const_tree, bool);
23735 @@ -71,6 +72,8 @@ extern tree default_builtin_reciprocal (
23737 extern bool default_builtin_vector_alignment_reachable (const_tree, bool);
23739 +extern int default_vector_min_alignment (const_tree);
23741 /* These are here, and not in hooks.[ch], because not all users of
23742 hooks.h include tm.h, and thus we don't have CUMULATIVE_ARGS. */
23744 @@ -87,6 +90,7 @@ extern const char *hook_invalid_arg_for_
23745 (const_tree, const_tree, const_tree);
23746 extern bool hook_bool_const_rtx_commutative_p (const_rtx, int);
23747 extern rtx default_function_value (const_tree, const_tree, bool);
23748 +extern rtx default_libcall_value (enum machine_mode, rtx);
23749 extern rtx default_internal_arg_pointer (void);
23750 #ifdef IRA_COVER_CLASSES
23751 extern const enum reg_class *default_ira_cover_classes (void);
23752 --- a/gcc/testsuite/g++.dg/abi/mangle-neon.C
23753 +++ b/gcc/testsuite/g++.dg/abi/mangle-neon.C
23756 // { dg-do compile }
23757 // { dg-require-effective-target arm_neon_ok }
23758 -// { dg-options "-mfpu=neon -mfloat-abi=softfp" }
23759 +// { dg-add-options arm_neon }
23761 #include <arm_neon.h>
23764 +++ b/gcc/testsuite/g++.dg/eh/ref1.C
23766 +// { dg-do run { xfail { ! arm-*-*eabi } } }
23768 +// catching a pointer to class by reference prohibits derived->base
23769 +// transformation. The generic C++ ABI gets this wrong. ARM EABI
23770 +// gets this right, except for exception specifications where a bug is
23773 +#include <stdio.h>
23787 + catch (A *&a) // { dg-bogus "earlier handler" "" { xfail { ! arm-*-*eabi } } }
23789 + printf ("fail, caught A*&%p\n", a);
23792 + catch (B *&b) // { dg-bogus "will be caught" "" { xfail { ! arm-*-*eabi } } }
23794 + printf ("pass, caught B*&%p\n", b);
23798 + printf ("fail, caught ...");
23805 + catch (A *a) // { dg-warning "by earlier handler" }
23807 + printf ("pass, caught A*%p\n", a);
23809 + catch (B *b) // { dg-warning "will be caught" }
23811 + printf ("fail, caught B*%p\n", b);
23816 + printf ("fail, caught ...");
23828 +++ b/gcc/testsuite/g++.dg/eh/ref2.C
23830 +// { dg-do run { xfail { ! arm-*-*eabi } } }
23832 +// catching a pointer to class by reference prohibits derived->base
23833 +// transformation. The generic C++ ABI gets this wrong. ARM EABI
23834 +// gets this right, except for exception specifications where a bug is
23837 +#include <stdio.h>
23838 +#include <exception>
23839 +#include <stdlib.h>
23847 +void One () throw (A *&)
23852 +void Two () throw (A *&, B *&)
23857 +void Three () throw (A *)
23862 +int Foo (void (*fn)())
23870 + printf ("pass, caught B*%p\n", b);
23874 + printf ("fail, caught ...");
23882 + printf ("pass, got unexpected exception\n");
23888 + if (Foo (&Three))
23894 + std::set_unexpected (handler);
23897 + printf ("fail, did not get unexpected exception\n");
23901 +++ b/gcc/testsuite/g++.dg/ext/altivec-17.C
23903 +// { dg-do compile { target powerpc*-*-* } }
23904 +// { dg-require-effective-target powerpc_altivec_ok }
23905 +// { dg-options "-maltivec" }
23907 +// Make sure that bool vectors have distinct names to int vectors
23909 +#define vector__ __attribute__((altivec (vector__)))
23910 +#define bool__ __attribute__((altivec(bool__)))
23912 +typedef vector__ unsigned int simd_type;
23913 +typedef vector__ bool__ int bool_simd_type;
23915 +void Foo (bool_simd_type const &a)
23917 + simd_type const &v = a; // { dg-error "'const unsigned int __vector__&' from expression of type 'const __bool int __vector__'" }
23920 +++ b/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-1.C
23922 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
23923 +/* { dg-do run { target arm*-*-* } } */
23924 +/* { dg-options "-mfp16-format=ieee" } */
23926 +#include "arm-fp16-ops.h"
23928 +++ b/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-2.C
23930 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
23931 +/* { dg-do run { target arm*-*-* } } */
23932 +/* { dg-options "-mfp16-format=ieee -ffast-math" } */
23934 +#include "arm-fp16-ops.h"
23936 +++ b/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-3.C
23938 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
23939 +/* { dg-do run { target arm*-*-* } } */
23940 +/* { dg-options "-mfp16-format=alternative" } */
23942 +#include "arm-fp16-ops.h"
23944 +++ b/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-4.C
23946 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
23947 +/* { dg-do run { target arm*-*-* } } */
23948 +/* { dg-options "-mfp16-format=alternative -ffast-math" } */
23950 +#include "arm-fp16-ops.h"
23952 +++ b/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C
23954 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
23955 +/* { dg-do compile { target arm*-*-* } } */
23956 +/* { dg-require-effective-target arm_neon_fp16_ok } */
23957 +/* { dg-options "-mfp16-format=ieee" } */
23958 +/* { dg-add-options arm_neon_fp16 } */
23960 +#include "arm-fp16-ops.h"
23962 +/* We've specified options for hardware float, including fp16 support, so
23963 + we should not see any calls to libfuncs here. */
23964 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf2" } } */
23965 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf3" } } */
23966 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
23967 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */
23968 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */
23970 +++ b/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C
23972 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
23973 +/* { dg-do compile { target arm*-*-* } } */
23974 +/* { dg-require-effective-target arm_neon_fp16_ok } */
23975 +/* { dg-options "-mfp16-format=ieee -ffast-math" } */
23976 +/* { dg-add-options arm_neon_fp16 } */
23978 +#include "arm-fp16-ops.h"
23980 +/* We've specified options for hardware float, including fp16 support, so
23981 + we should not see any calls to libfuncs here. */
23982 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf2" } } */
23983 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf3" } } */
23984 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
23985 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */
23986 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */
23988 +++ b/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-7.C
23990 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
23991 +/* { dg-do compile { target arm*-*-* } } */
23992 +/* { dg-require-effective-target arm_neon_ok } */
23993 +/* { dg-options "-mfp16-format=ieee" } */
23994 +/* { dg-add-options arm_neon } */
23996 +#include "arm-fp16-ops.h"
23998 +/* We've specified options for hardware float, so we should not see any
23999 + calls to libfuncs here except for those to the conversion functions. */
24000 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf2" } } */
24001 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf3" } } */
24002 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
24004 +++ b/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-8.C
24006 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
24007 +/* { dg-do compile { target arm*-*-* } } */
24008 +/* { dg-require-effective-target arm_neon_ok } */
24009 +/* { dg-options "-mfp16-format=ieee -ffast-math" } */
24010 +/* { dg-add-options arm_neon } */
24012 +#include "arm-fp16-ops.h"
24014 +/* We've specified options for hardware float, so we should not see any
24015 + calls to libfuncs here except for those to the conversion functions. */
24016 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf2" } } */
24017 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf3" } } */
24018 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
24020 +++ b/gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops.h
24022 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
24024 +#include <assert.h>
24026 +#define CHECK(e,r) assert ((e) == r)
24027 +#define CHECK2(e,r) (assert ((e) == r), temp = (e), assert (temp == r))
24028 +#define TEST(e) assert (e)
24029 +#define TESTNOT(e) assert (!(e))
24031 +volatile __fp16 h0 = 0.0;
24032 +volatile __fp16 h1 = 1.0;
24033 +volatile __fp16 h42 = 42.0;
24034 +volatile __fp16 hm2 = -2.0;
24035 +volatile __fp16 temp;
24037 +volatile float f0 = 0.0;
24038 +volatile float f1 = 1.0;
24039 +volatile float f42 = 42.0;
24040 +volatile float fm2 = -2.0;
24049 + CHECK2 (-h1, -1.0);
24050 + CHECK2 (+h1, 1.0);
24052 + CHECK (h1++, 1.0);
24054 + CHECK (++h1, 3.0);
24057 + CHECK (--h1, 2.0);
24059 + CHECK (h1--, 2.0);
24062 + CHECK2 (h42 * hm2, -84.0);
24063 + CHECK2 (h42 * (__fp16) -2.0, -84.0);
24064 + CHECK2 (h42 * fm2, -84.0);
24065 + CHECK2 (f42 * hm2, -84.0);
24067 + CHECK2 (h42 / hm2, -21.0);
24068 + CHECK2 (h42 / (__fp16) -2.0, -21.0);
24069 + CHECK2 (h42 / fm2, -21.0);
24070 + CHECK2 (f42 / hm2, -21.0);
24072 + CHECK2 (hm2 + h42, 40.0);
24073 + CHECK2 ((__fp16)-2.0 + h42, 40.0);
24074 + CHECK2 (hm2 + f42, 40.0);
24075 + CHECK2 (fm2 + h42, 40.0);
24077 + CHECK2 (hm2 - h42, -44.0);
24078 + CHECK2 ((__fp16)-2.0 - h42, -44.0);
24079 + CHECK2 (hm2 - f42, -44.0);
24080 + CHECK2 (fm2 - h42, -44.0);
24082 + TEST (hm2 < h42);
24083 + TEST (hm2 < (__fp16)42.0);
24084 + TEST (hm2 < f42);
24085 + TEST (fm2 < h42);
24087 + TEST (h42 > hm2);
24088 + TEST ((__fp16)42.0 > hm2);
24089 + TEST (h42 > fm2);
24090 + TEST (f42 > hm2);
24092 + TEST (hm2 <= h42);
24093 + TEST (hm2 <= (__fp16)42.0);
24094 + TEST (hm2 <= f42);
24095 + TEST (fm2 <= h42);
24097 + TEST (h42 >= hm2);
24098 + TEST (h42 >= (__fp16)-2.0);
24099 + TEST (h42 >= fm2);
24100 + TEST (f42 >= hm2);
24102 + TESTNOT (h1 == hm2);
24104 + TEST (h1 == (__fp16)1.0);
24108 + TEST (h1 != hm2);
24109 + TESTNOT (h1 != h1);
24110 + TESTNOT (h1 != (__fp16)1.0);
24111 + TESTNOT (h1 != f1);
24112 + TESTNOT (f1 != h1);
24114 + CHECK2 ((h1 ? hm2 : h42), -2.0);
24115 + CHECK2 ((h0 ? hm2 : h42), 42.0);
24117 + CHECK (h0 = h42, 42.0);
24118 + CHECK (h0, 42.0);
24119 + CHECK (h0 = (__fp16)-2.0, -2.0);
24120 + CHECK (h0, -2.0);
24121 + CHECK (h0 = f0, 0.0);
24124 + CHECK (h0 += h1, 1.0);
24126 + CHECK (h0 += (__fp16)1.0, 2.0);
24128 + CHECK (h0 += fm2, 0.0);
24131 + CHECK (h0 -= h1, -1.0);
24132 + CHECK (h0, -1.0);
24133 + CHECK (h0 -= (__fp16)1.0, -2.0);
24134 + CHECK (h0, -2.0);
24135 + CHECK (h0 -= fm2, 0.0);
24139 + CHECK (h0 *= hm2, 4.0);
24141 + CHECK (h0 *= (__fp16)-2.0, -8.0);
24142 + CHECK (h0, -8.0);
24143 + CHECK (h0 *= fm2, 16.0);
24144 + CHECK (h0, 16.0);
24146 + CHECK (h0 /= hm2, -8.0);
24147 + CHECK (h0, -8.0);
24148 + CHECK (h0 /= (__fp16)-2.0, 4.0);
24150 + CHECK (h0 /= fm2, -2.0);
24151 + CHECK (h0, -2.0);
24153 + CHECK ((h0, h1), 1.0);
24158 +++ b/gcc/testsuite/g++.dg/ext/arm-fp16/fp16-mangle-1.C
24160 +/* { dg-do compile { target arm*-*-* } } */
24161 +/* { dg-options "-mfp16-format=ieee" } */
24163 +/* Test mangling */
24165 +/* { dg-final { scan-assembler "\t.global\t_Z1fPDh" } } */
24166 +void f (__fp16 *x) { }
24168 +/* { dg-final { scan-assembler "\t.global\t_Z1gPDhS_" } } */
24169 +void g (__fp16 *x, __fp16 *y) { }
24171 +/* { dg-final { scan-assembler "\t.global\t_ZN1SIDhDhE1iE" } } */
24172 +template <typename T, typename U> struct S { static int i; };
24173 +template <> int S<__fp16, __fp16>::i = 3;
24175 +++ b/gcc/testsuite/g++.dg/ext/arm-fp16/fp16-overload-1.C
24177 +/* { dg-do compile { target arm*-*-* } } */
24178 +/* { dg-options "-mfp16-format=ieee" } */
24180 +/* __fp16 values are autoconverted to float and should therefore be treated
24181 + * just like float for overloading purposes. */
24183 +extern int frobnify (float x);
24184 +extern int frobnify (double x);
24188 + return frobnify ((__fp16)1.0);
24191 +/* { dg-final { scan-assembler "_Z8frobnifyf" } } */
24192 +/* { dg-final { scan-assembler-not " _Z8frobnifyd" } } */
24194 +++ b/gcc/testsuite/g++.dg/ext/arm-fp16/fp16-param-1.C
24196 +/* { dg-do compile { target arm*-*-* } } */
24197 +/* { dg-options "-mfp16-format=ieee" } */
24199 +/* Functions cannot have parameters of type __fp16. */
24200 +extern void f (__fp16); /* { dg-error "parameters cannot have __fp16 type" } */
24201 +extern void (*pf) (__fp16); /* { dg-error "parameters cannot have __fp16 type" } */
24203 +/* These should be OK. */
24204 +extern void g (__fp16 *);
24205 +extern void (*pg) (__fp16 *);
24207 +++ b/gcc/testsuite/g++.dg/ext/arm-fp16/fp16-return-1.C
24209 +/* { dg-do compile { target arm*-*-* } } */
24210 +/* { dg-options "-mfp16-format=ieee" } */
24212 +/* Functions cannot return type __fp16. */
24213 +extern __fp16 f (void); /* { dg-error "cannot return __fp16" } */
24214 +extern __fp16 (*pf) (void); /* { dg-error "cannot return __fp16" } */
24216 +/* These should be OK. */
24217 +extern __fp16 *g (void);
24218 +extern __fp16 *(*pg) (void);
24220 +++ b/gcc/testsuite/g++.dg/ext/dllexport2.C
24223 +// { dg-require-dll "" }
24224 +// { dg-additional-sources "dllexport2a.cc" }
24225 +// { dg-options "-O2" }
24227 +/* Test that inline functions declared "dllexport" appear in object
24228 + files, even if they are not called.
24230 + This behavior is required by the ARM C++ ABI:
24232 + Exporting a function that can be inlined should force the
24233 + creation and export of an out-of-line copy of it.
24235 + and should presumably also apply.
24237 + Visual Studio 2005 also honors that rule. */
24239 +__declspec(dllexport) inline void i1() {}
24241 +__declspec(dllexport) extern inline void e1() {}
24243 +/* It is invalid to declare the function inline after its definition. */
24245 +__declspec(dllexport) void i2() {}
24248 +__declspec(dllexport) extern void e2() {}
24252 +__declspec(dllexport) inline void i3() {}
24255 +__declspec(dllexport) inline void e3() {}
24258 +__declspec(dllexport) void i4();
24259 +inline void i4() {};
24261 +__declspec(dllexport) extern void e4();
24262 +inline void e4() {};
24264 +__declspec(dllexport) inline void i5();
24267 +__declspec(dllexport) inline void e5();
24268 +extern void e5() {};
24270 +/* Make sure that just declaring the function -- without defining it
24271 + -- does not cause errors. */
24272 +__declspec(dllexport) inline void i6();
24273 +__declspec(dllexport) extern inline void e6();
24275 +++ b/gcc/testsuite/g++.dg/ext/dllexport2a.cc
24299 +++ b/gcc/testsuite/g++.dg/ext/ms-1.C
24302 +// MS allows more things to be pointers to member functions
24303 +// { dg-options "-fms-extensions" }
24311 +void Quux (void (X::*) ());
24313 +void X::Foo (X *ptr) // { dg-message "candidates" }
24315 + Quux (Foo); // { dg-error "no matches" }
24318 --- a/gcc/testsuite/g++.dg/init/ref15.C
24319 +++ b/gcc/testsuite/g++.dg/init/ref15.C
24321 // PR c++/20416. We correctly constructed the temporary S in foo(),
24322 // but incorrectly destroyed it every time foo() was called.
24324 +// When using a wrapped target, there is no way to override the exit
24325 +// code after returning from main.
24326 +// { dg-do run { target unwrapped } }
24327 extern "C" void abort (void);
24328 extern "C" void _exit (int);
24331 +++ b/gcc/testsuite/g++.dg/opt/alias5.C
24333 +// { dg-options "-O2" }
24334 +// ICE in struct-alias
24336 +typedef int (*PFN)(void);
24343 +inline PFN Get (struct Container *tpl)
24349 +inline void Foo (PFN pfn)
24351 + Other (Get ((struct Container *)&pfn));
24358 +++ b/gcc/testsuite/g++.dg/other/arm-neon-1.C
24360 +/* Basic smoke test for arm_neon.h */
24362 +/* { dg-do assemble } */
24363 +/* { dg-require-effective-target arm_neon_ok } */
24364 +/* { dg-add-options arm_neon } */
24366 +#include "arm_neon.h"
24375 + res = vadd_f32(v.val[0], v.val[1]);
24376 + vst1_f32(a, res);
24379 +++ b/gcc/testsuite/g++.dg/other/armv7m-1.C
24381 +/* { dg-do run { target arm*-*-* } } */
24382 +/* Test Armv7m interrupt routines. */
24383 +#include <stdlib.h>
24385 +#ifdef __ARM_ARCH_7M__
24386 +void __attribute__((interrupt))
24391 + asm volatile ("" : "=r" (p) : "0" (&n));
24397 +void __attribute__((interrupt))
24408 + volatile register int sp asm("sp");
24410 + asm volatile ("mov %0, sp\n"
24413 + : "=&r" (before), "=r" (after) : "r" (foo)
24414 + : "memory", "cc", "r0", "r1", "r2", "r3", "ip", "lr");
24415 + if (before != after)
24417 + asm volatile ("mov %0, sp\n"
24418 + "sub sp, sp, #4\n"
24420 + "add sp, sp, #4\n"
24422 + : "=&r" (before), "=r" (after) : "r" (foo)
24423 + : "memory", "cc", "r0", "r1", "r2", "r3", "ip", "lr");
24424 + if (before != after)
24440 + if (before != sp)
24451 +++ b/gcc/testsuite/g++.dg/remove-local-statics-1.C
24453 +/* Verify that we do not eliminate a static variable in
24454 + main::Local::Foo. */
24456 +/* { dg-do compile } */
24457 +/* { dg-options "-O2 -fremove-local-statics" } */
24458 +/* { dg-final { scan-assembler "thestatic" } } */
24463 + static int thestatic = 0;
24465 + __attribute__((__noinline__))
24466 + static void Foo () { thestatic = 1; }
24472 + return thestatic++;
24475 +++ b/gcc/testsuite/g++.dg/remove-local-statics-2.C
24477 +/* Verify that we do not eliminate a static variable in
24478 + main due to its use in Local::Foo. */
24480 +/* { dg-do compile } */
24481 +/* { dg-options "-O2 -fremove-local-statics" } */
24482 +/* { dg-final { scan-assembler "thestatic" } } */
24487 + static int thestatic = 0;
24489 + __attribute__((__noinline__))
24490 + static int Foo () { return thestatic; }
24494 + thestatic = Local::Foo();
24496 + return thestatic++;
24498 --- a/gcc/testsuite/g++.dg/template/overload9.C
24499 +++ b/gcc/testsuite/g++.dg/template/overload9.C
24500 @@ -7,12 +7,12 @@ template <typename T> A<T>& operator<<(A
24501 template <typename T>
24504 - A<T>& operator<<(A<T>& (*)(A<T>&)); // { dg-message "candidate" }
24505 + A<T>& operator<<(A<T>& (*)(A<T>&));
24508 template <typename T> A<T>& foo(A<T>&);
24512 - c << (1, foo); // { dg-error "no match" }
24513 + c << (1, foo); // { dg-error "no context" }
24515 --- a/gcc/testsuite/g++.dg/torture/pr36191.C
24516 +++ b/gcc/testsuite/g++.dg/torture/pr36191.C
24519 // { dg-do compile }
24520 // { dg-options "-fnon-call-exceptions" }
24521 +// { dg-skip-if "Frame pointer required for unwind tables" { sh*-*-* } "-fomit-frame-pointer" "" }
24524 foo (__complex__ double x, double y)
24526 +++ b/gcc/testsuite/g++.dg/tree-ssa/sink-1.C
24528 +/* { dg-do run } */
24529 +/* { dg-options "-O1" } */
24535 + void * dostuff();
24537 + virtual int dovirtual() = 0;
24541 +class B : public A {
24544 + int dovirtual() { return 0;}
24548 +class C : public B {
24554 +void* A::dostuff()
24556 + return (void*)dovirtual();
24559 +/* tree-ssa-sink was sinking the inlined destructor for STUFF out of
24560 + the first inner block and into the second one, where it was ending up
24561 + after the inlined constructor for STUFF2. This is bad because
24562 + cfgexpand aliases STUFF and STUFF2 to the same storage at -O1
24563 + (i.e., without -fstrict-aliasing), with the result that STUFF2's
24564 + vtable was getting trashed. */
24573 + stuff2.dostuff();
24578 --- a/gcc/testsuite/g++.dg/vect/vect.exp
24579 +++ b/gcc/testsuite/g++.dg/vect/vect.exp
24580 @@ -105,7 +105,7 @@ if [istarget "powerpc-*paired*"] {
24581 } elseif [istarget "ia64-*-*"] {
24582 set dg-do-what-default run
24583 } elseif [is-effective-target arm_neon_ok] {
24584 - lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp"
24585 + eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
24586 if [is-effective-target arm_neon_hw] {
24587 set dg-do-what-default run
24589 --- a/gcc/testsuite/g++.dg/warn/null4.C
24590 +++ b/gcc/testsuite/g++.dg/warn/null4.C
24591 @@ -11,9 +11,22 @@ int foo (void)
24592 if (NULL < NULL) return -1; // { dg-warning "NULL used in arithmetic" }
24593 if (NULL >= 0) return -1; // { dg-warning "NULL used in arithmetic" }
24594 if (NULL <= 0) return -1; // { dg-warning "NULL used in arithmetic" }
24595 + // Adding to the NULL pointer, which has no specific type, should
24596 + // result in a warning; the type of the resulting expression is
24597 + // actually "int", not a pointer type.
24598 + if (NULL + 1) return -1; // { dg-warning "NULL used in arithmetic" }
24599 + if (1 + NULL) return -1; // { dg-warning "NULL used in arithmetic" }
24606 +typedef int S::*SPD;
24607 +typedef void (S::*SPF)(void);
24613 if (NULL) return -1;
24614 @@ -25,5 +38,18 @@ int bar (void)
24615 if (NULL != NULL) return -1;
24616 if (NULL == 0) return -1;
24617 if (NULL != 0) return -1;
24618 + // Subtraction of pointers is vaild, so using NULL is OK.
24619 + if (ip - NULL) return -1;
24620 + if (NULL - NULL) return -1;
24621 + // Comparing NULL with a pointer-to-member is OK.
24622 + if (NULL == spd) return -1;
24623 + if (spd == NULL) return -1;
24624 + if (NULL != spd) return -1;
24625 + if (spd != NULL) return -1;
24626 + if (NULL == spf) return -1;
24627 + if (spf == NULL) return -1;
24628 + if (NULL != spf) return -1;
24629 + if (spf != NULL) return -1;
24633 --- a/gcc/testsuite/g++.old-deja/g++.other/overload11.C
24634 +++ b/gcc/testsuite/g++.old-deja/g++.other/overload11.C
24635 @@ -54,11 +54,10 @@ int main (int argc, char **argv)
24638 ptr = (&ovl); // ok
24639 - // 13.4 indicates these are ok.
24640 - ptr = (0, ovl); // ok { dg-bogus "" "" { xfail *-*-* } }
24641 - ptr = (0, &ovl); // ok { dg-bogus "" "" { xfail *-*-* } }
24642 - ptr = (argc ? ovl : ovl); // ok { dg-bogus "" "" { xfail *-*-* } }
24643 - ptr = (argc ? &ovl : &ovl);// ok { dg-bogus "" "" { xfail *-*-* } }
24644 + ptr = (0, ovl); // ok { dg-error "no context" }
24645 + ptr = (0, &ovl); // ok { dg-error "no context" }
24646 + ptr = (argc ? ovl : ovl); // ok { dg-error "no context" }
24647 + ptr = (argc ? &ovl : &ovl);// ok { dg-error "no context" }
24649 vptr = (ovl); // { dg-error "" } no matching candidates
24650 vptr = (&ovl); // { dg-error "" } no matching candidates
24652 +++ b/gcc/testsuite/gcc.c-torture/execute/990208-1.x
24655 +# On ARM, with -Os, some of the functions that this test
24656 +# expects to be inlined are not inlined for code size
24657 +# reasons. This is not a bug, it's intentional,
24658 +# so stop this test from running.
24659 +set torture_eval_before_compile {
24660 + if { [istarget "arm-*-*"] && [string match {*-Os*} "$option"] } {
24666 \ No newline at end of file
24668 +++ b/gcc/testsuite/gcc.c-torture/execute/bcp-1.x
24671 +# On ARM, with -Os, some of the functions that this test
24672 +# expects to be inlined are not inlined for code size
24673 +# reasons. This is not a bug, it's intentional,
24674 +# so stop this test from running.
24675 +set torture_eval_before_compile {
24676 + if { [istarget "arm-*-*"] && [string match {*-Os*} "$option"] } {
24682 \ No newline at end of file
24683 --- a/gcc/testsuite/gcc.c-torture/execute/ieee/ieee.exp
24684 +++ b/gcc/testsuite/gcc.c-torture/execute/ieee/ieee.exp
24685 @@ -54,6 +54,9 @@ if { [istarget "alpha*-*-*"]
24686 || [istarget "sh*-*-*"] } then {
24687 lappend additional_flags "-mieee"
24689 +if [istarget "mips*-sde-*"] then {
24690 + lappend additional_flags "-Wl,--defsym=__cs3_mips_float_type=2" "-lcs3-mips-cp1" "-lcs3-mips-fpemu"
24693 # load support procs
24694 load_lib c-torture.exp
24695 --- a/gcc/testsuite/gcc.dg/builtin-redefine.c
24696 +++ b/gcc/testsuite/gcc.dg/builtin-redefine.c
24698 #define __TIME__ "X" /* Re-define while defined. */
24700 #define __TIME__ "Y" /* { dg-warning "\"__TIME__\" redefined" } */
24701 -/* { dg-warning "previous definition" "" { target *-*-* } 28 } */
24702 +/* { dg-message "previous definition" "" { target *-*-* } 28 } */
24704 #undef __TIME__ /* Undefine while defined. */
24707 #define __DATE__ "X" /* Re-define while defined. */
24709 #define __DATE__ "Y" /* { dg-warning "\"__DATE__\" redefined" } */
24710 -/* { dg-warning "previous definition" "" { target *-*-* } 39 } */
24711 +/* { dg-message "previous definition" "" { target *-*-* } 39 } */
24713 #undef __DATE__ /* Undefine while defined. */
24716 #define __TIMESTAMP__ "X" /* Re-define while defined. */
24718 #define __TIMESTAMP__ "Y" /* { dg-warning "\"__TIMESTAMP__\" redefined" } */
24719 -/* { dg-warning "previous definition" "" { target *-*-* } 48 } */
24720 +/* { dg-message "previous definition" "" { target *-*-* } 48 } */
24722 #undef __TIMESTAMP__ /* Undefine while defined. */
24724 --- a/gcc/testsuite/gcc.dg/compat/struct-layout-1_generate.c
24725 +++ b/gcc/testsuite/gcc.dg/compat/struct-layout-1_generate.c
24726 @@ -46,7 +46,7 @@ const char *dg_options[] = {
24727 "/* { dg-options \"%s-I%s\" } */\n",
24728 "/* { dg-options \"%s-I%s -Wno-abi\" } */\n",
24729 "/* { dg-options \"%s-I%s -mno-mmx -Wno-abi\" { target i?86-*-* x86_64-*-* } } */\n",
24730 -"/* { dg-options \"%s-I%s -fno-common\" { target hppa*-*-hpux* powerpc*-*-darwin* *-*-mingw32* *-*-cygwin* } } */\n",
24731 +"/* { dg-options \"%s-I%s -fno-common\" { target hppa*-*-hpux* powerpc*-*-darwin* } } */\n",
24732 "/* { dg-options \"%s-I%s -mno-mmx -fno-common -Wno-abi\" { target i?86-*-darwin* x86_64-*-darwin* } } */\n",
24733 "/* { dg-options \"%s-I%s -mno-base-addresses\" { target mmix-*-* } } */\n",
24734 "/* { dg-options \"%s-I%s -mlongcalls -mtext-section-literals\" { target xtensa*-*-* } } */\n"
24735 --- a/gcc/testsuite/gcc.dg/cpp/Wvariadic-1.c
24736 +++ b/gcc/testsuite/gcc.dg/cpp/Wvariadic-1.c
24738 #define f(x,...) /* { dg-error "variadic" } */
24739 #define g(x,y...) /* { dg-error "variadic" } */
24741 +/* { dg-message "warnings being treated as errors" "" { target *-*-* } 0 } */
24742 --- a/gcc/testsuite/gcc.dg/cpp/Wvariadic-3.c
24743 +++ b/gcc/testsuite/gcc.dg/cpp/Wvariadic-3.c
24746 #define g(x,y...) /* { dg-error "variadic" } */
24748 +/* { dg-message "warnings being treated as errors" "" { target *-*-* } 0 } */
24749 --- a/gcc/testsuite/gcc.dg/cpp/include2.c
24750 +++ b/gcc/testsuite/gcc.dg/cpp/include2.c
24752 /* Source: Neil Booth, 4 Nov 2000. */
24754 #include <silly\>> /* { dg-error "extra tokens" "" } */
24755 -#include "silly\"" /* { dg-error "extra tokens" "" } */
24757 /* These error is No such file or directory, just once. However, this
24758 message is locale-dependent, so don't test for it. */
24759 /* { dg-error "silly" "" { target *-*-* } 10 } */
24760 -/* { dg-error "missing" "" { target *-*-* } 11 } */
24761 +/* { dg-message "terminated" "" { target *-*-* } 0 } */
24763 +++ b/gcc/testsuite/gcc.dg/cpp/include2a.c
24765 +/* Copyright (C) 2000 Free Software Foundation, Inc. */
24767 +/* { dg-do preprocess } */
24769 +/* Tests that #include does not allow the terminating '>' or '"' to be
24770 + escaped, as per the standard. */
24772 +/* Source: Neil Booth, 4 Nov 2000. */
24774 +#include "silly\"" /* { dg-error "extra tokens" "" } */
24776 +/* These error is No such file or directory, just once. However, this
24777 + message is locale-dependent, so don't test for it. */
24778 +/* { dg-error "silly" "" { target *-*-* } 10 } */
24779 +/* { dg-error "missing" "" { target *-*-* } 10 } */
24780 +/* { dg-message "terminated" "" { target *-*-* } 0 } */
24782 +++ b/gcc/testsuite/gcc.dg/cpp/missing-header-1.c
24784 +/* Test that missing headers are fatal errors. PR 15638. */
24785 +/* { dg-do compile } */
24786 +/* { dg-options "" } */
24788 +#include "nonexistent.h" /* { dg-error "nonexistent.h" } */
24789 +/* { dg-message "terminated" "" { target *-*-* } 0 } */
24791 +/* This declaration should not receive any diagnostic. */
24794 +++ b/gcc/testsuite/gcc.dg/cpp/missing-header-MD.c
24796 +/* Test that missing user headers are fatal errors with -MD. */
24797 +/* { dg-do compile } */
24798 +/* { dg-options "-MD" } */
24800 +#include "nonexistent.h" /* { dg-error "nonexistent.h" } */
24801 +/* { dg-message "terminated" "" { target *-*-* } 0 } */
24803 +++ b/gcc/testsuite/gcc.dg/cpp/missing-header-MMD.c
24805 +/* Test that missing user headers are fatal errors with -MMD. */
24806 +/* { dg-do compile } */
24807 +/* { dg-options "-MMD" } */
24809 +#include "nonexistent.h" /* { dg-error "nonexistent.h" } */
24810 +/* { dg-message "terminated" "" { target *-*-* } 0 } */
24812 +++ b/gcc/testsuite/gcc.dg/cpp/missing-sysheader-MD.c
24814 +/* Test that missing system headers are fatal errors with -MD. */
24815 +/* { dg-do compile } */
24816 +/* { dg-options "-MD" } */
24818 +#include <nonexistent.h> /* { dg-error "nonexistent.h" } */
24819 +/* { dg-message "terminated" "" { target *-*-* } 0 } */
24821 +++ b/gcc/testsuite/gcc.dg/cpp/missing-sysheader-MMD.c
24823 +/* Test that missing system headers are fatal errors with -MMD. */
24824 +/* { dg-do compile } */
24825 +/* { dg-options "-MMD" } */
24827 +#include <nonexistent.h> /* { dg-error "nonexistent.h" } */
24828 +/* { dg-message "terminated" "" { target *-*-* } 0 } */
24829 --- a/gcc/testsuite/gcc.dg/cpp/redef2.c
24830 +++ b/gcc/testsuite/gcc.dg/cpp/redef2.c
24832 { dg-warning "redefined" "redef ro" { target *-*-* } 12 }
24833 { dg-warning "redefined" "redef va" { target *-*-* } 15 }
24835 - { dg-warning "previous" "prev def mac" { target *-*-* } 6 }
24836 - { dg-warning "previous" "prev def mac" { target *-*-* } 7 }
24837 - { dg-warning "previous" "prev def mac" { target *-*-* } 8 }
24838 - { dg-warning "previous" "prev def ro" { target *-*-* } 11 }
24839 - { dg-warning "previous" "prev def va" { target *-*-* } 14 }
24840 + { dg-message "previous" "prev def mac" { target *-*-* } 6 }
24841 + { dg-message "previous" "prev def mac" { target *-*-* } 7 }
24842 + { dg-message "previous" "prev def mac" { target *-*-* } 8 }
24843 + { dg-message "previous" "prev def ro" { target *-*-* } 11 }
24844 + { dg-message "previous" "prev def va" { target *-*-* } 14 }
24846 --- a/gcc/testsuite/gcc.dg/cpp/redef3.c
24847 +++ b/gcc/testsuite/gcc.dg/cpp/redef3.c
24849 { dg-warning "redefined" "redef B" { target *-*-* } 9 }
24850 { dg-warning "redefined" "redef D" { target *-*-* } 11 }
24851 { dg-warning "redefined" "redef E" { target *-*-* } 12 }
24852 - { dg-warning "previous" "prev def A" { target *-*-* } 6 }
24853 - { dg-warning "previous" "prev def B" { target *-*-* } 8 }
24854 - { dg-warning "previous" "prev def D/E" { target *-*-* } 0 }
24855 + { dg-message "previous" "prev def A" { target *-*-* } 6 }
24856 + { dg-message "previous" "prev def B" { target *-*-* } 8 }
24857 + { dg-message "previous" "prev def D/E" { target *-*-* } 0 }
24859 --- a/gcc/testsuite/gcc.dg/cpp/trad/redef2.c
24860 +++ b/gcc/testsuite/gcc.dg/cpp/trad/redef2.c
24863 /* { dg-do preprocess } */
24865 -#define foo bar /* { dg-warning "previous def" "foo prev def" } */
24866 +#define foo bar /* { dg-message "previous def" "foo prev def" } */
24867 #define foo barr /* { dg-warning "redefined" "foo redefined" } */
24870 -#define foo bar /* { dg-warning "previous def" "foo prev def 2" } */
24871 +#define foo bar /* { dg-message "previous def" "foo prev def 2" } */
24872 #define foo() bar /* { dg-warning "redefined" "foo redefined 2" } */
24875 -#define foo() bar /* { dg-warning "previous def" "foo prev def" } */
24876 +#define foo() bar /* { dg-message "previous def" "foo prev def" } */
24877 #define foo() barr /* { dg-warning "redefined" "foo redefined" } */
24879 -#define quux(thud) a thud b /* { dg-warning "previous def" "quux prev def" } */
24880 +#define quux(thud) a thud b /* { dg-message "previous def" "quux prev def" } */
24881 #define quux(thu) a thud b /* { dg-warning "redefined" "quux redefined" } */
24883 -#define bar(x, y) x+y /* { dg-warning "previous def" "bar prev def" } */
24884 +#define bar(x, y) x+y /* { dg-message "previous def" "bar prev def" } */
24885 #define bar(x, y) x+x /* { dg-warning "redefined" "bar redefined" } */
24887 -#define bat(x, y) x+y /* { dg-warning "previous def" "bat prev def" } */
24888 +#define bat(x, y) x+y /* { dg-message "previous def" "bat prev def" } */
24889 #define bat(x, y) x+ y /* { dg-warning "redefined" "bat redefined" } */
24891 -#define baz(x, y) x+y /* { dg-warning "previous def" "baz prev def" } */
24892 +#define baz(x, y) x+y /* { dg-message "previous def" "baz prev def" } */
24893 #define baz(x, y) x +y /* { dg-warning "redefined" "baz redefined" } */
24895 -#define f(x, y) "x y" /* { dg-warning "previous def" "f prev def" } */
24896 +#define f(x, y) "x y" /* { dg-message "previous def" "f prev def" } */
24897 #define f(x, y) "x y" /* { dg-warning "redefined" "f redefined" } */
24899 -#define g(x, y) 'x' /* { dg-warning "previous def" "g prev def" } */
24900 +#define g(x, y) 'x' /* { dg-message "previous def" "g prev def" } */
24901 #define g(x, y) ' x' /* { dg-warning "redefined" "g redefined" } */
24902 --- a/gcc/testsuite/gcc.dg/dll-4.c
24903 +++ b/gcc/testsuite/gcc.dg/dll-4.c
24904 @@ -11,5 +11,6 @@ int foo2 = 5; /* { dg-warning "redeclare
24905 int f () { return foo1 + foo2; }
24907 /* FIXME: We should scan the output of nm for this case. */
24908 -/* { dg-final { scan-assembler "(foo2:.*\.comm\[ \t_\]*foo1)" } } */
24909 +/* { dg-final { scan-assembler "(foo2:)" } } */
24910 +/* { dg-final { scan-assembler "(\.comm\[ \t_\]*foo1)" } } */
24911 /* { dg-final { scan-assembler-not "(__imp_|_imp__)" } } */
24913 +++ b/gcc/testsuite/gcc.dg/dll-6.c
24915 +/* { dg-do link } */
24916 +/* { dg-require-dll "" } */
24917 +/* { dg-additional-sources "dll-6a.c" } */
24918 +/* { dg-options "-w -O2 -std=gnu89" } */
24920 +/* Test that inline functions declared "dllexport" appear in object
24921 + files, even if they are not called.
24923 + This behavior is required by the ARM C++ ABI:
24925 + Exporting a function that can be inlined should force the
24926 + creation and export of an out-of-line copy of it.
24928 + and should presumably also apply.
24930 + Visual Studio 2005 also honors that rule. */
24932 +__declspec(dllexport) inline void i1() {}
24934 +__declspec(dllexport) extern inline void e1() {}
24936 +/* It is invalid to declare the function inline after its definition. */
24938 +__declspec(dllexport) void i2() {}
24941 +__declspec(dllexport) extern void e2() {}
24945 +__declspec(dllexport) inline void i3() {}
24948 +__declspec(dllexport) inline void e3() {}
24951 +__declspec(dllexport) void i4();
24952 +inline void i4() {};
24954 +__declspec(dllexport) extern void e4();
24955 +inline void e4() {};
24957 +__declspec(dllexport) inline void i5();
24960 +__declspec(dllexport) inline void e5();
24961 +extern void e5() {};
24963 +/* Make sure that just declaring the function -- without defining it
24964 + -- does not cause errors. */
24965 +__declspec(dllexport) inline void i6();
24966 +__declspec(dllexport) extern inline void e6();
24968 +++ b/gcc/testsuite/gcc.dg/dll-6a.c
24992 +++ b/gcc/testsuite/gcc.dg/dll-7.c
24994 +/* { dg-do link } */
24995 +/* { dg-require-dll "" } */
24996 +/* { dg-additional-sources "dll-7a.c" } */
24997 +/* { dg-options "-w -O2 -std=gnu99" } */
24999 +/* Test that inline functions declared "dllexport" appear in object
25000 + files, even if they are not called.
25002 + This behavior is required by the ARM C++ ABI:
25004 + Exporting a function that can be inlined should force the
25005 + creation and export of an out-of-line copy of it.
25007 + and should presumably also apply.
25009 + Visual Studio 2005 also honors that rule. */
25011 +__declspec(dllexport) inline void i1() {}
25013 +__declspec(dllexport) extern inline void e1() {}
25015 +/* It is invalid to declare the function inline after its definition. */
25017 +__declspec(dllexport) void i2() {}
25020 +__declspec(dllexport) extern void e2() {}
25024 +__declspec(dllexport) inline void i3() {}
25027 +__declspec(dllexport) inline void e3() {}
25030 +__declspec(dllexport) void i4();
25031 +inline void i4() {};
25033 +__declspec(dllexport) extern void e4();
25034 +inline void e4() {};
25036 +__declspec(dllexport) inline void i5();
25039 +__declspec(dllexport) inline void e5();
25040 +extern void e5() {};
25042 +/* Make sure that just declaring the function -- without defining it
25043 + -- does not cause errors. */
25044 +__declspec(dllexport) inline void i6();
25045 +__declspec(dllexport) extern inline void e6();
25047 +++ b/gcc/testsuite/gcc.dg/dll-7a.c
25071 +++ b/gcc/testsuite/gcc.dg/falign-labels-1.c
25073 +/* { dg-do run } */
25074 +/* { dg-options "-falign-labels=8" { target { ! { m68k*-*-* || fido*-*-* } } } } */
25076 +/* On ARMv7-A CPUs, this test resulted in incorrect code generation.
25077 + The code generated for the switch statement expected the jump table
25078 + to immediately follow the jump instruction, but -falign-labels
25079 + caused the label preceding the table to be aligned. */
25080 +/* M68K and fido only support -falign-labels argument <= 2. */
25112 --- a/gcc/testsuite/gcc.dg/fltconst-1.c
25113 +++ b/gcc/testsuite/gcc.dg/fltconst-1.c
25115 /* { dg-do compile } */
25116 -/* { dg-options "-std=gnu99" } */
25117 +/* { dg-options "-std=gnu99 -fshow-column" } */
25119 double a = 1.ld; /* { dg-error "12:invalid suffix" } */
25120 double b = 1.fd; /* { dg-error "12:invalid suffix" } */
25122 +++ b/gcc/testsuite/gcc.dg/m68k-fp-1.c
25124 +/* ColdFire has restricted addressing modes for float operands. */
25125 +/* { dg-do compile { target m68k-*-* } } */
25126 +/* { dg-options "-O0 -mcpu=547x -mhard-float" } */
25128 +double Foo (unsigned a)
25130 + unsigned local_data[16384] __attribute__((unused));
25137 --- a/gcc/testsuite/gcc.dg/pch/counter-2.c
25138 +++ b/gcc/testsuite/gcc.dg/pch/counter-2.c
25140 #include "counter-2.h" /* { dg-warning "not used because `__COUNTER__' is invalid" } */
25141 /* { dg-error "counter-2.h: No such file or directory" "no such file" { target *-*-* } 10 } */
25142 /* { dg-error "one or more PCH files were found, but they were invalid" "invalid files" { target *-*-* } 10 } */
25143 +/* { dg-message "terminated" "" { target *-*-* } 0 } */
25147 --- a/gcc/testsuite/gcc.dg/pch/valid-1.c
25148 +++ b/gcc/testsuite/gcc.dg/pch/valid-1.c
25150 #include "valid-1.h"/* { dg-warning "created with -gnone, but used with -g" } */
25151 /* { dg-error "No such file" "no such file" { target *-*-* } 3 } */
25152 /* { dg-error "they were invalid" "invalid files" { target *-*-* } 3 } */
25153 +/* { dg-message "terminated" "" { target *-*-* } 0 } */
25156 --- a/gcc/testsuite/gcc.dg/pch/valid-2.c
25157 +++ b/gcc/testsuite/gcc.dg/pch/valid-2.c
25159 #include "valid-2.h" /* { dg-warning "settings for -fexceptions do not match" } */
25160 /* { dg-error "No such file" "no such file" { target *-*-* } 3 } */
25161 /* { dg-error "they were invalid" "invalid files" { target *-*-* } 3 } */
25162 +/* { dg-message "terminated" "" { target *-*-* } 0 } */
25164 --- a/gcc/testsuite/gcc.dg/pch/warn-1.c
25165 +++ b/gcc/testsuite/gcc.dg/pch/warn-1.c
25167 #include "warn-1.h"/* { dg-warning "not used because .DEFINED_VALUE. is defined" } */
25168 /* { dg-error "No such file" "no such file" { target *-*-* } 5 } */
25169 /* { dg-error "they were invalid" "invalid files" { target *-*-* } 5 } */
25170 +/* { dg-message "terminated" "" { target *-*-* } 0 } */
25174 --- a/gcc/testsuite/gcc.dg/pr34263.c
25175 +++ b/gcc/testsuite/gcc.dg/pr34263.c
25177 /* { dg-do run } */
25178 -/* { dg-options "-O2 -fdump-tree-optimized" } */
25179 +/* { dg-options "-O2 -fdump-tree-optimized -fno-unroll-loops" } */
25180 /* Same test as 990128-1.c. */
25182 extern int printf (const char *,...);
25183 --- a/gcc/testsuite/gcc.dg/pragma-isr-trapa2.c
25184 +++ b/gcc/testsuite/gcc.dg/pragma-isr-trapa2.c
25186 /* { dg-do compile { target { { sh-*-* sh4*-*-* } && nonpic } } } */
25187 +/* { dg-skip-if "FPU Required" { "sh*-*-*" } { "-m*nofpu*" } { "" } } */
25188 +/* { dg-skip-if "FPU Required" { "sh*-*-*" } { "-m4al*" } { "" } } */
25189 /* { dg-options "-O -m4" } */
25191 extern void foo ();
25192 --- a/gcc/testsuite/gcc.dg/profile-dir-1.c
25193 +++ b/gcc/testsuite/gcc.dg/profile-dir-1.c
25195 /* { dg-do compile } */
25196 /* { dg-options "-O -fprofile-generate=. -fdump-tree-tree_profile" } */
25197 +/* { dg-require-host-local "" } */
25198 /* { dg-final { scan-tree-dump " ./profile-dir-1.gcda" "tree_profile" } } */
25201 --- a/gcc/testsuite/gcc.dg/profile-dir-2.c
25202 +++ b/gcc/testsuite/gcc.dg/profile-dir-2.c
25204 /* { dg-do compile } */
25205 /* { dg-options "-O -fprofile-generate -fdump-tree-tree_profile" } */
25206 +/* { dg-require-host-local "" } */
25207 /* { dg-final { scan-tree-dump "/profile-dir-2.gcda" "tree_profile" } } */
25210 --- a/gcc/testsuite/gcc.dg/profile-dir-3.c
25211 +++ b/gcc/testsuite/gcc.dg/profile-dir-3.c
25213 /* { dg-do compile } */
25214 /* { dg-options "-O -fprofile-generate -fprofile-dir=. -fdump-tree-tree_profile" } */
25215 +/* { dg-require-host-local "" } */
25216 /* { dg-final { scan-tree-dump " ./profile-dir-3.gcda" "tree_profile" } } */
25220 +++ b/gcc/testsuite/gcc.dg/promote-short-1.c
25222 +/* Verify that we promote a short loop index variable. */
25224 +/* { dg-do compile } */
25225 +/* { dg-options "-O2 -fpromote-loop-indices -fdump-tree-promoteshort" } */
25226 +/* { dg-final { scan-tree-dump-times "Promoting 1 variables" 1 "promoteshort" } } */
25227 +/* { dg-final { cleanup-tree-dump "promoteshort" } } */
25230 +test1 (short n, int *x)
25234 + for (i = 0; i < n; i++)
25238 +++ b/gcc/testsuite/gcc.dg/promote-short-10.c
25240 +/* Verify that we do not promote a short loop index variable when its
25241 + address is taken. */
25243 +/* { dg-do compile } */
25244 +/* { dg-options "-O2 -fpromote-loop-indices -fdump-tree-promoteshort" } */
25245 +/* { dg-final { scan-tree-dump-times "Found 0 candidates" 1 "promoteshort" } } */
25246 +/* { dg-final { cleanup-tree-dump "promoteshort" } } */
25248 +extern void outside (short *);
25251 +test1 (int n, int *x)
25255 + for (i = 0; i < n; i++)
25261 +++ b/gcc/testsuite/gcc.dg/promote-short-2.c
25263 +/* Verify that we do not promote a short loop index variable when it is
25264 + being stored to memory. */
25266 +/* { dg-do compile } */
25267 +/* { dg-options "-O2 -fpromote-loop-indices -fdump-tree-promoteshort" } */
25268 +/* { dg-final { scan-tree-dump-times "Promoting 0 variables" 1 "promoteshort" } } */
25269 +/* { dg-final { cleanup-tree-dump "promoteshort" } } */
25272 +test1 (short n, short *x)
25276 + for (i = 0; i < n; i++)
25280 +++ b/gcc/testsuite/gcc.dg/promote-short-3.c
25282 +/* Verify that we do not promote a short loop index variable when it is
25283 + being passed as a function parameter. */
25285 +/* { dg-do compile } */
25286 +/* { dg-options "-O2 -fpromote-loop-indices -fdump-tree-promoteshort" } */
25287 +/* { dg-final { scan-tree-dump-times "Promoting 0 variables" 1 "promoteshort" { xfail m68k*-*-* fido*-*-* i?86-*-* x86_64-*-* mips*-*-* sh*-*-* } } } */
25288 +/* { dg-final { cleanup-tree-dump "promoteshort" } } */
25290 +extern void outside (short);
25297 + for (i = 0; i < n; i++)
25301 +++ b/gcc/testsuite/gcc.dg/promote-short-4.c
25303 +/* Verify that we do not promote a short loop index variable when it is
25304 + modified within the loop. */
25306 +/* { dg-do compile } */
25307 +/* { dg-options "-O2 -fpromote-loop-indices -fdump-tree-promoteshort" } */
25308 +/* { dg-final { scan-tree-dump-times "Promoting 0 variables" 1 "promoteshort" } } */
25309 +/* { dg-final { cleanup-tree-dump "promoteshort" } } */
25312 +test1 (short n, int *x)
25316 + for (i = 0; i < n; i++)
25323 +++ b/gcc/testsuite/gcc.dg/promote-short-5.c
25325 +/* Verify that we do not promote a short loop index variable when it has
25326 + a non-unit-increment. */
25328 +/* { dg-do compile } */
25329 +/* { dg-options "-O2 -fpromote-loop-indices -fdump-tree-promoteshort" } */
25330 +/* { dg-final { scan-tree-dump-times "Promoting 0 variables" 1 "promoteshort" } } */
25331 +/* { dg-final { cleanup-tree-dump "promoteshort" } } */
25334 +test1 (short n, int *x)
25338 + for (i = 0; i < n; i+=2)
25344 +++ b/gcc/testsuite/gcc.dg/promote-short-6.c
25346 +/* Verify that we do promote a short loop index variable when it has
25347 + a non-unit-increment and -funsafe-loop-optimizations is in effect. */
25349 +/* { dg-do compile } */
25350 +/* { dg-options "-O2 -fpromote-loop-indices -funsafe-loop-optimizations -fdump-tree-promoteshort" } */
25351 +/* { dg-final { scan-tree-dump-times "Promoting 1 variables" 1 "promoteshort" } } */
25352 +/* { dg-final { cleanup-tree-dump "promoteshort" } } */
25355 +test1 (short n, int *x)
25359 + for (i = 0; i < n; i+=2)
25365 +++ b/gcc/testsuite/gcc.dg/promote-short-7.c
25367 +/* Verify that we do not promote a short loop index variable when the
25368 + loop in which it is used has a bound of wider type. */
25370 +/* { dg-do compile } */
25371 +/* { dg-options "-O2 -fpromote-loop-indices -fdump-tree-promoteshort" } */
25372 +/* { dg-final { scan-tree-dump-times "Promoting 0 variables" 1 "promoteshort" } } */
25373 +/* { dg-final { cleanup-tree-dump "promoteshort" } } */
25376 +test1 (int n, int *x)
25380 + for (i = 0; i < n; i++)
25386 +++ b/gcc/testsuite/gcc.dg/promote-short-8.c
25388 +/* Verify that we do promote a short loop index variable when the loop
25389 + in which it is used has a bound of wider type and
25390 + -funsafe-loop-optimizations is in effect. */
25392 +/* { dg-do compile } */
25393 +/* { dg-options "-O2 -fpromote-loop-indices -funsafe-loop-optimizations -fdump-tree-promoteshort" } */
25394 +/* { dg-final { scan-tree-dump-times "Promoting 1 variables" 1 "promoteshort" } } */
25395 +/* { dg-final { cleanup-tree-dump "promoteshort" } } */
25398 +test1 (int n, int *x)
25402 + for (i = 0; i < n; i++)
25408 +++ b/gcc/testsuite/gcc.dg/promote-short-9.c
25410 +/* -fpromote-loop-indices used to ICE on this. */
25412 +/* { dg-do compile } */
25413 +/* { dg-options "-O2 -fpromote-loop-indices" } */
25416 +lookup (char *haystack, char *needle)
25420 + for (x = haystack[-2]; x < *needle; x++)
25421 + haystack[x] = needle[x];
25426 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-1.c
25428 +/* Verify that we eliminate a static local variable where its uses
25429 + are dominated by a def. */
25431 +/* { dg-do compile } */
25432 +/* { dg-options "-O2 -fremove-local-statics" } */
25433 +/* { dg-final { scan-assembler-not "thestatic" } } */
25438 + static int thestatic;
25442 + return thestatic + x;
25445 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-10.c
25447 +/* Verify that we do not eliminate a static local variable when it is
25448 + live on return from a function call that recursively calls the
25449 + function in which the variable is defined. */
25451 +/* { dg-do compile } */
25452 +/* { dg-options "-O2 -fremove-local-statics" } */
25453 +/* { dg-final { scan-assembler "thestatic" } } */
25461 + return test1 (x - 1);
25467 + static int thestatic;
25472 + y = test2 (x - 1);
25480 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-11.c
25482 +/* Verify that we do not eliminate a static local variable when its
25483 + address is taken. */
25485 +/* { dg-do compile } */
25486 +/* { dg-options "-O2 -fremove-local-statics" } */
25487 +/* { dg-final { scan-assembler "thestatic" } } */
25492 + static int thestatic;
25496 + return &thestatic + x;
25499 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-12.c
25501 +/* Verify that we do not eliminate a static variable when it is declared
25502 + in a function that has nested functions. */
25504 +/* { dg-do compile } */
25505 +/* { dg-options "-O2 -fremove-local-statics" } */
25506 +/* { dg-final { scan-assembler "thestatic" } } */
25510 + static int thestatic;
25512 + int nested_test1 (int x)
25514 + return x + thestatic;
25519 + return thestatic + x + nested_test1 (x);
25522 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-13.c
25524 +/* We used to ICE on this test, because the call to BAR appeared to
25525 + define both static variables in FOO. Verify that we no longer do
25528 +/* { dg-do compile } */
25529 +/* { dg-options "-O2 -fremove-local-statics" } */
25530 +/* { dg-final { scan-assembler "static1" } } */
25531 +/* { dg-final { scan-assembler-not "static2" } } */
25534 + static int static1 = 0;
25535 + static int static2;
25537 + if (static2 = bar(i))
25539 + static2 = static1 + 30;
25541 + return static1 + static2;
25545 + if (i) { foo(i-1); return 0; }
25549 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-14.c
25551 +/* Verify that we do eliminate a static local variable whose last use is
25552 + in a statement containing a call expression. */
25554 +/* { dg-do compile } */
25555 +/* { dg-options "-O2 -fremove-local-statics" } */
25556 +/* { dg-final { scan-assembler-not "thestatic" } } */
25564 + return test1 (x - 1);
25570 + static int thestatic;
25575 + y = test2 (thestatic - 1);
25581 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-15.c
25583 +/* Verify that we do not consider an array variable for local static
25586 +/* { dg-do compile } */
25587 +/* { dg-options "-O2 -fremove-local-statics -fdump-tree-remlocstatic-details" } */
25598 +/* { dg-final { scan-tree-dump-times "static variables to consider" 0 "remlocstatic" } } */
25599 +/* { dg-final { cleanup-tree-dump "remlocstatic" } } */
25601 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-16.c
25603 +/* Verify that we do not consider an structure variable for local static
25606 +/* { dg-do compile } */
25607 +/* { dg-options "-O2 -fremove-local-statics -fdump-tree-remlocstatic-details" } */
25621 +/* { dg-final { scan-tree-dump-times "static variables to consider" 0 "remlocstatic" } } */
25622 +/* { dg-final { cleanup-tree-dump "remlocstatic" } } */
25624 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-17.c
25626 +/* Verify that we do not eliminate a static variable that is "defined"
25627 + by an asm that clobbers memory. */
25629 +/* { dg-do compile } */
25630 +/* { dg-options "-O2 -fremove-local-statics -fdump-tree-remlocstatic-details" } */
25634 + static int foo = 0;
25636 + __asm__ __volatile__ ("bogus" : : : "memory");
25643 +/* { dg-final { scan-tree-dump-times "static variables to consider" 0 "remlocstatic" } } */
25644 +/* { dg-final { cleanup-tree-dump "remlocstatic" } } */
25646 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-2.c
25648 +/* Verify that we do not eliminate a static local variable when its uses
25649 + are not dominated by a def. */
25651 +/* { dg-do compile } */
25652 +/* { dg-options "-O2 -fremove-local-statics" } */
25653 +/* { dg-final { scan-assembler "first_time" } } */
25658 + static int first_time;
25665 + return first_time + x;
25668 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-3.c
25670 +/* Verify that we do not eliminate a static local variable whose uses
25671 + are dominated by a def when the variable is volatile. */
25673 +/* { dg-do compile } */
25674 +/* { dg-options "-O2 -fremove-local-statics" } */
25675 +/* { dg-final { scan-assembler "thestatic" } } */
25680 + static volatile int thestatic;
25684 + return thestatic + x;
25687 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-4.c
25689 +/* Verify that we don't eliminate a global static variable. */
25691 +/* { dg-do compile } */
25692 +/* { dg-options "-O2 -fremove-local-statics" } */
25693 +/* { dg-final { scan-assembler "global_static" } } */
25695 +static int global_static;
25700 + global_static = x;
25702 + return global_static + x;
25705 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-5.c
25707 +/* Verify that we do not eliminate a static local variable whose uses
25708 + are dominated by a def when the function calls setjmp. */
25710 +/* { dg-do compile } */
25711 +/* { dg-options "-O2 -fremove-local-statics" } */
25712 +/* { dg-final { scan-assembler "thestatic" } } */
25714 +#include <setjmp.h>
25719 + static int thestatic;
25725 + retval = thestatic + x;
25732 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-6.c
25734 +/* Verify that we do not eliminate a static local variable whose uses
25735 + are dominated by a def when the variable is addressed. */
25737 +/* { dg-do compile } */
25738 +/* { dg-options "-O2 -fremove-local-statics" } */
25739 +/* { dg-final { scan-assembler "thestatic" } } */
25744 + static int thestatic;
25748 + return &thestatic + x;
25751 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-7.c
25753 +/* Verify that we eliminate a static local variable where it is defined
25754 + along all paths leading to a use.
25756 + XFAIL'd because our analysis is currently too weak. */
25758 +/* { dg-do compile } */
25759 +/* { dg-options "-O2 -fremove-local-statics" } */
25760 +/* { dg-final { scan-assembler-not "thestatic" } } */
25765 + static int thestatic;
25772 + return thestatic + x;
25775 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-8.c
25777 +/* Verify that we eliminate a static local variable when it is dead on
25778 + return from a function call that recursively calls the function in
25779 + which the variable is defined. */
25781 +/* { dg-do compile } */
25782 +/* { dg-options "-O2 -fremove-local-statics" } */
25783 +/* { dg-final { scan-assembler-not "thestatic" } } */
25794 + return test1 (x - 1);
25800 + static int thestatic;
25807 + return y + x + test1 (x - 1) + test2 (x - 1);
25811 +++ b/gcc/testsuite/gcc.dg/remove-local-statics-9.c
25813 +/* Verify that we eliminate a static local variable when it is live
25814 + on return from a function call that does not recursively call the
25815 + function in which the variable is defined. */
25817 +/* XFAIL'd because we don't utilize the callgraph properly. */
25819 +/* { dg-do compile } */
25820 +/* { dg-options "-O2 -fremove-local-statics" } */
25821 +/* { dg-final { scan-assembler-not "thestatic" { xfail *-*-* } } } */
25829 + return x + test2 (x - 1);
25835 + static int thestatic;
25840 + y = test2 (x - 1);
25848 +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-compile-assign.c
25850 +/* { dg-do compile { target arm*-*-* } } */
25851 +/* { dg-options "-mfp16-format=ieee" } */
25853 +/* Test basic assignments and conversions for __fp16. */
25857 +__fp16 h2 = 1234.0;
25860 +float f2 = -999.9;
25862 +void f (__fp16 *p)
25876 +/* Make sure we are not falling through to undefined libcalls. */
25877 +/* { dg-final { scan-assembler-not "__truncsfhf" } } */
25878 +/* { dg-final { scan-assembler-not "__extendhfsf" } } */
25880 +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-compile-convert.c
25882 +/* { dg-do compile { target arm*-*-* } } */
25883 +/* { dg-options "-mfp16-format=ieee" } */
25885 +/* Test basic assignments and conversions for __fp16. */
25888 +__fp16 h2 = 1234.0;
25895 +long long l1 = 1000.0;
25896 +long long l2 = 2000.0;
25897 +double d1 = -10000.0;
25898 +double d2 = -20000.0;
25918 +/* Make sure we are not falling through to undefined libcalls. */
25919 +/* { dg-final { scan-assembler-not "__float.ihf" } } */
25920 +/* { dg-final { scan-assembler-not "__fixhf.i" } } */
25921 +/* { dg-final { scan-assembler-not "__trunc.fhf" } } */
25922 +/* { dg-final { scan-assembler-not "__extendhf.f" } } */
25924 +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-int-convert-alt.c
25926 +/* Test floating-point conversions. Standard types and __fp16. */
25927 +/* { dg-do run { target arm*-*-* } } */
25928 +/* { dg-options "-mfp16-format=alternative" } */
25930 +#include "fp-int-convert.h"
25931 +#define FP16_MANT_DIG 11
25936 + TEST_I_F(signed char, unsigned char, float, FP16_MANT_DIG);
25937 + TEST_I_F(signed short, unsigned short, float, FP16_MANT_DIG);
25938 + TEST_I_F(signed int, unsigned int, float, FP16_MANT_DIG);
25939 + TEST_I_F(signed long, unsigned long, float, FP16_MANT_DIG);
25940 + TEST_I_F(signed long long, unsigned long long, float, FP16_MANT_DIG);
25944 +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-int-convert-ieee.c
25946 +/* Test floating-point conversions. Standard types and __fp16. */
25947 +/* { dg-do run { target arm*-*-* } } */
25948 +/* { dg-options "-mfp16-format=ieee" } */
25950 +#include "fp-int-convert.h"
25951 +#define FP16_MANT_DIG 11
25956 + TEST_I_F(signed char, unsigned char, float, FP16_MANT_DIG);
25957 + TEST_I_F(signed short, unsigned short, float, FP16_MANT_DIG);
25958 + TEST_I_F(signed int, unsigned int, float, FP16_MANT_DIG);
25959 + TEST_I_F(signed long, unsigned long, float, FP16_MANT_DIG);
25960 + TEST_I_F(signed long long, unsigned long long, float, FP16_MANT_DIG);
25964 +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-1.c
25966 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
25967 +/* { dg-do run { target arm*-*-* } } */
25968 +/* { dg-options "-mfp16-format=ieee" } */
25970 +#include "arm-fp16-ops.h"
25972 +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-2.c
25974 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
25975 +/* { dg-do run { target arm*-*-* } } */
25976 +/* { dg-options "-mfp16-format=ieee -ffast-math" } */
25978 +#include "arm-fp16-ops.h"
25980 +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-3.c
25982 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
25983 +/* { dg-do run { target arm*-*-* } } */
25984 +/* { dg-options "-mfp16-format=alternative" } */
25986 +#include "arm-fp16-ops.h"
25988 +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-4.c
25990 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
25991 +/* { dg-do run { target arm*-*-* } } */
25992 +/* { dg-options "-mfp16-format=alternative -ffast-math" } */
25994 +#include "arm-fp16-ops.h"
25996 +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c
25998 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
25999 +/* { dg-do compile { target arm*-*-* } } */
26000 +/* { dg-require-effective-target arm_neon_fp16_ok } */
26001 +/* { dg-options "-mfp16-format=ieee" } */
26002 +/* { dg-add-options arm_neon_fp16 } */
26004 +#include "arm-fp16-ops.h"
26006 +/* We've specified options for hardware float, including fp16 support, so
26007 + we should not see any calls to libfuncs here. */
26008 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf2" } } */
26009 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf3" } } */
26010 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
26011 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */
26012 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */
26014 +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c
26016 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
26017 +/* { dg-do compile { target arm*-*-* } } */
26018 +/* { dg-require-effective-target arm_neon_fp16_ok } */
26019 +/* { dg-options "-mfp16-format=ieee -ffast-math" } */
26020 +/* { dg-add-options arm_neon_fp16 } */
26022 +#include "arm-fp16-ops.h"
26024 +/* We've specified options for hardware float, including fp16 support, so
26025 + we should not see any calls to libfuncs here. */
26026 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf2" } } */
26027 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf3" } } */
26028 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
26029 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_h2f_ieee" } } */
26030 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_f2h_ieee" } } */
26032 +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-7.c
26034 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
26035 +/* { dg-do compile { target arm*-*-* } } */
26036 +/* { dg-require-effective-target arm_neon_ok } */
26037 +/* { dg-options "-mfp16-format=ieee" } */
26038 +/* { dg-add-options arm_neon } */
26040 +#include "arm-fp16-ops.h"
26042 +/* We've specified options for hardware float, so we should not see any
26043 + calls to libfuncs here except for those to the conversion functions. */
26044 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf2" } } */
26045 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf3" } } */
26046 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
26048 +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-ops-8.c
26050 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
26051 +/* { dg-do compile { target arm*-*-* } } */
26052 +/* { dg-require-effective-target arm_neon_ok } */
26053 +/* { dg-options "-mfp16-format=ieee -ffast-math" } */
26054 +/* { dg-add-options arm_neon } */
26056 +#include "arm-fp16-ops.h"
26058 +/* We've specified options for hardware float, so we should not see any
26059 + calls to libfuncs here except for those to the conversion functions. */
26060 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf2" } } */
26061 +/* { dg-final { scan-assembler-not "\tbl\t__.*hf3" } } */
26062 +/* { dg-final { scan-assembler-not "\tbl\t__gnu_h\[a-z\]*_ieee" } } */
26064 +++ b/gcc/testsuite/gcc.dg/torture/arm-fp16-ops.h
26066 +/* Test various operators on __fp16 and mixed __fp16/float operands. */
26068 +#include <assert.h>
26070 +#define CHECK(e,r) assert ((e) == r)
26071 +#define CHECK2(e,r) (assert ((e) == r), temp = (e), assert (temp == r))
26072 +#define TEST(e) assert (e)
26073 +#define TESTNOT(e) assert (!(e))
26075 +volatile __fp16 h0 = 0.0;
26076 +volatile __fp16 h1 = 1.0;
26077 +volatile __fp16 h42 = 42.0;
26078 +volatile __fp16 hm2 = -2.0;
26079 +volatile __fp16 temp;
26081 +volatile float f0 = 0.0;
26082 +volatile float f1 = 1.0;
26083 +volatile float f42 = 42.0;
26084 +volatile float fm2 = -2.0;
26093 + CHECK2 (-h1, -1.0);
26094 + CHECK2 (+h1, 1.0);
26096 + CHECK (h1++, 1.0);
26098 + CHECK (++h1, 3.0);
26101 + CHECK (--h1, 2.0);
26103 + CHECK (h1--, 2.0);
26106 + CHECK2 (h42 * hm2, -84.0);
26107 + CHECK2 (h42 * (__fp16) -2.0, -84.0);
26108 + CHECK2 (h42 * fm2, -84.0);
26109 + CHECK2 (f42 * hm2, -84.0);
26111 + CHECK2 (h42 / hm2, -21.0);
26112 + CHECK2 (h42 / (__fp16) -2.0, -21.0);
26113 + CHECK2 (h42 / fm2, -21.0);
26114 + CHECK2 (f42 / hm2, -21.0);
26116 + CHECK2 (hm2 + h42, 40.0);
26117 + CHECK2 ((__fp16)-2.0 + h42, 40.0);
26118 + CHECK2 (hm2 + f42, 40.0);
26119 + CHECK2 (fm2 + h42, 40.0);
26121 + CHECK2 (hm2 - h42, -44.0);
26122 + CHECK2 ((__fp16)-2.0 - h42, -44.0);
26123 + CHECK2 (hm2 - f42, -44.0);
26124 + CHECK2 (fm2 - h42, -44.0);
26126 + TEST (hm2 < h42);
26127 + TEST (hm2 < (__fp16)42.0);
26128 + TEST (hm2 < f42);
26129 + TEST (fm2 < h42);
26131 + TEST (h42 > hm2);
26132 + TEST ((__fp16)42.0 > hm2);
26133 + TEST (h42 > fm2);
26134 + TEST (f42 > hm2);
26136 + TEST (hm2 <= h42);
26137 + TEST (hm2 <= (__fp16)42.0);
26138 + TEST (hm2 <= f42);
26139 + TEST (fm2 <= h42);
26141 + TEST (h42 >= hm2);
26142 + TEST (h42 >= (__fp16)-2.0);
26143 + TEST (h42 >= fm2);
26144 + TEST (f42 >= hm2);
26146 + TESTNOT (h1 == hm2);
26148 + TEST (h1 == (__fp16)1.0);
26152 + TEST (h1 != hm2);
26153 + TESTNOT (h1 != h1);
26154 + TESTNOT (h1 != (__fp16)1.0);
26155 + TESTNOT (h1 != f1);
26156 + TESTNOT (f1 != h1);
26158 + CHECK2 ((h1 ? hm2 : h42), -2.0);
26159 + CHECK2 ((h0 ? hm2 : h42), 42.0);
26161 + CHECK (h0 = h42, 42.0);
26162 + CHECK (h0, 42.0);
26163 + CHECK (h0 = (__fp16)-2.0, -2.0);
26164 + CHECK (h0, -2.0);
26165 + CHECK (h0 = f0, 0.0);
26168 + CHECK (h0 += h1, 1.0);
26170 + CHECK (h0 += (__fp16)1.0, 2.0);
26172 + CHECK (h0 += fm2, 0.0);
26175 + CHECK (h0 -= h1, -1.0);
26176 + CHECK (h0, -1.0);
26177 + CHECK (h0 -= (__fp16)1.0, -2.0);
26178 + CHECK (h0, -2.0);
26179 + CHECK (h0 -= fm2, 0.0);
26183 + CHECK (h0 *= hm2, 4.0);
26185 + CHECK (h0 *= (__fp16)-2.0, -8.0);
26186 + CHECK (h0, -8.0);
26187 + CHECK (h0 *= fm2, 16.0);
26188 + CHECK (h0, 16.0);
26190 + CHECK (h0 /= hm2, -8.0);
26191 + CHECK (h0, -8.0);
26192 + CHECK (h0 /= (__fp16)-2.0, 4.0);
26194 + CHECK (h0 /= fm2, -2.0);
26195 + CHECK (h0, -2.0);
26197 + CHECK ((h0, h1), 1.0);
26201 --- a/gcc/testsuite/gcc.dg/torture/type-generic-1.c
26202 +++ b/gcc/testsuite/gcc.dg/torture/type-generic-1.c
26205 /* { dg-do run } */
26206 /* { dg-options "-mieee" { target alpha*-*-* sh*-*-* } } */
26207 +/* { dg-options "-Wl,--defsym=__cs3_mips_float_type=2 -lcs3-mips-cp1 -lcs3-mips-fpemu" { target mips*-*sde*-* } } */
26208 /* { dg-skip-if "No Inf/NaN support" { spu-*-* } } */
26210 #include "../tg-tests.h"
26211 --- a/gcc/testsuite/gcc.dg/tree-ssa/pr21559.c
26212 +++ b/gcc/testsuite/gcc.dg/tree-ssa/pr21559.c
26214 /* { dg-do compile } */
26215 -/* { dg-options "-O2 -fdump-tree-vrp1-details" } */
26216 +/* { dg-options "-O2 -fdump-tree-vrp1-details -fno-remove-local-statics" } */
26218 static int blocksize = 4096;
26220 --- a/gcc/testsuite/gcc.dg/tree-ssa/prefetch-7.c
26221 +++ b/gcc/testsuite/gcc.dg/tree-ssa/prefetch-7.c
26223 /* { dg-do compile { target i?86-*-* x86_64-*-* } } */
26224 /* { dg-require-effective-target ilp32 } */
26225 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=athlon" } } */
26226 /* { dg-options "-O2 -fprefetch-loop-arrays -march=athlon -msse2 -mfpmath=sse --param simultaneous-prefetches=100 --param max-unrolled-insns=1 -fdump-tree-aprefetch-details -fdump-tree-final_cleanup" } */
26229 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-6.c
26230 +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dse-6.c
26232 /* { dg-do compile } */
26233 -/* { dg-options "-O2 -fdump-tree-dse1" } */
26234 +/* { dg-options "-O2 -fdump-tree-dse1 -fno-remove-local-statics" } */
26239 +++ b/gcc/testsuite/gcc.dg/vect/aligned-section-anchors-nest-1.c
26241 +/* { dg-do compile } */
26242 +/* { dg-require-effective-target section_anchors } */
26243 +/* { dg-require-effective-target vect_int } */
26245 +#include <stdarg.h>
26246 +#include "tree-vect.h"
26250 +static int a[N][N];
26251 +static int b[N][N];
26252 +static int c[N][N];
26254 +void clobber(int *);
26261 + clobber (&a[0][0]);
26262 + clobber (&b[0][0]);
26263 + clobber (&c[0][0]);
26265 + for (i = 0; i < N; i++) {
26266 + for (j = 0; j < N; j++) {
26267 + c[j][i] += a[j][i] + c[j][i];
26273 +/* { dg-final { scan-ipa-dump-times "Increasing alignment of decl" 3 "increase_alignment" } } */
26274 +/* { dg-final { cleanup-ipa-dump "increase_alignment" } } */
26275 --- a/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-31.c
26276 +++ b/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-31.c
26277 @@ -88,5 +88,5 @@ int main (void)
26279 /* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" } } */
26280 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26281 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" } } */
26282 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { target { ! vect_element_align } } } } */
26283 /* { dg-final { cleanup-tree-dump "vect" } } */
26284 --- a/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-64.c
26285 +++ b/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-64.c
26286 @@ -84,5 +84,5 @@ int main (void)
26288 /* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" } } */
26289 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26290 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" } } */
26291 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { target { ! vect_element_align } } } } */
26292 /* { dg-final { cleanup-tree-dump "vect" } } */
26293 --- a/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-66.c
26294 +++ b/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-66.c
26295 @@ -79,5 +79,5 @@ int main (void)
26297 /* { dg-final { scan-tree-dump-times "vectorized 3 loops" 1 "vect" } } */
26298 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26299 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" } } */
26300 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { target { ! vect_element_align } } } } */
26301 /* { dg-final { cleanup-tree-dump "vect" } } */
26302 --- a/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-68.c
26303 +++ b/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-68.c
26304 @@ -88,5 +88,5 @@ int main (void)
26306 /* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" } } */
26307 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26308 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" } } */
26309 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { target { ! vect_element_align } } } } */
26310 /* { dg-final { cleanup-tree-dump "vect" } } */
26311 --- a/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-69.c
26312 +++ b/gcc/testsuite/gcc.dg/vect/no-section-anchors-vect-69.c
26313 @@ -114,7 +114,7 @@ int main (void)
26315 /* { dg-final { scan-tree-dump-times "vectorized 4 loops" 1 "vect" } } */
26316 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26317 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail {! vector_alignment_reachable} } } } */
26318 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail { vect_element_align || {! vector_alignment_reachable} } } } } */
26319 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" { target {! vector_alignment_reachable} } } } */
26320 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { target {! vector_alignment_reachable} } } } */
26321 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { target { { ! vector_alignment_reachable } && { ! vect_element_align } } } } } */
26322 /* { dg-final { cleanup-tree-dump "vect" } } */
26323 --- a/gcc/testsuite/gcc.dg/vect/section-anchors-vect-69.c
26324 +++ b/gcc/testsuite/gcc.dg/vect/section-anchors-vect-69.c
26325 @@ -115,6 +115,6 @@ int main (void)
26326 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26327 /* Alignment forced using versioning until the pass that increases alignment
26328 is extended to handle structs. */
26329 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 4 "vect" { target {vect_int && vector_alignment_reachable } } } } */
26330 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 4 "vect" { target { {vect_int && vector_alignment_reachable } && { ! vect_element_align } } } } } */
26331 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 4 "vect" { target {vect_int && {! vector_alignment_reachable} } } } } */
26332 /* { dg-final { cleanup-tree-dump "vect" } } */
26333 --- a/gcc/testsuite/gcc.dg/vect/slp-25.c
26334 +++ b/gcc/testsuite/gcc.dg/vect/slp-25.c
26335 @@ -56,5 +56,5 @@ int main (void)
26337 /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
26338 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26339 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail vect_no_align } } } */
26340 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26341 /* { dg-final { cleanup-tree-dump "vect" } } */
26342 --- a/gcc/testsuite/gcc.dg/vect/vect-109.c
26343 +++ b/gcc/testsuite/gcc.dg/vect/vect-109.c
26344 @@ -73,6 +73,6 @@ int main (void)
26347 /* { dg-final { scan-tree-dump-times "vectorized 0 loops" 2 "vect" } } */
26348 -/* { dg-final { scan-tree-dump-times "not vectorized: unsupported unaligned store" 2 "vect" } } */
26349 +/* { dg-final { scan-tree-dump-times "not vectorized: unsupported unaligned store" 2 "vect" { target { ! vect_element_align } } } } */
26350 /* { dg-final { cleanup-tree-dump "vect" } } */
26352 --- a/gcc/testsuite/gcc.dg/vect/vect-26.c
26353 +++ b/gcc/testsuite/gcc.dg/vect/vect-26.c
26354 @@ -37,5 +37,5 @@ int main (void)
26356 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26357 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26358 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" } } */
26359 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { target { ! vect_element_align } } } } */
26360 /* { dg-final { cleanup-tree-dump "vect" } } */
26361 --- a/gcc/testsuite/gcc.dg/vect/vect-27.c
26362 +++ b/gcc/testsuite/gcc.dg/vect/vect-27.c
26363 @@ -45,6 +45,6 @@ int main (void)
26364 /* The initialization induction loop (with aligned access) is also vectorized. */
26365 /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { xfail vect_no_align } } } */
26366 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target vect_no_align } } } */
26367 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail vect_no_align } } } */
26368 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" } } */
26369 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26370 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" { target { ! vect_element_align } } } } */
26371 /* { dg-final { cleanup-tree-dump "vect" } } */
26372 --- a/gcc/testsuite/gcc.dg/vect/vect-28.c
26373 +++ b/gcc/testsuite/gcc.dg/vect/vect-28.c
26374 @@ -40,6 +40,6 @@ int main (void)
26376 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26377 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26378 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { target vector_alignment_reachable } } } */
26379 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { target { vector_alignment_reachable && { ! vect_element_align } } } } } */
26380 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" { target { ! vector_alignment_reachable } } } } */
26381 /* { dg-final { cleanup-tree-dump "vect" } } */
26382 --- a/gcc/testsuite/gcc.dg/vect/vect-29.c
26383 +++ b/gcc/testsuite/gcc.dg/vect/vect-29.c
26384 @@ -50,7 +50,7 @@ int main (void)
26386 /* The initialization induction loop (with aligned access) is also vectorized. */
26387 /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" } } */
26388 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail vect_no_align } } } */
26389 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" } } */
26390 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26391 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" { target { ! vect_element_align } } } } */
26392 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning." 1 "vect" {target vect_no_align } } } */
26393 /* { dg-final { cleanup-tree-dump "vect" } } */
26394 --- a/gcc/testsuite/gcc.dg/vect/vect-33.c
26395 +++ b/gcc/testsuite/gcc.dg/vect/vect-33.c
26396 @@ -39,6 +39,6 @@ int main (void)
26398 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26399 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26400 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { target vector_alignment_reachable } } } */
26401 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { target { vector_alignment_reachable && { ! vect_element_align } } } } } */
26402 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" { target { ! vector_alignment_reachable } } } } */
26403 /* { dg-final { cleanup-tree-dump "vect" } } */
26404 --- a/gcc/testsuite/gcc.dg/vect/vect-42.c
26405 +++ b/gcc/testsuite/gcc.dg/vect/vect-42.c
26406 @@ -57,6 +57,6 @@ int main (void)
26408 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26409 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" { target { vect_no_align || { ! vector_alignment_reachable } } } } } */
26410 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || { ! vector_alignment_reachable } } } } } */
26411 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail {vect_no_align || { ! vector_alignment_reachable } } } } } */
26412 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { { vect_no_align || vect_element_align } || { ! vector_alignment_reachable } } } } } */
26413 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { { vect_no_align || vect_element_align } || { ! vector_alignment_reachable } } } } } */
26414 /* { dg-final { cleanup-tree-dump "vect" } } */
26415 --- a/gcc/testsuite/gcc.dg/vect/vect-44.c
26416 +++ b/gcc/testsuite/gcc.dg/vect/vect-44.c
26417 @@ -65,8 +65,8 @@ int main (void)
26418 two loads to be aligned). */
26420 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26421 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail vect_no_align } } } */
26422 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || {! vector_alignment_reachable} } } } } */
26423 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26424 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { { vect_no_align || vect_element_align } || {! vector_alignment_reachable} } } } } */
26425 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning." 3 "vect" { target vect_no_align } } } */
26426 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning." 1 "vect" { target { {! vector_alignment_reachable} && {! vect_no_align} } } } } */
26427 /* { dg-final { cleanup-tree-dump "vect" } } */
26428 --- a/gcc/testsuite/gcc.dg/vect/vect-48.c
26429 +++ b/gcc/testsuite/gcc.dg/vect/vect-48.c
26430 @@ -54,7 +54,7 @@ int main (void)
26431 (The store is aligned). */
26433 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26434 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail vect_no_align } } } */
26435 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" } } */
26436 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26437 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" { target { ! vect_element_align } } } } */
26438 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning." 2 "vect" { target vect_no_align } } } */
26439 /* { dg-final { cleanup-tree-dump "vect" } } */
26440 --- a/gcc/testsuite/gcc.dg/vect/vect-50.c
26441 +++ b/gcc/testsuite/gcc.dg/vect/vect-50.c
26442 @@ -61,8 +61,8 @@ int main (void)
26443 two loads to be aligned). */
26445 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26446 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail vect_no_align } } } */
26447 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || {! vector_alignment_reachable} } } } } */
26448 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26449 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { { vect_no_align || vect_element_align } || {! vector_alignment_reachable} } } } } */
26450 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning." 3 "vect" { target vect_no_align } } } */
26451 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning." 1 "vect" { target { {! vector_alignment_reachable} && {! vect_no_align} } } } } */
26452 /* { dg-final { cleanup-tree-dump "vect" } } */
26453 --- a/gcc/testsuite/gcc.dg/vect/vect-52.c
26454 +++ b/gcc/testsuite/gcc.dg/vect/vect-52.c
26455 @@ -55,7 +55,7 @@ int main (void)
26456 (The store is aligned). */
26458 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26459 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail vect_no_align } } } */
26460 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" } } */
26461 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26462 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" { target { ! vect_element_align } } } } */
26463 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning." 2 "vect" { target vect_no_align } } } */
26464 /* { dg-final { cleanup-tree-dump "vect" } } */
26465 --- a/gcc/testsuite/gcc.dg/vect/vect-54.c
26466 +++ b/gcc/testsuite/gcc.dg/vect/vect-54.c
26467 @@ -59,5 +59,5 @@ int main (void)
26469 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26470 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26471 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" } } */
26472 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { target { ! vect_element_align } } } } */
26473 /* { dg-final { cleanup-tree-dump "vect" } } */
26474 --- a/gcc/testsuite/gcc.dg/vect/vect-56.c
26475 +++ b/gcc/testsuite/gcc.dg/vect/vect-56.c
26476 @@ -67,6 +67,6 @@ int main (void)
26479 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail vect_no_align } } } */
26480 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail vect_no_align } } } */
26481 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" } } */
26482 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26483 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" { target { ! vect_element_align } } } } */
26484 /* { dg-final { cleanup-tree-dump "vect" } } */
26485 --- a/gcc/testsuite/gcc.dg/vect/vect-58.c
26486 +++ b/gcc/testsuite/gcc.dg/vect/vect-58.c
26487 @@ -58,5 +58,5 @@ int main (void)
26489 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26490 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26491 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" } } */
26492 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { target { ! vect_element_align } } } } */
26493 /* { dg-final { cleanup-tree-dump "vect" } } */
26494 --- a/gcc/testsuite/gcc.dg/vect/vect-60.c
26495 +++ b/gcc/testsuite/gcc.dg/vect/vect-60.c
26496 @@ -68,6 +68,6 @@ int main (void)
26499 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail vect_no_align } } } */
26500 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail vect_no_align } } } */
26501 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" } } */
26502 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26503 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" { target { ! vect_element_align } } } } */
26504 /* { dg-final { cleanup-tree-dump "vect" } } */
26505 --- a/gcc/testsuite/gcc.dg/vect/vect-70.c
26506 +++ b/gcc/testsuite/gcc.dg/vect/vect-70.c
26507 @@ -64,6 +64,6 @@ int main (void)
26509 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26510 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26511 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" {target vector_alignment_reachable } } } */
26512 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" {target { vector_alignment_reachable && { ! vect_element_align } } } } } */
26513 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" {target {! vector_alignment_reachable} } } } */
26514 /* { dg-final { cleanup-tree-dump "vect" } } */
26515 --- a/gcc/testsuite/gcc.dg/vect/vect-72.c
26516 +++ b/gcc/testsuite/gcc.dg/vect/vect-72.c
26517 @@ -46,6 +46,6 @@ int main (void)
26520 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail vect_no_align } } } */
26521 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail vect_no_align } } } */
26522 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" } } */
26523 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26524 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" { target { ! vect_element_align } } } } */
26525 /* { dg-final { cleanup-tree-dump "vect" } } */
26526 --- a/gcc/testsuite/gcc.dg/vect/vect-75.c
26527 +++ b/gcc/testsuite/gcc.dg/vect/vect-75.c
26528 @@ -45,5 +45,5 @@ int main (void)
26530 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26531 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" { target vect_no_align } } } */
26532 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail vect_no_align } } } */
26533 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26534 /* { dg-final { cleanup-tree-dump "vect" } } */
26535 --- a/gcc/testsuite/gcc.dg/vect/vect-87.c
26536 +++ b/gcc/testsuite/gcc.dg/vect/vect-87.c
26537 @@ -51,6 +51,6 @@ int main (void)
26538 /* Fails for targets that don't vectorize PLUS (e.g alpha). */
26539 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26540 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26541 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" {target vector_alignment_reachable } } } */
26542 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" {target { vector_alignment_reachable && { ! vect_element_align } } } } } */
26543 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" {target {! vector_alignment_reachable} } } } */
26544 /* { dg-final { cleanup-tree-dump "vect" } } */
26545 --- a/gcc/testsuite/gcc.dg/vect/vect-88.c
26546 +++ b/gcc/testsuite/gcc.dg/vect/vect-88.c
26547 @@ -51,6 +51,6 @@ int main (void)
26548 /* Fails for targets that don't vectorize PLUS (e.g alpha). */
26549 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26550 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26551 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" {target vector_alignment_reachable } } } */
26552 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" {target { vector_alignment_reachable && { ! vect_element_align } } } } } */
26553 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" {target {! vector_alignment_reachable} } } } */
26554 /* { dg-final { cleanup-tree-dump "vect" } } */
26555 --- a/gcc/testsuite/gcc.dg/vect/vect-89.c
26556 +++ b/gcc/testsuite/gcc.dg/vect/vect-89.c
26557 @@ -46,5 +46,5 @@ int main (void)
26559 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26560 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26561 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" } } */
26562 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { target { ! vect_element_align } } } } */
26563 /* { dg-final { cleanup-tree-dump "vect" } } */
26564 --- a/gcc/testsuite/gcc.dg/vect/vect-91.c
26565 +++ b/gcc/testsuite/gcc.dg/vect/vect-91.c
26566 @@ -59,6 +59,6 @@ main3 ()
26568 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 3 "vect" { xfail vect_no_int_add } } } */
26569 /* { dg-final { scan-tree-dump-times "accesses have the same alignment." 3 "vect" } } */
26570 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 3 "vect" {target vector_alignment_reachable } } } */
26571 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 3 "vect" {target { vector_alignment_reachable && { ! vect_element_align } } } } } */
26572 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 3 "vect" {target {! vector_alignment_reachable} } } } */
26573 /* { dg-final { cleanup-tree-dump "vect" } } */
26574 --- a/gcc/testsuite/gcc.dg/vect/vect-92.c
26575 +++ b/gcc/testsuite/gcc.dg/vect/vect-92.c
26576 @@ -92,5 +92,5 @@ int main (void)
26578 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 3 "vect" } } */
26579 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" } } */
26580 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 3 "vect" } } */
26581 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 3 "vect" { target { ! vect_element_align } } } } */
26582 /* { dg-final { cleanup-tree-dump "vect" } } */
26583 --- a/gcc/testsuite/gcc.dg/vect/vect-93.c
26584 +++ b/gcc/testsuite/gcc.dg/vect/vect-93.c
26585 @@ -72,7 +72,7 @@ int main (void)
26586 /* main && main1 together: */
26587 /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 2 "vect" { target powerpc*-*-* i?86-*-* x86_64-*-* } } } */
26588 /* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { target { vect_no_align && {! vector_alignment_reachable} } } } } */
26589 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 3 "vect" { xfail { vect_no_align || {! vector_alignment_reachable} } } } } */
26590 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 3 "vect" { xfail { { vect_no_align || vect_element_align } || {! vector_alignment_reachable} } } } } */
26593 /* { dg-final { scan-tree-dump-times "vectorized 2 loops" 1 "vect" { target !powerpc*-*-* !i?86-*-* !x86_64-*-* } } } */
26594 @@ -80,6 +80,6 @@ int main (void)
26597 /* { dg-final { scan-tree-dump-times "vectorized 0 loops" 1 "vect" { target vect_no_align } } } */
26598 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail vect_no_align } } } */
26599 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26601 /* { dg-final { cleanup-tree-dump "vect" } } */
26602 --- a/gcc/testsuite/gcc.dg/vect/vect-95.c
26603 +++ b/gcc/testsuite/gcc.dg/vect/vect-95.c
26604 @@ -62,8 +62,8 @@ int main (void)
26605 stores and generate misaligned accesses for the loads. For targets that
26606 don't support unaligned loads we version for all four accesses. */
26608 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail vect_no_align } } } */
26609 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 2 "vect" { xfail vect_no_align } } } */
26610 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26611 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26612 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 0 "vect" { target vect_no_align } } } */
26613 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 4 "vect" { target vect_no_align } } } */
26614 /* { dg-final { cleanup-tree-dump "vect" } } */
26615 --- a/gcc/testsuite/gcc.dg/vect/vect-align-2.c
26616 +++ b/gcc/testsuite/gcc.dg/vect/vect-align-2.c
26617 @@ -43,6 +43,6 @@ int main (void)
26620 /* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" } } */
26621 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" } } */
26622 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 1 "vect" { target { ! vect_element_align } } } } */
26623 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26624 /* { dg-final { cleanup-tree-dump "vect" } } */
26625 --- a/gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c
26626 +++ b/gcc/testsuite/gcc.dg/vect/vect-multitypes-1.c
26627 @@ -78,11 +78,11 @@ int main (void)
26631 -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail *-*-* } } } */
26632 -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail vect_no_align } } } */
26633 +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail { ! vect_element_align } } } } */
26634 +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26635 /* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail *-*-* } } } */
26636 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail vect_no_align } } } */
26637 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26638 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail *-*-* } } } */
26639 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail vect_no_align } } } */
26640 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26641 /* { dg-final { cleanup-tree-dump "vect" } } */
26643 --- a/gcc/testsuite/gcc.dg/vect/vect-multitypes-3.c
26644 +++ b/gcc/testsuite/gcc.dg/vect/vect-multitypes-3.c
26645 @@ -54,6 +54,6 @@ int main (void)
26647 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26648 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 3 "vect" { target vect_no_align } } } */
26649 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 3 "vect" {xfail vect_no_align } } } */
26650 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 3 "vect" {xfail { vect_no_align || vect_element_align } } } } */
26651 /* { dg-final { cleanup-tree-dump "vect" } } */
26653 --- a/gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c
26654 +++ b/gcc/testsuite/gcc.dg/vect/vect-multitypes-4.c
26655 @@ -85,11 +85,11 @@ int main (void)
26659 -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail *-*-* } } } */
26660 -/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail vect_no_align } } } */
26661 +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" { xfail { ! vect_element_align } } } } */
26662 +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26663 /* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 2 "vect" { xfail *-*-* } } } */
26664 -/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail vect_no_align } } } */
26665 +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26666 /* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 8 "vect" { xfail *-*-* } } } */
26667 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail vect_no_align } } } */
26668 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" { xfail { vect_no_align || vect_element_align } } } } */
26669 /* { dg-final { cleanup-tree-dump "vect" } } */
26671 --- a/gcc/testsuite/gcc.dg/vect/vect-multitypes-6.c
26672 +++ b/gcc/testsuite/gcc.dg/vect/vect-multitypes-6.c
26673 @@ -61,6 +61,6 @@ int main (void)
26675 /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail { sparc*-*-* && ilp32 } }} } */
26676 /* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 6 "vect" { target vect_no_align } } } */
26677 -/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 6 "vect" {xfail vect_no_align } } } */
26678 +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 6 "vect" {xfail { vect_no_align || vect_element_align } } } } */
26679 /* { dg-final { cleanup-tree-dump "vect" } } */
26682 +++ b/gcc/testsuite/gcc.dg/vect/vect-shift-2.c
26684 +/* { dg-require-effective-target vect_shift_char } */
26685 +/* { dg-require-effective-target vect_int } */
26687 +#include "tree-vect.h"
26691 +unsigned char dst[N] __attribute__((aligned(N)));
26692 +unsigned char src[N] __attribute__((aligned(N)));
26694 +__attribute__ ((noinline))
26695 +void array_shift(void)
26698 + for (i = 0; i < N; i++)
26699 + dst[i] = src[i] >> 3;
26707 + for (i = 0; i < N; i++)
26712 + for (i = 0; i < N; i++)
26719 +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26720 +/* { dg-final { cleanup-tree-dump "vect" } } */
26722 +++ b/gcc/testsuite/gcc.dg/vect/vect-shift-3.c
26724 +/* { dg-require-effective-target vect_shift } */
26725 +/* { dg-require-effective-target vect_int } */
26727 +#include "tree-vect.h"
26731 +unsigned short dst[N] __attribute__((aligned(N)));
26732 +unsigned short src[N] __attribute__((aligned(N)));
26734 +__attribute__ ((noinline))
26735 +void array_shift(void)
26738 + for (i = 0; i < N; i++)
26739 + dst[i] = src[i] >> 3;
26747 + for (i = 0; i < N; i++)
26752 + for (i = 0; i < N; i++)
26759 +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
26760 +/* { dg-final { cleanup-tree-dump "vect" } } */
26761 --- a/gcc/testsuite/gcc.dg/vect/vect.exp
26762 +++ b/gcc/testsuite/gcc.dg/vect/vect.exp
26763 @@ -97,7 +97,7 @@ if [istarget "powerpc-*paired*"] {
26764 } elseif [istarget "ia64-*-*"] {
26765 set dg-do-what-default run
26766 } elseif [is-effective-target arm_neon_ok] {
26767 - lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp"
26768 + eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
26769 if [is-effective-target arm_neon_hw] {
26770 set dg-do-what-default run
26772 @@ -183,6 +183,12 @@ lappend DEFAULT_VECTCFLAGS "-fsection-an
26773 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/section-anchors-*.\[cS\]]] \
26774 "" $DEFAULT_VECTCFLAGS
26776 +# alignment-sensitive -fsection-anchors tests
26777 +set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS
26778 +lappend DEFAULT_VECTCFLAGS "-fsection-anchors" "-fdump-ipa-increase_alignment"
26779 +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/aligned-section-anchors-*.\[cS\]]] \
26780 + "" $DEFAULT_VECTCFLAGS
26782 # -fno-section-anchors tests
26783 set DEFAULT_VECTCFLAGS $SAVED_DEFAULT_VECTCFLAGS
26784 lappend DEFAULT_VECTCFLAGS "-fno-section-anchors"
26785 --- a/gcc/testsuite/gcc.dg/vmx/vmx.exp
26786 +++ b/gcc/testsuite/gcc.dg/vmx/vmx.exp
26787 @@ -31,7 +31,7 @@ if {![istarget powerpc*-*-*]
26788 # nothing but extensions.
26789 global DEFAULT_VMXCFLAGS
26790 if ![info exists DEFAULT_VMXCFLAGS] then {
26791 - set DEFAULT_VMXCFLAGS "-maltivec -mabi=altivec -std=gnu99"
26792 + set DEFAULT_VMXCFLAGS "-maltivec -std=gnu99"
26795 # If the target system supports AltiVec instructions, the default action
26796 --- a/gcc/testsuite/gcc.misc-tests/i386-prefetch.exp
26797 +++ b/gcc/testsuite/gcc.misc-tests/i386-prefetch.exp
26798 @@ -90,6 +90,13 @@ load_lib torture-options.exp
26802 +if { [board_info target exists multilib_flags]
26803 + && [string match "* -march=*" " [board_info target multilib_flags] "] } {
26804 + # Multilib flags come after the -march flags we pass and override
26805 + # them, so skip these tests when such flags are passed.
26809 set-torture-options $PREFETCH_NONE
26810 gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/i386-pf-none-*.c]] ""
26813 +++ b/gcc/testsuite/gcc.target/arm/aapcs/aapcs.exp
26815 +# Copyright (C) 1997, 2004, 2006, 2007 Free Software Foundation, Inc.
26817 +# This program is free software; you can redistribute it and/or modify
26818 +# it under the terms of the GNU General Public License as published by
26819 +# the Free Software Foundation; either version 3 of the License, or
26820 +# (at your option) any later version.
26822 +# This program is distributed in the hope that it will be useful,
26823 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
26824 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26825 +# GNU General Public License for more details.
26827 +# You should have received a copy of the GNU General Public License
26828 +# along with GCC; see the file COPYING3. If not see
26829 +# <http://www.gnu.org/licenses/>.
26831 +# GCC testsuite that uses the `dg.exp' driver.
26833 +# Exit immediately if this isn't an ARM target.
26834 +if ![istarget arm*-*-*] then {
26838 +# Load support procs.
26839 +load_lib gcc-dg.exp
26841 +# Initialize `dg'.
26845 +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
26851 +++ b/gcc/testsuite/gcc.target/arm/aapcs/abitest.h
26853 +#define IN_FRAMEWORK
26900 +extern void abort (void);
26902 +__attribute__((naked)) void dumpregs () __asm("myfunc");
26903 +__attribute__((naked)) void dumpregs ()
26907 + "stmfd sp!, {r0-r3}\n\t"
26909 + "fstmdbs sp!, {s0-s15}\n\t"
26910 + "fstmdbd sp!, {d0-d7}\n\t"
26913 + "stmfd sp!, {ip, r14}\n\t"
26914 + "bl testfunc\n\t"
26915 + "ldmfd sp!, {r0, r14}\n\t"
26921 +#define LAST_ARG(type,val,offset) { type __x = val; if (memcmp(&__x, stack+offset, sizeof(type)) != 0) abort(); }
26922 +#define ARG(type,val,offset) LAST_ARG(type, val, offset)
26923 +#define ANON(type,val,offset) LAST_ARG(type, val, offset)
26924 +#define LAST_ANON(type,val,offset) LAST_ARG(type, val, offset)
26927 +void testfunc(char* stack)
26938 +#define LAST_ARG(type,val,offset) type
26939 +#define ARG(type,val,offset) LAST_ARG(type, val, offset),
26941 +#define ANON(type,val, offset)
26942 +#define LAST_ANON(type,val, offset)
26944 +#ifndef MYFUNCTYPE
26945 +#define MYFUNCTYPE void
26948 +MYFUNCTYPE myfunc(
26957 +#define LAST_ARG(type,val,offset) val
26958 +#define ARG(type,val,offset) LAST_ARG(type, val, offset),
26960 +#define LAST_ANON(type,val,offset) LAST_ARG(type, val, offset)
26961 +#define ANON(type,val,offset) LAST_ARG(type, val, offset),
26972 +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp1.c
26974 +/* Test AAPCS layout (VFP variant) */
26976 +/* { dg-do run { target arm*-*-eabi* } } */
26977 +/* { dg-require-effective-target arm_hard_vfp_ok } */
26978 +/* { dg-require-effective-target arm32 } */
26979 +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
26981 +#ifndef IN_FRAMEWORK
26983 +#define TESTFILE "vfp1.c"
26984 +#include "abitest.h"
26988 + ARG(double, 4.0, D0)
26989 + LAST_ARG(int, 3, R1)
26992 +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp10.c
26994 +/* Test AAPCS layout (VFP variant) */
26996 +/* { dg-do run { target arm*-*-eabi* } } */
26997 +/* { dg-require-effective-target arm_hard_vfp_ok } */
26998 +/* { dg-require-effective-target arm32 } */
26999 +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
27001 +#ifndef IN_FRAMEWORK
27003 +#define TESTFILE "vfp10.c"
27005 +__complex__ x = 1.0+2.0i;
27013 +} v = { 1, 2, 3, 4 };
27020 +struct z a = { 5.0, 6.0, 7.0, 8.0 };
27021 +struct z b = { 9.0, 10.0, 11.0, 12.0 };
27023 +#include "abitest.h"
27025 + /* A variadic function passes using the base ABI */
27026 + ARG(double, 11.0, R0)
27028 + ANON(struct z, a, R2)
27029 + ANON(struct z, b, STACK+24)
27030 + LAST_ANON(double, 0.5, STACK+56)
27033 +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp11.c
27035 +/* Test AAPCS layout (VFP variant) */
27037 +/* { dg-do run { target arm*-*-eabi* } } */
27038 +/* { dg-require-effective-target arm_hard_vfp_ok } */
27039 +/* { dg-require-effective-target arm32 } */
27040 +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
27042 +#ifndef IN_FRAMEWORK
27044 +#define TESTFILE "vfp11.c"
27046 +__complex__ x = 1.0+2.0i;
27054 +} v = { 1, 2, 3, 4 };
27061 +struct z a = { 5.0, 6.0, 7.0, 8.0 };
27062 +struct z b = { 9.0, 10.0, 11.0, 12.0 };
27064 +#define MYFUNCTYPE struct y
27066 +#include "abitest.h"
27069 + ARG(struct y, v, R2)
27070 + ARG(struct z, a, D0)
27071 + ARG(struct z, b, D4)
27072 + LAST_ARG(double, 0.5, STACK+8)
27075 +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp12.c
27077 +/* Test AAPCS layout (VFP variant) */
27079 +/* { dg-do run { target arm*-*-eabi* } } */
27080 +/* { dg-require-effective-target arm_hard_vfp_ok } */
27081 +/* { dg-require-effective-target arm32 } */
27082 +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
27084 +#ifndef IN_FRAMEWORK
27086 +#define TESTFILE "vfp12.c"
27088 +__complex__ x = 1.0+2.0i;
27096 +} v = { 1, 2, 3, 4 };
27103 +struct z a = { 5.0, 6.0, 7.0, 8.0 };
27104 +struct z b = { 9.0, 10.0, 11.0, 12.0 };
27106 +#include "abitest.h"
27109 + ARG(struct y, v, R1)
27110 + ARG(struct z, a, D0)
27111 + ARG(double, 1.0, D4)
27112 + ARG(struct z, b, STACK+8)
27113 + LAST_ARG(double, 0.5, STACK+40)
27116 +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp13.c
27118 +/* Test AAPCS layout (VFP variant) */
27120 +/* { dg-do run { target arm*-*-eabi* } } */
27121 +/* { dg-require-effective-target arm_hard_vfp_ok } */
27122 +/* { dg-require-effective-target arm32 } */
27123 +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
27125 +#ifndef IN_FRAMEWORK
27127 +#define TESTFILE "vfp13.c"
27129 +__complex__ x = 1.0+2.0i;
27137 +} v = { 1, 2, 3, 4 };
27144 +struct z a = { 5.0, 6.0, 7.0, 8.0 };
27145 +struct z b = { 9.0, 10.0, 11.0, 12.0 };
27147 +#include "abitest.h"
27151 + ARG(struct z, a, D0)
27152 + ARG(double, 1.0, D4)
27153 + ARG(struct z, b, STACK)
27155 + LAST_ARG(double, 0.5, STACK+32)
27158 +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp14.c
27160 +/* Test AAPCS layout (VFP variant) */
27162 +/* { dg-do run { target arm*-*-eabi* } } */
27163 +/* { dg-require-effective-target arm_hard_vfp_ok } */
27164 +/* { dg-require-effective-target arm32 } */
27165 +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
27167 +#ifndef IN_FRAMEWORK
27169 +#define TESTFILE "vfp14.c"
27171 +#include "abitest.h"
27173 + ARG(double, 1.0, D0)
27174 + ARG(double, 2.0, D1)
27175 + ARG(double, 3.0, D2)
27176 + ARG(double, 4.0, D3)
27177 + ARG(double, 5.0, D4)
27178 + ARG(double, 6.0, D5)
27179 + ARG(double, 7.0, D6)
27180 + ARG(double, 8.0, D7)
27181 + ARG(double, 9.0, STACK)
27182 + LAST_ARG(double, 10.0, STACK+8)
27185 +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp2.c
27187 +/* Test AAPCS layout (VFP variant) */
27189 +/* { dg-do run { target arm*-*-eabi* } } */
27190 +/* { dg-require-effective-target arm_hard_vfp_ok } */
27191 +/* { dg-require-effective-target arm32 } */
27192 +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
27194 +#ifndef IN_FRAMEWORK
27196 +#define TESTFILE "vfp2.c"
27197 +#include "abitest.h"
27200 + ARG(float, 1.0f, S0)
27201 + ARG(double, 4.0, D1)
27202 + ARG(float, 2.0f, S1)
27203 + ARG(double, 5.0, D2)
27204 + LAST_ARG(int, 3, R0)
27207 +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp3.c
27209 +/* Test AAPCS layout (VFP variant) */
27211 +/* { dg-do run { target arm*-*-eabi* } } */
27212 +/* { dg-require-effective-target arm_hard_vfp_ok } */
27213 +/* { dg-require-effective-target arm32 } */
27214 +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
27216 +#ifndef IN_FRAMEWORK
27218 +#define TESTFILE "vfp3.c"
27220 +__complex__ x = 1.0+2.0i;
27222 +#include "abitest.h"
27224 + ARG(float, 1.0f, S0)
27225 + ARG(__complex__ double, x, D1)
27226 + ARG(float, 2.0f, S1)
27227 + ARG(double, 5.0, D3)
27228 + LAST_ARG(int, 3, R0)
27231 +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp4.c
27233 +/* Test AAPCS layout (VFP variant) */
27235 +/* { dg-do run { target arm*-*-eabi* } } */
27236 +/* { dg-require-effective-target arm_hard_vfp_ok } */
27237 +/* { dg-require-effective-target arm32 } */
27238 +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
27240 +#ifndef IN_FRAMEWORK
27242 +#define TESTFILE "vfp4.c"
27244 +__complex__ float x = 1.0f + 2.0fi;
27245 +#include "abitest.h"
27247 + ARG(float, 1.0f, S0)
27248 + ARG(__complex__ float, x, S1)
27249 + ARG(float, 2.0f, S3)
27250 + ARG(double, 5.0, D2)
27251 + LAST_ARG(int, 3, R0)
27254 +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp5.c
27256 +/* Test AAPCS layout (VFP variant) */
27258 +/* { dg-do run { target arm*-*-eabi* } } */
27259 +/* { dg-require-effective-target arm_hard_vfp_ok } */
27260 +/* { dg-require-effective-target arm32 } */
27261 +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
27263 +#ifndef IN_FRAMEWORK
27265 +#define TESTFILE "vfp5.c"
27267 +__complex__ float x = 1.0+2.0i;
27275 +} v = { 1, 2, 3, 4 };
27277 +#include "abitest.h"
27279 + ARG(float, 1.0f, S0)
27280 + ARG(__complex__ float, x, S1)
27281 + ARG(float, 2.0f, S3)
27282 + ARG(double, 5.0, D2)
27283 + ARG(struct y, v, R0)
27284 + LAST_ARG(int, 3, STACK)
27287 +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp6.c
27289 +/* Test AAPCS layout (VFP variant) */
27291 +/* { dg-do run { target arm*-*-eabi* } } */
27292 +/* { dg-require-effective-target arm_hard_vfp_ok } */
27293 +/* { dg-require-effective-target arm32 } */
27294 +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
27296 +#ifndef IN_FRAMEWORK
27298 +#define TESTFILE "vfp6.c"
27300 +__complex__ float x = 1.0+2.0i;
27308 +} v = { 1, 2, 3, 4 };
27310 +#include "abitest.h"
27312 + ARG(struct y, v, R0)
27313 + ARG(float, 1.0f, S0)
27314 + ARG(__complex__ float, x, S1)
27315 + ARG(float, 2.0f, S3)
27316 + ARG(double, 5.0, D2)
27317 + LAST_ARG(int, 3, STACK)
27320 +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp7.c
27322 +/* Test AAPCS layout (VFP variant) */
27324 +/* { dg-do run { target arm*-*-eabi* } } */
27325 +/* { dg-require-effective-target arm_hard_vfp_ok } */
27326 +/* { dg-require-effective-target arm32 } */
27327 +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
27329 +#ifndef IN_FRAMEWORK
27331 +#define TESTFILE "vfp7.c"
27333 +__complex__ x = 1.0+2.0i;
27341 +} v = { 1, 2, 3, 4 };
27348 +struct z a = { 5.0, 6.0, 7.0, 8.0 };
27349 +struct z b = { 9.0, 10.0, 11.0, 12.0 };
27351 +#include "abitest.h"
27353 + ARG(struct z, a, D0)
27354 + ARG(struct z, b, D4)
27355 + ARG(double, 0.5, STACK)
27357 + LAST_ARG(struct y, v, STACK+8)
27360 +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp8.c
27362 +/* Test AAPCS layout (VFP variant) */
27364 +/* { dg-do run { target arm*-*-eabi* } } */
27365 +/* { dg-require-effective-target arm_hard_vfp_ok } */
27366 +/* { dg-require-effective-target arm32 } */
27367 +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
27369 +#ifndef IN_FRAMEWORK
27371 +#define TESTFILE "vfp8.c"
27373 +__complex__ x = 1.0+2.0i;
27381 +} v = { 1, 2, 3, 4 };
27388 +struct z a = { 5.0, 6.0, 7.0, 8.0 };
27389 +struct z b = { 9.0, 10.0, 11.0, 12.0 };
27391 +#include "abitest.h"
27394 + ARG(struct y, v, R1)
27395 + ARG(struct z, a, D0)
27396 + ARG(struct z, b, D4)
27397 + LAST_ARG(double, 0.5, STACK+8)
27400 +++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp9.c
27402 +/* Test AAPCS layout (VFP variant) */
27404 +/* { dg-do run { target arm*-*-eabi* } } */
27405 +/* { dg-require-effective-target arm_hard_vfp_ok } */
27406 +/* { dg-require-effective-target arm32 } */
27407 +/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard" } */
27409 +#ifndef IN_FRAMEWORK
27411 +#define TESTFILE "vfp9.c"
27413 +__complex__ x = 1.0+2.0i;
27421 +} v = { 1, 2, 3, 4 };
27428 +struct z a = { 5.0, 6.0, 7.0, 8.0 };
27429 +struct z b = { 9.0, 10.0, 11.0, 12.0 };
27431 +#include "abitest.h"
27433 + /* A variadic function passes using the base ABI */
27436 + ANON(struct z, a, R2)
27437 + ANON(struct z, b, STACK+24)
27438 + LAST_ANON(double, 0.5, STACK+56)
27441 +++ b/gcc/testsuite/gcc.target/arm/ctz.c
27443 +/* { dg-do compile } */
27444 +/* { dg-require-effective-target arm32 } */
27445 +/* { dg-options "-O2 -march=armv6t2" } */
27447 +unsigned int functest(unsigned int x)
27449 + return __builtin_ctz(x);
27452 +/* { dg-final { scan-assembler "rbit" } } */
27453 +/* { dg-final { scan-assembler "clz" } } */
27454 +/* { dg-final { scan-assembler-not "rsb" } } */
27455 --- a/gcc/testsuite/gcc.target/arm/eabi1.c
27456 +++ b/gcc/testsuite/gcc.target/arm/eabi1.c
27457 @@ -30,43 +30,48 @@
27458 #include <stdlib.h>
27461 -#define decl_float(code, type) \
27462 - extern type __aeabi_ ## code ## add (type, type); \
27463 - extern type __aeabi_ ## code ## div (type, type); \
27464 - extern type __aeabi_ ## code ## mul (type, type); \
27465 - extern type __aeabi_ ## code ## neg (type); \
27466 - extern type __aeabi_ ## code ## rsub (type, type); \
27467 - extern type __aeabi_ ## code ## sub (type, type); \
27468 - extern int __aeabi_ ## code ## cmpeq (type, type); \
27469 - extern int __aeabi_ ## code ## cmplt (type, type); \
27470 - extern int __aeabi_ ## code ## cmple (type, type); \
27471 - extern int __aeabi_ ## code ## cmpge (type, type); \
27472 - extern int __aeabi_ ## code ## cmpgt (type, type); \
27473 - extern int __aeabi_ ## code ## cmpun (type, type); \
27474 - extern int __aeabi_ ## code ## 2iz (type); \
27475 - extern unsigned int __aeabi_ ## code ## 2uiz (type); \
27476 - extern long long __aeabi_ ## code ## 2lz (type); \
27477 - extern unsigned long long __aeabi_ ## code ## 2ulz (type); \
27478 - extern type __aeabi_i2 ## code (int); \
27479 - extern type __aeabi_ui2 ## code (int); \
27480 - extern type __aeabi_l2 ## code (long long); \
27481 - extern type __aeabi_ul2 ## code (unsigned long long); \
27483 - type code ## zero = 0.0; \
27484 - type code ## one = 1.0; \
27485 - type code ## two = 2.0; \
27486 - type code ## four = 4.0; \
27487 - type code ## minus_one = -1.0; \
27488 - type code ## minus_two = -2.0; \
27489 - type code ## minus_four = -4.0; \
27490 - type code ## epsilon = 1E-32; \
27491 - type code ## NaN = 0.0 / 0.0;
27492 +/* All these functions are defined to use the base ABI, so use the
27493 + attribute to ensure the tests use the base ABI to call them even
27494 + when the VFP ABI is otherwise in effect. */
27495 +#define PCS __attribute__((pcs("aapcs")))
27497 +#define decl_float(code, type) \
27498 + extern type __aeabi_ ## code ## add (type, type) PCS; \
27499 + extern type __aeabi_ ## code ## div (type, type) PCS; \
27500 + extern type __aeabi_ ## code ## mul (type, type) PCS; \
27501 + extern type __aeabi_ ## code ## neg (type) PCS; \
27502 + extern type __aeabi_ ## code ## rsub (type, type) PCS; \
27503 + extern type __aeabi_ ## code ## sub (type, type) PCS; \
27504 + extern int __aeabi_ ## code ## cmpeq (type, type) PCS; \
27505 + extern int __aeabi_ ## code ## cmplt (type, type) PCS; \
27506 + extern int __aeabi_ ## code ## cmple (type, type) PCS; \
27507 + extern int __aeabi_ ## code ## cmpge (type, type) PCS; \
27508 + extern int __aeabi_ ## code ## cmpgt (type, type) PCS; \
27509 + extern int __aeabi_ ## code ## cmpun (type, type) PCS; \
27510 + extern int __aeabi_ ## code ## 2iz (type) PCS; \
27511 + extern unsigned int __aeabi_ ## code ## 2uiz (type) PCS; \
27512 + extern long long __aeabi_ ## code ## 2lz (type) PCS; \
27513 + extern unsigned long long __aeabi_ ## code ## 2ulz (type) PCS; \
27514 + extern type __aeabi_i2 ## code (int) PCS; \
27515 + extern type __aeabi_ui2 ## code (int) PCS; \
27516 + extern type __aeabi_l2 ## code (long long) PCS; \
27517 + extern type __aeabi_ul2 ## code (unsigned long long) PCS; \
27519 + type code ## zero = 0.0; \
27520 + type code ## one = 1.0; \
27521 + type code ## two = 2.0; \
27522 + type code ## four = 4.0; \
27523 + type code ## minus_one = -1.0; \
27524 + type code ## minus_two = -2.0; \
27525 + type code ## minus_four = -4.0; \
27526 + type code ## epsilon = 1E-32; \
27527 + type code ## NaN = 0.0 / 0.0;
27529 decl_float (d, double)
27530 decl_float (f, float)
27532 -extern float __aeabi_d2f (double);
27533 -extern double __aeabi_f2d (float);
27534 +extern float __aeabi_d2f (double) PCS;
27535 +extern double __aeabi_f2d (float) PCS;
27536 extern long long __aeabi_lmul (long long, long long);
27537 extern long long __aeabi_llsl (long long, int);
27538 extern long long __aeabi_llsr (long long, int);
27540 +++ b/gcc/testsuite/gcc.target/arm/fp16-builtins-1.c
27542 +/* Test type-generic builtins with __fp16 arguments.
27543 + Except as otherwise noted, they should behave exactly
27544 + the same as those with float arguments. */
27546 +/* { dg-do run } */
27547 +/* { dg-options "-mfp16-format=ieee -std=gnu99" } */
27549 +#include <stdlib.h>
27552 +volatile __fp16 h1, h2;
27553 +volatile float f1, f2;
27563 +set2 (double x, double y)
27571 +#define test1(p,x) \
27573 + hp = (p (h1) ? 1 : 0); \
27574 + fp = (p (f1) ? 1 : 0); \
27575 + if (hp ^ fp) abort ()
27577 +#define test2(p,x,y) \
27579 + hp = (p (h1, h2) ? 1 : 0); \
27580 + fp = (p (f1, f2) ? 1 : 0); \
27581 + if (hp ^ fp) abort ()
27588 + test1 (__builtin_isfinite, 17.0);
27589 + test1 (__builtin_isfinite, INFINITY);
27590 + test1 (__builtin_isinf, -0.5);
27591 + test1 (__builtin_isinf, INFINITY);
27592 + test1 (__builtin_isnan, 493.0);
27593 + test1 (__builtin_isnan, NAN);
27594 + test1 (__builtin_isnormal, 3.14159);
27596 + test2 (__builtin_isgreater, 5.0, 3.0);
27597 + test2 (__builtin_isgreater, 3.0, 5.0);
27598 + test2 (__builtin_isgreater, 73.5, 73.5);
27599 + test2 (__builtin_isgreater, 1.0, NAN);
27601 + test2 (__builtin_isgreaterequal, 5.0, 3.0);
27602 + test2 (__builtin_isgreaterequal, 3.0, 5.0);
27603 + test2 (__builtin_isgreaterequal, 73.5, 73.5);
27604 + test2 (__builtin_isgreaterequal, 1.0, NAN);
27606 + test2 (__builtin_isless, 5.0, 3.0);
27607 + test2 (__builtin_isless, 3.0, 5.0);
27608 + test2 (__builtin_isless, 73.5, 73.5);
27609 + test2 (__builtin_isless, 1.0, NAN);
27611 + test2 (__builtin_islessequal, 5.0, 3.0);
27612 + test2 (__builtin_islessequal, 3.0, 5.0);
27613 + test2 (__builtin_islessequal, 73.5, 73.5);
27614 + test2 (__builtin_islessequal, 1.0, NAN);
27616 + test2 (__builtin_islessgreater, 5.0, 3.0);
27617 + test2 (__builtin_islessgreater, 3.0, 5.0);
27618 + test2 (__builtin_islessgreater, 73.5, 73.5);
27619 + test2 (__builtin_islessgreater, 1.0, NAN);
27621 + test2 (__builtin_isunordered, 5.0, 3.0);
27622 + test2 (__builtin_isunordered, 3.0, 5.0);
27623 + test2 (__builtin_isunordered, 73.5, 73.5);
27624 + test2 (__builtin_isunordered, 1.0, NAN);
27626 + /* Test that __builtin_isnormal recognizes a denormalized __fp16 value,
27627 + even if it's representable as a normalized float. */
27629 + if (__builtin_isnormal (h1))
27635 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-1.c
27637 +/* { dg-do compile } */
27638 +/* { dg-options "-mfp16-format=alternative" } */
27642 +/* { dg-final { scan-assembler "\t.eabi_attribute 38, 2" } } */
27643 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27644 +/* { dg-final { scan-assembler "\t.space\t2" } } */
27646 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-10.c
27648 +/* { dg-do compile } */
27649 +/* { dg-options "-mfp16-format=alternative -pedantic -std=gnu99" } */
27653 +/* NaNs are not representable in the alternative format; we should get a
27655 +__fp16 xx = NAN; /* { dg-warning "overflow" } */
27657 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-11.c
27659 +/* { dg-do compile } */
27660 +/* { dg-options "-mfp16-format=alternative -pedantic -std=gnu99" } */
27664 +/* Infinities are not representable in the alternative format;
27665 + we should get a diagnostic, and the value set to the largest
27666 + representable value. */
27667 +/* 0x7fff = 32767 */
27668 +__fp16 xx = INFINITY; /* { dg-warning "overflow" } */
27670 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27671 +/* { dg-final { scan-assembler "\t.short\t32767" } } */
27673 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-12.c
27675 +/* { dg-do compile } */
27676 +/* { dg-options "-mfp16-format=alternative" } */
27678 +float xx __attribute__((mode(HF))) = 0.0;
27680 +/* { dg-final { scan-assembler "\t.eabi_attribute 38, 2" } } */
27681 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27682 +/* { dg-final { scan-assembler "\t.space\t2" } } */
27684 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-2.c
27686 +/* { dg-do compile } */
27687 +/* { dg-options "-mfp16-format=alternative" } */
27689 +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */
27690 +/* 0x3c00 = 15360 */
27693 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27694 +/* { dg-final { scan-assembler "\t.short\t15360" } } */
27696 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-3.c
27698 +/* { dg-do compile } */
27699 +/* { dg-options "-mfp16-format=alternative" } */
27701 +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */
27702 +/* 0xc000 = 49152 */
27705 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27706 +/* { dg-final { scan-assembler "\t.short\t49152" } } */
27708 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-4.c
27710 +/* { dg-do compile } */
27711 +/* { dg-options "-mfp16-format=alternative" } */
27713 +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */
27714 +/* 0x7bff = 31743 */
27715 +__fp16 xx = 65504.0;
27717 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27718 +/* { dg-final { scan-assembler "\t.short\t31743" } } */
27720 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-5.c
27722 +/* { dg-do compile } */
27723 +/* { dg-options "-mfp16-format=alternative" } */
27725 +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */
27726 +/* 0x3555 = 13653 */
27727 +__fp16 xx = (1.0/3.0);
27729 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27730 +/* { dg-final { scan-assembler "\t.short\t13653" } } */
27732 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-6.c
27734 +/* { dg-do compile } */
27735 +/* { dg-options "-mfp16-format=alternative" } */
27737 +/* This number is the maximum value representable in the alternative
27739 +/* 0x7fff = 32767 */
27740 +__fp16 xx = 131008.0;
27742 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27743 +/* { dg-final { scan-assembler "\t.short\t32767" } } */
27745 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-7.c
27747 +/* { dg-do compile } */
27748 +/* { dg-options "-mfp16-format=alternative -pedantic" } */
27750 +/* This number overflows the range of the alternative encoding. Since this
27751 + encoding doesn't have infinities, we should get a pedantic warning,
27752 + and the value should be set to the largest representable value. */
27753 +/* 0x7fff = 32767 */
27754 +__fp16 xx = 123456789.0; /* { dg-warning "overflow" } */
27756 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27757 +/* { dg-final { scan-assembler "\t.short\t32767" } } */
27759 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-8.c
27761 +/* { dg-do compile } */
27762 +/* { dg-options "-mfp16-format=alternative" } */
27764 +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */
27765 +/* This is the minimum normalized value. */
27766 +/* 0x0400 = 1024 */
27767 +__fp16 xx = 6.10352E-5;
27769 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27770 +/* { dg-final { scan-assembler "\t.short\t1024" } } */
27772 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-alt-9.c
27774 +/* { dg-do compile } */
27775 +/* { dg-options "-mfp16-format=alternative" } */
27777 +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */
27778 +/* This is the minimum denormalized value. */
27780 +__fp16 xx = 5.96046E-8;
27782 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27783 +/* { dg-final { scan-assembler "\t.short\t1" } } */
27785 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-exprtype.c
27787 +/* Test that expressions involving __fp16 values have the right types. */
27788 +/* { dg-do compile } */
27789 +/* { dg-options "-mfp16-format=ieee" } */
27791 +/* This produces a diagnostic if EXPR doesn't have type TYPE. */
27792 +#define CHECK(expr,type) \
27795 + __typeof (expr) *p = &v; \
27798 +volatile __fp16 f1;
27799 +volatile __fp16 f2;
27804 + CHECK (f1, __fp16);
27805 + CHECK (+f1, float);
27806 + CHECK (-f1, float);
27807 + CHECK (f1+f2, float);
27808 + CHECK ((__fp16)(f1+f2), __fp16);
27809 + CHECK ((__fp16)99.99, __fp16);
27810 + CHECK ((f1+f2, f1), __fp16);
27817 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-1.c
27819 +/* { dg-do compile } */
27820 +/* { dg-options "-mfp16-format=ieee" } */
27824 +/* { dg-final { scan-assembler "\t.eabi_attribute 38, 1" } } */
27825 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27826 +/* { dg-final { scan-assembler "\t.space\t2" } } */
27828 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-10.c
27830 +/* { dg-do compile } */
27831 +/* { dg-options "-mfp16-format=ieee -std=gnu99" } */
27835 +/* 0x7e00 = 32256 */
27838 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27839 +/* { dg-final { scan-assembler "\t.short\t32256" } } */
27841 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-11.c
27843 +/* { dg-do compile } */
27844 +/* { dg-options "-mfp16-format=ieee -std=gnu99" } */
27848 +/* 0x7c00 = 31744 */
27849 +__fp16 xx = INFINITY;
27851 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27852 +/* { dg-final { scan-assembler "\t.short\t31744" } } */
27854 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-12.c
27856 +/* { dg-do compile } */
27857 +/* { dg-options "-mfp16-format=ieee" } */
27859 +float xx __attribute__((mode(HF))) = 0.0;
27861 +/* { dg-final { scan-assembler "\t.eabi_attribute 38, 1" } } */
27862 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27863 +/* { dg-final { scan-assembler "\t.space\t2" } } */
27865 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-2.c
27867 +/* { dg-do compile } */
27868 +/* { dg-options "-mfp16-format=ieee" } */
27870 +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */
27871 +/* 0x3c00 = 15360 */
27874 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27875 +/* { dg-final { scan-assembler "\t.short\t15360" } } */
27877 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-3.c
27879 +/* { dg-do compile } */
27880 +/* { dg-options "-mfp16-format=ieee" } */
27882 +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */
27883 +/* 0xc000 = 49152 */
27886 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27887 +/* { dg-final { scan-assembler "\t.short\t49152" } } */
27889 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-4.c
27891 +/* { dg-do compile } */
27892 +/* { dg-options "-mfp16-format=ieee" } */
27894 +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */
27895 +/* 0x7bff = 31743 */
27896 +__fp16 xx = 65504.0;
27898 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27899 +/* { dg-final { scan-assembler "\t.short\t31743" } } */
27901 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-5.c
27903 +/* { dg-do compile } */
27904 +/* { dg-options "-mfp16-format=ieee" } */
27906 +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */
27907 +/* 0x3555 = 13653 */
27908 +__fp16 xx = (1.0/3.0);
27910 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27911 +/* { dg-final { scan-assembler "\t.short\t13653" } } */
27913 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-6.c
27915 +/* { dg-do compile } */
27916 +/* { dg-options "-mfp16-format=ieee" } */
27918 +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */
27919 +/* This number is too big and is represented as infinity. */
27920 +/* 0x7c00 = 31744 */
27921 +__fp16 xx = 131008.0;
27923 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27924 +/* { dg-final { scan-assembler "\t.short\t31744" } } */
27926 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-7.c
27928 +/* { dg-do compile } */
27929 +/* { dg-options "-mfp16-format=ieee -pedantic" } */
27931 +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */
27932 +/* This number is too big and is represented as infinity. */
27933 +/* We should *not* get an overflow warning here. */
27934 +/* 0x7c00 = 31744 */
27935 +__fp16 xx = 123456789.0;
27937 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27938 +/* { dg-final { scan-assembler "\t.short\t31744" } } */
27940 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-8.c
27942 +/* { dg-do compile } */
27943 +/* { dg-options "-mfp16-format=ieee" } */
27945 +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */
27946 +/* This is the minimum normalized value. */
27947 +/* 0x0400 = 1024 */
27948 +__fp16 xx = 6.10352E-5;
27950 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27951 +/* { dg-final { scan-assembler "\t.short\t1024" } } */
27953 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-ieee-9.c
27955 +/* { dg-do compile } */
27956 +/* { dg-options "-mfp16-format=ieee" } */
27958 +/* Encoding taken from: http://en.wikipedia.org/wiki/Half_precision */
27959 +/* This is the minimum denormalized value. */
27961 +__fp16 xx = 5.96046E-8;
27963 +/* { dg-final { scan-assembler "\t.size\txx, 2" } } */
27964 +/* { dg-final { scan-assembler "\t.short\t1" } } */
27966 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-none-1.c
27968 +/* { dg-do compile } */
27969 +/* { dg-options "-mfp16-format=none" } */
27971 +/* __fp16 type name is not recognized unless you explicitly enable it
27972 + by selecting -mfp16-format=ieee or -mfp16-format=alternative. */
27973 +__fp16 xx = 0.0; /* { dg-error "expected" } */
27975 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-none-2.c
27977 +/* { dg-do compile } */
27978 +/* { dg-options "-mfp16-format=none" } */
27980 +/* mode(HF) attributes are not recognized unless you explicitly enable
27981 + half-precision floating point by selecting -mfp16-format=ieee or
27982 + -mfp16-format=alternative. */
27983 +float xx __attribute__((mode(HF))) = 0.0; /* { dg-error "HF" } */
27985 +++ b/gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c
27987 +/* { dg-do compile } */
27988 +/* { dg-require-effective-target arm_neon_fp16_ok } */
27989 +/* { dg-options "-mfp16-format=ieee" } */
27990 +/* { dg-add-options arm_neon_fp16 } */
27992 +/* Test generation of VFP __fp16 instructions. */
27995 +__fp16 h2 = 1234.0;
27997 +float f2 = -999.9;
28005 +/* { dg-final { scan-assembler "\tvcvtb.f32.f16" } } */
28006 +/* { dg-final { scan-assembler "\tvcvtb.f16.f32" } } */
28008 +++ b/gcc/testsuite/gcc.target/arm/fp16-param-1.c
28010 +/* { dg-do compile } */
28011 +/* { dg-options "-mfp16-format=ieee" } */
28013 +/* Functions cannot have parameters of type __fp16. */
28014 +extern void f (__fp16); /* { dg-error "parameters cannot have __fp16 type" } */
28015 +extern void (*pf) (__fp16); /* { dg-error "parameters cannot have __fp16 type" } */
28017 +/* These should be OK. */
28018 +extern void g (__fp16 *);
28019 +extern void (*pg) (__fp16 *);
28021 +++ b/gcc/testsuite/gcc.target/arm/fp16-return-1.c
28023 +/* { dg-do compile } */
28024 +/* { dg-options "-mfp16-format=ieee" } */
28026 +/* Functions cannot return type __fp16. */
28027 +extern __fp16 f (void); /* { dg-error "cannot return __fp16" } */
28028 +extern __fp16 (*pf) (void); /* { dg-error "cannot return __fp16" } */
28030 +/* These should be OK. */
28031 +extern __fp16 *g (void);
28032 +extern __fp16 *(*pg) (void);
28034 +++ b/gcc/testsuite/gcc.target/arm/fp16-rounding-alt-1.c
28036 +/* Test intermediate rounding of double to float and then to __fp16, using
28037 + an example of a number that would round differently if it went directly
28038 + from double to __fp16. */
28040 +/* { dg-do run } */
28041 +/* { dg-options "-mfp16-format=alternative" } */
28043 +#include <stdlib.h>
28045 +/* The original double value. */
28046 +#define ORIG 0x1.0020008p0
28048 +/* The expected (double)((__fp16)((float)ORIG)) value. */
28049 +#define ROUNDED 0x1.0000000p0
28053 + unsigned short h;
28057 +ufh r = { ROUNDED };
28066 + /* Test that the rounding is correct for static initializers. */
28070 + /* Test that the rounding is correct for a casted constant expression
28071 + not in a static initializer. */
28072 + x.f = (__fp16)ORIG;
28076 + /* Test that the rounding is correct for a runtime conversion. */
28084 +++ b/gcc/testsuite/gcc.target/arm/fp16-rounding-ieee-1.c
28086 +/* Test intermediate rounding of double to float and then to __fp16, using
28087 + an example of a number that would round differently if it went directly
28088 + from double to __fp16. */
28090 +/* { dg-do run } */
28091 +/* { dg-options "-mfp16-format=ieee" } */
28093 +#include <stdlib.h>
28095 +/* The original double value. */
28096 +#define ORIG 0x1.0020008p0
28098 +/* The expected (double)((__fp16)((float)ORIG)) value. */
28099 +#define ROUNDED 0x1.0000000p0
28103 + unsigned short h;
28107 +ufh r = { ROUNDED };
28116 + /* Test that the rounding is correct for static initializers. */
28120 + /* Test that the rounding is correct for a casted constant expression
28121 + not in a static initializer. */
28122 + x.f = (__fp16)ORIG;
28126 + /* Test that the rounding is correct for a runtime conversion. */
28134 +++ b/gcc/testsuite/gcc.target/arm/fp16-unprototyped-1.c
28136 +/* Test promotion of __fp16 to double as arguments to unprototyped
28137 + function in another compilation unit. */
28139 +/* { dg-do run } */
28140 +/* { dg-options "-mfp16-format=ieee" } */
28141 +/* { dg-additional-sources "fp16-unprototyped-2.c" } */
28143 +#include <stdlib.h>
28147 +static __fp16 x = 42.0;
28148 +static __fp16 y = -42.0;
28158 +++ b/gcc/testsuite/gcc.target/arm/fp16-unprototyped-2.c
28160 +/* { dg-do compile } */
28161 +/* { dg-options "-mfp16-format=ieee" } */
28166 +f (double xx, double yy)
28168 + if (xx == 42.0 && yy == -42.0)
28173 +++ b/gcc/testsuite/gcc.target/arm/fp16-variadic-1.c
28175 +/* Test promotion of __fp16 to double as arguments to variadic function. */
28177 +/* { dg-do run } */
28178 +/* { dg-options "-mfp16-format=ieee" } */
28180 +#include <stdlib.h>
28181 +#include <stdarg.h>
28183 +extern int f (int n, ...);
28192 + va_start (ap, n);
28193 + xx = va_arg (ap, double);
28194 + yy = va_arg (ap, double);
28196 + if (xx == 42.0 && yy == -42.0)
28202 +static __fp16 x = 42.0;
28203 +static __fp16 y = -42.0;
28208 + if (!f (2, x, y))
28213 +++ b/gcc/testsuite/gcc.target/arm/frame-pointer-1.c
28215 +/* Check local register variables using a register conventionally
28216 + used as the frame pointer aren't clobbered under high register pressure. */
28217 +/* { dg-do run } */
28218 +/* { dg-options "-Os -mthumb -fomit-frame-pointer" } */
28220 +#include <stdlib.h>
28224 +void __attribute__((noinline)) foo(int p1, int p2, int p3, int p4)
28226 + if (global != 5 || p1 != 1 || p2 != 2 || p3 != 3 || p4 != 4)
28230 +int __attribute__((noinline)) test(int a, int b, int c, int d)
28232 + register unsigned long r __asm__("r7") = 0xdeadbeef;
28235 + /* ABCD are live after the call which should be enough
28236 + to cause r7 to be used if it weren't for the register variable. */
28240 + __asm__ __volatile__ ("mov %0, %2"
28242 + : "0" (e), "r" (r));
28244 + global = a+b+c+d;
28251 + if (test(1, 2, 3, 4) != 0xdeadbeef)
28253 + if (global != 10)
28258 +++ b/gcc/testsuite/gcc.target/arm/janus-2cc-shift-1.c
28260 +/* Check that a nop is inserted after a shift taking a register operand. */
28261 +/* { dg-do compile } */
28262 +/* { dg-options "-mfix-janus-2cc" } */
28263 +/* { dg-require-effective-target arm_not_thumb } */
28274 +/* { dg-final { scan-assembler "\tmov\tr\[0-9], r\[0-9], asl r\[0-9]\n\tnop\n" } } */
28275 +/* { dg-final { scan-assembler-not "\tmov\tr\[0-9], r\[0-9], asl #4\n\tnop\n" } } */
28278 +++ b/gcc/testsuite/gcc.target/arm/janus-2cc-shift-2.c
28280 +/* Check that a nop is inserted after a shift taking a register operand. */
28281 +/* { dg-do compile } */
28282 +/* { dg-options "-mfix-janus-2cc -mthumb" } */
28283 +/* { dg-require-effective-target arm_thumb1_ok } */
28294 +/* { dg-final { scan-assembler "\tlsl\tr\[0-9], r\[0-9], r\[0-9]\n\tnop\n" } } */
28295 +/* { dg-final { scan-assembler-not "\tlsl\tr\[0-9], r\[0-9], #4\n\tnop\n" } } */
28298 +++ b/gcc/testsuite/gcc.target/arm/naked-3.c
28300 +/* { dg-do compile } */
28301 +/* { dg-options "-O2 -Wall" } */
28302 +/* Check that we do not get warnings about missing return statements
28303 + or bogus looking noreturn functions. */
28304 +int __attribute__((naked))
28307 + __asm__ volatile ("mov r0, #1\r\nbx lr\n");
28310 +int __attribute__((naked,noreturn))
28313 + __asm__ volatile ("frob r0\n");
28316 +++ b/gcc/testsuite/gcc.target/arm/neon-modes-1.c
28318 +/* { dg-do compile } */
28319 +/* { dg-require-effective-target arm_neon_ok } */
28320 +/* { dg-options "-O1" } */
28321 +/* { dg-add-options arm_neon } */
28323 +#include <arm_neon.h>
28325 +void neon_internal_error(int *dst, int *src)
28327 + uint16x8x4_t sval;
28329 + sval = vld4q_u16((void *)src);
28330 + vst4q_u16((void *)dst,sval);
28333 +++ b/gcc/testsuite/gcc.target/arm/neon-vmla-1.c
28335 +/* { dg-require-effective-target arm_neon_hw } */
28336 +/* { dg-options "-O2 -ftree-vectorize" } */
28337 +/* { dg-add-options arm_neon } */
28338 +/* { dg-final { scan-assembler "vmla\\.f32" } } */
28340 +/* Verify that VMLA is used. */
28341 +void f1(int n, float a, float x[], float y[]) {
28343 + for (i = 0; i < n; ++i)
28344 + y[i] = a * x[i] + y[i];
28347 +++ b/gcc/testsuite/gcc.target/arm/neon-vmls-1.c
28349 +/* { dg-require-effective-target arm_neon_hw } */
28350 +/* { dg-options "-O2 -ftree-vectorize" } */
28351 +/* { dg-add-options arm_neon } */
28352 +/* { dg-final { scan-assembler "vmls\\.f32" } } */
28354 +/* Verify that VMLS is used. */
28355 +void f1(int n, float a, float x[], float y[]) {
28357 + for (i = 0; i < n; ++i)
28358 + y[i] = y[i] - a * x[i];
28361 +++ b/gcc/testsuite/gcc.target/arm/neon/vfp-shift-a2t2.c
28363 +/* Check that NEON vector shifts support immediate values == size. /*
28365 +/* { dg-do compile } */
28366 +/* { dg-require-effective-target arm_neon_ok } */
28367 +/* { dg-add-options arm_neon } */
28369 +#include <arm_neon.h>
28371 +uint16x8_t test_vshll_n_u8 (uint8x8_t a)
28373 + return vshll_n_u8(a, 8);
28376 +uint32x4_t test_vshll_n_u16 (uint16x4_t a)
28378 + return vshll_n_u16(a, 16);
28381 +uint64x2_t test_vshll_n_u32 (uint32x2_t a)
28383 + return vshll_n_u32(a, 32);
28386 +/* { dg-final { scan-assembler "vshll\.u16\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
28387 +/* { dg-final { scan-assembler "vshll\.u32\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
28388 +/* { dg-final { scan-assembler "vshll\.u8\[ \]+\[qQ\]\[0-9\]+, \[dD\]\[0-9\]+, #\[0-9\]+!?\(\[ \]+@\[a-zA-Z0-9 \]+\)?\n" } } */
28389 +/* { dg-final { cleanup-saved-temps } } */
28391 +++ b/gcc/testsuite/gcc.target/arm/pr40482.c
28393 +/* { dg-options "-mthumb -Os" } */
28394 +/* { dg-final { scan-assembler-not "ldr" } } */
28396 +unsigned int foo (unsigned int i )
28398 + return i | 0xff000000;
28401 +++ b/gcc/testsuite/gcc.target/arm/thumb2-mul-space-2.c
28403 +/* In Thumb-2 mode, when optimizing for size, generate a "muls"
28404 + instruction and use the resulting condition flags rather than a
28405 + separate compare instruction. */
28406 +/* { dg-options "-mthumb -Os" } */
28407 +/* { dg-require-effective-target arm_thumb2_ok } */
28408 +/* { dg-final { scan-assembler "muls" } } */
28409 +/* { dg-final { scan-assembler-not "cmp" } } */
28413 +void f(int i, int j)
28419 +++ b/gcc/testsuite/gcc.target/arm/thumb2-mul-space-3.c
28421 +/* In Thumb-2 mode, when optimizing for size, generate a "muls"
28422 + instruction and use the resulting condition flags rather than a
28423 + separate compare instruction. */
28424 +/* { dg-options "-mthumb -Os" } */
28425 +/* { dg-require-effective-target arm_thumb2_ok } */
28426 +/* { dg-final { scan-assembler "muls" } } */
28427 +/* { dg-final { scan-assembler-not "cmp" } } */
28431 +int f(int i, int j)
28439 +++ b/gcc/testsuite/gcc.target/arm/thumb2-mul-space.c
28441 +/* Use 16-bit multiply instruction in Thumb-2 mode when optimizing for
28443 +/* { dg-options "-mthumb -Os" } */
28444 +/* { dg-require-effective-target arm_thumb2_ok } */
28445 +/* { dg-final { scan-assembler "muls" } } */
28447 +int f(int i, int j)
28452 +++ b/gcc/testsuite/gcc.target/arm/thumb2-mul-speed.c
28454 +/* Do not use 16-bit multiply instructions in Thumb-2 mode when
28455 + optimizing for speed. */
28456 +/* { dg-options "-mthumb -O2" } */
28457 +/* { dg-require-effective-target arm_thumb2_ok } */
28458 +/* { dg-final { scan-assembler-not "muls" } } */
28460 +int f(int i, int j)
28467 +void g(int i, int j)
28473 +int h(int i, int j)
28482 +++ b/gcc/testsuite/gcc.target/arm/vfp-ldmdbd.c
28484 +/* { dg-do compile } */
28485 +/* { dg-require-effective-target arm_vfp_ok } */
28486 +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
28488 +extern void bar (double);
28491 +foo (double *p, double a, int n)
28498 +/* { dg-final { scan-assembler "fldmdbd" } } */
28500 +++ b/gcc/testsuite/gcc.target/arm/vfp-ldmdbs.c
28502 +/* { dg-do compile } */
28503 +/* { dg-require-effective-target arm_vfp_ok } */
28504 +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
28506 +extern void baz (float);
28509 +foo (float *p, float a, int n)
28516 +/* { dg-final { scan-assembler "fldmdbs" } } */
28518 +++ b/gcc/testsuite/gcc.target/arm/vfp-ldmiad.c
28520 +/* { dg-do compile } */
28521 +/* { dg-require-effective-target arm_vfp_ok } */
28522 +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
28524 +extern void bar (double);
28527 +foo (double *p, double a, int n)
28534 +/* { dg-final { scan-assembler "fldmiad" } } */
28536 +++ b/gcc/testsuite/gcc.target/arm/vfp-ldmias.c
28538 +/* { dg-do compile } */
28539 +/* { dg-require-effective-target arm_vfp_ok } */
28540 +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
28542 +extern void baz (float);
28545 +foo (float *p, float a, int n)
28552 +/* { dg-final { scan-assembler "fldmias" } } */
28554 +++ b/gcc/testsuite/gcc.target/arm/vfp-stmdbd.c
28556 +/* { dg-do compile } */
28557 +/* { dg-require-effective-target arm_vfp_ok } */
28558 +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
28561 +foo (double *p, double a, double b, int n)
28563 + double c = a + b;
28569 +/* { dg-final { scan-assembler "fstmdbd" } } */
28571 +++ b/gcc/testsuite/gcc.target/arm/vfp-stmdbs.c
28573 +/* { dg-do compile } */
28574 +/* { dg-require-effective-target arm_vfp_ok } */
28575 +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
28578 +foo (float *p, float a, float b, int n)
28586 +/* { dg-final { scan-assembler "fstmdbs" } } */
28588 +++ b/gcc/testsuite/gcc.target/arm/vfp-stmiad.c
28590 +/* { dg-do compile } */
28591 +/* { dg-require-effective-target arm_vfp_ok } */
28592 +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
28595 +foo (double *p, double a, double b, int n)
28597 + double c = a + b;
28603 +/* { dg-final { scan-assembler "fstmiad" } } */
28605 +++ b/gcc/testsuite/gcc.target/arm/vfp-stmias.c
28607 +/* { dg-do compile } */
28608 +/* { dg-require-effective-target arm_vfp_ok } */
28609 +/* { dg-options "-O2 -mfpu=vfp -mfloat-abi=softfp" } */
28612 +foo (float *p, float a, float b, int n)
28620 +/* { dg-final { scan-assembler "fstmias" } } */
28621 --- a/gcc/testsuite/gcc.target/i386/387-1.c
28622 +++ b/gcc/testsuite/gcc.target/i386/387-1.c
28624 /* Verify that -mno-fancy-math-387 works. */
28625 /* { dg-do compile } */
28626 /* { dg-require-effective-target ilp32 } */
28627 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */
28628 /* { dg-options "-O -ffast-math -mfpmath=387 -mno-fancy-math-387 -march=i386" } */
28629 /* { dg-final { scan-assembler "call\t(.*)sin" } } */
28630 /* { dg-final { scan-assembler "call\t(.*)cos" } } */
28631 --- a/gcc/testsuite/gcc.target/i386/387-5.c
28632 +++ b/gcc/testsuite/gcc.target/i386/387-5.c
28634 /* Verify that -mno-fancy-math-387 works. */
28635 /* { dg-do compile } */
28636 /* { dg-require-effective-target ilp32 } */
28637 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */
28638 /* { dg-options "-O -ffast-math -mfpmath=387 -mno-fancy-math-387 -march=i386" } */
28639 /* { dg-final { scan-assembler "call\t(.*)atan" } } */
28640 /* { dg-final { scan-assembler "call\t(.*)log1p" } } */
28641 --- a/gcc/testsuite/gcc.target/i386/cmov7.c
28642 +++ b/gcc/testsuite/gcc.target/i386/cmov7.c
28644 /* PR middle-end/33187 */
28646 /* { dg-do compile } */
28647 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=k8" } } */
28648 /* { dg-options "-O2 -ffast-math -march=k8 -mbranch-cost=5 -mfpmath=387" } */
28649 /* { dg-final { scan-assembler "fcmov" } } */
28651 --- a/gcc/testsuite/gcc.target/i386/funcspec-1.c
28652 +++ b/gcc/testsuite/gcc.target/i386/funcspec-1.c
28654 for a function that doesn't use attribute((option)). */
28655 /* { dg-do compile } */
28656 /* { dg-require-effective-target ilp32 } */
28657 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */
28658 /* { dg-options "-O3 -ftree-vectorize -march=i386" } */
28659 /* { dg-final { scan-assembler "addps\[ \t\]" } } */
28660 /* { dg-final { scan-assembler "fsubs\[ \t\]" } } */
28661 --- a/gcc/testsuite/gcc.target/i386/funcspec-8.c
28662 +++ b/gcc/testsuite/gcc.target/i386/funcspec-8.c
28664 /* Test whether using target specific options, we can use the x86 builtin
28665 functions in functions with the appropriate function specific options. */
28666 /* { dg-do compile } */
28667 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=k8" } } */
28668 /* { dg-options "-O2 -march=k8 -mfpmath=sse" } */
28670 typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
28671 --- a/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-1.c
28672 +++ b/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-1.c
28674 /* { dg-do preprocess } */
28675 /* { dg-require-effective-target ilp32 } */
28676 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */
28677 /* { dg-options "-march=i386" } */
28679 #ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
28680 --- a/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-2.c
28681 +++ b/gcc/testsuite/gcc.target/i386/gcc-have-sync-compare-and-swap-2.c
28683 /* { dg-do preprocess } */
28684 /* { dg-require-effective-target ilp32 } */
28685 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i486" } } */
28686 /* { dg-options "-march=i486" } */
28688 #ifndef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
28689 --- a/gcc/testsuite/gcc.target/i386/isa-10.c
28690 +++ b/gcc/testsuite/gcc.target/i386/isa-10.c
28692 /* { dg-do run } */
28693 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=x86-64" } } */
28694 /* { dg-options "-march=x86-64 -msse5 -mno-sse4" } */
28696 extern void abort (void);
28697 --- a/gcc/testsuite/gcc.target/i386/isa-6.c
28698 +++ b/gcc/testsuite/gcc.target/i386/isa-6.c
28700 /* { dg-do run } */
28701 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=amdfam10" } } */
28702 /* { dg-options "-march=amdfam10 -mno-sse4" } */
28704 extern void abort (void);
28705 --- a/gcc/testsuite/gcc.target/i386/isa-7.c
28706 +++ b/gcc/testsuite/gcc.target/i386/isa-7.c
28708 /* { dg-do run } */
28709 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=amdfam10" } } */
28710 /* { dg-options "-march=amdfam10 -msse5 -mno-sse4" } */
28712 extern void abort (void);
28713 --- a/gcc/testsuite/gcc.target/i386/isa-8.c
28714 +++ b/gcc/testsuite/gcc.target/i386/isa-8.c
28716 /* { dg-do run } */
28717 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=amdfam10" } } */
28718 /* { dg-options "-march=amdfam10 -msse5 -mno-sse4a" } */
28720 extern void abort (void);
28721 --- a/gcc/testsuite/gcc.target/i386/isa-9.c
28722 +++ b/gcc/testsuite/gcc.target/i386/isa-9.c
28724 /* { dg-do run } */
28725 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=amdfam10" } } */
28726 /* { dg-options "-march=amdfam10 -mno-sse5" } */
28728 extern void abort (void);
28729 --- a/gcc/testsuite/gcc.target/i386/lea.c
28730 +++ b/gcc/testsuite/gcc.target/i386/lea.c
28732 /* { dg-do compile } */
28733 /* { dg-require-effective-target ilp32 } */
28734 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=pentiumpro" } } */
28735 /* { dg-options "-O2 -march=pentiumpro" } */
28736 /* { dg-final { scan-assembler "leal" } } */
28739 +++ b/gcc/testsuite/gcc.target/i386/movbe-1.c
28741 +/* { dg-do compile } */
28742 +/* { dg-options "-O2 -mmovbe" } */
28749 + x = __builtin_bswap32 (i);
28755 + return __builtin_bswap32 (x);
28758 +/* { dg-final { scan-assembler-times "movbe\[ \t\]" 2 } } */
28760 +++ b/gcc/testsuite/gcc.target/i386/movbe-2.c
28762 +/* { dg-do compile } */
28763 +/* { dg-options "-O2 -mmovbe" } */
28765 +extern long long x;
28770 + x = __builtin_bswap64 (i);
28776 + return __builtin_bswap64 (x);
28779 +/* { dg-final { scan-assembler-times "movbe\[ \t\]" 4 { target ilp32 } } } */
28780 +/* { dg-final { scan-assembler-times "movbe\[ \t\]" 2 { target lp64 } } } */
28781 --- a/gcc/testsuite/gcc.target/i386/pentium4-not-mull.c
28782 +++ b/gcc/testsuite/gcc.target/i386/pentium4-not-mull.c
28784 /* { dg-do compile } */
28785 /* { dg-require-effective-target ilp32 } */
28786 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=pentium4" } } */
28787 /* { dg-options "-O2 -march=pentium4" } */
28788 /* { dg-final { scan-assembler-not "imull" } } */
28791 +++ b/gcc/testsuite/gcc.target/i386/pr37216.c
28793 +/* { dg-do run } */
28794 +/* { dg-options "-O3 -msse2" } */
28795 +/* { dg-options "-O3 -msse2 -mpe-aligned-commons" { target pe_aligned_commons } } */
28797 +#include "sse2-check.h"
28807 + for (i = 0; i < 64; i++)
28810 --- a/gcc/testsuite/gcc.target/i386/pr37843-1.c
28811 +++ b/gcc/testsuite/gcc.target/i386/pr37843-1.c
28813 /* { dg-do compile { target nonpic } } */
28814 /* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=5" } */
28815 /* { dg-final { scan-assembler "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
28816 -/* { dg-final { scan-assembler "call\[\\t \]*foo" } } */
28817 -/* { dg-final { scan-assembler-not "jmp\[\\t \]*foo" } } */
28818 +/* { dg-final { scan-assembler "call\[\\t \]*_?foo" } } */
28819 +/* { dg-final { scan-assembler-not "jmp\[\\t \]*_?foo" } } */
28821 extern int foo (void);
28823 --- a/gcc/testsuite/gcc.target/i386/pr37843-2.c
28824 +++ b/gcc/testsuite/gcc.target/i386/pr37843-2.c
28826 /* { dg-do compile { target nonpic } } */
28827 /* { dg-options "-O2 -mpreferred-stack-boundary=6 -mincoming-stack-boundary=6" } */
28828 /* { dg-final { scan-assembler-not "and\[lq\]?\[\\t \]*\\$-64,\[\\t \]*%\[re\]?sp" } } */
28829 -/* { dg-final { scan-assembler-not "call\[\\t \]*foo" } } */
28830 -/* { dg-final { scan-assembler "jmp\[\\t \]*foo" } } */
28831 +/* { dg-final { scan-assembler-not "call\[\\t \]*_?foo" } } */
28832 +/* { dg-final { scan-assembler "jmp\[\\t \]*_?foo" } } */
28834 extern int foo (void);
28836 --- a/gcc/testsuite/gcc.target/i386/pr37843-3.c
28837 +++ b/gcc/testsuite/gcc.target/i386/pr37843-3.c
28839 /* { dg-do compile { target { ilp32 && nonpic } } } */
28840 /* { dg-options "-O2 -msse2 -mpreferred-stack-boundary=4 -mstackrealign" } */
28841 /* { dg-final { scan-assembler-not "andl\[\\t \]*\\$-16,\[\\t \]*%\[re\]?sp" } } */
28842 -/* { dg-final { scan-assembler-not "call\[\\t \]*foo" } } */
28843 -/* { dg-final { scan-assembler "jmp\[\\t \]*foo" } } */
28844 +/* { dg-final { scan-assembler-not "call\[\\t \]*_?foo" } } */
28845 +/* { dg-final { scan-assembler "jmp\[\\t \]*_?foo" } } */
28847 #include <emmintrin.h>
28849 --- a/gcc/testsuite/gcc.target/i386/sse-5.c
28850 +++ b/gcc/testsuite/gcc.target/i386/sse-5.c
28852 /* { dg-do compile } */
28853 /* { dg-require-effective-target ilp32 } */
28854 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */
28855 /* { dg-options "-Winline -O2 -march=i386" } */
28857 typedef double v2df __attribute__ ((vector_size (16)));
28858 --- a/gcc/testsuite/gcc.target/i386/ssefn-1.c
28859 +++ b/gcc/testsuite/gcc.target/i386/ssefn-1.c
28861 /* { dg-final { scan-assembler "mulss" } } */
28862 /* { dg-final { scan-assembler-not "movsd" } } */
28863 /* { dg-final { scan-assembler-not "mulsd" } } */
28864 +/* { dg-skip-if "" { i?86-*-* x86_64-*-* } { "-march=*" } { "-march=i386" } } */
28865 /* { dg-options "-O2 -march=i386 -msse -mfpmath=sse -fno-inline" } */
28867 static float xs (void)
28869 +++ b/gcc/testsuite/gcc.target/m68k/20090709-1.c
28871 +/* { dg-do compile } */
28872 +/* There should be 3 occurrences of .LC0 in the code:
28873 + one for the definition of "0",
28874 + one for use in test1() and
28875 + one for use in test2().
28876 + FIXME: At the moment m68k GCC does not optimize test1() to nop
28877 + for some reason. */
28878 +/* { dg-final { scan-assembler-times ".LC0" 3 } } */
28880 +void dummy(char *arg);
28884 + char tmp[2] = "0";
28891 --- a/gcc/testsuite/gcc.target/m68k/pr36134.c
28892 +++ b/gcc/testsuite/gcc.target/m68k/pr36134.c
28896 This test ensures that the shorter LEA instruction is used in preference
28897 - to the longer ADD instruction. */
28898 + to the longer ADD instruction.
28900 + This preference is applicable to ColdFire only. On CPU32, we can
28901 + use a sequence of two ADDQ instructions, which is faster than the
28902 + LEA instruction. */
28904 /* { dg-do compile } */
28905 -/* { dg-options "-O2" } */
28906 +/* { dg-skip-if "" { *-*-* } { "-mcpu=*" } { "-mcpu=5208" } } */
28907 +/* { dg-options "-O2 -mcpu=5208" } */
28908 /* { dg-final { scan-assembler "lea" } } */
28909 /* { dg-final { scan-assembler-not "add" } } */
28912 +++ b/gcc/testsuite/gcc.target/m68k/tls-gd-xgot.c
28914 +/* { dg-do compile } */
28915 +/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
28916 +/* { dg-options "-O2 -fpic -mxgot" } */
28917 +/* { dg-final { scan-assembler "#foo@TLSGD,\%\[ad\]\[0-7\]" } } */
28918 +/* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */
28920 +extern int __thread foo;
28928 +++ b/gcc/testsuite/gcc.target/m68k/tls-gd.c
28930 +/* { dg-do compile } */
28931 +/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
28932 +/* { dg-options "-O2 -fpic" } */
28933 +/* { dg-final { scan-assembler "foo@TLSGD\\(\%a5\\)" } } */
28934 +/* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */
28936 +extern int __thread foo;
28944 +++ b/gcc/testsuite/gcc.target/m68k/tls-ie-xgot.c
28946 +/* { dg-do compile } */
28947 +/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
28948 +/* { dg-options "-O2 -mxgot" } */
28949 +/* { dg-final { scan-assembler "jsr __m68k_read_tp" } } */
28950 +/* { dg-final { scan-assembler "#foo@TLSIE,\%\[ad\]\[0-7\]" } } */
28952 +extern int __thread foo;
28960 +++ b/gcc/testsuite/gcc.target/m68k/tls-ie.c
28962 +/* { dg-do compile } */
28963 +/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
28964 +/* { dg-options "-O2" } */
28965 +/* { dg-final { scan-assembler "jsr __m68k_read_tp" } } */
28966 +/* { dg-final { scan-assembler "foo@TLSIE\\(\%a5\\)" } } */
28968 +extern int __thread foo;
28976 +++ b/gcc/testsuite/gcc.target/m68k/tls-ld-xgot-xtls.c
28978 +/* { dg-do compile } */
28979 +/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
28980 +/* { dg-options "-O2 -fpic -mxgot -mxtls" } */
28981 +/* { dg-final { scan-assembler "#foo@TLSLDM,\%\[ad\]\[0-7\]" } } */
28982 +/* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */
28983 +/* { dg-final { scan-assembler "#foo@TLSLDO,\%\[ad\]\[0-7\]" } } */
28985 +static int __thread foo;
28993 +++ b/gcc/testsuite/gcc.target/m68k/tls-ld-xgot.c
28995 +/* { dg-do compile } */
28996 +/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
28997 +/* { dg-options "-O2 -fpic -mxgot" } */
28998 +/* { dg-final { scan-assembler "#foo@TLSLDM,\%\[ad\]\[0-7\]" } } */
28999 +/* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */
29000 +/* { dg-final { scan-assembler "lea \\(foo@TLSLDO,\%a0\\)" } } */
29002 +static int __thread foo;
29010 +++ b/gcc/testsuite/gcc.target/m68k/tls-ld-xtls.c
29012 +/* { dg-do compile } */
29013 +/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
29014 +/* { dg-options "-O2 -fpic -mxtls" } */
29015 +/* { dg-final { scan-assembler "foo@TLSLDM\\(\%a5\\)" } } */
29016 +/* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */
29017 +/* { dg-final { scan-assembler "#foo@TLSLDO,\%\[ad\]\[0-7\]" } } */
29019 +static int __thread foo;
29027 +++ b/gcc/testsuite/gcc.target/m68k/tls-ld.c
29029 +/* { dg-do compile } */
29030 +/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
29031 +/* { dg-options "-O2 -fpic" } */
29032 +/* { dg-final { scan-assembler "foo@TLSLDM\\(\%a5\\)" } } */
29033 +/* { dg-final { scan-assembler "bsr.l __tls_get_addr@PLTPC" } } */
29034 +/* { dg-final { scan-assembler "lea \\(foo@TLSLDO,\%a0\\)" } } */
29036 +static int __thread foo;
29044 +++ b/gcc/testsuite/gcc.target/m68k/tls-le-xtls.c
29046 +/* { dg-do compile } */
29047 +/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
29048 +/* { dg-options "-O2 -mxtls" } */
29049 +/* { dg-final { scan-assembler "jsr __m68k_read_tp" } } */
29050 +/* { dg-final { scan-assembler "#foo@TLSLE,\%\[ad\]\[0-7\]" } } */
29052 +static int __thread foo;
29060 +++ b/gcc/testsuite/gcc.target/m68k/tls-le.c
29062 +/* { dg-do compile } */
29063 +/* { dg-skip-if "" { ! *-linux-* } { "*" } { "" } } */
29064 +/* { dg-options "-O2" } */
29065 +/* { dg-final { scan-assembler "jsr __m68k_read_tp" } } */
29066 +/* { dg-final { scan-assembler "lea \\(foo@TLSLE,\%a0\\)" } } */
29068 +static int __thread foo;
29076 +++ b/gcc/testsuite/gcc.target/mips/branch-2.c
29078 +/* Check that we correctly expand out-of-range branches */
29079 +/* { dg-do run } */
29080 +/* { dg-options "-O2 -mabi=32 -fPIC" } */
29082 +#include <stdlib.h>
29084 +/* This is weak so the compiler cannot assume that calls from this TU
29085 + necessarily arrive here. And hence that $gp may be clobbered in
29086 + o32 and o64 ABIs. */
29088 +void __attribute__ ((weak)) Foo (int i)
29090 + static int once = 0;
29092 + if (!i && once++)
29095 +#if (_ABIO32 || _ABIO64)
29096 + /* Clobber $gp */
29097 + __asm volatile ("li $gp,0");
29101 +#define N1(X) (Foo (X))
29102 +#define N2(X) (N1 (X), N1 (X+(1<<0)))
29103 +#define N3(X) (N2 (X), N2 (X+(1<<1)))
29104 +#define N4(X) (N3 (X), N3 (X+(1<<2)))
29105 +#define N5(X) (N4 (X), N4 (X+(1<<3)))
29106 +#define N6(X) (N5 (X), N5 (X+(1<<4)))
29107 +#define N7(X) (N6 (X), N6 (X+(1<<5)))
29108 +#define N8(X) (N7 (X), N7 (X+(1<<6)))
29109 +#define N9(X) (N8 (X), N8 (X+(1<<7)))
29110 +#define N10(X) (N9 (X), N9 (X+(1<<8)))
29111 +#define N11(X) (N10 (X), N10 (X+(1<<9)))
29112 +#define N12(X) (N11 (X), N11 (X+(1<<10)))
29113 +#define N13(X) (N12 (X), N12 (X+(1<<11)))
29114 +#define N14(X) (N13 (X), N13 (X+(1<<12)))
29122 --- a/gcc/testsuite/gcc.target/mips/clear-cache-2.c
29123 +++ b/gcc/testsuite/gcc.target/mips/clear-cache-2.c
29125 /* { dg-options "-O2 -mips32" } */
29126 /* { dg-final { scan-assembler-not "synci" } } */
29127 /* { dg-final { scan-assembler-not "jr.hb" } } */
29128 -/* { dg-final { scan-assembler "_flush_cache" } } */
29129 +/* { dg-final { scan-assembler "mips_sync_icache" { target { *-sde-* } } } } */
29130 +/* { dg-final { scan-assembler "_flush_cache" { target { ! *-sde-* } } } } */
29134 --- a/gcc/testsuite/gcc.target/mips/fpr-moves-5.c
29135 +++ b/gcc/testsuite/gcc.target/mips/fpr-moves-5.c
29137 /* { dg-options "-mabi=64 -mhard-float -O2 -EL" } */
29138 +/* { dg-require-effective-target mips_newabi_large_long_double } */
29141 foo (long double d, long double *x)
29142 --- a/gcc/testsuite/gcc.target/mips/fpr-moves-6.c
29143 +++ b/gcc/testsuite/gcc.target/mips/fpr-moves-6.c
29145 /* { dg-options "-mabi=64 -mhard-float -O2 -EB" } */
29146 +/* { dg-require-effective-target mips_newabi_large_long_double } */
29149 foo (long double d, long double *x)
29150 --- a/gcc/testsuite/gcc.target/mips/mips.exp
29151 +++ b/gcc/testsuite/gcc.target/mips/mips.exp
29152 @@ -229,6 +229,7 @@ foreach option {
29161 +++ b/gcc/testsuite/gcc.target/mips/octeon-useun.c
29163 +/* Check the mov_u[ls][dw] patterns. */
29164 +/* { dg-options "-march=octeon -O2 -mabi=64 -mocteon-useun -meb" } */
29165 +struct __attribute__((packed)) sl { unsigned long x; };
29166 +struct __attribute__((packed)) si { unsigned int x; };
29167 +unsigned long f1 (struct sl *s) { return s[0].x; };
29168 +unsigned int f2 (struct si *s) { return s[1].x; };
29169 +void f3 (struct sl *s, unsigned long x) { s[10].x = x; }
29170 +void f4 (struct si *s, unsigned int x) { s[11].x = x; }
29171 +void f5 (struct sl *s) { s[100].x = 0; }
29172 +void f6 (struct si *s) { s[101].x = 0; }
29173 +/* { dg-final { scan-assembler "\tjr?\t\\\$31\n\tuld\t\\\$2,0\\(\\\$4\\)\n" } } */
29174 +/* { dg-final { scan-assembler "\tulw\t\\\$2,4\\(\\\$4\\)\n" } } */
29175 +/* { dg-final { scan-assembler "\tjr?\t\\\$31\n\tusd\t\\\$5,80\\(\\\$4\\)\n" } } */
29176 +/* { dg-final { scan-assembler "\tjr?\t\\\$31\n\tusw\t\\\$5,44\\(\\\$4\\)\n" } } */
29177 +/* { dg-final { scan-assembler "\tjr?\t\\\$31\n\tusd\t\\\$0,800\\(\\\$4\\)\n" } } */
29178 +/* { dg-final { scan-assembler "\tjr?\t\\\$31\n\tusw\t\\\$0,404\\(\\\$4\\)\n" } } */
29179 --- a/gcc/testsuite/gcc.target/powerpc/altivec-consts.c
29180 +++ b/gcc/testsuite/gcc.target/powerpc/altivec-consts.c
29182 /* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
29183 /* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
29184 /* { dg-require-effective-target powerpc_altivec_ok } */
29185 -/* { dg-options "-maltivec -mabi=altivec -O2" } */
29186 +/* { dg-options "-maltivec -O2" } */
29188 /* Check that "easy" AltiVec constants are correctly synthesized. */
29190 --- a/gcc/testsuite/gcc.target/powerpc/altivec-varargs-1.c
29191 +++ b/gcc/testsuite/gcc.target/powerpc/altivec-varargs-1.c
29193 /* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */
29194 /* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */
29195 /* { dg-require-effective-target powerpc_altivec_ok } */
29196 -/* { dg-options "-maltivec -mabi=altivec -fno-inline" } */
29197 +/* { dg-options "-maltivec -fno-inline" } */
29199 #include <stdarg.h>
29201 --- a/gcc/testsuite/gcc.target/sh/20080410-1.c
29202 +++ b/gcc/testsuite/gcc.target/sh/20080410-1.c
29204 /* { dg-do compile { target "sh-*-*" } } */
29205 -/* { dg-options "-O0 -m4 -ml -fira" } */
29206 +/* { dg-options "-O0 -m4 -ml" } */
29207 /* { dg-final { scan-assembler-not "add\tr0,r0" } } */
29209 /* This test checks that chain reloads conflict. I they don't
29210 --- a/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c
29211 +++ b/gcc/testsuite/gcc.target/sh/sh4a-bitmovua.c
29212 @@ -35,15 +35,15 @@ long long f4() {
29216 -struct u0 { unsigned long long d : 32; } y0;
29217 +struct u0 { unsigned long long d : 32; } y_0;
29218 unsigned long long g0() {
29223 /* Unaligned load. */
29224 -struct u1 { long long c : 8; unsigned long long d : 32; } y1;
29225 +struct u1 { long long c : 8; unsigned long long d : 32; } y_1;
29226 unsigned long long g1() {
29231 /* Unaligned load. */
29232 --- a/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c
29233 +++ b/gcc/testsuite/gcc.target/sh/sh4a-memmovua.c
29235 /* { dg-final { scan-assembler-times "\tmovua\\.l\t(.*)+" 2 } } */
29238 -#include <stdlib.h>
29239 +#include <string.h>
29241 struct s { int i; char a[10], b[10]; } x;
29244 +++ b/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2a.c
29246 +/* Test for cross x86_64<->w64 abi standard calls. */
29247 +/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */
29248 +/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */
29249 +/* { dg-additional-sources "func-2b.c" } */
29251 +extern void __attribute__ ((sysv_abi)) abort (void);
29252 +long double func_cross (long double, double, float, long, int, char);
29254 +long double __attribute__ ((sysv_abi))
29255 +func_native (long double a, double b, float c, long d, int e, char f)
29258 + ret = a + (long double) b + (long double) c;
29259 + ret *= (long double) (d + (long) e);
29261 + ret += func_native (a,b,c,d,e,-f);
29265 +int __attribute__ ((sysv_abi))
29268 + if (func_cross (1.0,2.0,3.0,1,2,3)
29269 + != func_native (1.0,2.0,3.0,1,2,3))
29274 +++ b/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-2b.c
29276 +/* Test for cross x86_64<->w64 abi standard calls. */
29277 +/* { dg-options "-mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */
29279 +long double func_cross (long double a, double b, float c, long d, int e,
29283 + ret = a + (long double) b + (long double) c;
29284 + ret *= (long double) (d + (long) e);
29286 + ret += func_cross (a,b,c,d,e,-f);
29290 +++ b/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2a.c
29292 +/* Test for cross x86_64<->w64 abi standard calls via variable. */
29293 +/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */
29294 +/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */
29295 +/* { dg-additional-sources "func-indirect-2b.c" } */
29297 +extern void __attribute__ ((sysv_abi)) abort (void);
29298 +typedef int (*func)(void *, char *, char *, short, long long);
29299 +extern func get_callback (void);
29301 +int __attribute__ ((sysv_abi))
29304 + func callme = get_callback ();
29305 + if (callme (0, 0, 0, 0x1234, 0x1234567890abcdefLL))
29310 +++ b/gcc/testsuite/gcc.target/x86_64/abi/callabi/func-indirect-2b.c
29312 +/* Test for cross x86_64<->w64 abi standard calls via variable. */
29313 +/* { dg-options "-O2 -mabi=ms -std=gnu99 -ffast-math -fno-builtin" } */
29315 +typedef int (*func)(void *, char *, char *, short, long long);
29318 +callback (void *ptr, char *string1, char *string2, short number,
29324 + || number != 0x1234
29325 + || rand != 0x1234567890abcdefLL)
29332 +get_callback (void)
29337 +++ b/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4a.c
29339 +/* Test for cross x86_64<->w64 abi va_list calls. */
29340 +/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */
29341 +/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */
29342 +/* { dg-additional-sources "vaarg-4b.c" } */
29344 +extern __SIZE_TYPE__ __attribute__ ((sysv_abi)) strlen (const char *);
29345 +extern int __attribute__ ((sysv_abi)) sprintf (char *,const char *, ...);
29346 +extern void __attribute__ ((sysv_abi)) abort (void);
29348 +extern void do_cpy (char *, ...);
29350 +int __attribute__ ((sysv_abi))
29355 + do_cpy (s, "1","2","3","4", "5", "6", "7", "");
29357 + if (s[0] != '1' || s[1] !='2' || s[2] != '3' || s[3] != '4'
29358 + || s[4] != '5' || s[5] != '6' || s[6] != '7' || s[7] != 0)
29364 +++ b/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-4b.c
29366 +/* Test for cross x86_64<->w64 abi va_list calls. */
29367 +/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */
29369 +#include <stdarg.h>
29371 +extern __SIZE_TYPE__ __attribute__ ((sysv_abi)) strlen (const char *);
29372 +extern int __attribute__ ((sysv_abi)) sprintf (char *, const char *, ...);
29375 +vdo_cpy (char *s, va_list argp)
29377 + __SIZE_TYPE__ len;
29382 + e = va_arg (argp, char *);
29383 + if (*e == 0) break;
29384 + sprintf (r,"%s", e);
29390 +do_cpy (char *s, ...)
29393 + va_start (argp, s);
29394 + vdo_cpy (s, argp);
29398 +++ b/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5a.c
29400 +/* Test for cross x86_64<->w64 abi va_list calls. */
29401 +/* { dg-do run { target i?86-*-linux* x86_64-*-linux* } } */
29402 +/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */
29403 +/* { dg-additional-sources "vaarg-5b.c" } */
29405 +extern void __attribute__ ((sysv_abi)) abort (void);
29406 +extern int fct2 (int, ...);
29408 +#define SZ_ARGS 1ll,2ll,3ll,4ll,5ll,6ll,7ll,0ll
29410 +int __attribute__ ((sysv_abi))
29413 + if (fct2 (-1, SZ_ARGS) != 0)
29418 +++ b/gcc/testsuite/gcc.target/x86_64/abi/callabi/vaarg-5b.c
29420 +/* Test for cross x86_64<->w64 abi va_list calls. */
29421 +/* { dg-options "-O2 -mabi=ms -std=gnu99 -fno-builtin" } */
29423 +#include <stdarg.h>
29425 +#define SZ_ARGS 1ll,2ll,3ll,4ll,5ll,6ll,7ll,0ll
29427 +static int __attribute__ ((sysv_abi))
29428 +fct1 (va_list argp, ...)
29432 + __builtin_sysv_va_list argp_2;
29434 + __builtin_sysv_va_start (argp_2, argp);
29436 + p1 = va_arg (argp_2, long long);
29437 + p2 = va_arg (argp, long long);
29440 + } while (ret && p1 != 0);
29441 + __builtin_sysv_va_end (argp_2);
29447 +fct2 (int dummy, ...)
29452 + va_start (argp, dummy);
29453 + ret += fct1 (argp, SZ_ARGS);
29457 --- a/gcc/testsuite/gfortran.dg/vect/vect.exp
29458 +++ b/gcc/testsuite/gfortran.dg/vect/vect.exp
29459 @@ -98,7 +98,7 @@ if [istarget "powerpc-*paired*"] {
29460 } elseif [istarget "ia64-*-*"] {
29461 set dg-do-what-default run
29462 } elseif [is-effective-target arm_neon_ok] {
29463 - lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp"
29464 + eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
29465 if [is-effective-target arm_neon_hw] {
29466 set dg-do-what-default run
29468 --- a/gcc/testsuite/lib/prune.exp
29469 +++ b/gcc/testsuite/lib/prune.exp
29470 @@ -57,3 +57,34 @@ if { [info procs prune_warnings] == "" }
29475 +# Extend prune_warnings (provided by DejaGNU itself) to prune more
29476 +# things. The prune_gcc_output function above is called only by some
29477 +# tests; prune_warnings is used by all.
29478 +if { [info procs prune_warnings_orig] == "" } {
29479 + rename prune_warnings prune_warnings_orig
29481 + proc prune_warnings { text } {
29482 + set text [prune_warnings_orig $text]
29484 + if { [ishost "sparc*-*-solaris2*"] } {
29485 + # When testing a compiler built for SPARC Solaris 2.9 (or earlier)
29486 + # on a host running Solaris 2.10 (or later), we get this warning
29487 + # from the static linker when building with g++:
29489 + # libm.so.1, needed by .../libstdc++.so may conflict with
29492 + # The warning is issued because libstdc++ is linked against
29493 + # libm.so.1 (from the Solaris 2.9 sysroot), whereas Solaris 2.10
29494 + # provides both libm.so.2 and libm.so.1. On Solaris 2.10, libc.so
29495 + # depends on libm.so.2, so all programs pull in libm.so.2.
29497 + # Pulling both libraries must in fact be harmless, as, otherwise,
29498 + # programs built for Solaris 2.9 would break on Solaris 2.10.
29499 + regsub -all "(^|\n)\[^\n\]*: warning: libm.so.1, needed by \[^\n\]*, may conflict with libm.so.2" $text "" text
29505 --- a/gcc/testsuite/lib/target-supports.exp
29506 +++ b/gcc/testsuite/lib/target-supports.exp
29507 @@ -491,6 +491,7 @@ proc check_profiling_available { test_wh
29508 || [istarget avr-*-*]
29509 || [istarget bfin-*-*]
29510 || [istarget powerpc-*-eabi*]
29511 + || [istarget powerpc-*-elf]
29512 || [istarget cris-*-*]
29513 || [istarget crisv32-*-*]
29514 || [istarget fido-*-elf]
29515 @@ -618,6 +619,18 @@ proc check_effective_target_static {} {
29519 +# Return 1 if compilation with -mpe-aligned-commons is error-free
29520 +# for trivial code, 0 otherwise.
29522 +proc check_effective_target_pe_aligned_commons {} {
29523 + if { [istarget *-*-cygwin*] || [istarget *-*-mingw*] } {
29524 + return [check_no_compiler_messages pe_aligned_commons object {
29526 + } "-mpe-aligned-commons"]
29531 # Return 1 if the target supports -fstack-protector
29532 proc check_effective_target_fstack_protector {} {
29533 return [check_runtime fstack_protector {
29534 @@ -727,6 +740,15 @@ proc check_effective_target_mips16_attri
29535 } [add_options_for_mips16_attribute ""]]
29538 +# Return 1 if the target supports long double larger than double when
29539 +# using the new ABI, 0 otherwise.
29541 +proc check_effective_target_mips_newabi_large_long_double { } {
29542 + return [check_no_compiler_messages mips_newabi_large_long_double object {
29543 + int dummy[sizeof(long double) > sizeof(double) ? 1 : -1];
29547 # Return 1 if the current multilib does not generate PIC by default.
29549 proc check_effective_target_nonpic { } {
29550 @@ -1416,6 +1438,18 @@ proc check_effective_target_arm32 { } {
29554 +# Return 1 if this is an ARM target that only supports aligned vector accesses
29555 +proc check_effective_target_arm_vect_no_misalign { } {
29556 + return [check_no_compiler_messages arm_vect_no_misalign assembly {
29557 + #if !defined(__arm__) \
29558 + || (defined(__ARMEL__) \
29559 + && (!defined(__thumb__) || defined(__thumb2__)))
29566 # Return 1 if this is an ARM target supporting -mfpu=vfp
29567 # -mfloat-abi=softfp. Some multilibs may be incompatible with these
29569 @@ -1430,18 +1464,110 @@ proc check_effective_target_arm_vfp_ok {
29573 -# Return 1 if this is an ARM target supporting -mfpu=neon
29574 -# -mfloat-abi=softfp. Some multilibs may be incompatible with these
29575 +# Return 1 if this is an ARM target supporting -mfpu=vfp
29576 +# -mfloat-abi=hard. Some multilibs may be incompatible with these
29579 -proc check_effective_target_arm_neon_ok { } {
29580 +proc check_effective_target_arm_hard_vfp_ok { } {
29581 if { [check_effective_target_arm32] } {
29582 - return [check_no_compiler_messages arm_neon_ok object {
29584 - } "-mfpu=neon -mfloat-abi=softfp"]
29585 + return [check_no_compiler_messages arm_hard_vfp_ok executable {
29586 + int main() { return 0;}
29587 + } "-mfpu=vfp -mfloat-abi=hard"]
29594 +# Add the options needed for NEON. We need either -mfloat-abi=softfp
29595 +# or -mfloat-abi=hard, but if one is already specified by the
29596 +# multilib, use it. Similarly, if a -mfpu option already enables
29597 +# NEON, do not add -mfpu=neon.
29599 +proc add_options_for_arm_neon { flags } {
29600 + if { ! [check_effective_target_arm_neon_ok] } {
29603 + global et_arm_neon_flags
29604 + return "$flags $et_arm_neon_flags"
29607 +# Return 1 if this is an ARM target supporting -mfpu=neon
29608 +# -mfloat-abi=softfp or equivalent options. Some multilibs may be
29609 +# incompatible with these options. Also set et_arm_neon_flags to the
29610 +# best options to add.
29612 +proc check_effective_target_arm_neon_ok_nocache { } {
29613 + global et_arm_neon_flags
29614 + set et_arm_neon_flags ""
29615 + if { [check_effective_target_arm32] } {
29616 + foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp"} {
29617 + if { [check_no_compiler_messages_nocache arm_neon_ok object {
29618 + #include "arm_neon.h"
29621 + set et_arm_neon_flags $flags
29630 +proc check_effective_target_arm_neon_ok { } {
29631 + return [check_cached_effective_target arm_neon_ok \
29632 + check_effective_target_arm_neon_ok_nocache]
29635 +# Add the options needed for NEON. We need either -mfloat-abi=softfp
29636 +# or -mfloat-abi=hard, but if one is already specified by the
29637 +# multilib, use it.
29639 +proc add_options_for_arm_neon_fp16 { flags } {
29640 + if { ! [check_effective_target_arm_neon_fp16_ok] } {
29643 + global et_arm_neon_fp16_flags
29644 + return "$flags $et_arm_neon_fp16_flags"
29647 +# Return 1 if this is an ARM target supporting -mfpu=neon-fp16
29648 +# -mfloat-abi=softfp or equivalent options. Some multilibs may be
29649 +# incompatible with these options. Also set et_arm_neon_flags to the
29650 +# best options to add.
29652 +proc check_effective_target_arm_neon_fp16_ok_nocache { } {
29653 + global et_arm_neon_fp16_flags
29654 + set et_arm_neon_fp16_flags ""
29655 + if { [check_effective_target_arm32] } {
29656 + # Always add -mfpu=neon-fp16, since there is no preprocessor
29657 + # macro for FP16 support.
29658 + foreach flags {"-mfpu=neon-fp16" "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
29659 + if { [check_no_compiler_messages_nocache arm_neon_fp16_ok object {
29660 + #include "arm_neon.h"
29663 + set et_arm_neon_fp16_flags $flags
29672 +proc check_effective_target_arm_neon_fp16_ok { } {
29673 + return [check_cached_effective_target arm_neon_fp16_ok \
29674 + check_effective_target_arm_neon_fp16_ok_nocache]
29677 +# Return 1 if this is an arm target using 32-bit instructions, but not thumb
29678 +proc check_effective_target_arm_not_thumb { } {
29679 + return [check_no_compiler_messages arm_not_thumb assembly {
29680 + #if !defined(__arm__) || defined(__thumb__)
29686 # Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be
29687 @@ -1455,6 +1581,17 @@ proc check_effective_target_arm_thumb1_o
29691 +# Return 1 is this is an ARM target where -mthumb causes Thumb-2 to be
29694 +proc check_effective_target_arm_thumb2_ok { } {
29695 + return [check_no_compiler_messages arm_thumb2_ok assembly {
29696 + #if !defined(__thumb2__)
29702 # Return 1 if the target supports executing NEON instructions, 0
29703 # otherwise. Cache the result.
29705 @@ -1469,7 +1606,7 @@ proc check_effective_target_arm_neon_hw
29706 : "0" (a), "w" (b));
29709 - } "-mfpu=neon -mfloat-abi=softfp"]
29710 + } [add_options_for_arm_neon ""]]
29713 # Return 1 if this is a ARM target with NEON enabled.
29714 @@ -1512,6 +1649,19 @@ proc check_effective_target_arm_eabi { }
29718 +# Return 1 if this is an ARM target supporting -mcpu=iwmmxt.
29719 +# Some multilibs may be incompatible with this option.
29721 +proc check_effective_target_arm_iwmmxt_ok { } {
29722 + if { [check_effective_target_arm32] } {
29723 + return [check_no_compiler_messages arm_iwmmxt_ok object {
29725 + } "-mcpu=iwmmxt"]
29731 # Return 1 if this is a PowerPC target with floating-point registers.
29733 proc check_effective_target_powerpc_fprs { } {
29734 @@ -1708,6 +1858,26 @@ proc check_effective_target_vect_shift {
29735 return $et_vect_shift_saved
29738 +# Return 1 if the target supports hardware vector shift operation for char.
29740 +proc check_effective_target_vect_shift_char { } {
29741 + global et_vect_shift_char_saved
29743 + if [info exists et_vect_shift_char_saved] {
29744 + verbose "check_effective_target_vect_shift_char: using cached result" 2
29746 + set et_vect_shift_char_saved 0
29747 + if { ([istarget powerpc*-*-*]
29748 + && ![istarget powerpc-*-linux*paired*])
29749 + || [check_effective_target_arm32] } {
29750 + set et_vect_shift_char_saved 1
29754 + verbose "check_effective_target_vect_shift_char: returning $et_vect_shift_char_saved" 2
29755 + return $et_vect_shift_char_saved
29758 # Return 1 if the target supports hardware vectors of long, 0 otherwise.
29760 # This can change for different subtargets so do not cache the result.
29761 @@ -2167,7 +2337,7 @@ proc check_effective_target_vect_no_alig
29762 if { [istarget mipsisa64*-*-*]
29763 || [istarget sparc*-*-*]
29764 || [istarget ia64-*-*]
29765 - || [check_effective_target_arm32] } {
29766 + || [check_effective_target_arm_vect_no_misalign] } {
29767 set et_vect_no_align_saved 1
29770 @@ -2281,6 +2451,24 @@ proc check_effective_target_vector_align
29771 return $et_vector_alignment_reachable_for_64bit_saved
29774 +# Return 1 if the target only requires element alignment for vector accesses
29776 +proc check_effective_target_vect_element_align { } {
29777 + global et_vect_element_align
29779 + if [info exists et_vect_element_align] {
29780 + verbose "check_effective_target_vect_elemetn_align: using cached result" 2
29782 + set et_vect_element_align 0
29783 + if { [istarget arm*-*-*] } {
29784 + set et_vect_element_align 1
29788 + verbose "check_effective_target_vect_element_align: returning $et_vect_element_align" 2
29789 + return $et_vect_element_align
29792 # Return 1 if the target supports vector conditional operations, 0 otherwise.
29794 proc check_effective_target_vect_condition { } {
29795 @@ -2476,7 +2664,8 @@ proc check_effective_target_section_anch
29796 verbose "check_effective_target_section_anchors: using cached result" 2
29798 set et_section_anchors_saved 0
29799 - if { [istarget powerpc*-*-*] } {
29800 + if { [istarget powerpc*-*-*]
29801 + || [istarget arm*-*-*] } {
29802 set et_section_anchors_saved 1
29805 --- a/gcc/timevar.def
29806 +++ b/gcc/timevar.def
29807 @@ -134,6 +134,7 @@ DEFTIMEVAR (TV_TREE_LOOP_IVOPTS , "
29808 DEFTIMEVAR (TV_PREDCOM , "predictive commoning")
29809 DEFTIMEVAR (TV_TREE_LOOP_INIT , "tree loop init")
29810 DEFTIMEVAR (TV_TREE_LOOP_FINI , "tree loop fini")
29811 +DEFTIMEVAR (TV_TREE_LOOP_PROMOTE , "tree loop index promotion")
29812 DEFTIMEVAR (TV_TREE_CH , "tree copy headers")
29813 DEFTIMEVAR (TV_TREE_SSA_UNCPROP , "tree SSA uncprop")
29814 DEFTIMEVAR (TV_TREE_SSA_TO_NORMAL , "tree SSA to normal")
29815 @@ -141,6 +142,7 @@ DEFTIMEVAR (TV_TREE_NRV , "tree NR
29816 DEFTIMEVAR (TV_TREE_COPY_RENAME , "tree rename SSA copies")
29817 DEFTIMEVAR (TV_TREE_SSA_VERIFY , "tree SSA verifier")
29818 DEFTIMEVAR (TV_TREE_STMT_VERIFY , "tree STMT verifier")
29819 +DEFTIMEVAR (TV_TREE_RLS , "tree local static removal")
29820 DEFTIMEVAR (TV_TREE_SWITCH_CONVERSION, "tree switch initialization conversion")
29821 DEFTIMEVAR (TV_CGRAPH_VERIFY , "callgraph verifier")
29822 DEFTIMEVAR (TV_DOM_FRONTIERS , "dominance frontiers")
29825 @@ -139,6 +139,7 @@ extern int flag_unroll_loops;
29826 extern int flag_unroll_all_loops;
29827 extern int flag_unswitch_loops;
29828 extern int flag_cprop_registers;
29829 +extern int flag_remove_local_statics;
29830 extern int time_report;
29831 extern int flag_ira_coalesce;
29832 extern int flag_ira_move_spills;
29833 --- a/gcc/tree-cfg.c
29834 +++ b/gcc/tree-cfg.c
29835 @@ -47,6 +47,7 @@ along with GCC; see the file COPYING3.
29836 #include "value-prof.h"
29837 #include "pointer-set.h"
29838 #include "tree-inline.h"
29839 +#include "target.h"
29841 /* This file contains functions for building the Control Flow Graph (CFG)
29842 for a function tree. */
29843 @@ -7052,6 +7053,9 @@ execute_warn_function_return (void)
29847 + if (!targetm.warn_func_result())
29850 /* If we have a path to EXIT, then we do return. */
29851 if (TREE_THIS_VOLATILE (cfun->decl)
29852 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0)
29853 --- a/gcc/tree-pass.h
29854 +++ b/gcc/tree-pass.h
29855 @@ -323,6 +323,7 @@ extern struct gimple_opt_pass pass_scev_
29856 extern struct gimple_opt_pass pass_empty_loop;
29857 extern struct gimple_opt_pass pass_record_bounds;
29858 extern struct gimple_opt_pass pass_graphite_transforms;
29859 +extern struct gimple_opt_pass pass_promote_indices;
29860 extern struct gimple_opt_pass pass_if_conversion;
29861 extern struct gimple_opt_pass pass_loop_distribution;
29862 extern struct gimple_opt_pass pass_vectorize;
29863 @@ -388,6 +389,7 @@ extern struct gimple_opt_pass pass_reass
29864 extern struct gimple_opt_pass pass_rebuild_cgraph_edges;
29865 extern struct gimple_opt_pass pass_build_cgraph_edges;
29866 extern struct gimple_opt_pass pass_reset_cc_flags;
29867 +extern struct gimple_opt_pass pass_remove_local_statics;
29870 extern struct ipa_opt_pass pass_ipa_inline;
29871 --- a/gcc/tree-sra.c
29872 +++ b/gcc/tree-sra.c
29873 @@ -274,6 +274,12 @@ sra_type_can_be_decomposed_p (tree type)
29874 != TYPE_PRECISION (TREE_TYPE (t))))
29877 + /* Disable optimization of bitfields on BITS_BIG_ENDIAN
29878 + architectures. SRA doesn't properly handle padding bits
29879 + at the bottom, see issue6713. */
29880 + if (DECL_BIT_FIELD (t) && BITS_BIG_ENDIAN)
29883 saw_one_field = true;
29887 +++ b/gcc/tree-ssa-loop-promote.c
29889 +/* Promotion of shorter-than-word-size loop indices.
29890 + Copyright (C) 2009 Free Software Foundation, Inc.
29892 +This file is part of GCC.
29894 +GCC is free software; you can redistribute it and/or modify it
29895 +under the terms of the GNU General Public License as published by the
29896 +Free Software Foundation; either version 3, or (at your option) any
29899 +GCC is distributed in the hope that it will be useful, but WITHOUT
29900 +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
29901 +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
29904 +You should have received a copy of the GNU General Public License
29905 +along with GCC; see the file COPYING3. If not see
29906 +<http://www.gnu.org/licenses/>. */
29908 +/* This pass finds loop indices that are declared as
29909 + shorter-than-word-size and replaces them with word-sized loop
29910 + indices. (It assumes that word-sized quantities are the most
29911 + efficient type on which to do arithmetic.) The loop optimization
29912 + machinery has a difficult time seeing through the casts required to
29913 + promote such indices to word-sized quantities for memory addressing
29914 + and/or preserving the semantics of the source language (such as C).
29915 + The transformation also helps eliminate unnecessary
29916 + {sign,zero}-extensions required for the same.
29918 + Although this is most naturally expressed as a loop optimization
29919 + pass, we choose to place this pass some ways before the loop
29920 + optimization passes proper, so that other scalar optimizations will
29921 + run on our "cleaned-up" code. This decision has the negative of
29922 + requiring us to build and destroy all the loop optimization
29925 + The algorithm is relatively simple. For each single-exit loop, we
29926 + identify the loop index variable. If the loop index variable is
29927 + shorter than the word size, then we have a candidate for promotion.
29928 + We determine whether the scalar evolution of the loop index fits a
29929 + particular pattern (incremented by 1, compared against a
29930 + similarly-typed loop bound, and only modified by a single increment
29931 + within the loop), as well as examining the uses of the loop index to
29932 + ensure we are able to safely promote those uses (e.g. the loop index
29933 + must not be stored to memory or passed to function calls). If these
29934 + conditions are satisfied, we create an appropriate word-sized type
29935 + and replace all uses and defs of the loop index variable with the new
29938 +#include "config.h"
29939 +#include "system.h"
29940 +#include "coretypes.h"
29943 +#include "toplev.h"
29946 +#include "hard-reg-set.h"
29947 +#include "obstack.h"
29948 +#include "basic-block.h"
29949 +#include "pointer-set.h"
29953 +#include "gimple.h"
29954 +#include "hashtab.h"
29955 +#include "diagnostic.h"
29956 +#include "tree-flow.h"
29957 +#include "tree-dump.h"
29958 +#include "cfgloop.h"
29959 +#include "flags.h"
29960 +#include "timevar.h"
29961 +#include "tree-pass.h"
29963 +struct promote_info {
29964 + /* The loop being analyzed. */
29965 + struct loop *loop;
29967 + /* The GIMPLE_COND controlling exit from the loop. */
29968 + gimple exit_expr;
29970 + /* The loop index variable's SSA_NAME that is defined in a phi node in
29971 + LOOP->HEADER. Note that this SSA_NAME may be different than the
29972 + one appearing in EXIT_EXPR. */
29973 + tree loop_index_name;
29975 + /* The bound of the loop. */
29978 + /* Whether we've warned about things with
29979 + warn_unsafe_loop_optimizations. */
29982 + /* LOOP_INDEX_NAME's underlying VAR_DECL. */
29985 + /* The types to which defs/uses of LOOP_INDEX_NAME are cast via
29987 + VEC(tree, heap) *cast_types;
29989 + /* The number of times we have seen a cast to the corresponding type
29990 + (as determined by types_compatible_p) in CAST_TYPES. */
29991 + VEC(int, heap) *cast_counts;
29993 + /* Whether LOOP_INDEX_NAME is suitable for promotion. */
29994 + bool can_be_promoted_p;
29996 + /* If CAN_BE_PROMOTED_P, the promoted type. */
29997 + tree promoted_type;
29999 + /* If CAN_BE_PROMOTED_P, the promoted VAR_DECL. */
30000 + tree promoted_var;
30003 +/* A set of `struct promote_info'. */
30005 +static struct pointer_set_t *promotion_info;
30007 +/* A set of all potentially promotable SSA_NAMEs, used for quick
30008 +decision-making during analysis. */
30010 +static struct pointer_set_t *promotable_names;
30012 +/* A map from SSA_NAMEs to the VAR_DECL to which they will be
30015 +static struct pointer_map_t *variable_map;
30017 +/* A set of the stmts that we have already rebuilt with promoted variables. */
30019 +static struct pointer_set_t *promoted_stmts;
30022 +/* Add CASTED to PI->CAST_TYPES if we haven't seen CASTED before. */
30025 +add_casted_type (struct promote_info *pi, tree casted)
30030 + /* For this information to be useful later, CASTED must be wider than
30031 + the type of the variable. */
30032 + if (TYPE_PRECISION (casted) <= TYPE_PRECISION (TREE_TYPE (pi->var_decl)))
30035 + for (i = 0; VEC_iterate (tree, pi->cast_types, i, type); i++)
30036 + if (types_compatible_p (casted, type))
30038 + int c = VEC_index(int, pi->cast_counts, i);
30039 + VEC_replace(int, pi->cast_counts, i, ++c);
30043 + /* Haven't see the type before. */
30044 + VEC_safe_push (tree, heap, pi->cast_types, casted);
30045 + VEC_safe_push (int, heap, pi->cast_counts, 1);
30048 +/* Return the most-casted-to type in PI->CAST_TYPES. Return an
30049 + appropriately signed variant of size_type_node if the variable wasn't
30050 + cast in some fashion. */
30053 +choose_profitable_promoted_type (struct promote_info *pi)
30057 + tree type = NULL_TREE;
30060 + for (i = 0; VEC_iterate (int, pi->cast_counts, i, count); i++)
30061 + if (count > maxuse)
30064 + type = VEC_index (tree, pi->cast_types, i);
30067 + if (type == NULL_TREE)
30071 + fprintf (dump_file, "Warning, failed to find upcast type for ");
30072 + print_generic_expr (dump_file, pi->loop_index_name, 0);
30073 + fprintf (dump_file, "\n");
30075 + return (TYPE_UNSIGNED (TREE_TYPE (pi->var_decl))
30077 + : signed_type_for (size_type_node));
30080 + return signed_type_for (type);
30083 +/* Intuit the loop index for LOOP from PHI. There must be a path that
30084 + only goes through NOP_EXPRs or CONVERT_EXPRs from the result of PHI
30085 + to one of the operands of COND. If such a path cannot be found,
30086 + return NULL_TREE. If LIMIT is not NULL and a path can be found,
30087 + store the other operand of COND into LIMIT. */
30090 +find_promotion_candidate_from_phi (struct loop *loop, gimple cond,
30091 + gimple phi, tree *limit)
30094 + tree result, candidate;
30096 + result = candidate = PHI_RESULT (phi);
30097 + /* Must be an integer variable. */
30098 + if (TREE_CODE (TREE_TYPE (candidate)) != INTEGER_TYPE)
30099 + return NULL_TREE;
30101 + op0 = gimple_cond_lhs (cond);
30102 + op1 = gimple_cond_rhs (cond);
30104 + /* See if there's a path from CANDIDATE to an operand of COND. */
30107 + use_operand_p use;
30108 + imm_use_iterator iui;
30109 + gimple use_stmt = NULL;
30111 + if (candidate == op0)
30113 + if (limit) *limit = op1;
30116 + if (candidate == op1)
30118 + if (limit) *limit = op0;
30122 + /* Find a single use in the loop header. Give up if there's
30123 + multiple ones. */
30124 + FOR_EACH_IMM_USE_FAST (use, iui, candidate)
30126 + gimple stmt = USE_STMT (use);
30128 + if (gimple_bb (stmt) == loop->header)
30134 + fprintf (dump_file, "Rejecting ");
30135 + print_generic_expr (dump_file, candidate, 0);
30136 + fprintf (dump_file, " because it has multiple uses in the loop header (bb #%d).\n",
30137 + loop->header->index);
30138 + fprintf (dump_file, "first use: ");
30139 + print_gimple_stmt (dump_file, use_stmt, 0, 0);
30140 + fprintf (dump_file, "\nsecond use: ");
30141 + print_gimple_stmt (dump_file, stmt, 0, 0);
30142 + fprintf (dump_file, "\n(possibly more, but unanalyzed)\n");
30144 + return NULL_TREE;
30151 + /* No uses in the loop header, bail. */
30152 + if (use_stmt == NULL)
30153 + return NULL_TREE;
30155 + if (gimple_code (use_stmt) != GIMPLE_ASSIGN
30156 + || TREE_CODE (gimple_assign_lhs (use_stmt)) != SSA_NAME
30157 + || (gimple_assign_rhs_code (use_stmt) != NOP_EXPR
30158 + && gimple_assign_rhs_code (use_stmt) != CONVERT_EXPR))
30162 + fprintf (dump_file, "Rejecting ");
30163 + print_generic_expr (dump_file, candidate, 0);
30164 + fprintf (dump_file, " because of use in ");
30165 + print_gimple_stmt (dump_file, use_stmt, 0, 0);
30166 + fprintf (dump_file, "\n");
30168 + return NULL_TREE;
30171 + candidate = gimple_assign_lhs (use_stmt);
30174 + /* CANDIDATE is now what we believe to be the loop index variable. There
30175 + are two possibilities:
30177 + - CANDIDATE is not the "true" loop index variable, but rather is a
30178 + promoted version of RESULT, done for purposes of satisfying a
30179 + language's semantics;
30181 + - CANDIDATE is the "true" loop index variable. */
30182 + if (!types_compatible_p (TREE_TYPE (result), TREE_TYPE (candidate)))
30183 + candidate = result;
30185 + /* The type of candidate must be "short" to consider promoting it. */
30186 + if (TREE_CODE (TREE_TYPE (candidate)) != INTEGER_TYPE
30187 + || TYPE_PRECISION (TREE_TYPE (candidate)) >= TYPE_PRECISION (size_type_node))
30188 + return NULL_TREE;
30190 + return candidate;
30193 +/* Find the loop index variable of LOOP. LOOP's exit is controlled by
30194 + the COND_EXPR EXPR. IF we can't determine what the loop index
30195 + variable is, or EXPR does not appear to be analyzable, then return
30199 +find_promotion_candidate (struct loop *loop, gimple cond, tree *limit)
30201 + tree candidate = NULL_TREE;
30202 + gimple_stmt_iterator gsi;
30204 + switch (gimple_cond_code (cond))
30214 + return NULL_TREE;
30217 + /* We'd like to examine COND and intuit the loop index variable from
30218 + there. Instead, we're going to start from the phi nodes in BB and
30219 + attempt to work our way forwards to one of the operands of COND,
30220 + since starting from COND might yield an upcast loop index. If we
30221 + find multiple phi nodes whose results reach COND, then give up. */
30222 + for (gsi = gsi_start_phis (loop->header); !gsi_end_p (gsi); gsi_next (&gsi))
30224 + gimple phi = gsi_stmt (gsi);
30225 + tree t = find_promotion_candidate_from_phi (loop, cond, phi, limit);
30227 + if (t == NULL_TREE)
30229 + else if (candidate == NULL_TREE)
30235 + fprintf (dump_file, "Can't find a candidate from ");
30236 + print_gimple_stmt (dump_file, cond, 0, 0);
30237 + fprintf (dump_file, "\n because too many phi node results reach the condition.\n");
30239 + return NULL_TREE;
30243 + return candidate;
30246 +/* Return true if X is something that could be promoted. */
30249 +could_be_promoted (tree x)
30251 + return (TREE_CODE (x) == INTEGER_CST
30252 + || (TREE_CODE (x) == SSA_NAME
30253 + && pointer_set_contains (promotable_names, x)));
30256 +/* Examine the RHS of STMT's suitability with respect to being able to
30260 +check_rhs_for_promotability (struct promote_info *pi, tree var, gimple stmt,
30263 + enum tree_code subcode = gimple_assign_rhs_code (stmt);
30279 + tree op0 = gimple_assign_rhs1 (stmt);
30280 + tree op1 = gimple_assign_rhs2 (stmt);
30282 + ok = ((op0 == var && could_be_promoted (op1))
30283 + || (op1 == var && could_be_promoted (op0)));
30287 + if (gimple_expr_type (stmt) == NULL
30288 + || gimple_expr_type (stmt) == void_type_node)
30291 + /* This is conservative; it's possible that these sorts of nodes
30292 + could be promoted, but we'd have to be very careful about
30293 + checking in which parts of the COND_EXPR the promotable
30294 + variable(s) are. */
30299 + tree expr = gimple_assign_rhs1 (stmt);
30300 + ok = (expr == var || could_be_promoted (expr));
30303 + case INTEGER_CST:
30306 + case CONVERT_EXPR:
30309 + add_casted_type (pi, gimple_expr_type (stmt));
30312 + /* Fallthrough. */
30321 +/* Analyze the loop index VAR for promotability. The rules for
30322 + promotability are:
30326 + - The underlying variable may be used in NOP_EXPRs.
30328 + - The underlying variable may be used in simple arithmmetic
30329 + expressions so long as the other parts are potentially promotable
30330 + variables or constants (so we don't go willy-nilly on promoting
30333 + - The underlying variable may not be stored to memory.
30335 + - All uses must occur inside the loop.
30339 + - The underlying variable may not be loaded from memory; and
30341 + - The underlying variable may only be formed from expressions
30342 + involving potentially promotable varibles or constants.
30344 + Note that defs may occur outside of the loop; we do this to handle
30345 + initial conditions before entering the loop. */
30348 +analyze_loop_index_uses (tree var, struct promote_info *pi)
30350 + imm_use_iterator iui;
30351 + use_operand_p use;
30352 + gimple bad_stmt = NULL;
30353 + const char *reason = NULL;
30355 + FOR_EACH_IMM_USE_FAST (use, iui, var)
30358 + gimple use_stmt = USE_STMT (use);
30360 + /* Uses must exist only within the loop. */
30361 + bb = gimple_bb (use_stmt);
30365 + fprintf (dump_file, "Checking ");
30366 + print_gimple_stmt (dump_file, use_stmt, 0, 0);
30367 + fprintf (dump_file, "\n");
30370 + if (!flow_bb_inside_loop_p (pi->loop, bb))
30372 + bad_stmt = use_stmt;
30373 + reason = " is involved in stmt outside loop ";
30377 + /* We cannot store the index to memory. */
30378 + if (gimple_references_memory_p (use_stmt))
30380 + bad_stmt = use_stmt;
30381 + reason = " is stored to memory in ";
30385 + if (gimple_code (use_stmt) == GIMPLE_CALL)
30387 + /* We cannot pass the variable to a function. */
30388 + bad_stmt = use_stmt;
30389 + reason = " is passed to function in ";
30392 + else if (gimple_code (use_stmt) == GIMPLE_ASSIGN)
30394 + tree lhs = gimple_assign_lhs (use_stmt);
30396 + if (!check_rhs_for_promotability (pi, var, use_stmt,
30397 + /*is_assign=*/false))
30399 + bad_stmt = use_stmt;
30400 + reason = " is involved in non-promotable expression ";
30403 + else if ((TREE_CODE_CLASS (gimple_assign_rhs_code (use_stmt)) == tcc_binary
30404 + || gimple_assign_rhs_code (use_stmt) == SSA_NAME)
30405 + && !could_be_promoted (lhs))
30407 + bad_stmt = use_stmt;
30408 + reason = " is being assigned to non-promotable variable ";
30412 + else if (gimple_code (use_stmt) != GIMPLE_COND
30413 + && gimple_code (use_stmt) != GIMPLE_PHI)
30415 + /* Use of the variable in some statement we don't know how to
30417 + bad_stmt = use_stmt;
30418 + reason = " is used in unanalyzable expression in ";
30423 + if (bad_stmt && reason)
30427 + fprintf (dump_file, "Loop index ");
30428 + print_generic_expr (dump_file, var, 0);
30429 + fprintf (dump_file, "%s", reason);
30430 + print_gimple_stmt (dump_file, bad_stmt, 0, 0);
30431 + fprintf (dump_file, "\n");
30433 + pi->can_be_promoted_p = false;
30437 +/* Check that the uses and def of VAR, defined in STMT, conform to the
30438 + rules given above. */
30441 +analyze_loop_index (tree var, gimple stmt, void *data)
30443 + struct promote_info *pi = (struct promote_info *) data;
30447 + fprintf (dump_file, "Analyzing loop index ");
30448 + print_generic_expr (dump_file, var, 0);
30449 + fprintf (dump_file, " defined in ");
30450 + print_gimple_stmt (dump_file, stmt, 0, 0);
30451 + fprintf (dump_file, "\n");
30454 + /* Check the definition. */
30455 + switch (gimple_code (stmt))
30458 + /* Phi nodes are OK. */
30461 + case GIMPLE_ASSIGN:
30462 + if (!check_rhs_for_promotability (pi, var, stmt,
30463 + /*is_assign=*/true))
30465 + /* Fallthrough. */
30468 + /* Something we can't handle or the variable is being loaded from
30470 + pi->can_be_promoted_p = false;
30474 + if (gimple_code (stmt) == GIMPLE_PHI)
30478 + for (i = 0; i < gimple_phi_num_args (stmt); i++)
30480 + tree arg = PHI_ARG_DEF (stmt, i);
30482 + if (TREE_CODE (arg) == SSA_NAME)
30483 + pointer_set_insert (promotable_names, arg);
30486 + analyze_loop_index_uses (PHI_RESULT (stmt), pi);
30489 + analyze_loop_index_uses (var, pi);
30491 + /* Only worth continuing if we think the loop index can be
30496 + fprintf (dump_file, "Done analyzing ");
30497 + print_generic_expr (dump_file, var, 0);
30498 + fprintf (dump_file, " defined in ");
30499 + print_gimple_stmt (dump_file, stmt, 0, 0);
30500 + fprintf (dump_file, "...%s to analyze\n\n",
30501 + pi->can_be_promoted_p ? "continuing" : "not continuing");
30503 + return !pi->can_be_promoted_p;
30506 +/* Determine whether T is an INTEGER_CST or a single-use SSA_NAME
30507 + defined as the result of a NOP_EXPR or CONVERT_EXPR. Return the
30508 + operand of the NOP_EXPR or CONVERT_EXPR if so. */
30511 +upcast_operand_p (tree t)
30515 + if (TREE_CODE (t) == INTEGER_CST)
30518 + if (TREE_CODE (t) != SSA_NAME
30519 + || !has_single_use (t))
30520 + return NULL_TREE;
30522 + def = SSA_NAME_DEF_STMT (t);
30523 + if (gimple_code (def) != GIMPLE_ASSIGN)
30524 + return NULL_TREE;
30526 + if (gimple_assign_rhs_code (def) != CONVERT_EXPR
30527 + && gimple_assign_rhs_code (def) != NOP_EXPR)
30528 + return NULL_TREE;
30530 + return gimple_assign_rhs1 (def);
30533 +/* Check for the idiom:
30536 + unsigned short x.2, y.2, tmp;
30538 + x.2 = (unsigned short) x;
30539 + y.2 = (unsigned short) y;
30543 + which is generated by convert for avoiding signed arithmetic
30544 + overflow. RHS is TMP in the above statement. If RHS is
30545 + defined via such an idiom, store x and y into *OP0 and *OP1,
30546 + respectively. We permit y.2 to be a constant if necessary. */
30549 +signed_arithmetic_overflow_idiom_p (tree rhs, tree *op0, tree *op1)
30551 + gimple op_stmt = SSA_NAME_DEF_STMT (rhs);
30553 + bool yes = false;
30554 + enum tree_code code;
30556 + if (!has_single_use (rhs)
30557 + || gimple_code (op_stmt) != GIMPLE_ASSIGN)
30560 + /* This could probably profitably be expanded to consider
30561 + MINUS_EXPR, MULT_EXPR, etc. */
30562 + code = gimple_assign_rhs_code (op_stmt);
30563 + if (code != PLUS_EXPR)
30565 + x2 = gimple_assign_rhs1 (op_stmt);
30566 + y2 = gimple_assign_rhs2 (op_stmt);
30568 + x2 = upcast_operand_p (x2);
30569 + if (x2 == NULL_TREE)
30571 + y2 = upcast_operand_p (y2);
30572 + if (y2 == NULL_TREE)
30583 +/* Simple wrapper around flow_bb_inside_loop_p that handles NULL
30584 + statements and initial definitions of variables. */
30587 +stmt_in_loop_p (gimple t, struct loop *loop)
30594 + bb = gimple_bb (t);
30598 + return flow_bb_inside_loop_p (loop, bb);
30601 +/* The loop index should have a specific usage pattern:
30603 + - It should be defined in a phi node with two incoming values:
30605 + LI_phi = PHI (LI_out, LI_in)
30607 + - One incoming value, LI_out, should be from outside the loop.
30609 + - The other incoming value, LI_in, should be defined thusly:
30611 + LI_in = LI_phi + increment
30613 + - increment should be 1. We permit other increments with
30614 + -funsafe-loop-optimizations.
30616 + - Finally, in the comparison to exit the loop, the loop index must be
30617 + compared against a variable that has a type at least as precise as
30618 + the loop index's type. For instance, something like:
30623 + for (i = 0; i < limit; i++) ...
30625 + would not be permitted. */
30628 +analyze_loop_index_definition_pattern (struct promote_info *pi)
30630 + gimple phi = SSA_NAME_DEF_STMT (pi->loop_index_name);
30631 + bool ok = false, warn = false;
30633 + bool inside0, inside1;
30634 + gimple def0, def1;
30635 + tree op0, op1, increment = NULL_TREE;
30637 + if (gimple_code (phi) != GIMPLE_PHI
30638 + || gimple_phi_num_args (phi) != 2)
30641 + in0 = PHI_ARG_DEF (phi, 0);
30642 + in1 = PHI_ARG_DEF (phi, 1);
30644 + /* Figure out which value comes from outside the loop. */
30645 + def0 = TREE_CODE (in0) == SSA_NAME ? SSA_NAME_DEF_STMT (in0) : NULL;
30646 + def1 = TREE_CODE (in1) == SSA_NAME ? SSA_NAME_DEF_STMT (in1) : NULL;
30648 + inside0 = stmt_in_loop_p (def0, pi->loop);
30649 + inside1 = stmt_in_loop_p (def1, pi->loop);
30651 + if (inside0 && inside1)
30653 + else if (inside0)
30663 + else if (!inside1)
30666 + /* IN0 comes from outside the loop, IN1 from inside. Analyze IN1. */
30667 + if (gimple_code (def1) != GIMPLE_ASSIGN)
30670 + switch (gimple_assign_rhs_code (def1))
30672 + case CONVERT_EXPR:
30674 + if (!signed_arithmetic_overflow_idiom_p (gimple_assign_rhs1 (def1),
30679 + op0 = gimple_assign_rhs1 (def1);
30680 + op1 = gimple_assign_rhs2 (def1);
30683 + bool op0_li = op0 == PHI_RESULT (phi);
30684 + bool op1_li = op1 == PHI_RESULT (phi);
30685 + if (op0_li && op1_li)
30686 + /* This is weird, and definitely is not a case we can support
30687 + for promotion. */
30702 + /* Check that the exit condition for the loop is OK. */
30704 + enum tree_code code = gimple_cond_code (pi->exit_expr);
30706 + op0 = gimple_cond_lhs (pi->exit_expr);
30707 + op1 = gimple_cond_rhs (pi->exit_expr);
30709 + if (op0 == pi->loop_limit)
30714 + code = swap_tree_comparison (code);
30717 + if (code != LT_EXPR && code != LE_EXPR)
30720 + if (!types_compatible_p (TREE_TYPE (pi->loop_index_name),
30721 + TREE_TYPE (pi->loop_limit)))
30723 + switch (TREE_CODE (pi->loop_limit))
30725 + case INTEGER_CST:
30726 + if (!int_fits_type_p (pi->loop_limit,
30727 + TREE_TYPE (pi->loop_index_name)))
30732 + tree v = pi->loop_limit;
30733 + gimple def = SSA_NAME_DEF_STMT (v);
30735 + /* Backtrack through CONVERT_EXPRs and/or NOP_EXPRs to
30736 + determine if the variables "started out" as the same
30738 + while (gimple_code (def) == GIMPLE_ASSIGN)
30740 + enum tree_code rhs_code = gimple_assign_rhs_code (def);
30742 + if (rhs_code != NOP_EXPR && rhs_code != CONVERT_EXPR)
30745 + v = gimple_assign_rhs1 (def);
30746 + def = SSA_NAME_DEF_STMT (v);
30748 + /* Permit comparisons between non-compatible types with
30749 + flag_unsafe_loop_optimizations, since we can assume the
30750 + loop index does not overflow. */
30751 + if (types_compatible_p (TREE_TYPE (pi->loop_index_name),
30753 + || flag_unsafe_loop_optimizations)
30755 + /* Fallthrough. */
30763 + if (increment == NULL_TREE)
30765 + if (TREE_CODE (increment) != INTEGER_CST
30766 + || compare_tree_int (increment, 1) != 0)
30769 + if (!flag_unsafe_loop_optimizations)
30775 + if (warn && !pi->warned)
30777 + pi->warned = true;
30778 + /* We can promote unsigned indices only if -funsafe-loop-optimizations
30779 + is in effect, since the user might be depending on the modulo
30780 + wraparound behavior of unsigned types. */
30781 + if (warn_unsafe_loop_optimizations)
30783 + const char *wording;
30785 + wording = (flag_unsafe_loop_optimizations
30786 + ? N_("assuming that the loop counter does not overflow")
30787 + : N_("cannot optimize loop, the loop counter may overflow"));
30788 + warning (OPT_Wunsafe_loop_optimizations, "%s", gettext (wording));
30795 +/* Analyze the loop associated with PI_ to see if its loop index can be
30799 +analyze_loop (const void *pi_, void *data)
30801 + struct promote_info *pi = CONST_CAST (struct promote_info *,
30802 + (const struct promote_info *) pi_);
30803 + bool *changed = (bool *) data;
30805 + /* We previously determined we can't promote this; go ahead and
30806 + continue iterating. */
30807 + if (pi->loop_index_name == NULL_TREE)
30810 + /* Assume we can always promote the loop index, even if it doesn't
30812 + pi->can_be_promoted_p = true;
30816 + fprintf (dump_file, "Analyzing ");
30817 + print_generic_expr (dump_file, pi->loop_index_name, 0);
30818 + fprintf (dump_file, "\n");
30821 + if (pi->loop_index_name
30822 + && analyze_loop_index_definition_pattern (pi))
30824 + /* Clear any previously gathered information. */
30825 + VEC_truncate (tree, pi->cast_types, 0);
30826 + VEC_truncate (int, pi->cast_counts, 0);
30828 + walk_use_def_chains (pi->loop_index_name, analyze_loop_index, pi, false);
30831 + pi->can_be_promoted_p = false;
30833 + /* If we determined the loop index is used in strange ways, clear it
30834 + so we don't examine it again. */
30835 + if (!pi->can_be_promoted_p)
30836 + pi->loop_index_name = NULL_TREE;
30838 + /* Let our caller know whether to re-do the analysis. */
30839 + *changed = *changed || !pi->can_be_promoted_p;
30840 + /* Continue if PI is promotable. */
30841 + return pi->can_be_promoted_p;
30844 +/* Add PI_->LOOP_INDEX_NAME to the set of variables, DATA, that we are
30845 + considering for promotion. */
30848 +add_variable (const void *pi_, void *data ATTRIBUTE_UNUSED)
30850 + const struct promote_info *pi = (const struct promote_info *) pi_;
30851 + struct pointer_set_t *pset = (struct pointer_set_t *) data;
30854 + if (pi->loop_index_name != NULL_TREE)
30856 + presentp = pointer_set_insert (pset, pi->loop_index_name);
30857 + gcc_assert (!presentp);
30860 + /* Continue traversal. */
30864 +/* For each promotable variable:
30866 + - create a new, promoted VAR_DECL;
30868 + - walk through all the uses and defs and create new statements using
30869 + the promoted variables. We don't create new phi nodes; post-pass
30870 + SSA update will handle those for us. */
30872 +/* Make dump files readable. */
30873 +#define PROMOTED_VAR_SUFFIX ".promoted"
30875 +/* Create a variable NAME with TYPE and do the necessary work to inform
30876 + the SSA machinery about it. */
30879 +create_pli_var (tree type, char *name)
30881 + tree var = create_tmp_var (type, name);
30882 + create_var_ann (var);
30883 + mark_sym_for_renaming (var);
30884 + add_referenced_var (var);
30888 +/* Associate the SSA_NAME VAR with the promoted variable DATA. */
30891 +associate_name_with_var (tree var, gimple def_stmt, void *data)
30893 + tree promoted_var = (tree) data;
30896 + gcc_assert (promoted_var != NULL_TREE);
30898 + if (gimple_code (def_stmt) == GIMPLE_PHI)
30899 + var = PHI_RESULT (def_stmt);
30901 + p = pointer_map_insert (variable_map, var);
30907 + fprintf (dump_file, "Associating ");
30908 + print_generic_expr (dump_file, var, 0);
30909 + fprintf (dump_file, " with ");
30910 + print_generic_expr (dump_file, promoted_var, 0);
30911 + fprintf (dump_file, "\n\n");
30913 + *(tree *)p = promoted_var;
30916 + /* Continue traversal. */
30920 +/* Create a promoted variable for the variable from PI_. */
30923 +create_promoted_variable (const void *pi_, void *data ATTRIBUTE_UNUSED)
30925 + struct promote_info *pi = CONST_CAST (struct promote_info *,
30926 + (const struct promote_info *) pi_);
30928 + if (pi->can_be_promoted_p)
30930 + tree type = choose_profitable_promoted_type (pi);
30931 + tree orig_name = DECL_NAME (pi->var_decl);
30932 + size_t id_len = IDENTIFIER_LENGTH (orig_name);
30933 + size_t name_len = id_len + strlen (PROMOTED_VAR_SUFFIX) + 1;
30936 + name = (char *) alloca (name_len);
30937 + strcpy (name, IDENTIFIER_POINTER (orig_name));
30938 + strcpy (name + id_len, PROMOTED_VAR_SUFFIX);
30940 + pi->promoted_type = type;
30941 + pi->promoted_var = create_pli_var (type, name);
30945 + fprintf (dump_file, "Created new variable ");
30946 + print_generic_expr (dump_file, pi->promoted_var, 0);
30947 + fprintf (dump_file, " to stand in for ");
30948 + print_generic_expr (dump_file, pi->loop_index_name, 0);
30949 + fprintf (dump_file, "\n\n");
30952 + walk_use_def_chains (pi->loop_index_name,
30953 + associate_name_with_var,
30954 + pi->promoted_var, false);
30957 + /* Continue traversal. */
30961 +/* Rebuild T with newly promoted variables; STMT is the original
30962 + statement in which T appeared and may be equivalent to T. TYPE is
30963 + non-null when rebuilding the rhs of a GIMPLE_ASSIGN and indicates the
30964 + type of the lhs. */
30967 +rebuild_tree_with_promotion (tree t, gimple stmt, tree type,
30968 + gimple_stmt_iterator gsi,
30969 + struct promote_info *pi)
30973 + switch (TREE_CODE (t))
30976 + case CONVERT_EXPR:
30978 + tree pvar = rebuild_tree_with_promotion (TREE_OPERAND (t, 0), stmt, type, gsi, pi);
30980 + if (types_compatible_p (type, TREE_TYPE (pvar)))
30983 + return build1 (TREE_CODE (t), type, pvar);
30985 + case INTEGER_CST:
30987 + return build_int_cst_wide (pi->promoted_type,
30988 + TREE_INT_CST_LOW (t),
30989 + TREE_INT_CST_HIGH (t));
30993 + tree orig_op0 = TREE_OPERAND (t, 0);
30994 + op0 = rebuild_tree_with_promotion (orig_op0, stmt, type, gsi, pi);
30995 + gcc_assert (orig_op0 != op0);
30996 + TREE_OPERAND (t, 0) = op0;
31002 + type = pi->promoted_type;
31003 + goto binary_expr;
31010 + type = TREE_TYPE (t);
31012 + op0 = TREE_OPERAND (t, 0);
31013 + op1 = TREE_OPERAND (t, 1);
31014 + op0 = rebuild_tree_with_promotion (op0, stmt, type, gsi, pi);
31015 + op1 = rebuild_tree_with_promotion (op1, stmt, type, gsi, pi);
31016 + return build2 (TREE_CODE (t), type, op0, op1);
31019 + void **p = pointer_map_contains (variable_map, t);
31023 + /* This is unexpected, but it does happen if we were dealing
31024 + with COND_EXPRs and such. Just go ahead and create a
31025 + temporary for it. */
31026 + if (types_compatible_p (TREE_TYPE (t), pi->promoted_type)
31027 + || SSA_NAME_DEF_STMT (t) == stmt)
31030 + goto insert_cast;
31033 + return *(tree *)p;
31042 + tree to_upcast = t;
31044 + /* If we are dealing with a memory reference, then we can't have
31045 + wrap it in a NOP_EXPR; we need to load the value from memory
31046 + first, then convert it. */
31047 + if (!is_gimple_reg (to_upcast))
31049 + tree tmp = create_pli_var (TREE_TYPE (to_upcast),
31050 + CONST_CAST (char *, "loadtmp"));
31051 + gimple stmt = gimple_build_assign (tmp, to_upcast);
31052 + gsi_insert_before (&gsi, stmt, GSI_SAME_STMT);
31056 + tmp = create_pli_var (pi->promoted_type,
31057 + CONST_CAST (char *, "promotetmp"));
31058 + nop = build1 (NOP_EXPR, pi->promoted_type, to_upcast);
31059 + cast = gimple_build_assign (tmp, nop);
31062 + fprintf (dump_file, "Inserting cast ");
31063 + print_gimple_stmt (dump_file, cast, 0, 0);
31064 + fprintf (dump_file, " prior to ");
31065 + print_gimple_stmt (dump_file, stmt, 0, 0);
31066 + fprintf (dump_file, "\n");
31068 + gsi_insert_before (&gsi, cast, GSI_SAME_STMT);
31074 +/* Split E and place STMT in the block created by doing so. */
31077 +insert_along_edge (gimple stmt, edge e)
31079 + basic_block bb = split_edge (e);
31081 + gimple_set_bb (stmt, bb);
31082 + set_bb_seq (bb, gimple_seq_alloc_with_stmt (stmt));
31085 +/* Rebuild STMT, which contains uses or a def of the promotable variable
31086 + associated with PI. */
31089 +rebuild_with_promotion (gimple stmt, struct promote_info *pi)
31091 + gimple_stmt_iterator gsi;
31093 + if (pointer_set_insert (promoted_stmts, stmt))
31098 + fprintf (dump_file, "Rebuilding stmt ");
31099 + print_gimple_stmt (dump_file, stmt, 0, 0);
31100 + fprintf (dump_file, "\n");
31103 + gsi = gsi_for_stmt (stmt);
31105 + switch (gimple_code (stmt))
31107 + case GIMPLE_ASSIGN:
31109 + enum tree_code subcode = gimple_assign_rhs_code (stmt);
31110 + enum tree_code newcode = subcode;
31111 + tree lhs = gimple_assign_lhs (stmt);
31112 + tree rhs1 = gimple_assign_rhs1 (stmt);
31113 + tree rhs2 = gimple_assign_rhs2 (stmt);
31117 + /* If we are defining a promotable variable, check for special
31119 + v = pointer_map_contains (variable_map, lhs);
31121 + && *(tree *)v == pi->promoted_var
31122 + && (subcode == NOP_EXPR || subcode == CONVERT_EXPR)
31123 + && signed_arithmetic_overflow_idiom_p (rhs1, &x, &y))
31127 + if (TYPE_PRECISION (TREE_TYPE (rhs1))
31128 + >= TYPE_PRECISION (pi->promoted_type))
31131 + /* It's possible that we've already promoted the operands of
31132 + one or both of the NOP_EXPRs. In that case, we can
31133 + bypass the logic below and go straight to rebuilding the
31134 + rhs that we really want to transform. */
31135 + if (TREE_CODE (x) == VAR_DECL
31136 + || TREE_CODE (y) == VAR_DECL)
31138 + xp = pointer_map_contains (variable_map, x);
31139 + yp = pointer_map_contains (variable_map, y);
31141 + /* Nothing to see here. */
31142 + if (!types_compatible_p (TREE_TYPE (x),
31144 + || (xp == NULL && yp == NULL))
31146 + x = (xp == NULL ? NULL_TREE : *(tree *)xp);
31147 + y = (yp == NULL ? NULL_TREE : *(tree *)yp);
31149 + if (x != pi->promoted_var && y != pi->promoted_var)
31153 + newcode = PLUS_EXPR;
31158 + fprintf (dump_file, "Substituting ");
31159 + print_generic_expr (dump_file, x, 0);
31160 + fprintf (dump_file, " + ");
31161 + print_generic_expr (dump_file, y, 0);
31162 + fprintf (dump_file, " for rhs of original statement\n");
31169 + lhs = rebuild_tree_with_promotion (lhs, stmt, NULL, gsi, pi);
31170 + rhs1 = rebuild_tree_with_promotion (rhs1, stmt, NULL, gsi, pi);
31172 + rhs2 = rebuild_tree_with_promotion (rhs2, stmt, NULL, gsi, pi);
31174 + if (newcode != subcode)
31176 + gimple newstmt = gimple_build_assign_with_ops (newcode,
31177 + lhs, rhs1, rhs2);
31178 + gsi_replace (&gsi, newstmt, true);
31183 + gimple_assign_set_lhs (stmt, lhs);
31184 + gimple_assign_set_rhs1 (stmt, rhs1);
31186 + gimple_assign_set_rhs2 (stmt, rhs2);
31190 + case GIMPLE_COND:
31192 + tree lhs = gimple_cond_lhs (stmt);
31193 + tree rhs = gimple_cond_rhs (stmt);
31195 + lhs = rebuild_tree_with_promotion (lhs, stmt, NULL, gsi, pi);
31196 + rhs = rebuild_tree_with_promotion (rhs, stmt, NULL, gsi, pi);
31198 + gimple_cond_set_lhs (stmt, lhs);
31199 + gimple_cond_set_rhs (stmt, rhs);
31205 + bool promoted_result = could_be_promoted (PHI_RESULT (stmt));
31207 + for (i = 0; i < gimple_phi_num_args (stmt); i++)
31209 + tree var = gimple_phi_arg_def (stmt, i);
31210 + edge e = gimple_phi_arg_edge (stmt, i);
31211 + gimple assign = NULL;
31213 + if (TREE_CODE (var) == INTEGER_CST && promoted_result)
31215 + tree cst = build_int_cst_wide (pi->promoted_type,
31216 + TREE_INT_CST_LOW (var),
31217 + TREE_INT_CST_HIGH (var));
31219 + assign = gimple_build_assign (pi->promoted_var, cst);
31220 + insert_along_edge (assign, e);
31222 + else if (TREE_CODE (var) == SSA_NAME
31223 + && SSA_NAME_VAR (var) == pi->var_decl
31224 + && !promoted_result)
31226 + tree t = create_pli_var (TREE_TYPE (PHI_RESULT (stmt)),
31227 + CONST_CAST (char *, "promotetmp"));
31229 + assign = gimple_build_assign_with_ops (CONVERT_EXPR,
31230 + t, pi->promoted_var,
31233 + name = make_ssa_name (t, assign);
31234 + gimple_assign_set_lhs (assign, name);
31236 + insert_along_edge (assign, e);
31237 + SET_PHI_ARG_DEF (stmt, i, name);
31243 + gcc_unreachable ();
31248 + fprintf (dump_file, "Converted stmt ");
31249 + print_gimple_stmt (dump_file, stmt, 0, 0);
31250 + fprintf (dump_file, "\n\n");
31252 + update_stmt (stmt);
31255 +/* Helper function for promote_variable that walks over use/def
31259 +promote_variable_1 (tree var, gimple stmt, void *data)
31261 + struct promote_info *pi = (struct promote_info *) data;
31262 + imm_use_iterator imi;
31265 + rebuild_with_promotion (stmt, pi);
31267 + if (gimple_code (stmt) == GIMPLE_PHI)
31268 + var = PHI_RESULT (stmt);
31270 + if (could_be_promoted (var))
31271 + FOR_EACH_IMM_USE_STMT (use_stmt, imi, var)
31273 + rebuild_with_promotion (use_stmt, pi);
31279 +/* Convert all uses and defs of PI_->LOOP_INDEX_NAME as linked by
31280 + use-def chains to uses and defs of PI_->PROMOTED_VAR. */
31283 +promote_variable (const void *pi_, void *data ATTRIBUTE_UNUSED)
31285 + const struct promote_info *pi = (const struct promote_info *) pi_;
31287 + if (pi->can_be_promoted_p)
31289 + walk_use_def_chains (pi->loop_index_name, promote_variable_1,
31290 + CONST_CAST (struct promote_info *, pi), false);
31293 + /* Continue traversal. */
31297 +/* Free PI_ and its associated data. */
31300 +free_pi_entries (const void *pi_, void *data ATTRIBUTE_UNUSED)
31302 + struct promote_info *pi = CONST_CAST (struct promote_info *,
31303 + (const struct promote_info *) pi_);
31305 + VEC_free (tree, heap, pi->cast_types);
31306 + VEC_free (int, heap, pi->cast_counts);
31309 + /* Continue traversal. */
31313 +/* Collect information about variables that we believe to be loop
31314 + indices in PROMOTION_INFO. */
31317 +collect_promotion_candidates (void)
31319 + loop_iterator li;
31320 + struct loop *loop;
31322 + FOR_EACH_LOOP (li, loop, 0)
31324 + basic_block header = loop->header;
31325 + gimple exit_cond = last_stmt (header);
31327 + if (exit_cond && gimple_code (exit_cond) == GIMPLE_COND)
31330 + tree limit = NULL_TREE;
31332 + struct promote_info *pi;
31334 + loop_index = find_promotion_candidate (loop, exit_cond, &limit);
31335 + if (loop_index == NULL_TREE)
31337 + decl = SSA_NAME_VAR (loop_index);
31338 + if (TREE_ADDRESSABLE (decl))
31343 + fprintf (dump_file, "Found loop index ");
31344 + print_generic_expr (dump_file, loop_index, 0);
31345 + fprintf (dump_file, " involved in ");
31346 + print_gimple_stmt (dump_file, exit_cond, 0, 0);
31347 + fprintf (dump_file, "\n\n");
31350 + pi = XCNEW (struct promote_info);
31352 + pi->exit_expr = exit_cond;
31353 + pi->loop_index_name = loop_index;
31354 + pi->loop_limit = limit;
31355 + pi->var_decl = decl;
31356 + /* We think so, anyway... */
31357 + pi->can_be_promoted_p = true;
31358 + pointer_set_insert (promotion_info, pi);
31360 + else if (dump_file)
31362 + fprintf (dump_file, "\nSkipping analysis of loop %d (header bb #%d)\n",
31363 + loop->num, loop->header->index);
31366 + fprintf (dump_file, "Exit condition was ");
31367 + print_gimple_stmt (dump_file, exit_cond, 0, 0);
31368 + fprintf (dump_file, "\n");
31374 +/* Free memory associated with global variables that we used. */
31377 +pli_cleanup (void)
31379 + if (promoted_stmts)
31381 + pointer_set_destroy (promoted_stmts);
31382 + promoted_stmts = NULL;
31384 + if (variable_map)
31386 + pointer_map_destroy (variable_map);
31387 + variable_map = NULL;
31389 + if (promotable_names)
31391 + pointer_set_destroy (promotable_names);
31392 + promotable_names = NULL;
31394 + if (promotion_info)
31396 + pointer_set_traverse (promotion_info, free_pi_entries, NULL);
31397 + pointer_set_destroy (promotion_info);
31398 + promotion_info = NULL;
31402 +/* The guts of the pass. */
31404 +static unsigned int
31405 +promote_short_indices (void)
31407 + bool did_something = false;
31409 + size_t max_iterations, i, n_promoted;
31411 + promotion_info = pointer_set_create ();
31412 + collect_promotion_candidates ();
31415 + fprintf (dump_file, "Found %d candidates for promotion\n",
31416 + (int) pointer_set_n_elements (promotion_info));
31418 + /* Nothing to do. */
31419 + if (pointer_set_n_elements (promotion_info) == 0)
31422 + /* We have information about which variables are loop index variables.
31423 + We now need to determine the promotability of the loop indices.
31424 + Since the promotability of loop indices may depend on other loop
31425 + indices, we need to repeat this until we reach a fixed point. */
31427 + max_iterations = pointer_set_n_elements (promotion_info);
31430 + promotable_names = pointer_set_create ();
31435 + pointer_set_clear (promotable_names);
31436 + pointer_set_traverse (promotion_info, add_variable,
31437 + promotable_names);
31438 + n_promoted = pointer_set_n_elements (promotable_names);
31441 + fprintf (dump_file, "\nIteration %d, have %d variables to consider\n",
31442 + (int) i, (int) n_promoted);
31444 + if (n_promoted == 0)
31446 + gcc_assert (i < max_iterations);
31447 + pointer_set_traverse (promotion_info, analyze_loop, &changed);
31452 + fprintf (dump_file, "Promoting %d variables\n",
31453 + (int) n_promoted);
31455 + if (n_promoted != 0)
31457 + did_something = true;
31458 + variable_map = pointer_map_create ();
31459 + promoted_stmts = pointer_set_create ();
31460 + pointer_set_traverse (promotion_info, create_promoted_variable, NULL);
31461 + pointer_set_traverse (promotion_info, promote_variable, NULL);
31466 + return did_something ? TODO_update_ssa : 0;
31469 +/* Entry point for the short loop index promotion pass. */
31471 +static unsigned int
31472 +tree_short_index_promotion (void)
31474 + unsigned int changed = 0;
31476 + /* Initialize all the necessary loop infrastructure. */
31477 + loop_optimizer_init (LOOPS_HAVE_PREHEADERS | LOOPS_HAVE_SIMPLE_LATCHES | LOOPS_HAVE_RECORDED_EXITS);
31478 + add_noreturn_fake_exit_edges ();
31479 + connect_infinite_loops_to_exit ();
31481 + if (number_of_loops () > 1)
31482 + changed = promote_short_indices ();
31484 + /* Tear down loop optimization infrastructure. */
31485 + remove_fake_exit_edges ();
31486 + free_numbers_of_iterations_estimates ();
31487 + loop_optimizer_finalize ();
31493 +gate_short_index_promotion (void)
31495 + return optimize > 0 && flag_promote_loop_indices;
31498 +struct gimple_opt_pass pass_promote_indices =
31502 + "promoteshort", /* name */
31503 + gate_short_index_promotion, /* gate */
31504 + tree_short_index_promotion, /* execute */
31507 + 0, /* static_pass_number */
31508 + TV_TREE_LOOP_PROMOTE, /* tv_id */
31509 + PROP_cfg | PROP_ssa, /* properties_required */
31510 + 0, /* properties_provided */
31511 + 0, /* properties_destroyed */
31512 + 0, /* todo_flags_start */
31513 + TODO_dump_func | TODO_verify_loops
31514 + | TODO_ggc_collect /* todo_flags_finish */
31517 --- a/gcc/tree-ssa-pre.c
31518 +++ b/gcc/tree-ssa-pre.c
31519 @@ -104,6 +104,10 @@ along with GCC; see the file COPYING3.
31520 In order to make it fully redundant, we insert the expression into
31521 the predecessors where it is not available, but is ANTIC.
31523 + When optimizing for size, we only eliminate the partial redundancy
31524 + if we need to insert in only one predecessor. This avoids almost
31525 + completely the code size increase that PRE usually causes.
31527 For the partial anticipation case, we only perform insertion if it
31528 is partially anticipated in some block, and fully available in all
31529 of the predecessors.
31530 @@ -425,6 +429,7 @@ static pre_expr bitmap_find_leader (bitm
31531 static void bitmap_value_insert_into_set (bitmap_set_t, pre_expr);
31532 static void bitmap_value_replace_in_set (bitmap_set_t, pre_expr);
31533 static void bitmap_set_copy (bitmap_set_t, bitmap_set_t);
31534 +static void bitmap_set_and (bitmap_set_t, bitmap_set_t);
31535 static bool bitmap_set_contains_value (bitmap_set_t, unsigned int);
31536 static void bitmap_insert_into_set (bitmap_set_t, pre_expr);
31537 static void bitmap_insert_into_set_1 (bitmap_set_t, pre_expr, bool);
31538 @@ -2948,13 +2953,6 @@ insert_into_preds_of_block (basic_block
31542 - if (dump_file && (dump_flags & TDF_DETAILS))
31544 - fprintf (dump_file, "Found partial redundancy for expression ");
31545 - print_pre_expr (dump_file, expr);
31546 - fprintf (dump_file, " (%04d)\n", val);
31549 /* Make sure we aren't creating an induction variable. */
31550 if (block->loop_depth > 0 && EDGE_COUNT (block->preds) == 2
31551 && expr->kind != REFERENCE)
31552 @@ -3152,6 +3150,47 @@ insert_into_preds_of_block (basic_block
31556 +/* Indicate if, when optimizing for speed, it is appropriate to make
31557 + INSERTS_NEEDED insertions in order to make EXPR in BLOCK redundant. */
31559 +ppre_n_insert_for_speed_p (pre_expr expr, basic_block block,
31560 + unsigned int inserts_needed)
31562 + /* The more expensive EXPR is, the more we should be prepared to insert
31563 + in the predecessors of BLOCK to make EXPR fully redundant.
31564 + For now, only recognize AND, OR, XOR, PLUS and MINUS of a multiple-use
31565 + SSA_NAME with a constant as cheap. */
31568 + if (flag_tree_pre_partial_partial_obliviously)
31570 + if (expr->kind == NARY)
31572 + vn_nary_op_t nary = PRE_EXPR_NARY (expr);
31573 + switch (nary->opcode)
31576 + case BIT_AND_EXPR: case BIT_IOR_EXPR: case BIT_XOR_EXPR:
31577 + case PLUS_EXPR: case MINUS_EXPR:
31579 + gcc_assert (nary->length == 2);
31580 + name = nary->op[0];
31581 + cnst = nary->op[1];
31582 + if (TREE_CODE (name) != SSA_NAME || has_single_use (name))
31584 + if (!is_gimple_min_invariant (cnst))
31594 + return EDGE_COUNT (block->preds) * cost >= inserts_needed;
31598 /* Perform insertion of partially redundant values.
31599 For BLOCK, do the following:
31600 @@ -3186,6 +3225,7 @@ do_regular_insertion (basic_block block,
31603 bool by_some = false;
31604 + unsigned int inserts_needed = 0;
31605 bool cant_insert = false;
31606 bool all_same = true;
31607 pre_expr first_s = NULL;
31608 @@ -3240,6 +3280,7 @@ do_regular_insertion (basic_block block,
31610 avail[bprime->index] = eprime;
31612 + inserts_needed++;
31616 @@ -3249,6 +3290,11 @@ do_regular_insertion (basic_block block,
31617 first_s = edoubleprime;
31618 else if (!pre_expr_eq (first_s, edoubleprime))
31620 + /* If the available value is not a NAME, PREing this
31621 + value will probably result in a copy on the edge
31622 + to assign the expression to a register. */
31623 + if (edoubleprime->kind != NAME)
31624 + inserts_needed++;
31627 /* If we can insert it, it's not the same value
31628 @@ -3257,9 +3303,27 @@ do_regular_insertion (basic_block block,
31629 partially redundant. */
31630 if (!cant_insert && !all_same && by_some && dbg_cnt (treepre_insert))
31632 - if (insert_into_preds_of_block (block, get_expression_id (expr),
31634 - new_stuff = true;
31635 + if (dump_file && (dump_flags & TDF_DETAILS))
31637 + fprintf (dump_file,
31638 + "Found partial redundancy for expression ");
31639 + print_pre_expr (dump_file, expr);
31640 + fprintf (dump_file, " (%04d)\n", get_expr_value_id (expr));
31643 + /* If optimizing for size, insert at most one
31644 + new expression to avoid increasing code size. */
31645 + if (optimize_function_for_speed_p (cfun)
31646 + ? 1 : EDGE_COUNT (block->preds) - inserts_needed == 1)
31648 + insert_into_preds_of_block (block,
31649 + get_expression_id (expr),
31651 + else if (dump_file && (dump_flags & TDF_DETAILS))
31652 + fprintf (dump_file, "Not inserting (optimizing for %s)\n",
31653 + optimize_function_for_speed_p (cfun)
31654 + ? "speed" : "size");
31657 /* If all edges produce the same value and that value is
31658 an invariant, then the PHI has the same value on all
31659 @@ -3388,9 +3452,28 @@ do_partial_partial_insertion (basic_bloc
31660 if (!cant_insert && by_all && dbg_cnt (treepre_insert))
31662 pre_stats.pa_insert++;
31663 - if (insert_into_preds_of_block (block, get_expression_id (expr),
31665 - new_stuff = true;
31666 + if (dump_file && (dump_flags & TDF_DETAILS))
31668 + fprintf (dump_file,
31669 + "Found partial redundancy for expression ");
31670 + print_pre_expr (dump_file, expr);
31671 + fprintf (dump_file, " (%04d)\n", get_expr_value_id (expr));
31673 + /* Assuming the expression is 50% anticipatable, we have to
31674 + multiply the number of insertions needed by two for a cost
31676 + if (!optimize_function_for_speed_p (cfun)
31677 + || ppre_n_insert_for_speed_p (expr, block,
31678 + 2 * EDGE_COUNT (block->preds)))
31680 + insert_into_preds_of_block (block,
31681 + get_expression_id (expr),
31683 + else if (dump_file && (dump_flags & TDF_DETAILS))
31684 + fprintf (dump_file, "Not inserting (optimizing for %s)\n",
31685 + optimize_function_for_speed_p (cfun)
31686 + ? "speed" : "size");
31691 @@ -3431,7 +3514,9 @@ insert_aux (basic_block block)
31692 if (!single_pred_p (block))
31694 new_stuff |= do_regular_insertion (block, dom);
31695 - if (do_partial_partial)
31696 + /* Don't bother with partial-partial redundancies when
31697 + optimizing for size. */
31698 + if (do_partial_partial && ! optimize_function_for_size_p (cfun))
31699 new_stuff |= do_partial_partial_insertion (block, dom);
31702 @@ -4171,11 +4256,11 @@ fini_pre (bool do_fre)
31703 only wants to do full redundancy elimination. */
31705 static unsigned int
31706 -execute_pre (bool do_fre ATTRIBUTE_UNUSED)
31707 +execute_pre (bool do_fre)
31709 unsigned int todo = 0;
31711 - do_partial_partial = optimize > 2;
31712 + do_partial_partial = flag_tree_pre_partial_partial;
31714 /* This has to happen before SCCVN runs because
31715 loop_optimizer_init may create new phis, etc. */
31716 @@ -4247,19 +4332,20 @@ execute_pre (bool do_fre ATTRIBUTE_UNUSE
31720 -/* Gate and execute functions for PRE. */
31721 +/* Gate and execute functions for FRE/PRE. */
31723 static unsigned int
31726 - return TODO_rebuild_alias | execute_pre (false);
31727 + return TODO_rebuild_alias
31728 + | execute_pre (! flag_tree_pre);
31734 - /* PRE tends to generate bigger code. */
31735 - return flag_tree_pre != 0 && optimize_function_for_speed_p (cfun);
31736 + /* Run FRE even if we don't run PRE. */
31737 + return (flag_tree_fre || flag_tree_pre);
31740 struct gimple_opt_pass pass_pre =
31742 +++ b/gcc/tree-ssa-remove-local-statics.c
31744 +/* Local static variable elimination pass.
31745 + Copyright (C) 2007 Free Software Foundation, Inc.
31746 + Contributed by Nathan Froyd <froydnj@codesourcery.com>
31748 +This file is part of GCC.
31750 +GCC is free software; you can redistribute it and/or modify it
31751 +under the terms of the GNU General Public License as published by the
31752 +Free Software Foundation; either version 3, or (at your option) any
31755 +GCC is distributed in the hope that it will be useful, but WITHOUT
31756 +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
31757 +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
31760 +You should have received a copy of the GNU General Public License
31761 +along with GCC; see the file COPYING3. If not see
31762 +<http://www.gnu.org/licenses/>. */
31764 +/* Converting static function-local variables to automatic variables.
31766 + The motivating example is a function like:
31774 + for (i = 0; i != n; i++)
31778 + do other things with var...
31782 + Because VAR is static, doing things like code motion to loads and
31783 + stores of VAR is difficult. Furthermore, accesses to VAR are
31784 + inefficient. This pass aims to recognize the cases where it is not
31785 + necessary for VAR to be static and modify the code so that later
31786 + passes will do the appropriate optimizations.
31788 + The criteria for a static function-local variable V in a function F
31789 + being converted to an automatic variable are:
31791 + 1. F does not call setjmp; and
31792 + 2. V's address is never taken; and
31793 + 3. V is not declared volatile; and
31794 + 4. V is not used in any nested function;
31795 + 5. V is not an aggregate value (union, struct, array, etc.); and
31796 + 6. Every use of V is defined along all paths leading to the use.
31798 + NOTE: For ease of implementation, we currently treat a function call
31799 + as killing all previous definitions of static variables, since we
31814 + The use at (3) needs to pick up a possible definition made by the
31815 + call at (2). If the call at (2) does not call back into 'foo',
31816 + then the call is not a killing call. We currently treat it as
31819 +#include "config.h"
31820 +#include "system.h"
31821 +#include "coretypes.h"
31826 +#include "hard-reg-set.h"
31827 +#include "obstack.h"
31828 +#include "basic-block.h"
31831 +#include "gimple.h"
31832 +#include "hashtab.h"
31833 +#include "diagnostic.h"
31834 +#include "tree-flow.h"
31835 +#include "tree-dump.h"
31836 +#include "flags.h"
31837 +#include "timevar.h"
31838 +#include "tree-pass.h"
31840 +struct rls_decl_info
31842 + /* The variable declaration. */
31845 + /* Its index in rls_block_local_data. */
31848 + /* Whether we can optimize this variable. */
31849 + bool optimizable_p;
31851 + /* The new variable declaration, if we can optimize away the staticness
31852 + of 'orig_var'. */
31856 +/* Filled with 'struct rls_decl_info'; keyed off ORIG_VAR. */
31857 +static htab_t static_variables;
31859 +struct rls_stmt_info
31861 + /* The variable declaration. */
31864 + /* The statement in which we found a def or a use of the variable. */
31867 + /* Whether STMT represents a use of VAR. */
31870 + /* A bitmap whose entries denote what variables have been defined
31871 + when execution arrives at STMT. This field is only used when
31872 + USE_P is true. */
31876 +/* Filled with 'struct rls_stmt_info'; keyed off STMT. */
31877 +static htab_t defuse_statements;
31881 + /* The number of static variables we found. */
31882 + size_t n_statics;
31884 + /* The number of optimizable variables we found. */
31885 + size_t n_optimizable;
31888 +struct rls_block_dataflow_data {
31889 + /* A bitmap whose entries denote what variables have been defined on
31890 + entry to this block. */
31891 + sbitmap defined_in;
31893 + /* A bitmap whose entries denote what variables have been defined on
31894 + exit from this block. */
31895 + sbitmap defined_out;
31898 +/* Parameters for the 'static_variables' hash table. */
31901 +rls_hash_decl_info (const void *x)
31903 + return htab_hash_pointer
31904 + ((const void *) ((const struct rls_decl_info *) x)->orig_var);
31908 +rls_eq_decl_info (const void *x, const void *y)
31910 + const struct rls_decl_info *a = (const struct rls_decl_info *) x;
31911 + const struct rls_decl_info *b = (const struct rls_decl_info *) y;
31913 + return a->orig_var == b->orig_var;
31917 +rls_free_decl_info (void *info)
31922 +/* Parameters for the 'defuse_statements' hash table. */
31925 +rls_hash_use_info (const void *x)
31927 + return htab_hash_pointer
31928 + ((const void *) ((const struct rls_stmt_info *) x)->stmt);
31932 +rls_eq_use_info (const void *x, const void *y)
31934 + const struct rls_stmt_info *a = (const struct rls_stmt_info *) x;
31935 + const struct rls_stmt_info *b = (const struct rls_stmt_info *) y;
31937 + return a->stmt == b->stmt;
31941 +rls_free_use_info (void *info)
31943 + struct rls_stmt_info *stmt_info = (struct rls_stmt_info *) info;
31945 + if (stmt_info->defined)
31946 + sbitmap_free (stmt_info->defined);
31948 + free (stmt_info);
31951 +/* Initialize data structures and statistics. */
31958 + /* We expect relatively few static variables, hence the small
31959 + initial size for the hash table. */
31960 + static_variables = htab_create (8, rls_hash_decl_info,
31961 + rls_eq_decl_info, rls_free_decl_info);
31963 + /* We expect quite a few statements. */
31964 + defuse_statements = htab_create (128, rls_hash_use_info,
31965 + rls_eq_use_info, rls_free_use_info);
31969 + struct rls_block_dataflow_data *data;
31971 + data = XNEW (struct rls_block_dataflow_data);
31972 + memset (data, 0, sizeof (*data));
31976 + stats.n_statics = 0;
31977 + stats.n_optimizable = 0;
31980 +/* Free data structures. */
31987 + htab_delete (static_variables);
31988 + htab_delete (defuse_statements);
31992 + struct rls_block_dataflow_data *data
31993 + = (struct rls_block_dataflow_data *) bb->aux;
31995 + gcc_assert (data);
31997 + if (data->defined_in)
31998 + sbitmap_free (data->defined_in);
31999 + if (data->defined_out)
32000 + sbitmap_free (data->defined_out);
32007 +/* Doing the initial work to find static variables. */
32009 +/* Examine the defining statement for VAR and determine whether it is a
32010 + static variable we could potentially optimize. If so, stick in it
32011 + in the 'static_variables' hashtable.
32013 + STMT is the statement in which a definition or use of VAR occurs.
32014 + USE_P indicates whether VAR is used or defined in STMT. Enter STMT
32015 + into 'defuse_statements' as well for use during dataflow
32019 +maybe_discover_new_declaration (tree var, gimple stmt, bool use_p)
32021 + tree def_stmt = SSA_NAME_VAR (var);
32023 + if (TREE_CODE (def_stmt) == VAR_DECL
32024 + && DECL_CONTEXT (def_stmt) != NULL_TREE
32025 + && TREE_CODE (DECL_CONTEXT (def_stmt)) == FUNCTION_DECL
32026 + /* We cannot optimize away a static used in multiple functions (as
32027 + might happen in C++). */
32028 + && !DECL_NONLOCAL(def_stmt)
32029 + && TREE_STATIC (def_stmt)
32030 + /* We cannot optimize away aggregate statics, as we would have to
32031 + prove that definitions of every field of the aggregate dominate
32033 + && !AGGREGATE_TYPE_P (TREE_TYPE (def_stmt))
32034 + /* GCC doesn't normally treat vectors as aggregates; we need to,
32035 + though, since a user could use intrinsics to read/write
32036 + particular fields of the vector, thereby treating it as an
32038 + && TREE_CODE (TREE_TYPE (def_stmt)) != VECTOR_TYPE
32039 + && !TREE_ADDRESSABLE (def_stmt)
32040 + && !TREE_THIS_VOLATILE (def_stmt))
32042 + struct rls_decl_info dummy;
32045 + dummy.orig_var = def_stmt;
32046 + slot = htab_find_slot (static_variables, &dummy, INSERT);
32048 + if (*slot == NULL)
32050 + /* Found a use or a def of a new declaration. */
32051 + struct rls_decl_info *info = XNEW (struct rls_decl_info);
32053 + info->orig_var = def_stmt;
32054 + info->index = stats.n_statics++;
32055 + /* Optimistically assume that we can optimize. */
32056 + info->optimizable_p = true;
32057 + info->new_var = NULL_TREE;
32058 + *slot = (void *) info;
32061 + /* Enter the statement into DEFUSE_STATEMENTS. */
32063 + struct rls_stmt_info dummy;
32064 + struct rls_stmt_info *info;
32066 + dummy.stmt = stmt;
32067 + slot = htab_find_slot (defuse_statements, &dummy, INSERT);
32069 + /* We should never insert the same statement into the
32070 + hashtable twice. */
32071 + gcc_assert (*slot == NULL
32072 + || ((struct rls_stmt_info *)(*slot))->stmt == stmt);
32074 + if (*slot != NULL && ((struct rls_stmt_info *)(*slot))->stmt == stmt)
32077 + info = XNEW (struct rls_stmt_info);
32078 + info->var = def_stmt;
32079 + info->stmt = stmt;
32082 + fprintf (dump_file, "entering as %s ", use_p ? "use" : "def");
32083 + print_gimple_stmt (dump_file, stmt, 0, TDF_DETAILS | TDF_VOPS);
32085 + info->use_p = use_p;
32086 + /* We don't know how big to make the bitmap yet. */
32087 + info->defined = NULL;
32088 + *slot = (void *) info;
32093 +/* Grovel through all the statements in the program, looking for
32094 + SSA_NAMEs whose SSA_NAME_VAR is a VAR_DECL. We look at both use and
32095 + def SSA_NAMEs. */
32098 +find_static_nonvolatile_declarations (void)
32104 + gimple_stmt_iterator i;
32106 + for (i = gsi_start_bb (bb); !gsi_end_p (i); gsi_next (&i))
32109 + ssa_op_iter iter;
32110 + gimple stmt = gsi_stmt (i);
32112 + /* If there's a call expression in STMT, then previous passes
32113 + will have determined if the call transitively defines some
32114 + static variable. However, we need more precise
32115 + information--we need to know whether static variables are
32116 + live out after the call.
32118 + Since we'll never see something like:
32120 + staticvar = foo (bar, baz);
32122 + in GIMPLE (the result of the call will be assigned to a
32123 + normal, non-static local variable which is then assigned to
32124 + STATICVAR in a subsequent statement), don't bother finding
32125 + new declarations if we see a GIMPLE_CALL.
32127 + In a similar fashion, asm statements that clobber memory
32128 + will appear to define static variables. In general,
32129 + however, assuming that asm statements define static
32130 + variables would cause us to see that in the following
32133 + static int foo = 0;
32135 + __asm__ (... : "memory");
32138 + foo could be unstaticized because the asm has "defined"
32139 + foo. This is likely false. (Even if the asm does happen
32140 + to define foo--and only foo--that situation would be
32141 + sufficiently unusual that not optimizing it seems OK.) */
32142 + if (gimple_code (stmt) != GIMPLE_CALL
32143 + && gimple_code (stmt) != GIMPLE_ASM)
32144 + FOR_EACH_SSA_TREE_OPERAND (var, stmt, iter, SSA_OP_VDEF)
32146 + maybe_discover_new_declaration (var, stmt, false);
32149 + FOR_EACH_SSA_TREE_OPERAND (var, stmt, iter, SSA_OP_VUSE)
32151 + maybe_discover_new_declaration (var, stmt, true);
32158 +/* Determining if we have anything to optimize. */
32160 +/* Examine *SLOT (which is a 'struct rls_decl_info *') to see whether
32161 + the associated variable is optimizable. If it is, create a new,
32162 + non-static declaration for the variable; this new variable will be
32163 + used during a subsequent rewrite of the function. */
32165 +#define NEW_VAR_PREFIX ".unstatic"
32168 +maybe_create_new_variable (void **slot, void *data ATTRIBUTE_UNUSED)
32170 + struct rls_decl_info *info = (struct rls_decl_info *) *slot;
32171 + tree id_node = DECL_NAME (info->orig_var);
32172 + size_t id_len = IDENTIFIER_LENGTH (id_node);
32173 + size_t name_len = id_len + strlen (NEW_VAR_PREFIX) + 1;
32176 + /* Don't create a new variable multiple times. */
32177 + gcc_assert (!info->new_var);
32179 + /* Tie the new name to the old one to aid debugging dumps. */
32180 + name = (char *) alloca (name_len);
32181 + strcpy (name, IDENTIFIER_POINTER (id_node));
32182 + strcpy (name + id_len, NEW_VAR_PREFIX);
32183 + info->new_var = create_tmp_var (TREE_TYPE (info->orig_var), name);
32187 + fprintf (dump_file, "new variable ");
32188 + print_generic_expr (dump_file, info->new_var, 0);
32189 + fprintf (dump_file, "\n");
32192 + /* Inform SSA about this new variable. */
32193 + create_var_ann (info->new_var);
32194 + mark_sym_for_renaming (info->new_var);
32195 + /* We need to make sure we rebuild bits for the original variable,
32196 + such as virtual operands attached to statements. */
32197 + mark_sym_for_renaming (info->orig_var);
32198 + add_referenced_var (info->new_var);
32200 + /* Always continue scanning. */
32204 +#undef NEW_VAR_PREFIX
32206 +/* Traverse the 'defuse_statements' hash table. For every use,
32207 + determine if the associated variable is defined along all paths
32208 + leading to said use. Remove the associated variable from
32209 + 'static_variables' if it is not. */
32212 +check_definedness (void **slot, void *data ATTRIBUTE_UNUSED)
32214 + struct rls_stmt_info *info = (struct rls_stmt_info *) *slot;
32215 + struct rls_decl_info dummy;
32217 + /* We don't need to look at definitions. Continue scanning. */
32218 + if (!info->use_p)
32221 + dummy.orig_var = info->var;
32222 + slot = htab_find_slot (static_variables, &dummy, INSERT);
32224 + /* Might not be there because we deleted it already. */
32227 + struct rls_decl_info *decl = (struct rls_decl_info *) *slot;
32229 + if (!TEST_BIT (info->defined, decl->index))
32233 + fprintf (dump_file, "not optimizing ");
32234 + print_generic_expr (dump_file, decl->orig_var, 0);
32235 + fprintf (dump_file, "due to uncovered use in ");
32236 + print_gimple_stmt (dump_file, info->stmt, 0, 0);
32237 + fprintf (dump_file, "\n");
32240 + htab_clear_slot (static_variables, slot);
32241 + stats.n_optimizable--;
32245 + /* Continue scan. */
32249 +/* Check all statements in 'defuse_statements' to see if all the
32250 + statements that use a static variable have that variable defined
32251 + along all paths leading to the statement. Once that's done, go
32252 + through and create new, non-static variables for any static variables
32253 + that can be optimized. */
32256 +determine_optimizable_statics (void)
32258 + htab_traverse (defuse_statements, check_definedness, NULL);
32260 + htab_traverse (static_variables, maybe_create_new_variable, NULL);
32262 + return stats.n_optimizable;
32265 +/* Look at STMT to see if we have uses or defs of a static variable.
32266 + STMT is passed in DATA. Definitions of a static variable are found
32267 + by the presence of a V_MUST_DEF, while uses are found by the presence
32271 +unstaticize_variable (void **slot, void *data)
32273 + struct rls_decl_info *info = (struct rls_decl_info *) *slot;
32274 + gimple stmt = (gimple) data;
32277 + int continue_scan = 1;
32279 + /* We should have removed unoptimizable variables during an earlier
32281 + gcc_assert (info->optimizable_p);
32283 + /* Check for virtual definitions first. */
32284 + vdef = SINGLE_SSA_TREE_OPERAND (stmt, SSA_OP_VDEF);
32287 + && ZERO_SSA_OPERANDS (stmt, SSA_OP_DEF)
32288 + && gimple_code (stmt) == GIMPLE_ASSIGN
32289 + && TREE_CODE (gimple_assign_lhs (stmt)) == VAR_DECL
32290 + && gimple_assign_lhs(stmt) == info->orig_var)
32292 + /* Make the statement define the new name. The new name has
32293 + already been marked for renaming, so no need to do that
32295 + gimple_assign_set_lhs (stmt, info->new_var);
32298 + fprintf (dump_file, "found virtual definition!\n");
32299 + print_gimple_stmt (dump_file, stmt, 0, TDF_VOPS | TDF_DETAILS);
32300 + fprintf (dump_file, "\n");
32302 + continue_scan = 0;
32306 + /* Check for virtual uses. */
32307 + vuse = SINGLE_SSA_TREE_OPERAND (stmt, SSA_OP_VUSE);
32310 + && gimple_code (stmt) == GIMPLE_ASSIGN
32311 + && gimple_assign_rhs_code (stmt) == VAR_DECL
32312 + && gimple_assign_rhs1 (stmt) == info->orig_var)
32314 + /* Make the statement use the new name. */
32315 + gimple_assign_set_rhs1 (stmt, info->new_var);
32318 + fprintf (dump_file, "found virtual use!\n");
32319 + print_gimple_stmt (dump_file, stmt, 0, TDF_VOPS | TDF_DETAILS);
32320 + fprintf (dump_file, "\n");
32322 + continue_scan = 0;
32327 + if (!continue_scan)
32329 + /* None of the other optimizable static variables can occur
32330 + in this statement. Stop the scan. */
32331 + update_stmt (stmt);
32335 + fprintf (dump_file, "updated stmt\n");
32336 + print_gimple_stmt (dump_file, stmt, 0, TDF_VOPS | TDF_DETAILS);
32340 + return continue_scan;
32343 +/* Determine if we have any static variables we can optimize. If so,
32344 + replace any defs or uses of those variables in their defining/using
32348 +maybe_remove_static_from_declarations (void)
32350 + size_t n_optimizable = determine_optimizable_statics ();
32353 + if (n_optimizable)
32354 + /* Replace any optimizable variables with new, non-static variables. */
32357 + gimple_stmt_iterator gsi;
32359 + for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
32361 + gimple stmt = gsi_stmt (gsi);
32363 + htab_traverse (static_variables, unstaticize_variable, stmt);
32368 +/* Callback for htab_traverse to initialize the bitmap for *SLOT, which
32369 + is a 'struct rls_stmt_info'. */
32372 +initialize_statement_dataflow (void **slot, void *data ATTRIBUTE_UNUSED)
32374 + struct rls_stmt_info *info = (struct rls_stmt_info *) *slot;
32376 + gcc_assert (!info->defined);
32380 + info->defined = sbitmap_alloc (stats.n_statics);
32381 + /* Assume defined along all paths until otherwise informed. */
32382 + sbitmap_ones (info->defined);
32385 + /* Continue traversal. */
32389 +/* We have N_STATICS static variables to consider. Go through all the
32390 + blocks and all the use statements to initialize their bitmaps. */
32393 +initialize_block_and_statement_dataflow (size_t n_statics)
32399 + struct rls_block_dataflow_data *data
32400 + = (struct rls_block_dataflow_data *) bb->aux;
32402 + gcc_assert (data);
32404 + data->defined_in = sbitmap_alloc (n_statics);
32405 + sbitmap_zero (data->defined_in);
32406 + data->defined_out = sbitmap_alloc (n_statics);
32407 + sbitmap_zero (data->defined_out);
32410 + htab_traverse (defuse_statements, initialize_statement_dataflow, NULL);
32413 +/* Apply the individual effects of the stmts in BB to update the
32414 + dataflow analysis information for BB. */
32417 +compute_definedness_for_block (basic_block bb)
32419 + bool changed_p = false;
32420 + struct rls_block_dataflow_data *data
32421 + = (struct rls_block_dataflow_data *) bb->aux;
32422 + gimple_stmt_iterator gsi;
32424 + sbitmap_copy (data->defined_out, data->defined_in);
32426 + for (gsi = gsi_start_bb (bb); !gsi_end_p (gsi); gsi_next (&gsi))
32428 + gimple stmt = gsi_stmt (gsi);
32430 + if (gimple_code (stmt) == GIMPLE_CALL)
32431 + /* If there's a call expression in STMT, then previous passes
32432 + will have determined if the call transitively defines some
32433 + static variable. However, we need more precise
32434 + information--we need to know whether static variables are
32435 + live out after the call. In the absence of such information,
32436 + simply declare that all static variables are clobbered by the
32437 + call. A better analysis would be interprocedural and compute
32438 + the liveness information we require, but for now, we're being
32440 + sbitmap_zero (data->defined_out);
32443 + struct rls_stmt_info dummy;
32446 + /* See if this statement uses or defines a static variable. */
32447 + dummy.stmt = stmt;
32448 + slot = htab_find_slot (defuse_statements, &dummy, INSERT);
32450 + /* Check for uses. */
32451 + if (*slot != NULL)
32453 + struct rls_stmt_info *info = (struct rls_stmt_info *) *slot;
32457 + gcc_assert (info->defined);
32459 + /* Found a statement that uses a function-local static
32460 + variable. Copy the current state of definedness. */
32461 + sbitmap_copy (info->defined, data->defined_out);
32465 + struct rls_decl_info dummy;
32466 + struct rls_decl_info *decl;
32468 + gcc_assert (!info->defined);
32470 + /* Found a statement that defines a function-local static
32471 + variable. Look up the associated variable's information
32472 + and mark it as defined in the block. */
32473 + dummy.orig_var = info->var;
32474 + slot = htab_find_slot (static_variables, &dummy, INSERT);
32476 + gcc_assert (*slot);
32478 + decl = (struct rls_decl_info *) *slot;
32480 + SET_BIT (data->defined_out, decl->index);
32481 + changed_p |= true;
32488 +/* Solve the dataflow equations:
32490 + DEFINED_IN(b) = intersect DEFINED_OUT(p) for p in preds(b)
32491 + DEFINED_OUT(b) = VARIABLES_DEFINED (b, DEFINED_IN (b))
32493 + via a simple iterative solver. VARIABLES_DEFINED is computed by
32494 + 'compute_definedness_for_block'. */
32497 +compute_definedness (void)
32501 + sbitmap tmp_bitmap = sbitmap_alloc (stats.n_statics);
32503 + /* Compute initial sets. */
32506 + compute_definedness_for_block (bb);
32511 + changed_p = false;
32516 + edge_iterator ei;
32517 + struct rls_block_dataflow_data *data
32518 + = (struct rls_block_dataflow_data *) bb->aux;
32519 + bool bitmap_changed_p = false;
32521 + sbitmap_ones (tmp_bitmap);
32523 + gcc_assert (data);
32525 + /* We require information about whether a variable was defined
32526 + over all paths leading to a particular use. Therefore, we
32527 + intersect the DEFINED sets of all predecessors. */
32528 + FOR_EACH_EDGE (e, ei, bb->preds)
32530 + struct rls_block_dataflow_data *pred_data
32531 + = (struct rls_block_dataflow_data *) e->src->aux;
32533 + gcc_assert (pred_data);
32535 + sbitmap_a_and_b (tmp_bitmap, tmp_bitmap, pred_data->defined_out);
32538 + bitmap_changed_p = !sbitmap_equal (tmp_bitmap, data->defined_in);
32540 + if (bitmap_changed_p)
32542 + sbitmap_copy (data->defined_in, tmp_bitmap);
32543 + compute_definedness_for_block (bb);
32546 + changed_p |= bitmap_changed_p;
32548 + } while (changed_p);
32550 + sbitmap_free (tmp_bitmap);
32553 +static unsigned int
32554 +execute_rls (void)
32558 + find_static_nonvolatile_declarations ();
32560 + /* Can we optimize anything? */
32561 + if (stats.n_statics != 0)
32563 + stats.n_optimizable = stats.n_statics;
32566 + fprintf (dump_file, "found %d static variables to consider\n",
32567 + stats.n_statics);
32569 + initialize_block_and_statement_dataflow (stats.n_statics);
32571 + compute_definedness ();
32573 + maybe_remove_static_from_declarations ();
32576 + fprintf (dump_file, "removed %d static variables\n",
32577 + stats.n_optimizable);
32588 + return (flag_remove_local_statics != 0
32589 + && !cfun->calls_setjmp
32590 + && !cgraph_node (current_function_decl)->ever_was_nested);
32593 +struct gimple_opt_pass pass_remove_local_statics =
32597 + "remlocstatic", /* name */
32598 + gate_rls, /* gate */
32599 + execute_rls, /* execute */
32602 + 0, /* static_pass_number */
32603 + TV_TREE_RLS, /* tv_id */
32604 + PROP_cfg | PROP_ssa, /* properties_required */
32605 + 0, /* properties_provided */
32606 + 0, /* properties_destroyed */
32607 + 0, /* todo_flags_start */
32608 + TODO_dump_func | TODO_verify_ssa | TODO_verify_stmts
32609 + | TODO_rebuild_alias | TODO_update_ssa /* todo_flags_finish */
32612 --- a/gcc/tree-ssa-sink.c
32613 +++ b/gcc/tree-ssa-sink.c
32614 @@ -449,6 +449,47 @@ sink_code_in_bb (basic_block bb)
32619 + /* We cannot move statements that contain references to block-scope
32620 + variables out of that block, as this may lead to incorrect aliasing
32621 + when we lay out the stack frame in cfgexpand.c.
32622 + In lieu of more sophisticated analysis, be very conservative here
32623 + and prohibit moving any statement that references memory out of a
32624 + block with variables. */
32625 + if (gimple_references_memory_p (stmt))
32627 + tree fromblock = gimple_block (stmt);
32629 + && fromblock != current_function_decl
32630 + && !BLOCK_VARS (fromblock))
32631 + fromblock = BLOCK_SUPERCONTEXT (fromblock);
32632 + if (fromblock && fromblock != current_function_decl)
32637 + if (gsi_end_p (togsi))
32638 + tostmt = gimple_seq_last_stmt (gsi_seq (togsi));
32640 + tostmt = gsi_stmt (togsi);
32642 + toblock = gimple_block (tostmt);
32646 + && toblock != current_function_decl
32647 + && toblock != fromblock)
32648 + toblock = BLOCK_SUPERCONTEXT (toblock);
32649 + if (!toblock || toblock != fromblock)
32651 + if (!gsi_end_p (gsi))
32661 fprintf (dump_file, "Sinking ");
32662 --- a/gcc/tree-ssa-structalias.c
32663 +++ b/gcc/tree-ssa-structalias.c
32664 @@ -2928,7 +2928,8 @@ get_constraint_for_component_ref (tree t
32665 /* Some people like to do cute things like take the address of
32668 - while (!SSA_VAR_P (forzero) && !CONSTANT_CLASS_P (forzero))
32669 + while (!SSA_VAR_P (forzero) && TREE_CODE (forzero) != FUNCTION_DECL
32670 + && !CONSTANT_CLASS_P (forzero))
32671 forzero = TREE_OPERAND (forzero, 0);
32673 if (CONSTANT_CLASS_P (forzero) && integer_zerop (forzero))
32674 --- a/gcc/tree-vect-analyze.c
32675 +++ b/gcc/tree-vect-analyze.c
32676 @@ -1459,7 +1459,7 @@ vect_compute_data_ref_alignment (struct
32679 base = build_fold_indirect_ref (base_addr);
32680 - alignment = ssize_int (TYPE_ALIGN (vectype)/BITS_PER_UNIT);
32681 + alignment = ssize_int (targetm.vectorize.vector_min_alignment (vectype));
32683 if ((aligned_to && tree_int_cst_compare (aligned_to, alignment) < 0)
32685 @@ -1510,7 +1510,8 @@ vect_compute_data_ref_alignment (struct
32686 /* At this point we assume that the base is aligned. */
32687 gcc_assert (base_aligned
32688 || (TREE_CODE (base) == VAR_DECL
32689 - && DECL_ALIGN (base) >= TYPE_ALIGN (vectype)));
32690 + && (DECL_ALIGN (base)
32691 + >= targetm.vectorize.vector_min_alignment (vectype))));
32693 /* Modulo alignment. */
32694 misalign = size_binop (TRUNC_MOD_EXPR, misalign, alignment);
32695 --- a/gcc/tree-vect-transform.c
32696 +++ b/gcc/tree-vect-transform.c
32697 @@ -5444,7 +5444,21 @@ vectorizable_store (gimple stmt, gimple_
32698 vect_permute_store_chain(). */
32699 vec_oprnd = VEC_index (tree, result_chain, i);
32701 - data_ref = build_fold_indirect_ref (dataref_ptr);
32702 + if (alignment_support_scheme == dr_aligned
32703 + && !targetm.vectorize.always_misalign(vectype))
32705 + data_ref = build_fold_indirect_ref (dataref_ptr);
32709 + /* TODO: Record actual alignment in always_misalign case. */
32710 + int mis = DR_MISALIGNMENT (first_dr);
32712 + tmis = (mis == -1 ? size_zero_node : size_int (mis));
32713 + tmis = size_binop (MULT_EXPR, tmis, size_int(BITS_PER_UNIT));
32715 + build2 (MISALIGNED_INDIRECT_REF, vectype, dataref_ptr, tmis);
32718 /* Arguments are ready. Create the new vector stmt. */
32719 new_stmt = gimple_build_assign (data_ref, vec_oprnd);
32720 @@ -6623,10 +6637,15 @@ vectorizable_load (gimple stmt, gimple_s
32723 gcc_assert (aligned_access_p (first_dr));
32724 - data_ref = build_fold_indirect_ref (dataref_ptr);
32726 + if (!targetm.vectorize.always_misalign(vectype))
32728 + data_ref = build_fold_indirect_ref (dataref_ptr);
32731 + /* Fall through... */
32732 case dr_unaligned_supported:
32734 + /* TODO: Record actual alignment in always_misalign case. */
32735 int mis = DR_MISALIGNMENT (first_dr);
32736 tree tmis = (mis == -1 ? size_zero_node : size_int (mis));
32738 @@ -7597,7 +7616,7 @@ vect_gen_niters_for_prolog_loop (loop_ve
32739 gimple dr_stmt = DR_STMT (dr);
32740 stmt_vec_info stmt_info = vinfo_for_stmt (dr_stmt);
32741 tree vectype = STMT_VINFO_VECTYPE (stmt_info);
32742 - int vectype_align = TYPE_ALIGN (vectype) / BITS_PER_UNIT;
32743 + int vectype_align = targetm.vectorize.vector_min_alignment (vectype);
32744 tree niters_type = TREE_TYPE (loop_niters);
32746 int element_size = GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (DR_REF (dr))));
32747 --- a/gcc/tree-vectorizer.c
32748 +++ b/gcc/tree-vectorizer.c
32749 @@ -2868,11 +2868,13 @@ increase_alignment (void)
32750 vnode = vnode->next_needed)
32752 tree vectype, decl = vnode->decl;
32754 unsigned int alignment;
32756 - if (TREE_CODE (TREE_TYPE (decl)) != ARRAY_TYPE)
32757 + t = TREE_TYPE(decl);
32758 + if (TREE_CODE (t) != ARRAY_TYPE)
32760 - vectype = get_vectype_for_scalar_type (TREE_TYPE (TREE_TYPE (decl)));
32761 + vectype = get_vectype_for_scalar_type (strip_array_types (t));
32764 alignment = TYPE_ALIGN (vectype);
32765 @@ -2887,6 +2889,7 @@ increase_alignment (void)
32767 fprintf (dump_file, "Increasing alignment of decl: ");
32768 print_generic_expr (dump_file, decl, TDF_SLIM);
32769 + fprintf (dump_file, "\n");
32775 @@ -4062,6 +4062,7 @@ handle_dll_attribute (tree * pnode, tree
32776 bool *no_add_attrs)
32778 tree node = *pnode;
32779 + bool is_dllimport;
32781 /* These attributes may apply to structure and union types being created,
32782 but otherwise should pass to the declaration involved. */
32783 @@ -4109,9 +4110,11 @@ handle_dll_attribute (tree * pnode, tree
32787 + is_dllimport = is_attribute_p ("dllimport", name);
32789 /* Report error on dllimport ambiguities seen now before they cause
32791 - else if (is_attribute_p ("dllimport", name))
32792 + if (is_dllimport)
32794 /* Honor any target-specific overrides. */
32795 if (!targetm.valid_dllimport_attribute_p (node))
32796 @@ -4153,6 +4156,9 @@ handle_dll_attribute (tree * pnode, tree
32797 if (*no_add_attrs == false)
32798 DECL_DLLIMPORT_P (node) = 1;
32800 + else if (DECL_DECLARED_INLINE_P (node))
32801 + /* An exported function, even if inline, must be emitted. */
32802 + DECL_EXTERNAL (node) = 0;
32804 /* Report error if symbol is not accessible at global scope. */
32805 if (!TREE_PUBLIC (node)
32808 @@ -381,8 +381,10 @@ struct tree_base GTY(())
32809 unsigned lang_flag_5 : 1;
32810 unsigned lang_flag_6 : 1;
32811 unsigned visited : 1;
32812 + unsigned packed_flag : 1;
32813 + unsigned user_align : 1;
32815 - unsigned spare : 23;
32816 + unsigned spare : 21;
32818 union tree_ann_d *ann;
32820 @@ -2140,7 +2142,7 @@ extern enum machine_mode vector_type_mod
32822 /* 1 if the alignment for this type was requested by "aligned" attribute,
32823 0 if it is the default for this type. */
32824 -#define TYPE_USER_ALIGN(NODE) (TYPE_CHECK (NODE)->type.user_align)
32825 +#define TYPE_USER_ALIGN(NODE) (TYPE_CHECK (NODE)->common.base.user_align)
32827 /* The alignment for NODE, in bytes. */
32828 #define TYPE_ALIGN_UNIT(NODE) (TYPE_ALIGN (NODE) / BITS_PER_UNIT)
32829 @@ -2246,7 +2248,7 @@ extern enum machine_mode vector_type_mod
32831 /* Indicated that objects of this type should be laid out in as
32832 compact a way as possible. */
32833 -#define TYPE_PACKED(NODE) (TYPE_CHECK (NODE)->type.packed_flag)
32834 +#define TYPE_PACKED(NODE) (TYPE_CHECK (NODE)->common.base.packed_flag)
32836 /* Used by type_contains_placeholder_p to avoid recomputation.
32837 Values are: 0 (unknown), 1 (false), 2 (true). Never access
32838 @@ -2265,17 +2267,16 @@ struct tree_type GTY(())
32842 - unsigned int precision : 9;
32843 - ENUM_BITFIELD(machine_mode) mode : 7;
32845 - unsigned string_flag : 1;
32846 + unsigned int precision : 10;
32847 unsigned no_force_blk_flag : 1;
32848 unsigned needs_constructing_flag : 1;
32849 unsigned transparent_union_flag : 1;
32850 - unsigned packed_flag : 1;
32851 unsigned restrict_flag : 1;
32852 unsigned contains_placeholder_bits : 2;
32854 + ENUM_BITFIELD(machine_mode) mode : 8;
32856 + unsigned string_flag : 1;
32857 unsigned lang_flag_0 : 1;
32858 unsigned lang_flag_1 : 1;
32859 unsigned lang_flag_2 : 1;
32860 @@ -2283,7 +2284,6 @@ struct tree_type GTY(())
32861 unsigned lang_flag_4 : 1;
32862 unsigned lang_flag_5 : 1;
32863 unsigned lang_flag_6 : 1;
32864 - unsigned user_align : 1;
32866 unsigned int align;
32867 alias_set_type alias_set;
32868 @@ -2584,7 +2584,7 @@ struct tree_memory_partition_tag GTY(())
32869 #define DECL_ALIGN_UNIT(NODE) (DECL_ALIGN (NODE) / BITS_PER_UNIT)
32870 /* Set if the alignment of this DECL has been set by the user, for
32871 example with an 'aligned' attribute. */
32872 -#define DECL_USER_ALIGN(NODE) (DECL_COMMON_CHECK (NODE)->decl_common.user_align)
32873 +#define DECL_USER_ALIGN(NODE) (DECL_COMMON_CHECK (NODE)->common.base.user_align)
32874 /* Holds the machine mode corresponding to the declaration of a variable or
32875 field. Always equal to TYPE_MODE (TREE_TYPE (decl)) except for a
32877 @@ -2621,7 +2621,7 @@ struct tree_memory_partition_tag GTY(())
32878 example, for a FUNCTION_DECL, DECL_SAVED_TREE may be non-NULL and
32879 DECL_EXTERNAL may be true simultaneously; that can be the case for
32880 a C99 "extern inline" function. */
32881 -#define DECL_EXTERNAL(NODE) (DECL_COMMON_CHECK (NODE)->decl_common.decl_flag_2)
32882 +#define DECL_EXTERNAL(NODE) (DECL_COMMON_CHECK (NODE)->decl_common.decl_flag_1)
32884 /* Nonzero in a ..._DECL means this variable is ref'd from a nested function.
32885 For VAR_DECL nodes, PARM_DECL nodes, and FUNCTION_DECL nodes.
32886 @@ -2696,7 +2696,6 @@ struct tree_decl_common GTY(())
32887 unsigned ignored_flag : 1;
32888 unsigned abstract_flag : 1;
32889 unsigned artificial_flag : 1;
32890 - unsigned user_align : 1;
32891 unsigned preserve_flag: 1;
32892 unsigned debug_expr_is_from : 1;
32894 @@ -2712,22 +2711,20 @@ struct tree_decl_common GTY(())
32895 /* In LABEL_DECL, this is DECL_ERROR_ISSUED.
32896 In VAR_DECL and PARM_DECL, this is DECL_REGISTER. */
32897 unsigned decl_flag_0 : 1;
32898 - /* In FIELD_DECL, this is DECL_PACKED. */
32899 - unsigned decl_flag_1 : 1;
32900 /* In FIELD_DECL, this is DECL_BIT_FIELD
32901 In VAR_DECL and FUNCTION_DECL, this is DECL_EXTERNAL.
32902 - In TYPE_DECL, this is TYPE_DECL_SUPRESS_DEBUG. */
32903 - unsigned decl_flag_2 : 1;
32904 + In TYPE_DECL, this is TYPE_DECL_SUPPRESS_DEBUG. */
32905 + unsigned decl_flag_1 : 1;
32906 /* In FIELD_DECL, this is DECL_NONADDRESSABLE_P
32907 - In VAR_DECL and PARM_DECL, this is DECL_HAS_VALUE_EXPR. */
32908 - unsigned decl_flag_3 : 1;
32909 + In VAR_DECL and PARM_DECL, this is DECL_HAS_VALUE_EXPR_P. */
32910 + unsigned decl_flag_2 : 1;
32911 /* Logically, these two would go in a theoretical base shared by var and
32913 unsigned gimple_reg_flag : 1;
32914 /* In a DECL with pointer type, set if no TBAA should be done. */
32915 unsigned no_tbaa_flag : 1;
32916 /* Padding so that 'align' can be on a 32-bit boundary. */
32917 - unsigned decl_common_unused : 2;
32918 + unsigned decl_common_unused : 4;
32920 unsigned int align : 24;
32921 /* DECL_OFFSET_ALIGN, used only for FIELD_DECLs. */
32922 @@ -2751,7 +2748,7 @@ extern void decl_value_expr_insert (tree
32923 decl itself. This should only be used for debugging; once this field has
32924 been set, the decl itself may not legitimately appear in the function. */
32925 #define DECL_HAS_VALUE_EXPR_P(NODE) \
32926 - (TREE_CHECK2 (NODE, VAR_DECL, PARM_DECL)->decl_common.decl_flag_3)
32927 + (TREE_CHECK2 (NODE, VAR_DECL, PARM_DECL)->decl_common.decl_flag_2)
32928 #define DECL_VALUE_EXPR(NODE) \
32929 (decl_value_expr_lookup (DECL_WRTL_CHECK (NODE)))
32930 #define SET_DECL_VALUE_EXPR(NODE, VAL) \
32931 @@ -2830,11 +2827,11 @@ struct tree_decl_with_rtl GTY(())
32932 #define DECL_FCONTEXT(NODE) (FIELD_DECL_CHECK (NODE)->field_decl.fcontext)
32934 /* In a FIELD_DECL, indicates this field should be bit-packed. */
32935 -#define DECL_PACKED(NODE) (FIELD_DECL_CHECK (NODE)->decl_common.decl_flag_1)
32936 +#define DECL_PACKED(NODE) (FIELD_DECL_CHECK (NODE)->common.base.packed_flag)
32938 /* Nonzero in a FIELD_DECL means it is a bit field, and must be accessed
32940 -#define DECL_BIT_FIELD(NODE) (FIELD_DECL_CHECK (NODE)->decl_common.decl_flag_2)
32941 +#define DECL_BIT_FIELD(NODE) (FIELD_DECL_CHECK (NODE)->decl_common.decl_flag_1)
32943 /* Used in a FIELD_DECL to indicate that we cannot form the address of
32944 this component. This makes it possible for Type-Based Alias Analysis
32945 @@ -2852,7 +2849,7 @@ struct tree_decl_with_rtl GTY(())
32946 accesses to s.i must not be given the alias set of the type of 'i'
32947 (int) but instead directly that of the type of 's' (struct S). */
32948 #define DECL_NONADDRESSABLE_P(NODE) \
32949 - (FIELD_DECL_CHECK (NODE)->decl_common.decl_flag_3)
32950 + (FIELD_DECL_CHECK (NODE)->decl_common.decl_flag_2)
32952 struct tree_field_decl GTY(())
32954 @@ -3337,7 +3334,7 @@ struct tree_function_decl GTY(())
32955 into stabs. Instead it will generate cross reference ('x') of names.
32956 This uses the same flag as DECL_EXTERNAL. */
32957 #define TYPE_DECL_SUPPRESS_DEBUG(NODE) \
32958 - (TYPE_DECL_CHECK (NODE)->decl_common.decl_flag_2)
32959 + (TYPE_DECL_CHECK (NODE)->decl_common.decl_flag_1)
32961 /* Getter of the imported declaration associated to the
32962 IMPORTED_DECL node. */
32963 --- a/gcc/unwind-dw2.c
32964 +++ b/gcc/unwind-dw2.c
32965 @@ -1414,16 +1414,12 @@ uw_advance_context (struct _Unwind_Conte
32966 /* Fill in CONTEXT for top-of-stack. The only valid registers at this
32967 level will be the return address and the CFA. */
32969 -#define uw_init_context(CONTEXT) \
32972 - /* Do any necessary initialization to access arbitrary stack frames. \
32973 - On the SPARC, this means flushing the register windows. */ \
32974 - __builtin_unwind_init (); \
32975 - uw_init_context_1 (CONTEXT, __builtin_dwarf_cfa (), \
32976 - __builtin_return_address (0)); \
32979 +#define uw_init_context(CONTEXT) \
32980 + /* Do any necessary initialization to access arbitrary stack frames. \
32981 + On the SPARC, this means flushing the register windows. */ \
32982 + (__builtin_unwind_init (), \
32983 + uw_init_context_1 ((CONTEXT), __builtin_dwarf_cfa (), \
32984 + __builtin_return_address (0)))
32987 init_dwarf_reg_size_table (void)
32988 @@ -1431,7 +1427,7 @@ init_dwarf_reg_size_table (void)
32989 __builtin_init_dwarf_reg_size_table (dwarf_reg_size_table);
32993 +static _Unwind_Reason_Code
32994 uw_init_context_1 (struct _Unwind_Context *context,
32995 void *outer_cfa, void *outer_ra)
32997 @@ -1445,7 +1441,8 @@ uw_init_context_1 (struct _Unwind_Contex
32998 context->flags = EXTENDED_CONTEXT_BIT;
33000 code = uw_frame_state_for (context, &fs);
33001 - gcc_assert (code == _URC_NO_REASON);
33002 + if (code != _URC_NO_REASON)
33007 @@ -1471,6 +1468,8 @@ uw_init_context_1 (struct _Unwind_Contex
33008 initialization context, then we can't see it in the given
33009 call frame data. So have the initialization context tell us. */
33010 context->ra = __builtin_extract_return_addr (outer_ra);
33012 + return _URC_NO_REASON;
33016 --- a/gcc/unwind-sjlj.c
33017 +++ b/gcc/unwind-sjlj.c
33018 @@ -292,10 +292,11 @@ uw_advance_context (struct _Unwind_Conte
33019 uw_update_context (context, fs);
33022 -static inline void
33023 +static inline _Unwind_Reason_Code
33024 uw_init_context (struct _Unwind_Context *context)
33026 context->fc = _Unwind_SjLj_GetContext ();
33027 + return _URC_NO_REASON;
33030 static void __attribute__((noreturn))
33031 --- a/gcc/unwind.inc
33032 +++ b/gcc/unwind.inc
33033 @@ -85,7 +85,8 @@ _Unwind_RaiseException(struct _Unwind_Ex
33034 _Unwind_Reason_Code code;
33036 /* Set up this_context to describe the current stack frame. */
33037 - uw_init_context (&this_context);
33038 + code = uw_init_context (&this_context);
33039 + gcc_assert (code == _URC_NO_REASON);
33040 cur_context = this_context;
33042 /* Phase 1: Search. Unwind the stack, calling the personality routine
33043 @@ -198,7 +199,8 @@ _Unwind_ForcedUnwind (struct _Unwind_Exc
33044 struct _Unwind_Context this_context, cur_context;
33045 _Unwind_Reason_Code code;
33047 - uw_init_context (&this_context);
33048 + code = uw_init_context (&this_context);
33049 + gcc_assert (code == _URC_NO_REASON);
33050 cur_context = this_context;
33052 exc->private_1 = (_Unwind_Ptr) stop;
33053 @@ -221,7 +223,8 @@ _Unwind_Resume (struct _Unwind_Exception
33054 struct _Unwind_Context this_context, cur_context;
33055 _Unwind_Reason_Code code;
33057 - uw_init_context (&this_context);
33058 + code = uw_init_context (&this_context);
33059 + gcc_assert (code == _URC_NO_REASON);
33060 cur_context = this_context;
33062 /* Choose between continuing to process _Unwind_RaiseException
33063 @@ -251,7 +254,8 @@ _Unwind_Resume_or_Rethrow (struct _Unwin
33064 if (exc->private_1 == 0)
33065 return _Unwind_RaiseException (exc);
33067 - uw_init_context (&this_context);
33068 + code = uw_init_context (&this_context);
33069 + gcc_assert (code == _URC_NO_REASON);
33070 cur_context = this_context;
33072 code = _Unwind_ForcedUnwind_Phase2 (exc, &cur_context);
33073 @@ -280,7 +284,9 @@ _Unwind_Backtrace(_Unwind_Trace_Fn trace
33074 struct _Unwind_Context context;
33075 _Unwind_Reason_Code code;
33077 - uw_init_context (&context);
33078 + code = uw_init_context (&context);
33079 + if (code != _URC_NO_REASON)
33080 + return _URC_FATAL_PHASE1_ERROR;
33086 @@ -1126,11 +1126,14 @@ align_variable (tree decl, bool dont_out
33088 #ifdef DATA_ALIGNMENT
33089 unsigned int data_align = DATA_ALIGNMENT (TREE_TYPE (decl), align);
33091 + unsigned int data_align = align;
33093 + data_align = alignment_for_aligned_arrays (TREE_TYPE (decl), data_align);
33094 /* Don't increase alignment too much for TLS variables - TLS space
33095 is too precious. */
33096 if (! DECL_THREAD_LOCAL_P (decl) || data_align <= BITS_PER_WORD)
33097 align = data_align;
33099 #ifdef CONSTANT_ALIGNMENT
33100 if (DECL_INITIAL (decl) != 0 && DECL_INITIAL (decl) != error_mark_node)
33102 @@ -3198,6 +3201,10 @@ build_constant_desc (tree exp)
33103 set_mem_alias_set (rtl, 0);
33104 set_mem_alias_set (rtl, const_alias_set);
33106 + /* We cannot share RTX'es in pool entries.
33107 + Mark this piece of RTL as required for unsharing. */
33108 + RTX_FLAG (rtl, used) = 1;
33110 /* Set flags or add text to the name to record information, such as
33111 that it is a local symbol. If the name is changed, the macro
33112 ASM_OUTPUT_LABELREF will have to know how to strip this
33113 --- a/gcc/vmsdbgout.c
33114 +++ b/gcc/vmsdbgout.c
33115 @@ -213,6 +213,7 @@ const struct gcc_debug_hooks vmsdbg_debu
33116 debug_nothing_int, /* handle_pch */
33117 debug_nothing_rtx, /* var_location */
33118 debug_nothing_void, /* switch_text_section */
33119 + debug_nothing_tree_tree, /* set_name */
33120 0 /* start_end_main_source_file */
33123 --- a/include/libiberty.h
33124 +++ b/include/libiberty.h
33125 @@ -591,6 +591,10 @@ extern int pexecute (const char *, char
33127 extern int pwait (int, int *, int);
33129 +/* Convert a Cygwin path to a Windows path. */
33131 +extern int cygpath (const char *, char []);
33133 #if !HAVE_DECL_ASPRINTF
33134 /* Like sprintf but provides a pointer to malloc'd storage, which must
33135 be freed by the caller. */
33136 --- a/libcpp/Makefile.in
33137 +++ b/libcpp/Makefile.in
33138 @@ -72,13 +72,12 @@ ALL_CFLAGS = $(CFLAGS) $(WARN_CFLAGS) $(
33139 libcpp_a_OBJS = charset.o directives.o directives-only.o errors.o \
33140 expr.o files.o identifiers.o init.o lex.o line-map.o macro.o \
33141 mkdeps.o pch.o symtab.o traditional.o
33142 -makedepend_OBJS = makedepend.o
33144 libcpp_a_SOURCES = charset.c directives.c directives-only.c errors.c \
33145 expr.c files.c identifiers.c init.c lex.c line-map.c macro.c \
33146 mkdeps.c pch.c symtab.c traditional.c
33148 -all: libcpp.a makedepend$(EXEEXT) $(USED_CATALOGS)
33149 +all: libcpp.a $(USED_CATALOGS)
33152 .SUFFIXES: .c .gmo .o .obj .po .pox
33153 @@ -88,12 +87,6 @@ libcpp.a: $(libcpp_a_OBJS)
33154 $(AR) $(ARFLAGS) libcpp.a $(libcpp_a_OBJS)
33157 -makedepend$(EXEEXT): $(makedepend_OBJS) libcpp.a ../libiberty/libiberty.a
33158 - @rm -f makedepend$(EXEEXT)
33159 - $(CC) $(CFLAGS) $(LDFLAGS) -o makedepend$(EXEEXT) \
33160 - $(makedepend_OBJS) libcpp.a ../libiberty/libiberty.a \
33161 - $(LIBINTL) $(LIBICONV)
33163 # Rules to rebuild the configuration
33165 Makefile: $(srcdir)/Makefile.in config.status
33166 @@ -165,7 +158,7 @@ mostlyclean:
33170 - -rm -rf makedepend$(EXEEXT) libcpp.a $(srcdir)/autom4te.cache
33171 + -rm -rf libcpp.a $(srcdir)/autom4te.cache
33174 -rm -f config.h stamp-h1 config.status config.cache config.log \
33175 @@ -247,7 +240,7 @@ po/$(PACKAGE).pot: $(libcpp_a_SOURCES)
33176 sed 's:$(srcdir)/::g' <po/$(PACKAGE).pot.tmp >po/$(PACKAGE).pot
33177 rm po/$(PACKAGE).pot.tmp
33179 -TAGS_SOURCES = $(libcpp_a_SOURCES) makedepend.c internal.h ucnid.h \
33180 +TAGS_SOURCES = $(libcpp_a_SOURCES) internal.h ucnid.h \
33181 include/line-map.h include/symtab.h include/cpp-id-data.h \
33182 include/cpplib.h include/mkdeps.h system.h
33184 @@ -259,7 +252,7 @@ TAGS: $(TAGS_SOURCES)
33188 --include $(patsubst %.o, $(DEPDIR)/%.Po, $(libcpp_a_OBJS) $(makedepend_OBJS))
33189 +-include $(patsubst %.o, $(DEPDIR)/%.Po, $(libcpp_a_OBJS))
33191 # Dependencies on generated headers have to be explicit.
33192 init.o: localedir.h
33193 --- a/libcpp/directives.c
33194 +++ b/libcpp/directives.c
33195 @@ -2376,13 +2376,6 @@ handle_assertion (cpp_reader *pfile, con
33196 run_directive (pfile, type, str, count);
33199 -/* The number of errors for a given reader. */
33201 -cpp_errors (cpp_reader *pfile)
33203 - return pfile->errors;
33206 /* The options structure. */
33208 cpp_get_options (cpp_reader *pfile)
33209 --- a/libcpp/errors.c
33210 +++ b/libcpp/errors.c
33211 @@ -28,171 +28,69 @@ along with this program; see the file CO
33212 #include "cpplib.h"
33213 #include "internal.h"
33215 -static void print_location (cpp_reader *, source_location, unsigned int);
33217 -/* Print the logical file location (LINE, COL) in preparation for a
33218 - diagnostic. Outputs the #include chain if it has changed. A line
33219 - of zero suppresses the include stack, and outputs the program name
33222 -print_location (cpp_reader *pfile, source_location line, unsigned int col)
33225 - fprintf (stderr, "%s: ", progname);
33228 - const struct line_map *map;
33229 - linenum_type lin;
33231 - map = linemap_lookup (pfile->line_table, line);
33232 - linemap_print_containing_files (pfile->line_table, map);
33234 - lin = SOURCE_LINE (map, line);
33237 - col = SOURCE_COLUMN (map, line);
33243 - fprintf (stderr, "%s:", map->to_file);
33244 - else if (CPP_OPTION (pfile, show_column) == 0)
33245 - fprintf (stderr, "%s:%u:", map->to_file, lin);
33247 - fprintf (stderr, "%s:%u:%u:", map->to_file, lin, col);
33249 - fputc (' ', stderr);
33253 -/* Set up for a diagnostic: print the file and line, bump the error
33254 - counter, etc. SRC_LOC is the logical line number; zero means to print
33255 - at the location of the previously lexed token, which tends to be
33256 - the correct place by default. The column number can be specified either
33257 - using COLUMN or (if COLUMN==0) extracting SOURCE_COLUMN from SRC_LOC.
33258 - (This may seem redundant, but is useful when pre-scanning (cleaning) a line,
33259 - when we haven't yet verified whether the current line_map has a
33260 - big enough max_column_hint.)
33262 - Returns 0 if the error has been suppressed. */
33264 -_cpp_begin_message (cpp_reader *pfile, int code,
33265 - source_location src_loc, unsigned int column)
33267 - int level = CPP_DL_EXTRACT (code);
33271 - case CPP_DL_WARNING:
33272 - case CPP_DL_PEDWARN:
33273 - if (cpp_in_system_header (pfile)
33274 - && ! CPP_OPTION (pfile, warn_system_headers))
33276 - /* Fall through. */
33278 - case CPP_DL_WARNING_SYSHDR:
33279 - if (CPP_OPTION (pfile, warnings_are_errors)
33280 - || (level == CPP_DL_PEDWARN && CPP_OPTION (pfile, pedantic_errors)))
33282 - if (CPP_OPTION (pfile, inhibit_errors))
33284 - level = CPP_DL_ERROR;
33287 - else if (CPP_OPTION (pfile, inhibit_warnings))
33291 - case CPP_DL_ERROR:
33292 - if (CPP_OPTION (pfile, inhibit_errors))
33294 - /* ICEs cannot be inhibited. */
33300 - print_location (pfile, src_loc, column);
33301 - if (CPP_DL_WARNING_P (level))
33302 - fputs (_("warning: "), stderr);
33303 - else if (level == CPP_DL_ICE)
33304 - fputs (_("internal error: "), stderr);
33306 - fputs (_("error: "), stderr);
33311 -/* Don't remove the blank before do, as otherwise the exgettext
33312 - script will mistake this as a function definition */
33313 -#define v_message(msgid, ap) \
33314 - do { vfprintf (stderr, _(msgid), ap); putc ('\n', stderr); } while (0)
33316 -/* Exported interface. */
33318 /* Print an error at the location of the previously lexed token. */
33321 cpp_error (cpp_reader * pfile, int level, const char *msgid, ...)
33323 source_location src_loc;
33328 va_start (ap, msgid);
33330 - if (CPP_OPTION (pfile, client_diagnostic))
33331 - pfile->cb.error (pfile, level, _(msgid), &ap);
33333 + if (CPP_OPTION (pfile, traditional))
33335 - if (CPP_OPTION (pfile, traditional))
33337 - if (pfile->state.in_directive)
33338 - src_loc = pfile->directive_line;
33340 - src_loc = pfile->line_table->highest_line;
33342 - /* We don't want to refer to a token before the beginning of the
33343 - current run -- that is invalid. */
33344 - else if (pfile->cur_token == pfile->cur_run->base)
33346 - if (pfile->cur_run->prev != NULL)
33347 - src_loc = pfile->cur_run->prev->limit->src_loc;
33351 + if (pfile->state.in_directive)
33352 + src_loc = pfile->directive_line;
33355 - src_loc = pfile->cur_token[-1].src_loc;
33358 - if (_cpp_begin_message (pfile, level, src_loc, 0))
33359 - v_message (msgid, ap);
33360 + src_loc = pfile->line_table->highest_line;
33362 + /* We don't want to refer to a token before the beginning of the
33363 + current run -- that is invalid. */
33364 + else if (pfile->cur_token == pfile->cur_run->base)
33366 + if (pfile->cur_run->prev != NULL)
33367 + src_loc = pfile->cur_run->prev->limit->src_loc;
33373 + src_loc = pfile->cur_token[-1].src_loc;
33376 + if (!pfile->cb.error)
33378 + ret = pfile->cb.error (pfile, level, src_loc, 0, _(msgid), &ap);
33384 /* Print an error at a specific location. */
33387 cpp_error_with_line (cpp_reader *pfile, int level,
33388 source_location src_loc, unsigned int column,
33389 const char *msgid, ...)
33394 va_start (ap, msgid);
33396 - if (_cpp_begin_message (pfile, level, src_loc, column))
33397 - v_message (msgid, ap);
33398 + if (!pfile->cb.error)
33400 + ret = pfile->cb.error (pfile, level, src_loc, column, _(msgid), &ap);
33408 cpp_errno (cpp_reader *pfile, int level, const char *msgid)
33410 if (msgid[0] == '\0')
33411 msgid = _("stdout");
33413 - cpp_error (pfile, level, "%s: %s", msgid, xstrerror (errno));
33414 + return cpp_error (pfile, level, "%s: %s", msgid, xstrerror (errno));
33416 --- a/libcpp/files.c
33417 +++ b/libcpp/files.c
33418 @@ -488,7 +488,6 @@ _cpp_find_file (cpp_reader *pfile, const
33422 - open_file_failed (pfile, file, angle_brackets);
33425 cpp_error (pfile, CPP_DL_ERROR,
33426 @@ -497,6 +496,7 @@ _cpp_find_file (cpp_reader *pfile, const
33427 cpp_error (pfile, CPP_DL_ERROR,
33428 "use -Winvalid-pch for more information");
33430 + open_file_failed (pfile, file, angle_brackets);
33434 @@ -934,15 +934,28 @@ open_file_failed (cpp_reader *pfile, _cp
33436 errno = file->err_no;
33437 if (print_dep && CPP_OPTION (pfile, deps.missing_files) && errno == ENOENT)
33438 - deps_add_dep (pfile->deps, file->name);
33440 + deps_add_dep (pfile->deps, file->name);
33441 + /* If the preprocessor output (other than dependency information) is
33442 + being used, we must also flag an error. */
33443 + if (CPP_OPTION (pfile, deps.need_preprocessor_output))
33444 + cpp_errno (pfile, CPP_DL_FATAL, file->path);
33448 - /* If we are outputting dependencies but not for this file then
33449 - don't error because we can still produce correct output. */
33450 - if (CPP_OPTION (pfile, deps.style) && ! print_dep)
33451 - cpp_errno (pfile, CPP_DL_WARNING, file->path);
33452 + /* If we are not outputting dependencies, or if we are and dependencies
33453 + were requested for this file, or if preprocessor output is needed
33454 + in addition to dependency information, this is an error.
33456 + Otherwise (outputting dependencies but not for this file, and not
33457 + using the preprocessor output), we can still produce correct output
33458 + so it's only a warning. */
33459 + if (CPP_OPTION (pfile, deps.style) == DEPS_NONE
33461 + || CPP_OPTION (pfile, deps.need_preprocessor_output))
33462 + cpp_errno (pfile, CPP_DL_FATAL, file->path);
33464 - cpp_errno (pfile, CPP_DL_ERROR, file->path);
33465 + cpp_errno (pfile, CPP_DL_WARNING, file->path);
33469 --- a/libcpp/include/cpplib.h
33470 +++ b/libcpp/include/cpplib.h
33471 @@ -302,22 +302,9 @@ struct cpp_options
33472 /* Nonzero means print names of header files (-H). */
33473 unsigned char print_include_names;
33475 - /* Nonzero means cpp_pedwarn causes a hard error. */
33476 - unsigned char pedantic_errors;
33478 - /* Nonzero means don't print warning messages. */
33479 - unsigned char inhibit_warnings;
33481 /* Nonzero means complain about deprecated features. */
33482 unsigned char warn_deprecated;
33484 - /* Nonzero means don't suppress warnings from system headers. */
33485 - unsigned char warn_system_headers;
33487 - /* Nonzero means don't print error messages. Has no option to
33488 - select it, but can be set by a user of cpplib (e.g. fix-header). */
33489 - unsigned char inhibit_errors;
33491 /* Nonzero means warn if slash-star appears in a comment. */
33492 unsigned char warn_comments;
33494 @@ -353,9 +340,6 @@ struct cpp_options
33495 explicitly undefined. */
33496 unsigned char warn_builtin_macro_redefined;
33498 - /* Nonzero means turn warnings into errors. */
33499 - unsigned char warnings_are_errors;
33501 /* Nonzero means we should look for header.gcc files that remap file
33503 unsigned char remap;
33504 @@ -432,6 +416,10 @@ struct cpp_options
33506 /* If true, no dependency is generated on the main file. */
33507 bool ignore_main_file;
33509 + /* If true, intend to use the preprocessor output (e.g., for compilation)
33510 + in addition to the dependency info. */
33511 + bool need_preprocessor_output;
33514 /* Target-specific features set by the front end or client. */
33515 @@ -450,9 +438,6 @@ struct cpp_options
33516 /* Nonzero means __STDC__ should have the value 0 in system headers. */
33517 unsigned char stdc_0_in_system_headers;
33519 - /* True means error callback should be used for diagnostics. */
33520 - bool client_diagnostic;
33522 /* True disables tokenization outside of preprocessing directives. */
33523 bool directives_only;
33525 @@ -492,10 +477,11 @@ struct cpp_callbacks
33527 cpp_hashnode * (*macro_to_expand) (cpp_reader *, const cpp_token *);
33529 - /* Called to emit a diagnostic if client_diagnostic option is true.
33530 - This callback receives the translated message. */
33531 - void (*error) (cpp_reader *, int, const char *, va_list *)
33532 - ATTRIBUTE_FPTR_PRINTF(3,0);
33533 + /* Called to emit a diagnostic. This callback receives the
33534 + translated message. */
33535 + bool (*error) (cpp_reader *, int, source_location, unsigned int,
33536 + const char *, va_list *)
33537 + ATTRIBUTE_FPTR_PRINTF(5,0);
33539 /* Callbacks for when a macro is expanded, or tested (whether
33540 defined or not at the time) in #ifdef, #ifndef or "defined". */
33541 @@ -697,19 +683,13 @@ extern void cpp_init_iconv (cpp_reader *
33543 /* Call this to finish preprocessing. If you requested dependency
33544 generation, pass an open stream to write the information to,
33545 - otherwise NULL. It is your responsibility to close the stream.
33547 - Returns cpp_errors (pfile). */
33548 -extern int cpp_finish (cpp_reader *, FILE *deps_stream);
33549 + otherwise NULL. It is your responsibility to close the stream. */
33550 +extern void cpp_finish (cpp_reader *, FILE *deps_stream);
33552 /* Call this to release the handle at the end of preprocessing. Any
33553 - use of the handle after this function returns is invalid. Returns
33554 - cpp_errors (pfile). */
33555 + use of the handle after this function returns is invalid. */
33556 extern void cpp_destroy (cpp_reader *);
33558 -/* Error count. */
33559 -extern unsigned int cpp_errors (cpp_reader *);
33561 extern unsigned int cpp_token_len (const cpp_token *);
33562 extern unsigned char *cpp_token_as_text (cpp_reader *, const cpp_token *);
33563 extern unsigned char *cpp_spell_token (cpp_reader *, const cpp_token *,
33564 @@ -835,24 +815,23 @@ cpp_num cpp_num_sign_extend (cpp_num, si
33565 /* An internal consistency check failed. Prints "internal error: ",
33566 otherwise the same as CPP_DL_ERROR. */
33567 #define CPP_DL_ICE 0x04
33568 -/* Extracts a diagnostic level from an int. */
33569 -#define CPP_DL_EXTRACT(l) (l & 0xf)
33570 -/* Nonzero if a diagnostic level is one of the warnings. */
33571 -#define CPP_DL_WARNING_P(l) (CPP_DL_EXTRACT (l) >= CPP_DL_WARNING \
33572 - && CPP_DL_EXTRACT (l) <= CPP_DL_PEDWARN)
33573 +/* An informative note following a warning. */
33574 +#define CPP_DL_NOTE 0x05
33575 +/* A fatal error. */
33576 +#define CPP_DL_FATAL 0x06
33578 /* Output a diagnostic of some kind. */
33579 -extern void cpp_error (cpp_reader *, int, const char *msgid, ...)
33580 +extern bool cpp_error (cpp_reader *, int, const char *msgid, ...)
33581 ATTRIBUTE_PRINTF_3;
33583 /* Output a diagnostic with "MSGID: " preceding the
33584 error string of errno. No location is printed. */
33585 -extern void cpp_errno (cpp_reader *, int, const char *msgid);
33586 +extern bool cpp_errno (cpp_reader *, int, const char *msgid);
33588 /* Same as cpp_error, except additionally specifies a position as a
33589 (translation unit) physical line and physical column. If the line is
33590 zero, then no location is printed. */
33591 -extern void cpp_error_with_line (cpp_reader *, int, source_location, unsigned,
33592 +extern bool cpp_error_with_line (cpp_reader *, int, source_location, unsigned,
33593 const char *msgid, ...) ATTRIBUTE_PRINTF_5;
33596 --- a/libcpp/include/line-map.h
33597 +++ b/libcpp/include/line-map.h
33598 @@ -144,12 +144,6 @@ extern const struct line_map *linemap_ad
33599 extern const struct line_map *linemap_lookup
33600 (struct line_maps *, source_location);
33602 -/* Print the file names and line numbers of the #include commands
33603 - which led to the map MAP, if any, to stderr. Nothing is output if
33604 - the most recently listed stack is the same as the current one. */
33605 -extern void linemap_print_containing_files (struct line_maps *,
33606 - const struct line_map *);
33608 /* Converts a map and a source_location to source line. */
33609 #define SOURCE_LINE(MAP, LOC) \
33610 ((((LOC) - (MAP)->start_location) >> (MAP)->column_bits) + (MAP)->to_line)
33611 --- a/libcpp/init.c
33612 +++ b/libcpp/init.c
33613 @@ -631,12 +631,11 @@ read_original_directory (cpp_reader *pfi
33616 /* This is called at the end of preprocessing. It pops the last
33617 - buffer and writes dependency output, and returns the number of
33619 + buffer and writes dependency output.
33621 Maybe it should also reset state, such that you could call
33622 cpp_start_read with a new filename to restart processing. */
33625 cpp_finish (cpp_reader *pfile, FILE *deps_stream)
33627 /* Warn about unused macros before popping the final buffer. */
33628 @@ -651,9 +650,8 @@ cpp_finish (cpp_reader *pfile, FILE *dep
33629 while (pfile->buffer)
33630 _cpp_pop_buffer (pfile);
33632 - /* Don't write the deps file if there are errors. */
33633 if (CPP_OPTION (pfile, deps.style) != DEPS_NONE
33634 - && deps_stream && pfile->errors == 0)
33637 deps_write (pfile->deps, deps_stream, 72);
33639 @@ -664,8 +662,6 @@ cpp_finish (cpp_reader *pfile, FILE *dep
33640 /* Report on headers that could use multiple include guards. */
33641 if (CPP_OPTION (pfile, print_include_names))
33642 _cpp_report_missing_guards (pfile);
33644 - return pfile->errors;
33648 --- a/libcpp/internal.h
33649 +++ b/libcpp/internal.h
33650 @@ -398,9 +398,6 @@ struct cpp_reader
33651 /* Nonzero prevents the lexer from re-using the token runs. */
33652 unsigned int keep_tokens;
33654 - /* Error counter for exit code. */
33655 - unsigned int errors;
33657 /* Buffer to hold macro definition string. */
33658 unsigned char *macro_buffer;
33659 unsigned int macro_buffer_len;
33660 --- a/libcpp/line-map.c
33661 +++ b/libcpp/line-map.c
33662 @@ -302,45 +302,6 @@ linemap_lookup (struct line_maps *set, s
33663 return &set->maps[mn];
33666 -/* Print the file names and line numbers of the #include commands
33667 - which led to the map MAP, if any, to stderr. Nothing is output if
33668 - the most recently listed stack is the same as the current one. */
33671 -linemap_print_containing_files (struct line_maps *set,
33672 - const struct line_map *map)
33674 - if (MAIN_FILE_P (map) || set->last_listed == map->included_from)
33677 - set->last_listed = map->included_from;
33678 - map = INCLUDED_FROM (set, map);
33680 - fprintf (stderr, _("In file included from %s:%u"),
33681 - map->to_file, LAST_SOURCE_LINE (map));
33683 - while (! MAIN_FILE_P (map))
33685 - map = INCLUDED_FROM (set, map);
33686 - /* Translators note: this message is used in conjunction
33687 - with "In file included from %s:%ld" and some other
33688 - tricks. We want something like this:
33690 - | In file included from sys/select.h:123,
33691 - | from sys/types.h:234,
33692 - | from userfile.c:31:
33693 - | bits/select.h:45: <error message here>
33695 - with all the "from"s lined up.
33696 - The trailing comma is at the beginning of this message,
33697 - and the trailing colon is not translated. */
33698 - fprintf (stderr, _(",\n from %s:%u"),
33699 - map->to_file, LAST_SOURCE_LINE (map));
33702 - fputs (":\n", stderr);
33705 /* Print an include trace, for e.g. the -H option of the preprocessor. */
33708 --- a/libcpp/macro.c
33709 +++ b/libcpp/macro.c
33710 @@ -1833,11 +1833,13 @@ _cpp_create_definition (cpp_reader *pfil
33712 if (warn_of_redefinition (pfile, node, macro))
33714 - cpp_error_with_line (pfile, CPP_DL_PEDWARN, pfile->directive_line, 0,
33715 - "\"%s\" redefined", NODE_NAME (node));
33717 + warned = cpp_error_with_line (pfile, CPP_DL_PEDWARN,
33718 + pfile->directive_line, 0,
33719 + "\"%s\" redefined", NODE_NAME (node));
33721 - if (node->type == NT_MACRO && !(node->flags & NODE_BUILTIN))
33722 - cpp_error_with_line (pfile, CPP_DL_PEDWARN,
33723 + if (warned && node->type == NT_MACRO && !(node->flags & NODE_BUILTIN))
33724 + cpp_error_with_line (pfile, CPP_DL_NOTE,
33725 node->value.macro->line, 0,
33726 "this is the location of the previous definition");
33728 --- a/libcpp/makedepend.c
33731 -/* Dependency generator utility.
33732 - Copyright (C) 2004 Free Software Foundation, Inc.
33733 - Contributed by Zack Weinberg, May 2004
33735 -This program is free software; you can redistribute it and/or modify it
33736 -under the terms of the GNU General Public License as published by the
33737 -Free Software Foundation; either version 2, or (at your option) any
33740 -This program is distributed in the hope that it will be useful,
33741 -but WITHOUT ANY WARRANTY; without even the implied warranty of
33742 -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33743 -GNU General Public License for more details.
33745 -You should have received a copy of the GNU General Public License
33746 -along with this program; if not, write to the Free Software
33747 -Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
33749 - In other words, you are welcome to use, share and improve this program.
33750 - You are forbidden to forbid anyone else to use, share and improve
33751 - what you give them. Help stamp out software-hoarding! */
33753 -#include "config.h"
33754 -#include "system.h"
33755 -#include "line-map.h"
33756 -#include "cpplib.h"
33757 -#include "getopt.h"
33758 -#include "mkdeps.h"
33760 -const char *progname;
33761 -const char *vpath;
33763 -static const char *output_file;
33764 -static bool had_errors;
33766 -/* Option lists, to give to cpplib before each input file. */
33767 -struct cmd_line_macro
33769 - struct cmd_line_macro *next;
33771 - const char *macro;
33774 -static struct cmd_line_macro *cmd_line_macros;
33775 -static cpp_dir *cmd_line_searchpath;
33778 -add_clm (const char *macro, bool is_undef)
33780 - struct cmd_line_macro *clm = XNEW (struct cmd_line_macro);
33781 - clm->next = cmd_line_macros;
33782 - clm->is_undef = is_undef;
33783 - clm->macro = macro;
33784 - cmd_line_macros = clm;
33788 -add_dir (char *name, bool sysp)
33790 - cpp_dir *dir = XNEW (cpp_dir);
33791 - dir->next = cmd_line_searchpath;
33792 - dir->name = name;
33793 - dir->sysp = sysp;
33794 - dir->construct = 0;
33795 - dir->user_supplied_p = 1;
33796 - cmd_line_searchpath = dir;
33799 -/* Command line processing. */
33801 -static void ATTRIBUTE_NORETURN
33802 -usage (int errcode)
33805 -"usage: %s [-vh] [-V vpath] [-Dname[=def]...] [-Uname] [-Idir...] [-o file] sources...\n",
33811 -parse_options (int argc, char **argv)
33813 - static const struct option longopts[] = {
33814 - { "--help", no_argument, 0, 'h' },
33819 - switch (getopt_long (argc, argv, "hD:U:I:J:o:V:", longopts, 0))
33821 - case 'h': usage (0);
33822 - case 'D': add_clm (optarg, false); break;
33823 - case 'U': add_clm (optarg, true); break;
33824 - case 'I': add_dir (optarg, false); break;
33825 - case 'J': add_dir (optarg, true); break;
33829 - fprintf (stderr, "%s: too many output files\n", progname);
33832 - output_file = optarg;
33837 - fprintf (stderr, "%s: too many vpaths\n", progname);
33843 - usage (2); /* getopt has issued the error message. */
33845 - case -1: /* end of options */
33846 - if (optind == argc)
33848 - fprintf (stderr, "%s: no input files\n", progname);
33858 -/* Set up cpplib from command line options. */
33859 -static cpp_reader *
33860 -reader_init (struct line_maps *line_table)
33862 - cpp_reader *reader;
33863 - cpp_options *options;
33865 - linemap_init (line_table);
33866 - reader = cpp_create_reader (CLK_GNUC89, 0, line_table);
33868 - /* Ignore warnings and errors (we don't have access to system
33869 - headers). Request dependency output. */
33870 - options = cpp_get_options (reader);
33871 - options->inhibit_warnings = 1;
33872 - options->inhibit_errors = 1;
33873 - options->deps.style = DEPS_USER;
33875 - /* Further initialization. */
33876 - cpp_post_options (reader);
33877 - cpp_init_iconv (reader);
33878 - cpp_set_include_chains (reader, cmd_line_searchpath, cmd_line_searchpath,
33882 - struct deps *deps = cpp_get_deps (reader);
33883 - deps_add_vpath (deps, vpath);
33889 -/* Process one input source file. */
33891 -process_file (const char *file)
33893 - struct line_maps line_table;
33894 - cpp_reader *reader = reader_init (&line_table);
33896 - if (!cpp_read_main_file (reader, file))
33897 - had_errors = true;
33900 - struct cmd_line_macro *clm;
33902 - cpp_init_builtins (reader, true);
33903 - for (clm = cmd_line_macros; clm; clm = clm->next)
33904 - (clm->is_undef ? cpp_undef : cpp_define) (reader, clm->macro);
33906 - cpp_scan_nooutput (reader);
33907 - if (cpp_finish (reader, stdout))
33908 - had_errors = true;
33910 - cpp_destroy (reader);
33911 - linemap_free (&line_table);
33914 -/* Master control. */
33917 -main(int argc, char **argv)
33919 - int first_input, i;
33921 - progname = argv[0];
33922 - xmalloc_set_program_name (progname);
33924 - first_input = parse_options (argc, argv);
33926 - if (!freopen (output_file, "w", stdout))
33928 - perror (output_file);
33932 - for (i = first_input; i < argc; i++)
33933 - process_file (argv[i]);
33935 - return had_errors;
33937 --- a/libgcc/Makefile.in
33938 +++ b/libgcc/Makefile.in
33939 @@ -389,18 +389,24 @@ libgcc-s-objects += $(patsubst %,%_s$(ob
33943 +ifeq ($(LIB2_DIVMOD_EXCEPTION_FLAGS),)
33944 +# Provide default flags for compiling divmod functions, if they haven't been
33945 +# set already by a target-specific Makefile fragment.
33946 +LIB2_DIVMOD_EXCEPTION_FLAGS := -fexceptions -fnon-call-exceptions
33949 # Build LIB2_DIVMOD_FUNCS.
33950 lib2-divmod-o = $(patsubst %,%$(objext),$(LIB2_DIVMOD_FUNCS))
33951 $(lib2-divmod-o): %$(objext): $(gcc_srcdir)/libgcc2.c
33952 $(gcc_compile) -DL$* -c $(gcc_srcdir)/libgcc2.c \
33953 - -fexceptions -fnon-call-exceptions $(vis_hide)
33954 + $(LIB2_DIVMOD_EXCEPTION_FLAGS) $(vis_hide)
33955 libgcc-objects += $(lib2-divmod-o)
33957 ifeq ($(enable_shared),yes)
33958 lib2-divmod-s-o = $(patsubst %,%_s$(objext),$(LIB2_DIVMOD_FUNCS))
33959 $(lib2-divmod-s-o): %_s$(objext): $(gcc_srcdir)/libgcc2.c
33960 $(gcc_s_compile) -DL$* -c $(gcc_srcdir)/libgcc2.c \
33961 - -fexceptions -fnon-call-exceptions
33962 + $(LIB2_DIVMOD_EXCEPTION_FLAGS)
33963 libgcc-s-objects += $(lib2-divmod-s-o)
33966 --- a/libgcc/config.host
33967 +++ b/libgcc/config.host
33968 @@ -203,12 +203,15 @@ arm*-*-netbsdelf*)
33971 arm*-*-linux*) # ARM GNU/Linux with ELF
33972 + tmake_file="${tmake_file} arm/t-divmod-ef"
33974 arm*-*-uclinux*) # ARM ucLinux
33975 + tmake_file="${tmake_file} arm/t-divmod-ef"
33979 arm*-*-eabi* | arm*-*-symbianelf* )
33980 + tmake_file="${tmake_file} arm/t-divmod-ef"
33984 @@ -394,8 +397,12 @@ mips-sgi-irix[56]*)
33985 mips*-*-netbsd*) # NetBSD/mips, either endian.
33988 + extra_parts="$extra_parts crtfastmath.o"
33989 + tmake_file="{$tmake_file} mips/t-crtfm"
33991 mips*-*-linux*) # Linux MIPS, either endian.
33992 + extra_parts="$extra_parts crtfastmath.o"
33993 + tmake_file="{$tmake_file} mips/t-crtfm"
33998 +++ b/libgcc/config/arm/t-divmod-ef
34000 +# On ARM, specifying -fnon-call-exceptions will needlessly pull in
34001 +# the unwinder in simple programs which use 64-bit division. Omitting
34002 +# the option is safe.
34003 +LIB2_DIVMOD_EXCEPTION_FLAGS := -fexceptions
34005 +++ b/libgcc/config/mips/t-crtfm
34007 +crtfastmath.o: $(gcc_srcdir)/config/mips/crtfastmath.c
34008 + $(gcc_compile) -c $(gcc_srcdir)/config/mips/crtfastmath.c
34010 --- a/libgcc/config/rs6000/t-ppccomm
34011 +++ b/libgcc/config/rs6000/t-ppccomm
34012 @@ -101,3 +101,63 @@ ncrti$(objext): ncrti.S
34014 ncrtn$(objext): ncrtn.S
34015 $(crt_compile) -c ncrtn.S
34017 +crtsavres$(objext): crtsavres.S
34018 + $(crt_compile) -c crtsavres.S
34020 +crtsavfpr$(objext): crtsavfpr.S
34021 + $(crt_compile) -c crtsavfpr.S
34023 +crtresfpr$(objext): crtresfpr.S
34024 + $(crt_compile) -c crtresfpr.S
34026 +crtsavgpr$(objext): crtsavgpr.S
34027 + $(crt_compile) -c crtsavgpr.S
34029 +crtresgpr$(objext): crtresgpr.S
34030 + $(crt_compile) -c crtresgpr.S
34032 +crtresxfpr$(objext): crtresxfpr.S
34033 + $(crt_compile) -c crtresxfpr.S
34035 +crtresxgpr$(objext): crtresxgpr.S
34036 + $(crt_compile) -c crtresxgpr.S
34038 +e500crtres32gpr$(objext): e500crtres32gpr.S
34039 + $(crt_compile) -c e500crtres32gpr.S
34041 +e500crtres64gpr$(objext): e500crtres64gpr.S
34042 + $(crt_compile) -c e500crtres64gpr.S
34044 +e500crtres64gprctr$(objext): e500crtres64gprctr.S
34045 + $(crt_compile) -c e500crtres64gprctr.S
34047 +e500crtrest32gpr$(objext): e500crtrest32gpr.S
34048 + $(crt_compile) -c e500crtrest32gpr.S
34050 +e500crtrest64gpr$(objext): e500crtrest64gpr.S
34051 + $(crt_compile) -c e500crtrest64gpr.S
34053 +e500crtresx32gpr$(objext): e500crtresx32gpr.S
34054 + $(crt_compile) -c e500crtresx32gpr.S
34056 +e500crtresx64gpr$(objext): e500crtresx64gpr.S
34057 + $(crt_compile) -c e500crtresx64gpr.S
34059 +e500crtsav32gpr$(objext): e500crtsav32gpr.S
34060 + $(crt_compile) -c e500crtsav32gpr.S
34062 +e500crtsav64gpr$(objext): e500crtsav64gpr.S
34063 + $(crt_compile) -c e500crtsav64gpr.S
34065 +e500crtsav64gprctr$(objext): e500crtsav64gprctr.S
34066 + $(crt_compile) -c e500crtsav64gprctr.S
34068 +e500crtsavg32gpr$(objext): e500crtsavg32gpr.S
34069 + $(crt_compile) -c e500crtsavg32gpr.S
34071 +e500crtsavg64gpr$(objext): e500crtsavg64gpr.S
34072 + $(crt_compile) -c e500crtsavg64gpr.S
34074 +e500crtsavg64gprctr$(objext): e500crtsavg64gprctr.S
34075 + $(crt_compile) -c e500crtsavg64gprctr.S
34076 --- a/libgcc/shared-object.mk
34077 +++ b/libgcc/shared-object.mk
34078 @@ -8,11 +8,13 @@ base := $(basename $(notdir $o))
34080 ifeq ($(suffix $o),.c)
34082 +c_flags-$(base)$(objext) := $(c_flags)
34083 $(base)$(objext): $o
34084 - $(gcc_compile) $(c_flags) -c $< $(vis_hide)
34085 + $(gcc_compile) $(c_flags-$@) -c $< $(vis_hide)
34087 +c_flags-$(base)_s$(objext) := $(c_flags)
34088 $(base)_s$(objext): $o
34089 - $(gcc_s_compile) $(c_flags) -c $<
34090 + $(gcc_s_compile) $(c_flags-$@) -c $<
34094 --- a/libgcc/static-object.mk
34095 +++ b/libgcc/static-object.mk
34096 @@ -8,8 +8,9 @@ base := $(basename $(notdir $o))
34098 ifeq ($(suffix $o),.c)
34100 +c_flags-$(base)$(objext) := $(c_flags)
34101 $(base)$(objext): $o
34102 - $(gcc_compile) $(c_flags) -c $< $(vis_hide)
34103 + $(gcc_compile) $(c_flags-$@) -c $< $(vis_hide)
34107 --- a/libgomp/Makefile.am
34108 +++ b/libgomp/Makefile.am
34110 ## Process this file with automake to produce Makefile.in
34112 +datarootdir = @datarootdir@
34114 +htmldir = @htmldir@
34117 ACLOCAL_AMFLAGS = -I .. -I ../config
34118 SUBDIRS = testsuite
34120 @@ -41,6 +46,12 @@ if USE_FORTRAN
34121 nodist_finclude_HEADERS = omp_lib.h omp_lib.f90 omp_lib.mod omp_lib_kinds.mod
34124 +LTLDFLAGS = $(shell $(SHELL) $(top_srcdir)/../libtool-ldflags $(LDFLAGS))
34126 +LINK = $(LIBTOOL) --tag CC --mode=link $(CCLD) $(AM_CCFLAGS) $(CFLAGS) \
34127 + $(AM_LDFLAGS) $(LTLDFLAGS) -o $@
34130 omp_lib_kinds.mod: omp_lib.mod
34132 omp_lib.mod: omp_lib.f90
34133 @@ -50,10 +61,30 @@ fortran.o: libgomp_f.h
34134 env.lo: libgomp_f.h
34137 +HTMLS_INSTALL=libgomp
34138 +HTMLS_BUILD=libgomp/index.html
34140 -# No install-html or install-pdf support in automake yet
34141 -.PHONY: install-html install-pdf
34143 +$(HTMLS_BUILD): $(info_TEXINFOS)
34144 + $(TEXI2HTML) $(MAKEINFOFLAGS) -I$(srcdir) -o $(@D) $<
34146 +html__strip_dir = `echo $$p | sed -e 's|^.*/||'`;
34148 +install-html: $(HTMLS_BUILD)
34149 + @$(NORMAL_INSTALL)
34150 + test -z "$(htmldir)" || $(mkinstalldirs) "$(DESTDIR)$(htmldir)"
34151 + @list='$(HTMLS_INSTALL)'; for p in $$list; do \
34152 + if test -f "$$p" || test -d "$$p"; then d=""; else d="$(srcdir)/"; fi; \
34153 + f=$(html__strip_dir) \
34154 + if test -d "$$d$$p"; then \
34155 + echo " $(mkinstalldirs) '$(DESTDIR)$(htmldir)/$$f'"; \
34156 + $(mkinstalldirs) "$(DESTDIR)$(htmldir)/$$f" || exit 1; \
34157 + echo " $(INSTALL_DATA) '$$d$$p'/* '$(DESTDIR)$(htmldir)/$$f'"; \
34158 + $(INSTALL_DATA) "$$d$$p"/* "$(DESTDIR)$(htmldir)/$$f"; \
34160 + echo " $(INSTALL_DATA) '$$d$$p' '$(DESTDIR)$(htmldir)/$$f'"; \
34161 + $(INSTALL_DATA) "$$d$$p" "$(DESTDIR)$(htmldir)/$$f"; \
34165 install-pdf: $(PDFS)
34167 @@ -71,6 +102,7 @@ install-pdf: $(PDFS)
34168 # `texinfo.tex' for your package. The value of this variable should be
34169 # the relative path from the current `Makefile.am' to `texinfo.tex'.
34170 TEXINFO_TEX = ../gcc/doc/include/texinfo.tex
34171 +TEXI2HTML = $(MAKEINFO) --html
34173 # Defines info, dvi, pdf and html targets
34174 MAKEINFOFLAGS = -I $(srcdir)/../gcc/doc/include
34175 --- a/libgomp/Makefile.in
34176 +++ b/libgomp/Makefile.in
34177 @@ -97,8 +97,6 @@ LTCOMPILE = $(LIBTOOL) --tag=CC --mode=c
34178 $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) \
34179 $(AM_CFLAGS) $(CFLAGS)
34181 -LINK = $(LIBTOOL) --tag=CC --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \
34182 - $(AM_LDFLAGS) $(LDFLAGS) -o $@
34183 SOURCES = $(libgomp_la_SOURCES)
34184 DIST_SOURCES = $(libgomp_la_SOURCES)
34186 @@ -259,6 +257,8 @@ build_os = @build_os@
34187 build_vendor = @build_vendor@
34188 config_path = @config_path@
34189 datadir = @datadir@
34190 +datarootdir = @datarootdir@
34192 enable_shared = @enable_shared@
34193 enable_static = @enable_static@
34194 exec_prefix = @exec_prefix@
34195 @@ -267,6 +267,7 @@ host_alias = @host_alias@
34196 host_cpu = @host_cpu@
34197 host_os = @host_os@
34198 host_vendor = @host_vendor@
34199 +htmldir = @htmldir@
34200 includedir = @includedir@
34201 infodir = @infodir@
34202 install_sh = @install_sh@
34203 @@ -280,6 +281,7 @@ mandir = @mandir@
34204 mkdir_p = @mkdir_p@
34205 multi_basedir = @multi_basedir@
34206 oldincludedir = @oldincludedir@
34209 program_transform_name = @program_transform_name@
34210 sbindir = @sbindir@
34211 @@ -317,6 +319,13 @@ libgomp_la_SOURCES = alloc.c barrier.c c
34212 nodist_noinst_HEADERS = libgomp_f.h
34213 nodist_libsubinclude_HEADERS = omp.h
34214 @USE_FORTRAN_TRUE@nodist_finclude_HEADERS = omp_lib.h omp_lib.f90 omp_lib.mod omp_lib_kinds.mod
34215 +LTLDFLAGS = $(shell $(SHELL) $(top_srcdir)/../libtool-ldflags $(LDFLAGS))
34216 +LINK = $(LIBTOOL) --tag CC --mode=link $(CCLD) $(AM_CCFLAGS) $(CFLAGS) \
34217 + $(AM_LDFLAGS) $(LTLDFLAGS) -o $@
34219 +HTMLS_INSTALL = libgomp
34220 +HTMLS_BUILD = libgomp/index.html
34221 +html__strip_dir = `echo $$p | sed -e 's|^.*/||'`;
34223 # Automake Documentation:
34224 # If your package has Texinfo files in many directories, you can use the
34225 @@ -324,6 +333,7 @@ nodist_libsubinclude_HEADERS = omp.h
34226 # `texinfo.tex' for your package. The value of this variable should be
34227 # the relative path from the current `Makefile.am' to `texinfo.tex'.
34228 TEXINFO_TEX = ../gcc/doc/include/texinfo.tex
34229 +TEXI2HTML = $(MAKEINFO) --html
34231 # Defines info, dvi, pdf and html targets
34232 MAKEINFOFLAGS = -I $(srcdir)/../gcc/doc/include
34233 @@ -1085,9 +1095,25 @@ fortran.o: libgomp_f.h
34234 env.lo: libgomp_f.h
34237 -# No install-html or install-pdf support in automake yet
34238 -.PHONY: install-html install-pdf
34240 +$(HTMLS_BUILD): $(info_TEXINFOS)
34241 + $(TEXI2HTML) $(MAKEINFOFLAGS) -I$(srcdir) -o $(@D) $<
34243 +install-html: $(HTMLS_BUILD)
34244 + @$(NORMAL_INSTALL)
34245 + test -z "$(htmldir)" || $(mkinstalldirs) "$(DESTDIR)$(htmldir)"
34246 + @list='$(HTMLS_INSTALL)'; for p in $$list; do \
34247 + if test -f "$$p" || test -d "$$p"; then d=""; else d="$(srcdir)/"; fi; \
34248 + f=$(html__strip_dir) \
34249 + if test -d "$$d$$p"; then \
34250 + echo " $(mkinstalldirs) '$(DESTDIR)$(htmldir)/$$f'"; \
34251 + $(mkinstalldirs) "$(DESTDIR)$(htmldir)/$$f" || exit 1; \
34252 + echo " $(INSTALL_DATA) '$$d$$p'/* '$(DESTDIR)$(htmldir)/$$f'"; \
34253 + $(INSTALL_DATA) "$$d$$p"/* "$(DESTDIR)$(htmldir)/$$f"; \
34255 + echo " $(INSTALL_DATA) '$$d$$p' '$(DESTDIR)$(htmldir)/$$f'"; \
34256 + $(INSTALL_DATA) "$$d$$p" "$(DESTDIR)$(htmldir)/$$f"; \
34260 install-pdf: $(PDFS)
34262 --- a/libgomp/configure
34263 +++ b/libgomp/configure
34264 @@ -457,7 +457,7 @@ ac_includes_default="\
34265 # include <unistd.h>
34268 -ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS GENINSRC_TRUE GENINSRC_FALSE build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CYGPATH_W PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM mkdir_p AWK SET_MAKE am__leading_dot AMTAR am__tar am__untar multi_basedir toolexecdir toolexeclibdir CC ac_ct_CC EXEEXT OBJEXT DEPDIR am__include am__quote AMDEP_TRUE AMDEP_FALSE AMDEPBACKSLASH CCDEPMODE am__fastdepCC_TRUE am__fastdepCC_FALSE CFLAGS AR ac_ct_AR RANLIB ac_ct_RANLIB PERL BUILD_INFO_TRUE BUILD_INFO_FALSE LIBTOOL SED EGREP FGREP GREP LD DUMPBIN ac_ct_DUMPBIN NM LN_S OBJDUMP ac_ct_OBJDUMP lt_ECHO DSYMUTIL ac_ct_DSYMUTIL NMEDIT ac_ct_NMEDIT LIPO ac_ct_LIPO OTOOL ac_ct_OTOOL OTOOL64 ac_ct_OTOOL64 CPP CPPFLAGS enable_shared enable_static MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT FC FCFLAGS LDFLAGS ac_ct_FC libtool_VERSION SECTION_LDFLAGS OPT_LDFLAGS LIBGOMP_BUILD_VERSIONED_SHLIB_TRUE LIBGOMP_BUILD_VERSIONED_SHLIB_FALSE config_path XCFLAGS XLDFLAGS link_gomp USE_FORTRAN_TRUE USE_FORTRAN_FALSE OMP_LOCK_SIZE OMP_LOCK_ALIGN OMP_NEST_LOCK_SIZE OMP_NEST_LOCK_ALIGN OMP_LOCK_KIND OMP_NEST_LOCK_KIND OMP_LOCK_25_SIZE OMP_LOCK_25_ALIGN OMP_NEST_LOCK_25_SIZE OMP_NEST_LOCK_25_ALIGN OMP_LOCK_25_KIND OMP_NEST_LOCK_25_KIND LIBOBJS LTLIBOBJS'
34269 +ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS GENINSRC_TRUE GENINSRC_FALSE build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CYGPATH_W PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM mkdir_p AWK SET_MAKE am__leading_dot AMTAR am__tar am__untar multi_basedir toolexecdir toolexeclibdir datarootdir docdir pdfdir htmldir CC ac_ct_CC EXEEXT OBJEXT DEPDIR am__include am__quote AMDEP_TRUE AMDEP_FALSE AMDEPBACKSLASH CCDEPMODE am__fastdepCC_TRUE am__fastdepCC_FALSE CFLAGS AR ac_ct_AR RANLIB ac_ct_RANLIB PERL BUILD_INFO_TRUE BUILD_INFO_FALSE LIBTOOL SED EGREP FGREP GREP LD DUMPBIN ac_ct_DUMPBIN NM LN_S OBJDUMP ac_ct_OBJDUMP lt_ECHO DSYMUTIL ac_ct_DSYMUTIL NMEDIT ac_ct_NMEDIT LIPO ac_ct_LIPO OTOOL ac_ct_OTOOL OTOOL64 ac_ct_OTOOL64 CPP CPPFLAGS enable_shared enable_static MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT FC FCFLAGS LDFLAGS ac_ct_FC libtool_VERSION SECTION_LDFLAGS OPT_LDFLAGS LIBGOMP_BUILD_VERSIONED_SHLIB_TRUE LIBGOMP_BUILD_VERSIONED_SHLIB_FALSE config_path XCFLAGS XLDFLAGS link_gomp USE_FORTRAN_TRUE USE_FORTRAN_FALSE OMP_LOCK_SIZE OMP_LOCK_ALIGN OMP_NEST_LOCK_SIZE OMP_NEST_LOCK_ALIGN OMP_LOCK_KIND OMP_NEST_LOCK_KIND OMP_LOCK_25_SIZE OMP_LOCK_25_ALIGN OMP_NEST_LOCK_25_SIZE OMP_NEST_LOCK_25_ALIGN OMP_LOCK_25_KIND OMP_NEST_LOCK_25_KIND LIBOBJS LTLIBOBJS'
34273 @@ -1029,6 +1029,10 @@ Optional Features:
34275 --with-PACKAGE[=ARG] use PACKAGE [ARG=yes]
34276 --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no)
34277 + --with-datarootdir=DIR Use DIR as the data root [PREFIX/share]
34278 + --with-docdir=DIR Install documentation in DIR [DATAROOTDIR]
34279 + --with-pdfdir install pdf in this directory.
34280 + --with-htmldir=DIR html documentation in in DIR [DOCDIR]
34281 --with-pic try to use only PIC/non-PIC objects [default=use
34283 --with-gnu-ld assume the C compiler uses GNU ld [default=no]
34284 @@ -2201,6 +2205,46 @@ esac
34289 +# Check whether --with-datarootdir or --without-datarootdir was given.
34290 +if test "${with_datarootdir+set}" = set; then
34291 + withval="$with_datarootdir"
34292 + datarootdir="\${prefix}/$with_datarootdir"
34294 + datarootdir='$(prefix)/share'
34299 +# Check whether --with-docdir or --without-docdir was given.
34300 +if test "${with_docdir+set}" = set; then
34301 + withval="$with_docdir"
34302 + docdir="\${prefix}/$with_docdir"
34304 + docdir='$(datarootdir)'
34309 +# Check whether --with-pdfdir or --without-pdfdir was given.
34310 +if test "${with_pdfdir+set}" = set; then
34311 + withval="$with_pdfdir"
34312 + pdfdir="\${prefix}/${withval}"
34314 + pdfdir="\${docdir}"
34319 +# Check whether --with-htmldir or --without-htmldir was given.
34320 +if test "${with_htmldir+set}" = set; then
34321 + withval="$with_htmldir"
34322 + htmldir="\${prefix}/$with_htmldir"
34324 + htmldir='$(docdir)'
34328 # Check the compiler.
34329 # The same as in boehm-gc and libstdc++. Have to borrow it from there.
34330 # We must force CC to /not/ be precious variables; otherwise
34331 @@ -4156,13 +4200,13 @@ if test "${lt_cv_nm_interface+set}" = se
34333 lt_cv_nm_interface="BSD nm"
34334 echo "int some_variable = 0;" > conftest.$ac_ext
34335 - (eval echo "\"\$as_me:4159: $ac_compile\"" >&5)
34336 + (eval echo "\"\$as_me:4203: $ac_compile\"" >&5)
34337 (eval "$ac_compile" 2>conftest.err)
34338 cat conftest.err >&5
34339 - (eval echo "\"\$as_me:4162: $NM \\\"conftest.$ac_objext\\\"\"" >&5)
34340 + (eval echo "\"\$as_me:4206: $NM \\\"conftest.$ac_objext\\\"\"" >&5)
34341 (eval "$NM \"conftest.$ac_objext\"" 2>conftest.err > conftest.out)
34342 cat conftest.err >&5
34343 - (eval echo "\"\$as_me:4165: output\"" >&5)
34344 + (eval echo "\"\$as_me:4209: output\"" >&5)
34345 cat conftest.out >&5
34346 if $GREP 'External.*some_variable' conftest.out > /dev/null; then
34347 lt_cv_nm_interface="MS dumpbin"
34348 @@ -5320,7 +5364,7 @@ ia64-*-hpux*)
34351 # Find out which ABI we are using.
34352 - echo '#line 5323 "configure"' > conftest.$ac_ext
34353 + echo '#line 5367 "configure"' > conftest.$ac_ext
34354 if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
34355 (eval $ac_compile) 2>&5
34357 @@ -7101,11 +7145,11 @@ else
34358 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
34359 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
34360 -e 's:$: $lt_compiler_flag:'`
34361 - (eval echo "\"\$as_me:7104: $lt_compile\"" >&5)
34362 + (eval echo "\"\$as_me:7148: $lt_compile\"" >&5)
34363 (eval "$lt_compile" 2>conftest.err)
34365 cat conftest.err >&5
34366 - echo "$as_me:7108: \$? = $ac_status" >&5
34367 + echo "$as_me:7152: \$? = $ac_status" >&5
34368 if (exit $ac_status) && test -s "$ac_outfile"; then
34369 # The compiler can only warn and ignore the option if not recognized
34370 # So say no if there are warnings other than the usual output.
34371 @@ -7440,11 +7484,11 @@ else
34372 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
34373 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
34374 -e 's:$: $lt_compiler_flag:'`
34375 - (eval echo "\"\$as_me:7443: $lt_compile\"" >&5)
34376 + (eval echo "\"\$as_me:7487: $lt_compile\"" >&5)
34377 (eval "$lt_compile" 2>conftest.err)
34379 cat conftest.err >&5
34380 - echo "$as_me:7447: \$? = $ac_status" >&5
34381 + echo "$as_me:7491: \$? = $ac_status" >&5
34382 if (exit $ac_status) && test -s "$ac_outfile"; then
34383 # The compiler can only warn and ignore the option if not recognized
34384 # So say no if there are warnings other than the usual output.
34385 @@ -7545,11 +7589,11 @@ else
34386 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
34387 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
34388 -e 's:$: $lt_compiler_flag:'`
34389 - (eval echo "\"\$as_me:7548: $lt_compile\"" >&5)
34390 + (eval echo "\"\$as_me:7592: $lt_compile\"" >&5)
34391 (eval "$lt_compile" 2>out/conftest.err)
34393 cat out/conftest.err >&5
34394 - echo "$as_me:7552: \$? = $ac_status" >&5
34395 + echo "$as_me:7596: \$? = $ac_status" >&5
34396 if (exit $ac_status) && test -s out/conftest2.$ac_objext
34398 # The compiler can only warn and ignore the option if not recognized
34399 @@ -7600,11 +7644,11 @@ else
34400 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
34401 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
34402 -e 's:$: $lt_compiler_flag:'`
34403 - (eval echo "\"\$as_me:7603: $lt_compile\"" >&5)
34404 + (eval echo "\"\$as_me:7647: $lt_compile\"" >&5)
34405 (eval "$lt_compile" 2>out/conftest.err)
34407 cat out/conftest.err >&5
34408 - echo "$as_me:7607: \$? = $ac_status" >&5
34409 + echo "$as_me:7651: \$? = $ac_status" >&5
34410 if (exit $ac_status) && test -s out/conftest2.$ac_objext
34412 # The compiler can only warn and ignore the option if not recognized
34413 @@ -10412,7 +10456,7 @@ else
34414 lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
34415 lt_status=$lt_dlunknown
34416 cat > conftest.$ac_ext <<_LT_EOF
34417 -#line 10415 "configure"
34418 +#line 10459 "configure"
34419 #include "confdefs.h"
34422 @@ -10508,7 +10552,7 @@ else
34423 lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
34424 lt_status=$lt_dlunknown
34425 cat > conftest.$ac_ext <<_LT_EOF
34426 -#line 10511 "configure"
34427 +#line 10555 "configure"
34428 #include "confdefs.h"
34431 @@ -10859,7 +10903,7 @@ fi
34434 # Provide some information about the compiler.
34435 -echo "$as_me:10862:" \
34436 +echo "$as_me:10906:" \
34437 "checking for Fortran compiler version" >&5
34438 ac_compiler=`set X $ac_compile; echo $2`
34439 { (eval echo "$as_me:$LINENO: \"$ac_compiler --version </dev/null >&5\"") >&5
34440 @@ -11095,7 +11139,7 @@ fi
34443 # Provide some information about the compiler.
34444 -echo "$as_me:11098:" \
34445 +echo "$as_me:11142:" \
34446 "checking for Fortran compiler version" >&5
34447 ac_compiler=`set X $ac_compile; echo $2`
34448 { (eval echo "$as_me:$LINENO: \"$ac_compiler --version </dev/null >&5\"") >&5
34449 @@ -11835,11 +11879,11 @@ else
34450 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
34451 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
34452 -e 's:$: $lt_compiler_flag:'`
34453 - (eval echo "\"\$as_me:11838: $lt_compile\"" >&5)
34454 + (eval echo "\"\$as_me:11882: $lt_compile\"" >&5)
34455 (eval "$lt_compile" 2>conftest.err)
34457 cat conftest.err >&5
34458 - echo "$as_me:11842: \$? = $ac_status" >&5
34459 + echo "$as_me:11886: \$? = $ac_status" >&5
34460 if (exit $ac_status) && test -s "$ac_outfile"; then
34461 # The compiler can only warn and ignore the option if not recognized
34462 # So say no if there are warnings other than the usual output.
34463 @@ -11934,11 +11978,11 @@ else
34464 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
34465 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
34466 -e 's:$: $lt_compiler_flag:'`
34467 - (eval echo "\"\$as_me:11937: $lt_compile\"" >&5)
34468 + (eval echo "\"\$as_me:11981: $lt_compile\"" >&5)
34469 (eval "$lt_compile" 2>out/conftest.err)
34471 cat out/conftest.err >&5
34472 - echo "$as_me:11941: \$? = $ac_status" >&5
34473 + echo "$as_me:11985: \$? = $ac_status" >&5
34474 if (exit $ac_status) && test -s out/conftest2.$ac_objext
34476 # The compiler can only warn and ignore the option if not recognized
34477 @@ -11986,11 +12030,11 @@ else
34478 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
34479 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
34480 -e 's:$: $lt_compiler_flag:'`
34481 - (eval echo "\"\$as_me:11989: $lt_compile\"" >&5)
34482 + (eval echo "\"\$as_me:12033: $lt_compile\"" >&5)
34483 (eval "$lt_compile" 2>out/conftest.err)
34485 cat out/conftest.err >&5
34486 - echo "$as_me:11993: \$? = $ac_status" >&5
34487 + echo "$as_me:12037: \$? = $ac_status" >&5
34488 if (exit $ac_status) && test -s out/conftest2.$ac_objext
34490 # The compiler can only warn and ignore the option if not recognized
34491 @@ -15133,7 +15177,8 @@ _ACEOF
34492 cat confdefs.h >>conftest.$ac_ext
34493 cat >>conftest.$ac_ext <<_ACEOF
34494 /* end confdefs.h. */
34495 -$ac_includes_default
34496 +/* no standard headers */
34501 @@ -15197,7 +15242,8 @@ _ACEOF
34502 cat confdefs.h >>conftest.$ac_ext
34503 cat >>conftest.$ac_ext <<_ACEOF
34504 /* end confdefs.h. */
34505 -$ac_includes_default
34506 +/* no standard headers */
34511 @@ -15238,7 +15284,8 @@ _ACEOF
34512 cat confdefs.h >>conftest.$ac_ext
34513 cat >>conftest.$ac_ext <<_ACEOF
34514 /* end confdefs.h. */
34515 -$ac_includes_default
34516 +/* no standard headers */
34521 @@ -15295,7 +15342,8 @@ _ACEOF
34522 cat confdefs.h >>conftest.$ac_ext
34523 cat >>conftest.$ac_ext <<_ACEOF
34524 /* end confdefs.h. */
34525 -$ac_includes_default
34526 +/* no standard headers */
34531 @@ -15336,7 +15384,8 @@ _ACEOF
34532 cat confdefs.h >>conftest.$ac_ext
34533 cat >>conftest.$ac_ext <<_ACEOF
34534 /* end confdefs.h. */
34535 -$ac_includes_default
34536 +/* no standard headers */
34541 @@ -15401,7 +15450,8 @@ _ACEOF
34542 cat confdefs.h >>conftest.$ac_ext
34543 cat >>conftest.$ac_ext <<_ACEOF
34544 /* end confdefs.h. */
34545 -$ac_includes_default
34546 +/* no standard headers */
34551 @@ -15469,7 +15519,8 @@ _ACEOF
34552 cat confdefs.h >>conftest.$ac_ext
34553 cat >>conftest.$ac_ext <<_ACEOF
34554 /* end confdefs.h. */
34555 -$ac_includes_default
34556 +/* no standard headers */
34558 long longval () { return (long) (sizeof (void *)); }
34559 unsigned long ulongval () { return (long) (sizeof (void *)); }
34561 @@ -15557,7 +15608,8 @@ _ACEOF
34562 cat confdefs.h >>conftest.$ac_ext
34563 cat >>conftest.$ac_ext <<_ACEOF
34564 /* end confdefs.h. */
34565 -$ac_includes_default
34566 +/* no standard headers */
34571 @@ -15621,7 +15673,8 @@ _ACEOF
34572 cat confdefs.h >>conftest.$ac_ext
34573 cat >>conftest.$ac_ext <<_ACEOF
34574 /* end confdefs.h. */
34575 -$ac_includes_default
34576 +/* no standard headers */
34581 @@ -15662,7 +15715,8 @@ _ACEOF
34582 cat confdefs.h >>conftest.$ac_ext
34583 cat >>conftest.$ac_ext <<_ACEOF
34584 /* end confdefs.h. */
34585 -$ac_includes_default
34586 +/* no standard headers */
34591 @@ -15719,7 +15773,8 @@ _ACEOF
34592 cat confdefs.h >>conftest.$ac_ext
34593 cat >>conftest.$ac_ext <<_ACEOF
34594 /* end confdefs.h. */
34595 -$ac_includes_default
34596 +/* no standard headers */
34601 @@ -15760,7 +15815,8 @@ _ACEOF
34602 cat confdefs.h >>conftest.$ac_ext
34603 cat >>conftest.$ac_ext <<_ACEOF
34604 /* end confdefs.h. */
34605 -$ac_includes_default
34606 +/* no standard headers */
34611 @@ -15825,7 +15881,8 @@ _ACEOF
34612 cat confdefs.h >>conftest.$ac_ext
34613 cat >>conftest.$ac_ext <<_ACEOF
34614 /* end confdefs.h. */
34615 -$ac_includes_default
34616 +/* no standard headers */
34621 @@ -15893,7 +15950,8 @@ _ACEOF
34622 cat confdefs.h >>conftest.$ac_ext
34623 cat >>conftest.$ac_ext <<_ACEOF
34624 /* end confdefs.h. */
34625 -$ac_includes_default
34626 +/* no standard headers */
34628 long longval () { return (long) (sizeof (long)); }
34629 unsigned long ulongval () { return (long) (sizeof (long)); }
34631 @@ -15981,7 +16039,8 @@ _ACEOF
34632 cat confdefs.h >>conftest.$ac_ext
34633 cat >>conftest.$ac_ext <<_ACEOF
34634 /* end confdefs.h. */
34635 -$ac_includes_default
34636 +/* no standard headers */
34641 @@ -16045,7 +16104,8 @@ _ACEOF
34642 cat confdefs.h >>conftest.$ac_ext
34643 cat >>conftest.$ac_ext <<_ACEOF
34644 /* end confdefs.h. */
34645 -$ac_includes_default
34646 +/* no standard headers */
34651 @@ -16086,7 +16146,8 @@ _ACEOF
34652 cat confdefs.h >>conftest.$ac_ext
34653 cat >>conftest.$ac_ext <<_ACEOF
34654 /* end confdefs.h. */
34655 -$ac_includes_default
34656 +/* no standard headers */
34661 @@ -16143,7 +16204,8 @@ _ACEOF
34662 cat confdefs.h >>conftest.$ac_ext
34663 cat >>conftest.$ac_ext <<_ACEOF
34664 /* end confdefs.h. */
34665 -$ac_includes_default
34666 +/* no standard headers */
34671 @@ -16184,7 +16246,8 @@ _ACEOF
34672 cat confdefs.h >>conftest.$ac_ext
34673 cat >>conftest.$ac_ext <<_ACEOF
34674 /* end confdefs.h. */
34675 -$ac_includes_default
34676 +/* no standard headers */
34681 @@ -16249,7 +16312,8 @@ _ACEOF
34682 cat confdefs.h >>conftest.$ac_ext
34683 cat >>conftest.$ac_ext <<_ACEOF
34684 /* end confdefs.h. */
34685 -$ac_includes_default
34686 +/* no standard headers */
34691 @@ -16317,7 +16381,8 @@ _ACEOF
34692 cat confdefs.h >>conftest.$ac_ext
34693 cat >>conftest.$ac_ext <<_ACEOF
34694 /* end confdefs.h. */
34695 -$ac_includes_default
34696 +/* no standard headers */
34698 long longval () { return (long) (sizeof (int)); }
34699 unsigned long ulongval () { return (long) (sizeof (int)); }
34701 @@ -16401,7 +16466,8 @@ _ACEOF
34702 cat confdefs.h >>conftest.$ac_ext
34703 cat >>conftest.$ac_ext <<_ACEOF
34704 /* end confdefs.h. */
34705 -$ac_includes_default
34706 +/* no standard headers */
34711 @@ -16465,7 +16531,8 @@ _ACEOF
34712 cat confdefs.h >>conftest.$ac_ext
34713 cat >>conftest.$ac_ext <<_ACEOF
34714 /* end confdefs.h. */
34715 -$ac_includes_default
34716 +/* no standard headers */
34721 @@ -16506,7 +16573,8 @@ _ACEOF
34722 cat confdefs.h >>conftest.$ac_ext
34723 cat >>conftest.$ac_ext <<_ACEOF
34724 /* end confdefs.h. */
34725 -$ac_includes_default
34726 +/* no standard headers */
34731 @@ -16563,7 +16631,8 @@ _ACEOF
34732 cat confdefs.h >>conftest.$ac_ext
34733 cat >>conftest.$ac_ext <<_ACEOF
34734 /* end confdefs.h. */
34735 -$ac_includes_default
34736 +/* no standard headers */
34741 @@ -16604,7 +16673,8 @@ _ACEOF
34742 cat confdefs.h >>conftest.$ac_ext
34743 cat >>conftest.$ac_ext <<_ACEOF
34744 /* end confdefs.h. */
34745 -$ac_includes_default
34746 +/* no standard headers */
34751 @@ -16669,7 +16739,8 @@ _ACEOF
34752 cat confdefs.h >>conftest.$ac_ext
34753 cat >>conftest.$ac_ext <<_ACEOF
34754 /* end confdefs.h. */
34755 -$ac_includes_default
34756 +/* no standard headers */
34761 @@ -16737,7 +16808,8 @@ _ACEOF
34762 cat confdefs.h >>conftest.$ac_ext
34763 cat >>conftest.$ac_ext <<_ACEOF
34764 /* end confdefs.h. */
34765 -$ac_includes_default
34766 +/* no standard headers */
34768 long longval () { return (long) (sizeof (short)); }
34769 unsigned long ulongval () { return (long) (sizeof (short)); }
34771 @@ -16821,7 +16893,8 @@ _ACEOF
34772 cat confdefs.h >>conftest.$ac_ext
34773 cat >>conftest.$ac_ext <<_ACEOF
34774 /* end confdefs.h. */
34775 -$ac_includes_default
34776 +/* no standard headers */
34781 @@ -16885,7 +16958,8 @@ _ACEOF
34782 cat confdefs.h >>conftest.$ac_ext
34783 cat >>conftest.$ac_ext <<_ACEOF
34784 /* end confdefs.h. */
34785 -$ac_includes_default
34786 +/* no standard headers */
34791 @@ -16926,7 +17000,8 @@ _ACEOF
34792 cat confdefs.h >>conftest.$ac_ext
34793 cat >>conftest.$ac_ext <<_ACEOF
34794 /* end confdefs.h. */
34795 -$ac_includes_default
34796 +/* no standard headers */
34801 @@ -16983,7 +17058,8 @@ _ACEOF
34802 cat confdefs.h >>conftest.$ac_ext
34803 cat >>conftest.$ac_ext <<_ACEOF
34804 /* end confdefs.h. */
34805 -$ac_includes_default
34806 +/* no standard headers */
34811 @@ -17024,7 +17100,8 @@ _ACEOF
34812 cat confdefs.h >>conftest.$ac_ext
34813 cat >>conftest.$ac_ext <<_ACEOF
34814 /* end confdefs.h. */
34815 -$ac_includes_default
34816 +/* no standard headers */
34821 @@ -17089,7 +17166,8 @@ _ACEOF
34822 cat confdefs.h >>conftest.$ac_ext
34823 cat >>conftest.$ac_ext <<_ACEOF
34824 /* end confdefs.h. */
34825 -$ac_includes_default
34826 +/* no standard headers */
34831 @@ -17157,7 +17235,8 @@ _ACEOF
34832 cat confdefs.h >>conftest.$ac_ext
34833 cat >>conftest.$ac_ext <<_ACEOF
34834 /* end confdefs.h. */
34835 -$ac_includes_default
34836 +/* no standard headers */
34838 long longval () { return (long) (sizeof (char)); }
34839 unsigned long ulongval () { return (long) (sizeof (char)); }
34841 @@ -17906,6 +17985,64 @@ if { (eval echo "$as_me:$LINENO: \"$ac_l
34843 echo "$as_me:$LINENO: \$? = $ac_status" >&5
34844 (exit $ac_status); }; }; then
34845 + chktls_save_LDFLAGS="$LDFLAGS"
34848 + LDFLAGS="-shared -Wl,--no-undefined $LDFLAGS"
34851 + chktls_save_CFLAGS="$CFLAGS"
34852 + CFLAGS="-fPIC $CFLAGS"
34853 + cat >conftest.$ac_ext <<_ACEOF
34854 +int f() { return 0; }
34856 +rm -f conftest.$ac_objext conftest$ac_exeext
34857 +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
34858 + (eval $ac_link) 2>conftest.er1
34860 + grep -v '^ *+' conftest.er1 >conftest.err
34861 + rm -f conftest.er1
34862 + cat conftest.err >&5
34863 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
34864 + (exit $ac_status); } &&
34865 + { ac_try='test -z "$ac_c_werror_flag"
34866 + || test ! -s conftest.err'
34867 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
34868 + (eval $ac_try) 2>&5
34870 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
34871 + (exit $ac_status); }; } &&
34872 + { ac_try='test -s conftest$ac_exeext'
34873 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
34874 + (eval $ac_try) 2>&5
34876 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
34877 + (exit $ac_status); }; }; then
34878 + cat >conftest.$ac_ext <<_ACEOF
34879 +__thread int a; int b; int f() { return a = b; }
34881 +rm -f conftest.$ac_objext conftest$ac_exeext
34882 +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
34883 + (eval $ac_link) 2>conftest.er1
34885 + grep -v '^ *+' conftest.er1 >conftest.err
34886 + rm -f conftest.er1
34887 + cat conftest.err >&5
34888 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
34889 + (exit $ac_status); } &&
34890 + { ac_try='test -z "$ac_c_werror_flag"
34891 + || test ! -s conftest.err'
34892 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
34893 + (eval $ac_try) 2>&5
34895 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
34896 + (exit $ac_status); }; } &&
34897 + { ac_try='test -s conftest$ac_exeext'
34898 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
34899 + (eval $ac_try) 2>&5
34901 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
34902 + (exit $ac_status); }; }; then
34903 gcc_cv_have_tls=yes
34905 echo "$as_me: failed program was:" >&5
34906 @@ -17915,6 +18052,24 @@ gcc_cv_have_tls=no
34908 rm -f conftest.err conftest.$ac_objext \
34909 conftest$ac_exeext conftest.$ac_ext
34911 + echo "$as_me: failed program was:" >&5
34912 +sed 's/^/| /' conftest.$ac_ext >&5
34914 +gcc_cv_have_tls=yes
34916 +rm -f conftest.err conftest.$ac_objext \
34917 + conftest$ac_exeext conftest.$ac_ext
34918 + CFLAGS="$chktls_save_CFLAGS"
34919 + LDFLAGS="$chktls_save_LDFLAGS"
34921 + echo "$as_me: failed program was:" >&5
34922 +sed 's/^/| /' conftest.$ac_ext >&5
34924 +gcc_cv_have_tls=no
34926 +rm -f conftest.err conftest.$ac_objext \
34927 + conftest$ac_exeext conftest.$ac_ext
34931 @@ -22801,6 +22956,10 @@ s,@am__untar@,$am__untar,;t t
34932 s,@multi_basedir@,$multi_basedir,;t t
34933 s,@toolexecdir@,$toolexecdir,;t t
34934 s,@toolexeclibdir@,$toolexeclibdir,;t t
34935 +s,@datarootdir@,$datarootdir,;t t
34936 +s,@docdir@,$docdir,;t t
34937 +s,@pdfdir@,$pdfdir,;t t
34938 +s,@htmldir@,$htmldir,;t t
34940 s,@ac_ct_CC@,$ac_ct_CC,;t t
34941 s,@EXEEXT@,$EXEEXT,;t t
34942 --- a/libgomp/configure.ac
34943 +++ b/libgomp/configure.ac
34944 @@ -94,6 +94,30 @@ esac
34945 AC_SUBST(toolexecdir)
34946 AC_SUBST(toolexeclibdir)
34948 +AC_ARG_WITH(datarootdir,
34949 +[ --with-datarootdir=DIR Use DIR as the data root [[PREFIX/share]]],
34950 +datarootdir="\${prefix}/$with_datarootdir",
34951 +datarootdir='$(prefix)/share')
34952 +AC_SUBST(datarootdir)
34954 +AC_ARG_WITH(docdir,
34955 +[ --with-docdir=DIR Install documentation in DIR [[DATAROOTDIR]]],
34956 +docdir="\${prefix}/$with_docdir",
34957 +docdir='$(datarootdir)')
34960 +AC_ARG_WITH(pdfdir,
34961 +[ --with-pdfdir install pdf in this directory.],
34962 +[pdfdir="\${prefix}/${withval}"],
34963 +[pdfdir="\${docdir}"])
34966 +AC_ARG_WITH(htmldir,
34967 +[ --with-htmldir=DIR html documentation in in DIR [[DOCDIR]]],
34968 +htmldir="\${prefix}/$with_htmldir",
34969 +htmldir='$(docdir)')
34972 # Check the compiler.
34973 # The same as in boehm-gc and libstdc++. Have to borrow it from there.
34974 # We must force CC to /not/ be precious variables; otherwise
34975 --- a/libgomp/libgomp.texi
34976 +++ b/libgomp/libgomp.texi
34977 @@ -94,7 +94,7 @@ for multi-platform shared-memory paralle
34978 How you can copy and share this manual.
34979 * Funding:: How to help assure continued work for free
34981 -* Index:: Index of this documentation.
34982 +* Library Index:: Index of this documentation.
34986 @@ -1713,8 +1713,8 @@ Bugs in the GNU OpenMP implementation sh
34988 @c ---------------------------------------------------------------------
34992 +@node Library Index
34993 +@unnumbered Library Index
34997 --- a/libgomp/testsuite/Makefile.in
34998 +++ b/libgomp/testsuite/Makefile.in
34999 @@ -177,6 +177,8 @@ build_os = @build_os@
35000 build_vendor = @build_vendor@
35001 config_path = @config_path@
35002 datadir = @datadir@
35003 +datarootdir = @datarootdir@
35005 enable_shared = @enable_shared@
35006 enable_static = @enable_static@
35007 exec_prefix = @exec_prefix@
35008 @@ -185,6 +187,7 @@ host_alias = @host_alias@
35009 host_cpu = @host_cpu@
35010 host_os = @host_os@
35011 host_vendor = @host_vendor@
35012 +htmldir = @htmldir@
35013 includedir = @includedir@
35014 infodir = @infodir@
35015 install_sh = @install_sh@
35016 @@ -198,6 +201,7 @@ mandir = @mandir@
35017 mkdir_p = @mkdir_p@
35018 multi_basedir = @multi_basedir@
35019 oldincludedir = @oldincludedir@
35022 program_transform_name = @program_transform_name@
35023 sbindir = @sbindir@
35024 --- a/libiberty/Makefile.in
35025 +++ b/libiberty/Makefile.in
35026 @@ -124,7 +124,7 @@ COMPILE.c = $(CC) -c @DEFS@ $(CFLAGS) $(
35027 CFILES = alloca.c argv.c asprintf.c atexit.c \
35028 basename.c bcmp.c bcopy.c bsearch.c bzero.c \
35029 calloc.c choose-temp.c clock.c concat.c cp-demangle.c \
35030 - cp-demint.c cplus-dem.c \
35031 + cp-demint.c cplus-dem.c cygpath.c \
35033 fdmatch.c ffs.c fibheap.c filename_cmp.c floatformat.c \
35034 fnmatch.c fopen_unlocked.c \
35035 @@ -182,7 +182,7 @@ REQUIRED_OFILES = \
35036 # maint-missing" and "make check".
35037 CONFIGURED_OFILES = ./asprintf.o ./atexit.o \
35038 ./basename.o ./bcmp.o ./bcopy.o ./bsearch.o ./bzero.o \
35039 - ./calloc.o ./clock.o ./copysign.o \
35040 + ./calloc.o ./clock.o ./copysign.o ./cygpath.o \
35043 ./getcwd.o ./getpagesize.o ./gettimeofday.o \
35044 @@ -619,6 +619,13 @@ $(CONFIGURED_OFILES): stamp-picdir
35046 $(COMPILE.c) $(srcdir)/cplus-dem.c $(OUTPUT_OPTION)
35048 +./cygpath.o: $(srcdir)/cygpath.c config.h $(INCDIR)/ansidecl.h \
35049 + $(INCDIR)/libiberty.h
35050 + if [ x"$(PICFLAG)" != x ]; then \
35051 + $(COMPILE.c) $(PICFLAG) $(srcdir)/cygpath.c -o pic/$@; \
35053 + $(COMPILE.c) $(srcdir)/cygpath.c $(OUTPUT_OPTION)
35055 ./dyn-string.o: $(srcdir)/dyn-string.c config.h $(INCDIR)/ansidecl.h \
35056 $(INCDIR)/dyn-string.h $(INCDIR)/libiberty.h
35057 if [ x"$(PICFLAG)" != x ]; then \
35058 --- a/libiberty/argv.c
35059 +++ b/libiberty/argv.c
35060 @@ -119,6 +119,24 @@ void freeargv (char **vector)
35065 +consume_whitespace (const char **input)
35067 + while (ISSPACE (**input))
35074 +only_whitespace (const char* input)
35076 + while (*input != EOS && ISSPACE (*input))
35079 + return (*input == EOS);
35084 @deftypefn Extension char** buildargv (char *@var{sp})
35085 @@ -179,10 +197,8 @@ char **buildargv (const char *input)
35088 /* Pick off argv[argc] */
35089 - while (ISBLANK (*input))
35093 + consume_whitespace (&input);
35095 if ((maxargc == 0) || (argc >= (maxargc - 1)))
35097 /* argv needs initialization, or expansion */
35098 @@ -278,10 +294,7 @@ char **buildargv (const char *input)
35102 - while (ISSPACE (*input))
35106 + consume_whitespace (&input);
35108 while (*input != EOS);
35110 @@ -420,8 +433,17 @@ expandargv (int *argcp, char ***argvp)
35112 /* Add a NUL terminator. */
35113 buffer[len] = '\0';
35114 - /* Parse the string. */
35115 - file_argv = buildargv (buffer);
35116 + /* If the file is empty or contains only whitespace, buildargv would
35117 + return a single empty argument. In this context we want no arguments,
35119 + if (only_whitespace (buffer))
35121 + file_argv = (char **) xmalloc (sizeof (char *));
35122 + file_argv[0] = NULL;
35125 + /* Parse the string. */
35126 + file_argv = buildargv (buffer);
35127 /* If *ARGVP is not already dynamically allocated, copy it. */
35130 @@ -434,7 +456,7 @@ expandargv (int *argcp, char ***argvp)
35132 /* Count the number of arguments. */
35134 - while (file_argv[file_argc] && *file_argv[file_argc])
35135 + while (file_argv[file_argc])
35137 /* Now, insert FILE_ARGV into ARGV. The "+1" below handles the
35138 NULL terminator at the end of ARGV. */
35139 --- a/libiberty/configure
35140 +++ b/libiberty/configure
35141 @@ -8891,6 +8891,20 @@ case "${host}" in
35145 +# On MinGW, add support for Cygwin paths.
35149 + "cygpath.$ac_objext" | \
35150 + *" cygpath.$ac_objext" | \
35151 + "cygpath.$ac_objext "* | \
35152 + *" cygpath.$ac_objext "* ) ;;
35153 + *) LIBOBJS="$LIBOBJS cygpath.$ac_objext" ;;
35159 if test x$gcc_no_link = xyes; then
35160 if test "x${ac_cv_func_mmap_fixed_mapped+set}" != xset; then
35161 ac_cv_func_mmap_fixed_mapped=no
35162 --- a/libiberty/configure.ac
35163 +++ b/libiberty/configure.ac
35164 @@ -663,6 +663,13 @@ case "${host}" in
35168 +# On MinGW, add support for Cygwin paths.
35171 + AC_LIBOBJ([cygpath])
35175 libiberty_AC_FUNC_STRNCMP
35177 # Install a library built with a cross compiler in $(tooldir) rather
35179 +++ b/libiberty/cygpath.c
35181 +/* Support Cygwin paths under MinGW.
35182 + Copyright (C) 2006 Free Software Foundation, Inc.
35183 + Written by CodeSourcery.
35185 +This file is part of the libiberty library.
35186 +Libiberty is free software; you can redistribute it and/or modify it
35187 +under the terms of the GNU Library General Public License as published
35188 +by the Free Software Foundation; either version 2 of the License, or
35189 +(at your option) any later version.
35191 +Libiberty is distributed in the hope that it will be useful,
35192 +but WITHOUT ANY WARRANTY; without even the implied warranty of
35193 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
35194 +Library General Public License for more details.
35196 +You should have received a copy of the GNU Library General Public
35197 +License along with libiberty; see the file COPYING.LIB. If not, write
35198 +to the Free Software Foundation, Inc., 51 Franklin Street - Fifth
35199 +Floor, Boston, MA 02110-1301, USA. */
35201 +#include <windows.h>
35202 +#include <errno.h>
35203 +#include <fcntl.h>
35204 +#include <sys/stat.h>
35205 +#include <sys/types.h>
35207 +#include <process.h>
35208 +#include <stdbool.h>
35209 +#include <stdio.h>
35210 +#include <stdlib.h>
35211 +#include "libiberty.h"
35213 +/* If non-zero, we have attempted to use cygpath. CYGPATH_PEX may
35214 + still be NULL, if cygpath is unavailable. */
35215 +static int cygpath_initialized;
35217 +/* If non-NULL, an instance of cygpath connected via a pipe. */
35218 +static struct pex_obj *cygpath_pex;
35220 +/* The input to cygpath. */
35221 +static FILE *cygpath_in;
35223 +/* The output from cygpath. */
35224 +static FILE *cygpath_out;
35226 +/* If non-NULL, a file to which path translations are logged. */
35227 +static FILE *cygpath_log;
35229 +/* Record MESSAGE in the CYGPATH_LOG. MESSAGE is a format string,
35230 + which is expected to have a single "%s" field, to be replaced by
35233 +cygpath_log_msg_arg (const char *message, const char *arg)
35235 + if (!cygpath_log)
35237 + fprintf (cygpath_log, "[%d] cygpath: ", _getpid ());
35238 + fprintf (cygpath_log, message, arg);
35239 + fprintf (cygpath_log, "\n");
35240 + fflush (cygpath_log);
35243 +/* Record MESSAGE in the CYGPATH_LOG. */
35245 +cygpath_log_msg (const char *message)
35247 + cygpath_log_msg_arg ("%s", message);
35250 +/* An error has occured. Add the MESSAGE to the CYGPATH_LOG, noting
35251 + the cause of the error based on errno. */
35253 +cygpath_perror (const char *message)
35255 + if (!cygpath_log)
35257 + fprintf (cygpath_log, "[%d] cygpath: error: %s: %s\n",
35258 + _getpid(), message, strerror (errno));
35259 + fflush (cygpath_log);
35262 +/* Closes CYGPATH_PEX and frees all associated
35265 +cygpath_close (void)
35267 + /* Free resources. */
35270 + fclose (cygpath_out);
35271 + cygpath_out = NULL;
35275 + fclose (cygpath_in);
35276 + cygpath_in = NULL;
35280 + pex_free (cygpath_pex);
35281 + cygpath_pex = NULL;
35285 + cygpath_log_msg ("end");
35286 + cygpath_log = NULL;
35290 +/* CYG_PATH is a pointer to a Cygwin path. This function converts the
35291 + Cygwin path to a Windows path, storing the result in
35292 + WIN32_PATH. Returns true if the conversion was successful; false
35295 +cygpath (const char *cyg_path, char win32_path[MAX_PATH + 1])
35300 + /* Special-case the empty path. cygpath cannot handle the empty
35301 + path correctly. It ignores the empty line, waiting for a
35302 + non-empty line, which in turn causes an application using this
35303 + function to appear stuck. */
35304 + if (cyg_path[0] == '\0')
35306 + win32_path[0] = '\0';
35310 + retrying = false;
35313 + if (!cygpath_initialized)
35315 + const char *argv[] = { "cygpath", "-w", "-f", "-", NULL };
35316 + const char *cygpath_path;
35320 + /* If we are unable to invoke cygpath, we do not want to try
35321 + again. So, we set the initialized flag at this point; if
35322 + errors occur during the invocation, it will remain set. */
35323 + cygpath_initialized = 1;
35324 + /* Check to see if the user wants cygpath support. */
35325 + cygpath_path = getenv ("CYGPATH");
35326 + if (!cygpath_path)
35327 + /* The user doesn't need to support Cygwin paths. */
35329 + /* If debugging, open the log file. */
35330 + log = getenv ("CSL_DEBUG_CYGPATH");
35331 + if (log && log[0])
35333 + /* The log file is opened for "append" so that multiple
35334 + processes (perhaps invoked from "make") can share it. */
35335 + cygpath_log = fopen (log, "a");
35337 + cygpath_log_msg ("begin");
35339 + /* If the environment variable is set to a non-empty string, use
35340 + that string as the path to cygpath. */
35341 + if (cygpath_path[0] != '\0')
35342 + argv[0] = cygpath_path;
35343 + /* Create the pex object. */
35344 + cygpath_pex = pex_init (PEX_SEARCH | PEX_USE_PIPES,
35345 + "cygpath", NULL);
35346 + if (!cygpath_pex)
35348 + /* Get the FILE we will use to write to the child. */
35349 + cygpath_in = pex_input_pipe (cygpath_pex, /*binary=*/0);
35352 + /* Start the child process. */
35353 + if (pex_run (cygpath_pex, PEX_SEARCH | PEX_USE_PIPES,
35354 + argv[0], (char**) argv,
35358 + /* Get the FILE we will use to read from the child. */
35359 + cygpath_out = pex_read_output (cygpath_pex, /*binary=*/1);
35360 + if (!cygpath_out)
35363 + else if (!cygpath_pex)
35364 + /* We previously tried to use cygpath, but something went wrong. */
35367 + /* Write CYG_PATH to the child, on a line by itself. */
35368 + cygpath_log_msg_arg ("-> %s", cyg_path);
35369 + if (fprintf (cygpath_in, "%s\n", cyg_path) < 0)
35371 + cygpath_perror ("write failed");
35374 + /* Flush the output. (We cannot set the stream into line-buffered
35375 + mode with setvbuf because Windows treats _IOLBF as a synonym for
35377 + if (fflush (cygpath_in))
35378 + cygpath_perror ("flush failed");
35379 + /* Read the output. */
35384 + if (!fgets (win32_path, MAX_PATH, cygpath_out))
35386 + if (ferror (cygpath_out))
35387 + cygpath_perror ("read failed");
35390 + cygpath_log_msg ("error: EOF");
35391 + /* Unfortunately, cygpath sometimes crashes for no
35392 + apparent reason. We give it two chances... */
35396 + cygpath_log_msg ("retrying");
35397 + cygpath_close ();
35398 + cygpath_initialized = 0;
35404 + pathlen = strlen (win32_path);
35405 + if (pathlen == 0 && ok)
35406 + /* This isn't a well-formed response from cygpath. */
35408 + if (win32_path[pathlen - 1] == '\n')
35410 + win32_path[pathlen - 1] = '\0';
35411 + cygpath_log_msg_arg ("<- %s", win32_path);
35414 + /* We didn't reach the end of the line. There's no point in
35415 + trying to use this output, since we know the length of
35416 + paths are limited to MAX_PATH characters, but we read the
35417 + entire line so that we are still in sync with
35421 + cygpath_log_msg_arg ("error: invalid response: %s",
35432 +/* Returns the handle for the MVCRT DLL, or NULL if it is not
35437 + static HMODULE dll = (HMODULE)(-1);
35439 + /* After we call LoadLibrary, DLL will be either a valid handle or
35440 + NULL, so this check ensures that we only try to load the library
35442 + if (dll == (HMODULE)(-1))
35443 + dll = LoadLibrary ("msvcrt.dll");
35448 +/* Call the underlying MSVCRT fopen with PATH and MODE, and return
35449 + what it returns. */
35451 +msvcrt_fopen (const char *path, const char *mode)
35453 + typedef FILE *(fopen_type)(const char *path,
35454 + const char *mode);
35456 + static fopen_type *f = NULL;
35458 + /* Get the address of "fopen". */
35461 + HMODULE dll = msvcrt_dll ();
35467 + f = (fopen_type *) GetProcAddress (dll, "fopen");
35475 + /* Call fopen. */
35476 + return (*f)(path, mode);
35480 +fopen (const char *path, const char *mode)
35483 + char win32_path[MAX_PATH + 1];
35485 + /* Assume PATH is a Windows path. */
35486 + f = msvcrt_fopen (path, mode);
35487 + if (f || errno != ENOENT)
35489 + /* Perhaps it is a Cygwin path? */
35490 + if (cygpath (path, win32_path))
35491 + f = msvcrt_fopen (win32_path, mode);
35496 +open (const char *path, int oflag, ...)
35499 + char win32_path[MAX_PATH + 1];
35502 + if ((oflag & _O_CREAT))
35505 + va_start (ap, oflag);
35506 + pmode = va_arg (ap, int);
35510 + /* Assume PATH is a Windows path. */
35511 + fd = _open (path, oflag, pmode);
35512 + if (fd != -1 || errno != ENOENT)
35514 + /* Perhaps it is a Cygwin path? */
35515 + if (cygpath (path, win32_path))
35516 + fd = _open (win32_path, oflag, pmode);
35521 +stat (const char *path, struct stat *buffer)
35524 + char win32_path[MAX_PATH + 1];
35526 + /* Assume PATH is a Windows path. */
35527 + r = _stat (path, (struct _stat *) buffer);
35528 + if (r != -1 || errno != ENOENT)
35530 + /* Perhaps it is a Cygwin path? */
35531 + if (cygpath (path, win32_path))
35532 + r = _stat (win32_path, (struct _stat *) buffer);
35537 +access (const char *path, int mode)
35540 + char win32_path[MAX_PATH + 1];
35543 + /* Some GNU tools mistakenly defined X_OK to 1 on Windows. */
35544 + mode = mode & ~1;
35546 + /* Assume PATH is a Windows path. */
35547 + r = _access (path, mode);
35548 + if (r != -1 || errno != ENOENT)
35550 + /* Perhaps it is a Cygwin path? */
35551 + if (cygpath (path, win32_path))
35552 + r = _access (win32_path, mode);
35556 +/* Given the WINDOWS_CODE (typically the result of GetLastError), set
35557 + ERRNO to the corresponding error code. If there is no obvious
35558 + correspondence, ERRNO will be set to EACCES. */
35560 +set_errno_from_windows_code (DWORD windows_code)
35562 + int mapping[][2] = {
35563 + {ERROR_ACCESS_DENIED, EACCES},
35564 + {ERROR_ACCOUNT_DISABLED, EACCES},
35565 + {ERROR_ACCOUNT_RESTRICTION, EACCES},
35566 + {ERROR_ALREADY_ASSIGNED, EBUSY},
35567 + {ERROR_ALREADY_EXISTS, EEXIST},
35568 + {ERROR_ARITHMETIC_OVERFLOW, ERANGE},
35569 + {ERROR_BAD_COMMAND, EIO},
35570 + {ERROR_BAD_DEVICE, ENODEV},
35571 + {ERROR_BAD_DRIVER_LEVEL, ENXIO},
35572 + {ERROR_BAD_EXE_FORMAT, ENOEXEC},
35573 + {ERROR_BAD_FORMAT, ENOEXEC},
35574 + {ERROR_BAD_LENGTH, EINVAL},
35575 + {ERROR_BAD_PATHNAME, ENOENT},
35576 + {ERROR_BAD_PIPE, EPIPE},
35577 + {ERROR_BAD_UNIT, ENODEV},
35578 + {ERROR_BAD_USERNAME, EINVAL},
35579 + {ERROR_BROKEN_PIPE, EPIPE},
35580 + {ERROR_BUFFER_OVERFLOW, ENOMEM},
35581 + {ERROR_BUSY, EBUSY},
35582 + {ERROR_BUSY_DRIVE, EBUSY},
35583 + {ERROR_CALL_NOT_IMPLEMENTED, ENOSYS},
35584 + {ERROR_CRC, EIO},
35585 + {ERROR_CURRENT_DIRECTORY, EINVAL},
35586 + {ERROR_DEVICE_IN_USE, EBUSY},
35587 + {ERROR_DIR_NOT_EMPTY, EEXIST},
35588 + {ERROR_DIRECTORY, ENOENT},
35589 + {ERROR_DISK_CHANGE, EIO},
35590 + {ERROR_DISK_FULL, ENOSPC},
35591 + {ERROR_DRIVE_LOCKED, EBUSY},
35592 + {ERROR_ENVVAR_NOT_FOUND, EINVAL},
35593 + {ERROR_EXE_MARKED_INVALID, ENOEXEC},
35594 + {ERROR_FILE_EXISTS, EEXIST},
35595 + {ERROR_FILE_INVALID, ENODEV},
35596 + {ERROR_FILE_NOT_FOUND, ENOENT},
35597 + {ERROR_FILENAME_EXCED_RANGE, ENAMETOOLONG},
35598 + {ERROR_GEN_FAILURE, EIO},
35599 + {ERROR_HANDLE_DISK_FULL, ENOSPC},
35600 + {ERROR_INSUFFICIENT_BUFFER, ENOMEM},
35601 + {ERROR_INVALID_ACCESS, EINVAL},
35602 + {ERROR_INVALID_ADDRESS, EFAULT},
35603 + {ERROR_INVALID_BLOCK, EFAULT},
35604 + {ERROR_INVALID_DATA, EINVAL},
35605 + {ERROR_INVALID_DRIVE, ENODEV},
35606 + {ERROR_INVALID_EXE_SIGNATURE, ENOEXEC},
35607 + {ERROR_INVALID_FLAGS, EINVAL},
35608 + {ERROR_INVALID_FUNCTION, ENOSYS},
35609 + {ERROR_INVALID_HANDLE, EBADF},
35610 + {ERROR_INVALID_LOGON_HOURS, EACCES},
35611 + {ERROR_INVALID_NAME, ENOENT},
35612 + {ERROR_INVALID_OWNER, EINVAL},
35613 + {ERROR_INVALID_PARAMETER, EINVAL},
35614 + {ERROR_INVALID_PASSWORD, EPERM},
35615 + {ERROR_INVALID_PRIMARY_GROUP, EINVAL},
35616 + {ERROR_INVALID_SIGNAL_NUMBER, EINVAL},
35617 + {ERROR_INVALID_TARGET_HANDLE, EIO},
35618 + {ERROR_INVALID_WORKSTATION, EACCES},
35619 + {ERROR_IO_DEVICE, EIO},
35620 + {ERROR_IO_INCOMPLETE, EINTR},
35621 + {ERROR_LOCKED, EBUSY},
35622 + {ERROR_LOGON_FAILURE, EACCES},
35623 + {ERROR_MAPPED_ALIGNMENT, EINVAL},
35624 + {ERROR_META_EXPANSION_TOO_LONG, E2BIG},
35625 + {ERROR_MORE_DATA, EPIPE},
35626 + {ERROR_NEGATIVE_SEEK, ESPIPE},
35627 + {ERROR_NO_DATA, EPIPE},
35628 + {ERROR_NO_MORE_SEARCH_HANDLES, EIO},
35629 + {ERROR_NO_PROC_SLOTS, EAGAIN},
35630 + {ERROR_NO_SUCH_PRIVILEGE, EACCES},
35631 + {ERROR_NOACCESS, EFAULT},
35632 + {ERROR_NONE_MAPPED, EINVAL},
35633 + {ERROR_NOT_ENOUGH_MEMORY, ENOMEM},
35634 + {ERROR_NOT_READY, ENODEV},
35635 + {ERROR_NOT_SAME_DEVICE, EXDEV},
35636 + {ERROR_OPEN_FAILED, EIO},
35637 + {ERROR_OPERATION_ABORTED, EINTR},
35638 + {ERROR_OUTOFMEMORY, ENOMEM},
35639 + {ERROR_PASSWORD_EXPIRED, EACCES},
35640 + {ERROR_PATH_BUSY, EBUSY},
35641 + {ERROR_PATH_NOT_FOUND, ENOTDIR},
35642 + {ERROR_PIPE_BUSY, EBUSY},
35643 + {ERROR_PIPE_CONNECTED, EPIPE},
35644 + {ERROR_PIPE_LISTENING, EPIPE},
35645 + {ERROR_PIPE_NOT_CONNECTED, EPIPE},
35646 + {ERROR_PRIVILEGE_NOT_HELD, EACCES},
35647 + {ERROR_READ_FAULT, EIO},
35648 + {ERROR_SEEK, ESPIPE},
35649 + {ERROR_SEEK_ON_DEVICE, ESPIPE},
35650 + {ERROR_SHARING_BUFFER_EXCEEDED, ENFILE},
35651 + {ERROR_STACK_OVERFLOW, ENOMEM},
35652 + {ERROR_SWAPERROR, ENOENT},
35653 + {ERROR_TOO_MANY_MODULES, EMFILE},
35654 + {ERROR_TOO_MANY_OPEN_FILES, EMFILE},
35655 + {ERROR_UNRECOGNIZED_MEDIA, ENXIO},
35656 + {ERROR_UNRECOGNIZED_VOLUME, ENODEV},
35657 + {ERROR_WAIT_NO_CHILDREN, ECHILD},
35658 + {ERROR_WRITE_FAULT, EIO},
35659 + {ERROR_WRITE_PROTECT, EROFS}
35660 +/* MinGW does not define ETXTBSY as yet.
35661 + {ERROR_LOCK_VIOLATION, ETXTBSY},
35662 + {ERROR_SHARING_VIOLATION, ETXTBSY},
35668 + for (i = 0; i < sizeof (mapping)/sizeof (mapping[0]); ++i)
35669 + if (mapping[i][0] == windows_code)
35671 + errno = mapping[i][1];
35675 + /* Unrecognized error. Use EACCESS to have some error code,
35676 + not misleading "No error" thing. */
35680 +int rename (const char *oldpath, const char *newpath)
35683 + int oldpath_converted = 0;
35684 + char win32_oldpath[MAX_PATH + 1];
35685 + char win32_newpath[MAX_PATH + 1];
35687 + /* Older versions of the cygpath program called FindFirstFile, but
35688 + not FindClose. As a result, a long-running cygpath program ends
35689 + up leaking these handles, and, as a result, the Windows kernel
35690 + will not let us remove or rename things in directories. Therefore,
35691 + we kill the child cygpath program now.
35693 + The defect in cygpath was corrected by this patch:
35695 + http://cygwin.com/ml/cygwin-patches/2007-q1/msg00033.html
35697 + but older versions of cygpath will be in use for the forseeable
35700 + cygpath_close ();
35701 + cygpath_initialized = 0;
35703 + /* Assume all paths are Windows paths. */
35704 + r = MoveFileEx (oldpath, newpath, MOVEFILE_REPLACE_EXISTING);
35707 + else if (GetLastError () != ERROR_PATH_NOT_FOUND)
35710 + /* Perhaps the old path is a cygwin path? */
35711 + if (cygpath (oldpath, win32_oldpath))
35713 + oldpath_converted = 1;
35714 + r = MoveFileEx (win32_oldpath, newpath, MOVEFILE_REPLACE_EXISTING);
35717 + else if (GetLastError () != ERROR_PATH_NOT_FOUND)
35721 + /* Perhaps the new path is a cygwin path? */
35722 + if (cygpath (newpath, win32_newpath))
35724 + r = MoveFileEx (oldpath_converted ? win32_oldpath : oldpath,
35725 + win32_newpath, MOVEFILE_REPLACE_EXISTING);
35730 + set_errno_from_windows_code (GetLastError ());
35734 +int remove (const char *pathname)
35737 + char win32_path[MAX_PATH + 1];
35739 + cygpath_close ();
35740 + cygpath_initialized = 0;
35742 + /* Assume PATH is a Windows path. */
35743 + r = _unlink (pathname);
35744 + if (r != -1 || errno != ENOENT)
35746 + /* Perhaps it is a Cygwin path? */
35747 + if (cygpath (pathname, win32_path))
35748 + r = _unlink (win32_path);
35752 +int unlink(const char *pathname)
35754 + return remove (pathname);
35758 +chdir (const char *path)
35761 + char win32_path[MAX_PATH + 1];
35763 + /* Assume PATH is a Windows path. */
35764 + ret = _chdir (path);
35765 + if (ret != -1 || errno != ENOENT)
35767 + /* Perhaps it is a Cygwin path? */
35768 + if (cygpath (path, win32_path))
35769 + ret = _chdir (win32_path);
35772 --- a/libiberty/lrealpath.c
35773 +++ b/libiberty/lrealpath.c
35774 @@ -138,6 +138,17 @@ lrealpath (const char *filename)
35776 char buf[MAX_PATH];
35779 + if (_access (filename, F_OK) != 0)
35781 + char cygbuf[MAX_PATH + 1];
35782 + /* The file does not exist. It's fine to call lrealpath
35783 + on a non-existing path... but if this would be an existing
35784 + path after cygpath conversion, use that instead. */
35785 + if (cygpath (filename, cygbuf) && _access (cygbuf, F_OK) == 0)
35786 + filename = cygbuf;
35789 DWORD len = GetFullPathName (filename, MAX_PATH, buf, &basename);
35790 if (len == 0 || len > MAX_PATH - 1)
35791 return strdup (filename);
35792 --- a/libiberty/pex-win32.c
35793 +++ b/libiberty/pex-win32.c
35794 @@ -119,7 +119,7 @@ static int
35795 pex_win32_open_read (struct pex_obj *obj ATTRIBUTE_UNUSED, const char *name,
35798 - return _open (name, _O_RDONLY | (binary ? _O_BINARY : _O_TEXT));
35799 + return open (name, _O_RDONLY | (binary ? _O_BINARY : _O_TEXT));
35802 /* Open a file for writing. */
35803 @@ -130,10 +130,10 @@ pex_win32_open_write (struct pex_obj *ob
35805 /* Note that we can't use O_EXCL here because gcc may have already
35806 created the temporary file via make_temp_file. */
35807 - return _open (name,
35808 - (_O_WRONLY | _O_CREAT | _O_TRUNC
35809 - | (binary ? _O_BINARY : _O_TEXT)),
35810 - _S_IREAD | _S_IWRITE);
35811 + return open (name,
35812 + (_O_WRONLY | _O_CREAT | _O_TRUNC
35813 + | (binary ? _O_BINARY : _O_TEXT)),
35814 + _S_IREAD | _S_IWRITE);
35817 /* Close a file. */
35818 @@ -746,6 +746,28 @@ pex_win32_exec_child (struct pex_obj *ob
35819 OSVERSIONINFO version_info;
35821 PROCESS_INFORMATION pi;
35822 + int orig_out, orig_in, orig_err;
35823 + BOOL separate_stderr = !(flags & PEX_STDERR_TO_STDOUT);
35825 + /* Ensure we have inheritable descriptors to pass to the child, and close the
35826 + original descriptors. */
35828 + in = _dup (orig_in);
35829 + if (orig_in != STDIN_FILENO)
35830 + _close (orig_in);
35833 + out = _dup (orig_out);
35834 + if (orig_out != STDOUT_FILENO)
35835 + _close (orig_out);
35837 + if (separate_stderr)
35839 + orig_err = errdes;
35840 + errdes = _dup (orig_err);
35841 + if (orig_err != STDERR_FILENO)
35842 + _close (orig_err);
35845 stdin_handle = INVALID_HANDLE_VALUE;
35846 stdout_handle = INVALID_HANDLE_VALUE;
35847 @@ -753,7 +775,7 @@ pex_win32_exec_child (struct pex_obj *ob
35849 stdin_handle = (HANDLE) _get_osfhandle (in);
35850 stdout_handle = (HANDLE) _get_osfhandle (out);
35851 - if (!(flags & PEX_STDERR_TO_STDOUT))
35852 + if (separate_stderr)
35853 stderr_handle = (HANDLE) _get_osfhandle (errdes);
35855 stderr_handle = stdout_handle;
35856 @@ -822,12 +844,13 @@ pex_win32_exec_child (struct pex_obj *ob
35857 *errmsg = "CreateProcess";
35860 - /* Close the standard output and standard error handles in the
35862 - if (out != STDOUT_FILENO)
35863 - obj->funcs->close (obj, out);
35864 - if (errdes != STDERR_FILENO)
35865 - obj->funcs->close (obj, errdes);
35866 + /* Close the standard input, standard output and standard error handles
35867 + in the parent. */
35871 + if (separate_stderr)
35876 @@ -883,7 +906,7 @@ static int
35877 pex_win32_pipe (struct pex_obj *obj ATTRIBUTE_UNUSED, int *p,
35880 - return _pipe (p, 256, binary ? _O_BINARY : _O_TEXT);
35881 + return _pipe (p, 256, (binary ? _O_BINARY : _O_TEXT) | _O_NOINHERIT);
35884 /* Get a FILE pointer to read from a file descriptor. */
35885 --- a/libiberty/testsuite/test-expandargv.c
35886 +++ b/libiberty/testsuite/test-expandargv.c
35887 @@ -107,6 +107,38 @@ const char *test_data[] = {
35891 + /* Test 4 - Check for options beginning with an empty line. */
35892 + "\na\nb", /* Test 4 data */
35894 + "@test-expandargv-4.lst",
35901 + /* Test 5 - Check for options containing an empty argument. */
35902 + "a\n''\nb", /* Test 5 data */
35904 + "@test-expandargv-5.lst",
35912 + /* Test 6 - Check for options containing a quoted newline. */
35913 + "a\n'a\n\nb'\nb", /* Test 6 data */
35915 + "@test-expandargv-6.lst",
35923 0 /* Test done marker, don't remove. */
35926 @@ -246,7 +278,7 @@ run_tests (const char **test_data)
35927 /* Compare each of the argv's ... */
35929 for (k = 0; k < argc_after; k++)
35930 - if (strncmp (argv_before[k], argv_after[k], strlen(argv_after[k])) != 0)
35931 + if (strcmp (argv_before[k], argv_after[k]) != 0)
35933 printf ("FAIL: test-expandargv-%d. Arguments don't match.\n", i);
35935 --- a/libjava/Makefile.am
35936 +++ b/libjava/Makefile.am
35937 @@ -55,9 +55,14 @@ endif
35939 dbexec_LTLIBRARIES = libjvm.la
35941 -pkgconfigdir = $(libdir)/pkgconfig
35942 +# Install the pkgconfig file in a target-specific directory, since the
35943 +# libraries it indicates
35945 -jardir = $(datadir)/java
35946 +pkgconfigdir = $(toolexeclibdir)/pkgconfig
35948 +# We install the JAR in a target-specific directory so that toolchains
35949 +# build from different sources can be installed in the same directory.
35950 +jardir = $(prefix)/$(target_noncanonical)/share/java
35951 jar_DATA = libgcj-$(gcc_version).jar libgcj-tools-$(gcc_version).jar
35953 jar_DATA += $(ECJ_BUILD_JAR)
35954 --- a/libjava/Makefile.in
35955 +++ b/libjava/Makefile.in
35956 @@ -915,8 +915,14 @@ toolexeclib_LTLIBRARIES = libgcj.la libg
35957 $(am__append_2) $(am__append_3)
35958 toolexecmainlib_DATA = libgcj.spec
35959 dbexec_LTLIBRARIES = libjvm.la
35960 -pkgconfigdir = $(libdir)/pkgconfig
35961 -jardir = $(datadir)/java
35963 +# Install the pkgconfig file in a target-specific directory, since the
35964 +# libraries it indicates
35965 +pkgconfigdir = $(toolexeclibdir)/pkgconfig
35967 +# We install the JAR in a target-specific directory so that toolchains
35968 +# build from different sources can be installed in the same directory.
35969 +jardir = $(prefix)/$(target_noncanonical)/share/java
35970 jar_DATA = libgcj-$(gcc_version).jar libgcj-tools-$(gcc_version).jar \
35972 @JAVA_HOME_SET_FALSE@JAVA_HOME_DIR = $(prefix)
35973 --- a/libjava/classpath/Makefile.in
35974 +++ b/libjava/classpath/Makefile.in
35975 @@ -380,9 +380,12 @@ sysconfdir = @sysconfdir@
35977 target_alias = @target_alias@
35978 target_cpu = @target_cpu@
35979 +target_noncanonical = @target_noncanonical@
35980 target_os = @target_os@
35981 target_vendor = @target_vendor@
35982 +toolexecdir = @toolexecdir@
35983 toolexeclibdir = @toolexeclibdir@
35984 +toolexecmainlibdir = @toolexecmainlibdir@
35985 uudecode = @uudecode@
35986 vm_classes = @vm_classes@
35988 --- a/libjava/classpath/configure
35989 +++ b/libjava/classpath/configure
35990 @@ -461,7 +461,7 @@ ac_includes_default="\
35991 # include <unistd.h>
35994 -ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os JAVA_MAINTAINER_MODE_TRUE JAVA_MAINTAINER_MODE_FALSE GENINSRC_TRUE GENINSRC_FALSE multi_basedir INSTALL_BINARIES_TRUE INSTALL_BINARIES_FALSE LIBVERSION CLASSPATH_MODULE CLASSPATH_CONVENIENCE INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CYGPATH_W PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM mkdir_p AWK SET_MAKE am__leading_dot AMTAR am__tar am__untar CREATE_COLLECTIONS_TRUE CREATE_COLLECTIONS_FALSE CREATE_JNI_LIBRARIES_TRUE CREATE_JNI_LIBRARIES_FALSE CREATE_CORE_JNI_LIBRARIES_TRUE CREATE_CORE_JNI_LIBRARIES_FALSE CREATE_GCONF_PEER_LIBRARIES_TRUE CREATE_GCONF_PEER_LIBRARIES_FALSE CREATE_GSTREAMER_PEER_LIBRARIES_TRUE CREATE_GSTREAMER_PEER_LIBRARIES_FALSE default_toolkit CREATE_XMLJ_LIBRARY_TRUE CREATE_XMLJ_LIBRARY_FALSE CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT DEPDIR am__include am__quote AMDEP_TRUE AMDEP_FALSE AMDEPBACKSLASH CCDEPMODE am__fastdepCC_TRUE am__fastdepCC_FALSE CPP EGREP CREATE_ALSA_LIBRARIES_TRUE CREATE_ALSA_LIBRARIES_FALSE CREATE_DSSI_LIBRARIES_TRUE CREATE_DSSI_LIBRARIES_FALSE CREATE_GTK_PEER_LIBRARIES_TRUE CREATE_GTK_PEER_LIBRARIES_FALSE CREATE_QT_PEER_LIBRARIES_TRUE CREATE_QT_PEER_LIBRARIES_FALSE CREATE_PLUGIN_TRUE CREATE_PLUGIN_FALSE CREATE_GJDOC_TRUE CREATE_GJDOC_FALSE toolexeclibdir nativeexeclibdir glibjdir CREATE_JNI_HEADERS_TRUE CREATE_JNI_HEADERS_FALSE CREATE_GJDOC_PARSER_TRUE CREATE_GJDOC_PARSER_FALSE CREATE_WRAPPERS_TRUE CREATE_WRAPPERS_FALSE LN_S LIBTOOL SED FGREP GREP LD DUMPBIN ac_ct_DUMPBIN NM OBJDUMP ac_ct_OBJDUMP AR ac_ct_AR RANLIB ac_ct_RANLIB lt_ECHO DSYMUTIL ac_ct_DSYMUTIL NMEDIT ac_ct_NMEDIT LIPO ac_ct_LIPO OTOOL ac_ct_OTOOL OTOOL64 ac_ct_OTOOL64 CXX CXXFLAGS ac_ct_CXX CXXDEPMODE am__fastdepCXX_TRUE am__fastdepCXX_FALSE CXXCPP PERL COLLECTIONS_PREFIX LIBMAGIC LIBICONV LTLIBICONV WARNING_CFLAGS EXTRA_CFLAGS STRICT_WARNING_CFLAGS ERROR_CFLAGS PKG_CONFIG XML_CFLAGS XML_LIBS XSLT_CFLAGS XSLT_LIBS X_CFLAGS X_PRE_LIBS X_LIBS X_EXTRA_LIBS GTK_CFLAGS GTK_LIBS FREETYPE2_CFLAGS FREETYPE2_LIBS PANGOFT2_CFLAGS PANGOFT2_LIBS CAIRO_CFLAGS CAIRO_LIBS XTEST_LIBS GCONF_CFLAGS GCONF_LIBS GDK_CFLAGS GDK_LIBS GSTREAMER_CFLAGS GSTREAMER_LIBS GSTREAMER_BASE_CFLAGS GSTREAMER_BASE_LIBS GSTREAMER_PLUGINS_BASE_CFLAGS GSTREAMER_PLUGINS_BASE_LIBS GST_PLUGIN_LDFLAGS GSTREAMER_FILE_READER GSTREAMER_MIXER_PROVIDER QT_CFLAGS QT_LIBS MOC MOZILLA_CFLAGS MOZILLA_LIBS GLIB_CFLAGS GLIB_LIBS PLUGIN_DIR GMP_CFLAGS GMP_LIBS USER_JAVAH CLASSPATH_INCLUDES vm_classes MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT LIBDEBUG INIT_LOAD_LIBRARY ECJ_JAR JAVA_LANG_SYSTEM_EXPLICIT_INITIALIZATION REMOVE MKDIR CP DATE FIND ZIP JAR WITH_JAR_TRUE WITH_JAR_FALSE INSTALL_GLIBJ_ZIP_TRUE INSTALL_GLIBJ_ZIP_FALSE INSTALL_CLASS_FILES_TRUE INSTALL_CLASS_FILES_FALSE BUILD_CLASS_FILES_TRUE BUILD_CLASS_FILES_FALSE EXAMPLESDIR TOOLSDIR GJDOC CREATE_API_DOCS_TRUE CREATE_API_DOCS_FALSE JAY JAY_SKELETON REGEN_PARSERS_TRUE REGEN_PARSERS_FALSE USE_PREBUILT_GLIBJ_ZIP_TRUE USE_PREBUILT_GLIBJ_ZIP_FALSE PATH_TO_GLIBJ_ZIP JAVA uudecode JAVAC JAVAC_IS_GCJ GCJ_JAVAC_TRUE GCJ_JAVAC_FALSE ANTLR_JAR ANTLR ac_ct_ANTLR JAVAC_MEM_OPT USE_ESCHER_TRUE USE_ESCHER_FALSE PATH_TO_ESCHER ENABLE_LOCAL_SOCKETS_TRUE ENABLE_LOCAL_SOCKETS_FALSE DEFAULT_PREFS_PEER WANT_NATIVE_BIG_INTEGER CREATE_GMPBI_LIBRARY_TRUE CREATE_GMPBI_LIBRARY_FALSE LIBOBJS LTLIBOBJS'
35995 +ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os JAVA_MAINTAINER_MODE_TRUE JAVA_MAINTAINER_MODE_FALSE GENINSRC_TRUE GENINSRC_FALSE multi_basedir INSTALL_BINARIES_TRUE INSTALL_BINARIES_FALSE LIBVERSION CLASSPATH_MODULE CLASSPATH_CONVENIENCE INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CYGPATH_W PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM mkdir_p AWK SET_MAKE am__leading_dot AMTAR am__tar am__untar CREATE_COLLECTIONS_TRUE CREATE_COLLECTIONS_FALSE CREATE_JNI_LIBRARIES_TRUE CREATE_JNI_LIBRARIES_FALSE CREATE_CORE_JNI_LIBRARIES_TRUE CREATE_CORE_JNI_LIBRARIES_FALSE CREATE_GCONF_PEER_LIBRARIES_TRUE CREATE_GCONF_PEER_LIBRARIES_FALSE CREATE_GSTREAMER_PEER_LIBRARIES_TRUE CREATE_GSTREAMER_PEER_LIBRARIES_FALSE default_toolkit CREATE_XMLJ_LIBRARY_TRUE CREATE_XMLJ_LIBRARY_FALSE CC CFLAGS LDFLAGS CPPFLAGS ac_ct_CC EXEEXT OBJEXT DEPDIR am__include am__quote AMDEP_TRUE AMDEP_FALSE AMDEPBACKSLASH CCDEPMODE am__fastdepCC_TRUE am__fastdepCC_FALSE CPP EGREP CREATE_ALSA_LIBRARIES_TRUE CREATE_ALSA_LIBRARIES_FALSE CREATE_DSSI_LIBRARIES_TRUE CREATE_DSSI_LIBRARIES_FALSE CREATE_GTK_PEER_LIBRARIES_TRUE CREATE_GTK_PEER_LIBRARIES_FALSE CREATE_QT_PEER_LIBRARIES_TRUE CREATE_QT_PEER_LIBRARIES_FALSE CREATE_PLUGIN_TRUE CREATE_PLUGIN_FALSE CREATE_GJDOC_TRUE CREATE_GJDOC_FALSE target_noncanonical toolexecdir toolexecmainlibdir toolexeclibdir nativeexeclibdir glibjdir CREATE_JNI_HEADERS_TRUE CREATE_JNI_HEADERS_FALSE CREATE_GJDOC_PARSER_TRUE CREATE_GJDOC_PARSER_FALSE CREATE_WRAPPERS_TRUE CREATE_WRAPPERS_FALSE LN_S LIBTOOL SED FGREP GREP LD DUMPBIN ac_ct_DUMPBIN NM OBJDUMP ac_ct_OBJDUMP AR ac_ct_AR RANLIB ac_ct_RANLIB lt_ECHO DSYMUTIL ac_ct_DSYMUTIL NMEDIT ac_ct_NMEDIT LIPO ac_ct_LIPO OTOOL ac_ct_OTOOL OTOOL64 ac_ct_OTOOL64 CXX CXXFLAGS ac_ct_CXX CXXDEPMODE am__fastdepCXX_TRUE am__fastdepCXX_FALSE CXXCPP PERL COLLECTIONS_PREFIX LIBMAGIC LIBICONV LTLIBICONV WARNING_CFLAGS EXTRA_CFLAGS STRICT_WARNING_CFLAGS ERROR_CFLAGS PKG_CONFIG XML_CFLAGS XML_LIBS XSLT_CFLAGS XSLT_LIBS X_CFLAGS X_PRE_LIBS X_LIBS X_EXTRA_LIBS GTK_CFLAGS GTK_LIBS FREETYPE2_CFLAGS FREETYPE2_LIBS PANGOFT2_CFLAGS PANGOFT2_LIBS CAIRO_CFLAGS CAIRO_LIBS XTEST_LIBS GCONF_CFLAGS GCONF_LIBS GDK_CFLAGS GDK_LIBS GSTREAMER_CFLAGS GSTREAMER_LIBS GSTREAMER_BASE_CFLAGS GSTREAMER_BASE_LIBS GSTREAMER_PLUGINS_BASE_CFLAGS GSTREAMER_PLUGINS_BASE_LIBS GST_PLUGIN_LDFLAGS GSTREAMER_FILE_READER GSTREAMER_MIXER_PROVIDER QT_CFLAGS QT_LIBS MOC MOZILLA_CFLAGS MOZILLA_LIBS GLIB_CFLAGS GLIB_LIBS PLUGIN_DIR GMP_CFLAGS GMP_LIBS USER_JAVAH CLASSPATH_INCLUDES vm_classes MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT LIBDEBUG INIT_LOAD_LIBRARY ECJ_JAR JAVA_LANG_SYSTEM_EXPLICIT_INITIALIZATION REMOVE MKDIR CP DATE FIND ZIP JAR WITH_JAR_TRUE WITH_JAR_FALSE INSTALL_GLIBJ_ZIP_TRUE INSTALL_GLIBJ_ZIP_FALSE INSTALL_CLASS_FILES_TRUE INSTALL_CLASS_FILES_FALSE BUILD_CLASS_FILES_TRUE BUILD_CLASS_FILES_FALSE EXAMPLESDIR TOOLSDIR GJDOC CREATE_API_DOCS_TRUE CREATE_API_DOCS_FALSE JAY JAY_SKELETON REGEN_PARSERS_TRUE REGEN_PARSERS_FALSE USE_PREBUILT_GLIBJ_ZIP_TRUE USE_PREBUILT_GLIBJ_ZIP_FALSE PATH_TO_GLIBJ_ZIP JAVA uudecode JAVAC JAVAC_IS_GCJ GCJ_JAVAC_TRUE GCJ_JAVAC_FALSE ANTLR_JAR ANTLR ac_ct_ANTLR JAVAC_MEM_OPT USE_ESCHER_TRUE USE_ESCHER_FALSE PATH_TO_ESCHER ENABLE_LOCAL_SOCKETS_TRUE ENABLE_LOCAL_SOCKETS_FALSE DEFAULT_PREFS_PEER WANT_NATIVE_BIG_INTEGER CREATE_GMPBI_LIBRARY_TRUE CREATE_GMPBI_LIBRARY_FALSE LIBOBJS LTLIBOBJS'
35999 @@ -1063,6 +1063,9 @@ Optional Features:
36000 (disabled by --disable-gmp) default=yes
36001 --disable-gjdoc compile GJDoc (disabled by --disable-gjdoc)
36003 + --enable-version-specific-runtime-libs
36004 + specify that runtime libraries should be installed
36005 + in a compiler-specific directory
36006 --enable-regen-headers automatically regenerate JNI headers default=yes if
36007 headers don't exist
36008 --enable-regen-gjdoc-parser
36009 @@ -4838,11 +4841,57 @@ else
36013 +# Check whether --enable-version-specific-runtime-libs or --disable-version-specific-runtime-libs was given.
36014 +if test "${enable_version_specific_runtime_libs+set}" = set; then
36015 + enableval="$enable_version_specific_runtime_libs"
36016 + case "$enableval" in
36017 + yes) version_specific_libs=yes ;;
36018 + no) version_specific_libs=no ;;
36019 + *) { { echo "$as_me:$LINENO: error: Unknown argument to enable/disable version-specific libs" >&5
36020 +echo "$as_me: error: Unknown argument to enable/disable version-specific libs" >&2;}
36021 + { (exit 1); exit 1; }; };;
36024 + version_specific_libs=no
36028 + case ${host_alias} in
36029 + "") host_noncanonical=${build_noncanonical} ;;
36030 + *) host_noncanonical=${host_alias} ;;
36032 + case ${target_alias} in
36033 + "") target_noncanonical=${host_noncanonical} ;;
36034 + *) target_noncanonical=${target_alias} ;;
36038 - multi_os_directory=`$CC -print-multi-os-directory`
36039 - case $multi_os_directory in
36040 - .) toolexeclibdir=${libdir} ;; # Avoid trailing /.
36041 - *) toolexeclibdir=${libdir}/${multi_os_directory} ;;
36042 + case ${version_specific_libs} in
36044 + # Need the gcc compiler version to know where to install libraries
36045 + # and header files if --enable-version-specific-runtime-libs option
36047 + includedir='$(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/include/'
36048 + toolexecdir='$(libdir)/gcc/$(target_noncanonical)'
36049 + toolexecmainlibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)'
36050 + toolexeclibdir=$toolexecmainlibdir
36053 + if test -n "$with_cross_host" &&
36054 + test x"$with_cross_host" != x"no"; then
36055 + # Install a library built with a cross compiler in tooldir, not libdir.
36056 + toolexecdir='$(exec_prefix)/$(target_noncanonical)'
36057 + toolexecmainlibdir='$(toolexecdir)/lib'
36059 + toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)'
36060 + toolexecmainlibdir='$(libdir)'
36062 + multi_os_directory=`$CC -print-multi-os-directory`
36063 + case $multi_os_directory in
36064 + .) toolexeclibdir=$toolexecmainlibdir ;; # Avoid trailing /.
36065 + *) toolexeclibdir=$toolexecmainlibdir/$multi_os_directory ;;
36071 @@ -5753,13 +5802,13 @@ if test "${lt_cv_nm_interface+set}" = se
36073 lt_cv_nm_interface="BSD nm"
36074 echo "int some_variable = 0;" > conftest.$ac_ext
36075 - (eval echo "\"\$as_me:5756: $ac_compile\"" >&5)
36076 + (eval echo "\"\$as_me:5807: $ac_compile\"" >&5)
36077 (eval "$ac_compile" 2>conftest.err)
36078 cat conftest.err >&5
36079 - (eval echo "\"\$as_me:5759: $NM \\\"conftest.$ac_objext\\\"\"" >&5)
36080 + (eval echo "\"\$as_me:5810: $NM \\\"conftest.$ac_objext\\\"\"" >&5)
36081 (eval "$NM \"conftest.$ac_objext\"" 2>conftest.err > conftest.out)
36082 cat conftest.err >&5
36083 - (eval echo "\"\$as_me:5762: output\"" >&5)
36084 + (eval echo "\"\$as_me:5813: output\"" >&5)
36085 cat conftest.out >&5
36086 if $GREP 'External.*some_variable' conftest.out > /dev/null; then
36087 lt_cv_nm_interface="MS dumpbin"
36088 @@ -6905,7 +6954,7 @@ ia64-*-hpux*)
36091 # Find out which ABI we are using.
36092 - echo '#line 6908 "configure"' > conftest.$ac_ext
36093 + echo '#line 6959 "configure"' > conftest.$ac_ext
36094 if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
36095 (eval $ac_compile) 2>&5
36097 @@ -8191,11 +8240,11 @@ else
36098 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
36099 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
36100 -e 's:$: $lt_compiler_flag:'`
36101 - (eval echo "\"\$as_me:8194: $lt_compile\"" >&5)
36102 + (eval echo "\"\$as_me:8245: $lt_compile\"" >&5)
36103 (eval "$lt_compile" 2>conftest.err)
36105 cat conftest.err >&5
36106 - echo "$as_me:8198: \$? = $ac_status" >&5
36107 + echo "$as_me:8249: \$? = $ac_status" >&5
36108 if (exit $ac_status) && test -s "$ac_outfile"; then
36109 # The compiler can only warn and ignore the option if not recognized
36110 # So say no if there are warnings other than the usual output.
36111 @@ -8530,11 +8579,11 @@ else
36112 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
36113 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
36114 -e 's:$: $lt_compiler_flag:'`
36115 - (eval echo "\"\$as_me:8533: $lt_compile\"" >&5)
36116 + (eval echo "\"\$as_me:8584: $lt_compile\"" >&5)
36117 (eval "$lt_compile" 2>conftest.err)
36119 cat conftest.err >&5
36120 - echo "$as_me:8537: \$? = $ac_status" >&5
36121 + echo "$as_me:8588: \$? = $ac_status" >&5
36122 if (exit $ac_status) && test -s "$ac_outfile"; then
36123 # The compiler can only warn and ignore the option if not recognized
36124 # So say no if there are warnings other than the usual output.
36125 @@ -8635,11 +8684,11 @@ else
36126 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
36127 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
36128 -e 's:$: $lt_compiler_flag:'`
36129 - (eval echo "\"\$as_me:8638: $lt_compile\"" >&5)
36130 + (eval echo "\"\$as_me:8689: $lt_compile\"" >&5)
36131 (eval "$lt_compile" 2>out/conftest.err)
36133 cat out/conftest.err >&5
36134 - echo "$as_me:8642: \$? = $ac_status" >&5
36135 + echo "$as_me:8693: \$? = $ac_status" >&5
36136 if (exit $ac_status) && test -s out/conftest2.$ac_objext
36138 # The compiler can only warn and ignore the option if not recognized
36139 @@ -8690,11 +8739,11 @@ else
36140 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
36141 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
36142 -e 's:$: $lt_compiler_flag:'`
36143 - (eval echo "\"\$as_me:8693: $lt_compile\"" >&5)
36144 + (eval echo "\"\$as_me:8744: $lt_compile\"" >&5)
36145 (eval "$lt_compile" 2>out/conftest.err)
36147 cat out/conftest.err >&5
36148 - echo "$as_me:8697: \$? = $ac_status" >&5
36149 + echo "$as_me:8748: \$? = $ac_status" >&5
36150 if (exit $ac_status) && test -s out/conftest2.$ac_objext
36152 # The compiler can only warn and ignore the option if not recognized
36153 @@ -11557,7 +11606,7 @@ else
36154 lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
36155 lt_status=$lt_dlunknown
36156 cat > conftest.$ac_ext <<_LT_EOF
36157 -#line 11560 "configure"
36158 +#line 11611 "configure"
36159 #include "confdefs.h"
36162 @@ -11653,7 +11702,7 @@ else
36163 lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
36164 lt_status=$lt_dlunknown
36165 cat > conftest.$ac_ext <<_LT_EOF
36166 -#line 11656 "configure"
36167 +#line 11707 "configure"
36168 #include "confdefs.h"
36171 @@ -16084,11 +16133,11 @@ else
36172 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
36173 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
36174 -e 's:$: $lt_compiler_flag:'`
36175 - (eval echo "\"\$as_me:16087: $lt_compile\"" >&5)
36176 + (eval echo "\"\$as_me:16138: $lt_compile\"" >&5)
36177 (eval "$lt_compile" 2>conftest.err)
36179 cat conftest.err >&5
36180 - echo "$as_me:16091: \$? = $ac_status" >&5
36181 + echo "$as_me:16142: \$? = $ac_status" >&5
36182 if (exit $ac_status) && test -s "$ac_outfile"; then
36183 # The compiler can only warn and ignore the option if not recognized
36184 # So say no if there are warnings other than the usual output.
36185 @@ -16183,11 +16232,11 @@ else
36186 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
36187 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
36188 -e 's:$: $lt_compiler_flag:'`
36189 - (eval echo "\"\$as_me:16186: $lt_compile\"" >&5)
36190 + (eval echo "\"\$as_me:16237: $lt_compile\"" >&5)
36191 (eval "$lt_compile" 2>out/conftest.err)
36193 cat out/conftest.err >&5
36194 - echo "$as_me:16190: \$? = $ac_status" >&5
36195 + echo "$as_me:16241: \$? = $ac_status" >&5
36196 if (exit $ac_status) && test -s out/conftest2.$ac_objext
36198 # The compiler can only warn and ignore the option if not recognized
36199 @@ -16235,11 +16284,11 @@ else
36200 -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
36201 -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
36202 -e 's:$: $lt_compiler_flag:'`
36203 - (eval echo "\"\$as_me:16238: $lt_compile\"" >&5)
36204 + (eval echo "\"\$as_me:16289: $lt_compile\"" >&5)
36205 (eval "$lt_compile" 2>out/conftest.err)
36207 cat out/conftest.err >&5
36208 - echo "$as_me:16242: \$? = $ac_status" >&5
36209 + echo "$as_me:16293: \$? = $ac_status" >&5
36210 if (exit $ac_status) && test -s out/conftest2.$ac_objext
36212 # The compiler can only warn and ignore the option if not recognized
36213 @@ -29270,7 +29319,7 @@ EOF
36214 if uudecode$EXEEXT Test.uue; then
36215 ac_cv_prog_uudecode_base64=yes
36217 - echo "configure: 29273: uudecode had trouble decoding base 64 file 'Test.uue'" >&5
36218 + echo "configure: 29324: uudecode had trouble decoding base 64 file 'Test.uue'" >&5
36219 echo "configure: failed file was:" >&5
36221 ac_cv_prog_uudecode_base64=no
36222 @@ -29417,7 +29466,7 @@ else
36223 JAVA_TEST=Object.java
36224 CLASS_TEST=Object.class
36225 cat << \EOF > $JAVA_TEST
36226 -/* #line 29420 "configure" */
36227 +/* #line 29471 "configure" */
36230 public class Object
36231 @@ -29466,7 +29515,7 @@ JAVA_TEST=Test.java
36232 CLASS_TEST=Test.class
36234 cat << \EOF > $JAVA_TEST
36235 -/* [#]line 29469 "configure" */
36236 +/* [#]line 29520 "configure" */
36237 public class Test {
36238 public static void main (String args[]) {
36240 @@ -29786,7 +29835,7 @@ else
36241 JAVA_TEST=Object.java
36242 CLASS_TEST=Object.class
36243 cat << \EOF > $JAVA_TEST
36244 -/* #line 29789 "configure" */
36245 +/* #line 29840 "configure" */
36248 public class Object
36249 @@ -29827,7 +29876,7 @@ fi
36250 JAVA_TEST=Test.java
36251 CLASS_TEST=Test.class
36252 cat << \EOF > $JAVA_TEST
36253 - /* #line 29830 "configure" */
36254 + /* #line 29881 "configure" */
36257 public static void main(String args)
36258 @@ -31681,6 +31730,9 @@ s,@CREATE_PLUGIN_TRUE@,$CREATE_PLUGIN_TR
36259 s,@CREATE_PLUGIN_FALSE@,$CREATE_PLUGIN_FALSE,;t t
36260 s,@CREATE_GJDOC_TRUE@,$CREATE_GJDOC_TRUE,;t t
36261 s,@CREATE_GJDOC_FALSE@,$CREATE_GJDOC_FALSE,;t t
36262 +s,@target_noncanonical@,$target_noncanonical,;t t
36263 +s,@toolexecdir@,$toolexecdir,;t t
36264 +s,@toolexecmainlibdir@,$toolexecmainlibdir,;t t
36265 s,@toolexeclibdir@,$toolexeclibdir,;t t
36266 s,@nativeexeclibdir@,$nativeexeclibdir,;t t
36267 s,@glibjdir@,$glibjdir,;t t
36268 --- a/libjava/classpath/configure.ac
36269 +++ b/libjava/classpath/configure.ac
36270 @@ -316,6 +316,16 @@ dnl defined to the same value for all mu
36271 dnl so that we can refer to the multilib installation directories from
36272 dnl classpath's build files.
36273 dnl -----------------------------------------------------------
36274 +AC_ARG_ENABLE(version-specific-runtime-libs,
36275 + AS_HELP_STRING([--enable-version-specific-runtime-libs],
36276 + [specify that runtime libraries should be installed in a compiler-specific directory]),
36277 + [case "$enableval" in
36278 + yes) version_specific_libs=yes ;;
36279 + no) version_specific_libs=no ;;
36280 + *) AC_MSG_ERROR([Unknown argument to enable/disable version-specific libs]);;
36282 + [version_specific_libs=no]
36284 CLASSPATH_TOOLEXECLIBDIR
36286 dnl -----------------------------------------------------------
36287 --- a/libjava/classpath/doc/Makefile.in
36288 +++ b/libjava/classpath/doc/Makefile.in
36289 @@ -357,9 +357,12 @@ sysconfdir = @sysconfdir@
36291 target_alias = @target_alias@
36292 target_cpu = @target_cpu@
36293 +target_noncanonical = @target_noncanonical@
36294 target_os = @target_os@
36295 target_vendor = @target_vendor@
36296 +toolexecdir = @toolexecdir@
36297 toolexeclibdir = @toolexeclibdir@
36298 +toolexecmainlibdir = @toolexecmainlibdir@
36299 uudecode = @uudecode@
36300 vm_classes = @vm_classes@
36302 --- a/libjava/classpath/doc/api/Makefile.in
36303 +++ b/libjava/classpath/doc/api/Makefile.in
36304 @@ -334,9 +334,12 @@ sysconfdir = @sysconfdir@
36306 target_alias = @target_alias@
36307 target_cpu = @target_cpu@
36308 +target_noncanonical = @target_noncanonical@
36309 target_os = @target_os@
36310 target_vendor = @target_vendor@
36311 +toolexecdir = @toolexecdir@
36312 toolexeclibdir = @toolexeclibdir@
36313 +toolexecmainlibdir = @toolexecmainlibdir@
36314 uudecode = @uudecode@
36315 vm_classes = @vm_classes@
36316 @CREATE_API_DOCS_TRUE@noinst_DATA = html
36317 --- a/libjava/classpath/examples/Makefile.in
36318 +++ b/libjava/classpath/examples/Makefile.in
36319 @@ -343,9 +343,12 @@ sysconfdir = @sysconfdir@
36321 target_alias = @target_alias@
36322 target_cpu = @target_cpu@
36323 +target_noncanonical = @target_noncanonical@
36324 target_os = @target_os@
36325 target_vendor = @target_vendor@
36326 +toolexecdir = @toolexecdir@
36327 toolexeclibdir = @toolexeclibdir@
36328 +toolexecmainlibdir = @toolexecmainlibdir@
36329 uudecode = @uudecode@
36330 vm_classes = @vm_classes@
36331 GLIBJ_CLASSPATH = '$(top_builddir)/lib/glibj.zip:$(top_builddir)/lib'
36332 --- a/libjava/classpath/external/Makefile.in
36333 +++ b/libjava/classpath/external/Makefile.in
36334 @@ -341,9 +341,12 @@ sysconfdir = @sysconfdir@
36336 target_alias = @target_alias@
36337 target_cpu = @target_cpu@
36338 +target_noncanonical = @target_noncanonical@
36339 target_os = @target_os@
36340 target_vendor = @target_vendor@
36341 +toolexecdir = @toolexecdir@
36342 toolexeclibdir = @toolexeclibdir@
36343 +toolexecmainlibdir = @toolexecmainlibdir@
36344 uudecode = @uudecode@
36345 vm_classes = @vm_classes@
36346 SUBDIRS = sax w3c_dom relaxngDatatype jsr166
36347 --- a/libjava/classpath/external/jsr166/Makefile.in
36348 +++ b/libjava/classpath/external/jsr166/Makefile.in
36349 @@ -332,9 +332,12 @@ sysconfdir = @sysconfdir@
36351 target_alias = @target_alias@
36352 target_cpu = @target_cpu@
36353 +target_noncanonical = @target_noncanonical@
36354 target_os = @target_os@
36355 target_vendor = @target_vendor@
36356 +toolexecdir = @toolexecdir@
36357 toolexeclibdir = @toolexeclibdir@
36358 +toolexecmainlibdir = @toolexecmainlibdir@
36359 uudecode = @uudecode@
36360 vm_classes = @vm_classes@
36361 EXTRA_DIST = IMPORTING \
36362 --- a/libjava/classpath/external/relaxngDatatype/Makefile.in
36363 +++ b/libjava/classpath/external/relaxngDatatype/Makefile.in
36364 @@ -332,9 +332,12 @@ sysconfdir = @sysconfdir@
36366 target_alias = @target_alias@
36367 target_cpu = @target_cpu@
36368 +target_noncanonical = @target_noncanonical@
36369 target_os = @target_os@
36370 target_vendor = @target_vendor@
36371 +toolexecdir = @toolexecdir@
36372 toolexeclibdir = @toolexeclibdir@
36373 +toolexecmainlibdir = @toolexecmainlibdir@
36374 uudecode = @uudecode@
36375 vm_classes = @vm_classes@
36376 EXTRA_DIST = README.txt \
36377 --- a/libjava/classpath/external/sax/Makefile.in
36378 +++ b/libjava/classpath/external/sax/Makefile.in
36379 @@ -332,9 +332,12 @@ sysconfdir = @sysconfdir@
36381 target_alias = @target_alias@
36382 target_cpu = @target_cpu@
36383 +target_noncanonical = @target_noncanonical@
36384 target_os = @target_os@
36385 target_vendor = @target_vendor@
36386 +toolexecdir = @toolexecdir@
36387 toolexeclibdir = @toolexeclibdir@
36388 +toolexecmainlibdir = @toolexecmainlibdir@
36389 uudecode = @uudecode@
36390 vm_classes = @vm_classes@
36391 EXTRA_DIST = README \
36392 --- a/libjava/classpath/external/w3c_dom/Makefile.in
36393 +++ b/libjava/classpath/external/w3c_dom/Makefile.in
36394 @@ -332,9 +332,12 @@ sysconfdir = @sysconfdir@
36396 target_alias = @target_alias@
36397 target_cpu = @target_cpu@
36398 +target_noncanonical = @target_noncanonical@
36399 target_os = @target_os@
36400 target_vendor = @target_vendor@
36401 +toolexecdir = @toolexecdir@
36402 toolexeclibdir = @toolexeclibdir@
36403 +toolexecmainlibdir = @toolexecmainlibdir@
36404 uudecode = @uudecode@
36405 vm_classes = @vm_classes@
36406 EXTRA_DIST = README \
36407 --- a/libjava/classpath/include/Makefile.in
36408 +++ b/libjava/classpath/include/Makefile.in
36409 @@ -333,9 +333,12 @@ sysconfdir = @sysconfdir@
36411 target_alias = @target_alias@
36412 target_cpu = @target_cpu@
36413 +target_noncanonical = @target_noncanonical@
36414 target_os = @target_os@
36415 target_vendor = @target_vendor@
36416 +toolexecdir = @toolexecdir@
36417 toolexeclibdir = @toolexeclibdir@
36418 +toolexecmainlibdir = @toolexecmainlibdir@
36419 uudecode = @uudecode@
36420 vm_classes = @vm_classes@
36421 @CREATE_JNI_HEADERS_FALSE@DISTCLEANFILES = jni_md.h config-int.h
36422 --- a/libjava/classpath/lib/Makefile.in
36423 +++ b/libjava/classpath/lib/Makefile.in
36424 @@ -337,9 +337,12 @@ sysconfdir = @sysconfdir@
36426 target_alias = @target_alias@
36427 target_cpu = @target_cpu@
36428 +target_noncanonical = @target_noncanonical@
36429 target_os = @target_os@
36430 target_vendor = @target_vendor@
36431 +toolexecdir = @toolexecdir@
36432 toolexeclibdir = @toolexeclibdir@
36433 +toolexecmainlibdir = @toolexecmainlibdir@
36434 uudecode = @uudecode@
36435 vm_classes = @vm_classes@
36436 JAVA_DEPEND = java.dep
36437 --- a/libjava/classpath/m4/acinclude.m4
36438 +++ b/libjava/classpath/m4/acinclude.m4
36439 @@ -247,11 +247,45 @@ dnl GCJ LOCAL: Calculate toolexeclibdir
36440 dnl -----------------------------------------------------------
36441 AC_DEFUN([CLASSPATH_TOOLEXECLIBDIR],
36443 - multi_os_directory=`$CC -print-multi-os-directory`
36444 - case $multi_os_directory in
36445 - .) toolexeclibdir=${libdir} ;; # Avoid trailing /.
36446 - *) toolexeclibdir=${libdir}/${multi_os_directory} ;;
36447 + case ${host_alias} in
36448 + "") host_noncanonical=${build_noncanonical} ;;
36449 + *) host_noncanonical=${host_alias} ;;
36451 + case ${target_alias} in
36452 + "") target_noncanonical=${host_noncanonical} ;;
36453 + *) target_noncanonical=${target_alias} ;;
36455 + AC_SUBST(target_noncanonical)
36457 + case ${version_specific_libs} in
36459 + # Need the gcc compiler version to know where to install libraries
36460 + # and header files if --enable-version-specific-runtime-libs option
36462 + includedir='$(libdir)/gcc/$(target_noncanonical)/$(gcc_version)/include/'
36463 + toolexecdir='$(libdir)/gcc/$(target_noncanonical)'
36464 + toolexecmainlibdir='$(toolexecdir)/$(gcc_version)$(MULTISUBDIR)'
36465 + toolexeclibdir=$toolexecmainlibdir
36468 + if test -n "$with_cross_host" &&
36469 + test x"$with_cross_host" != x"no"; then
36470 + # Install a library built with a cross compiler in tooldir, not libdir.
36471 + toolexecdir='$(exec_prefix)/$(target_noncanonical)'
36472 + toolexecmainlibdir='$(toolexecdir)/lib'
36474 + toolexecdir='$(libdir)/gcc-lib/$(target_noncanonical)'
36475 + toolexecmainlibdir='$(libdir)'
36477 + multi_os_directory=`$CC -print-multi-os-directory`
36478 + case $multi_os_directory in
36479 + .) toolexeclibdir=$toolexecmainlibdir ;; # Avoid trailing /.
36480 + *) toolexeclibdir=$toolexecmainlibdir/$multi_os_directory ;;
36484 + AC_SUBST(toolexecdir)
36485 + AC_SUBST(toolexecmainlibdir)
36486 AC_SUBST(toolexeclibdir)
36489 --- a/libjava/classpath/native/Makefile.in
36490 +++ b/libjava/classpath/native/Makefile.in
36491 @@ -340,9 +340,12 @@ sysconfdir = @sysconfdir@
36493 target_alias = @target_alias@
36494 target_cpu = @target_cpu@
36495 +target_noncanonical = @target_noncanonical@
36496 target_os = @target_os@
36497 target_vendor = @target_vendor@
36498 +toolexecdir = @toolexecdir@
36499 toolexeclibdir = @toolexeclibdir@
36500 +toolexecmainlibdir = @toolexecmainlibdir@
36501 uudecode = @uudecode@
36502 vm_classes = @vm_classes@
36503 @CREATE_JNI_LIBRARIES_TRUE@JNIDIR = jni
36504 --- a/libjava/classpath/native/fdlibm/Makefile.in
36505 +++ b/libjava/classpath/native/fdlibm/Makefile.in
36506 @@ -359,9 +359,12 @@ sysconfdir = @sysconfdir@
36508 target_alias = @target_alias@
36509 target_cpu = @target_cpu@
36510 +target_noncanonical = @target_noncanonical@
36511 target_os = @target_os@
36512 target_vendor = @target_vendor@
36513 +toolexecdir = @toolexecdir@
36514 toolexeclibdir = @toolexeclibdir@
36515 +toolexecmainlibdir = @toolexecmainlibdir@
36516 uudecode = @uudecode@
36517 vm_classes = @vm_classes@
36518 noinst_LTLIBRARIES = libfdlibm.la
36519 --- a/libjava/classpath/native/jawt/Makefile.in
36520 +++ b/libjava/classpath/native/jawt/Makefile.in
36521 @@ -359,9 +359,12 @@ sysconfdir = @sysconfdir@
36523 target_alias = @target_alias@
36524 target_cpu = @target_cpu@
36525 +target_noncanonical = @target_noncanonical@
36526 target_os = @target_os@
36527 target_vendor = @target_vendor@
36528 +toolexecdir = @toolexecdir@
36529 toolexeclibdir = @toolexeclibdir@
36530 +toolexecmainlibdir = @toolexecmainlibdir@
36531 uudecode = @uudecode@
36532 vm_classes = @vm_classes@
36533 nativeexeclib_LTLIBRARIES = libjawt.la
36534 --- a/libjava/classpath/native/jni/Makefile.in
36535 +++ b/libjava/classpath/native/jni/Makefile.in
36536 @@ -340,9 +340,12 @@ sysconfdir = @sysconfdir@
36538 target_alias = @target_alias@
36539 target_cpu = @target_cpu@
36540 +target_noncanonical = @target_noncanonical@
36541 target_os = @target_os@
36542 target_vendor = @target_vendor@
36543 +toolexecdir = @toolexecdir@
36544 toolexeclibdir = @toolexeclibdir@
36545 +toolexecmainlibdir = @toolexecmainlibdir@
36546 uudecode = @uudecode@
36547 vm_classes = @vm_classes@
36548 @CREATE_CORE_JNI_LIBRARIES_TRUE@JNIDIRS = native-lib java-io java-lang java-net java-nio java-util
36549 --- a/libjava/classpath/native/jni/classpath/Makefile.in
36550 +++ b/libjava/classpath/native/jni/classpath/Makefile.in
36551 @@ -350,9 +350,12 @@ sysconfdir = @sysconfdir@
36553 target_alias = @target_alias@
36554 target_cpu = @target_cpu@
36555 +target_noncanonical = @target_noncanonical@
36556 target_os = @target_os@
36557 target_vendor = @target_vendor@
36558 +toolexecdir = @toolexecdir@
36559 toolexeclibdir = @toolexeclibdir@
36560 +toolexecmainlibdir = @toolexecmainlibdir@
36561 uudecode = @uudecode@
36562 vm_classes = @vm_classes@
36564 --- a/libjava/classpath/native/jni/gconf-peer/Makefile.in
36565 +++ b/libjava/classpath/native/jni/gconf-peer/Makefile.in
36566 @@ -359,9 +359,12 @@ sysconfdir = @sysconfdir@
36568 target_alias = @target_alias@
36569 target_cpu = @target_cpu@
36570 +target_noncanonical = @target_noncanonical@
36571 target_os = @target_os@
36572 target_vendor = @target_vendor@
36573 +toolexecdir = @toolexecdir@
36574 toolexeclibdir = @toolexeclibdir@
36575 +toolexecmainlibdir = @toolexecmainlibdir@
36576 uudecode = @uudecode@
36577 vm_classes = @vm_classes@
36578 nativeexeclib_LTLIBRARIES = libgconfpeer.la
36579 --- a/libjava/classpath/native/jni/gstreamer-peer/Makefile.in
36580 +++ b/libjava/classpath/native/jni/gstreamer-peer/Makefile.in
36581 @@ -361,9 +361,12 @@ sysconfdir = @sysconfdir@
36583 target_alias = @target_alias@
36584 target_cpu = @target_cpu@
36585 +target_noncanonical = @target_noncanonical@
36586 target_os = @target_os@
36587 target_vendor = @target_vendor@
36588 +toolexecdir = @toolexecdir@
36589 toolexeclibdir = @toolexeclibdir@
36590 +toolexecmainlibdir = @toolexecmainlibdir@
36591 uudecode = @uudecode@
36592 vm_classes = @vm_classes@
36593 nativeexeclib_LTLIBRARIES = libgstreamerpeer.la
36594 --- a/libjava/classpath/native/jni/gtk-peer/Makefile.in
36595 +++ b/libjava/classpath/native/jni/gtk-peer/Makefile.in
36596 @@ -397,9 +397,12 @@ sysconfdir = @sysconfdir@
36598 target_alias = @target_alias@
36599 target_cpu = @target_cpu@
36600 +target_noncanonical = @target_noncanonical@
36601 target_os = @target_os@
36602 target_vendor = @target_vendor@
36603 +toolexecdir = @toolexecdir@
36604 toolexeclibdir = @toolexeclibdir@
36605 +toolexecmainlibdir = @toolexecmainlibdir@
36606 uudecode = @uudecode@
36607 vm_classes = @vm_classes@
36608 nativeexeclib_LTLIBRARIES = libgtkpeer.la
36609 --- a/libjava/classpath/native/jni/java-io/Makefile.in
36610 +++ b/libjava/classpath/native/jni/java-io/Makefile.in
36611 @@ -361,9 +361,12 @@ sysconfdir = @sysconfdir@
36613 target_alias = @target_alias@
36614 target_cpu = @target_cpu@
36615 +target_noncanonical = @target_noncanonical@
36616 target_os = @target_os@
36617 target_vendor = @target_vendor@
36618 +toolexecdir = @toolexecdir@
36619 toolexeclibdir = @toolexeclibdir@
36620 +toolexecmainlibdir = @toolexecmainlibdir@
36621 uudecode = @uudecode@
36622 vm_classes = @vm_classes@
36623 nativeexeclib_LTLIBRARIES = libjavaio.la
36624 --- a/libjava/classpath/native/jni/java-lang/Makefile.in
36625 +++ b/libjava/classpath/native/jni/java-lang/Makefile.in
36626 @@ -375,9 +375,12 @@ sysconfdir = @sysconfdir@
36628 target_alias = @target_alias@
36629 target_cpu = @target_cpu@
36630 +target_noncanonical = @target_noncanonical@
36631 target_os = @target_os@
36632 target_vendor = @target_vendor@
36633 +toolexecdir = @toolexecdir@
36634 toolexeclibdir = @toolexeclibdir@
36635 +toolexecmainlibdir = @toolexecmainlibdir@
36636 uudecode = @uudecode@
36637 vm_classes = @vm_classes@
36638 nativeexeclib_LTLIBRARIES = libjavalang.la libjavalangreflect.la libjavalangmanagement.la
36639 --- a/libjava/classpath/native/jni/java-math/Makefile.in
36640 +++ b/libjava/classpath/native/jni/java-math/Makefile.in
36641 @@ -359,9 +359,12 @@ sysconfdir = @sysconfdir@
36643 target_alias = @target_alias@
36644 target_cpu = @target_cpu@
36645 +target_noncanonical = @target_noncanonical@
36646 target_os = @target_os@
36647 target_vendor = @target_vendor@
36648 +toolexecdir = @toolexecdir@
36649 toolexeclibdir = @toolexeclibdir@
36650 +toolexecmainlibdir = @toolexecmainlibdir@
36651 uudecode = @uudecode@
36652 vm_classes = @vm_classes@
36653 nativeexeclib_LTLIBRARIES = libjavamath.la
36654 --- a/libjava/classpath/native/jni/java-net/Makefile.in
36655 +++ b/libjava/classpath/native/jni/java-net/Makefile.in
36656 @@ -371,9 +371,12 @@ sysconfdir = @sysconfdir@
36658 target_alias = @target_alias@
36659 target_cpu = @target_cpu@
36660 +target_noncanonical = @target_noncanonical@
36661 target_os = @target_os@
36662 target_vendor = @target_vendor@
36663 +toolexecdir = @toolexecdir@
36664 toolexeclibdir = @toolexeclibdir@
36665 +toolexecmainlibdir = @toolexecmainlibdir@
36666 uudecode = @uudecode@
36667 vm_classes = @vm_classes@
36668 nativeexeclib_LTLIBRARIES = libjavanet.la
36669 --- a/libjava/classpath/native/jni/java-nio/Makefile.in
36670 +++ b/libjava/classpath/native/jni/java-nio/Makefile.in
36671 @@ -369,9 +369,12 @@ sysconfdir = @sysconfdir@
36673 target_alias = @target_alias@
36674 target_cpu = @target_cpu@
36675 +target_noncanonical = @target_noncanonical@
36676 target_os = @target_os@
36677 target_vendor = @target_vendor@
36678 +toolexecdir = @toolexecdir@
36679 toolexeclibdir = @toolexeclibdir@
36680 +toolexecmainlibdir = @toolexecmainlibdir@
36681 uudecode = @uudecode@
36682 vm_classes = @vm_classes@
36683 nativeexeclib_LTLIBRARIES = libjavanio.la
36684 --- a/libjava/classpath/native/jni/java-util/Makefile.in
36685 +++ b/libjava/classpath/native/jni/java-util/Makefile.in
36686 @@ -358,9 +358,12 @@ sysconfdir = @sysconfdir@
36688 target_alias = @target_alias@
36689 target_cpu = @target_cpu@
36690 +target_noncanonical = @target_noncanonical@
36691 target_os = @target_os@
36692 target_vendor = @target_vendor@
36693 +toolexecdir = @toolexecdir@
36694 toolexeclibdir = @toolexeclibdir@
36695 +toolexecmainlibdir = @toolexecmainlibdir@
36696 uudecode = @uudecode@
36697 vm_classes = @vm_classes@
36698 nativeexeclib_LTLIBRARIES = libjavautil.la
36699 --- a/libjava/classpath/native/jni/midi-alsa/Makefile.in
36700 +++ b/libjava/classpath/native/jni/midi-alsa/Makefile.in
36701 @@ -361,9 +361,12 @@ sysconfdir = @sysconfdir@
36703 target_alias = @target_alias@
36704 target_cpu = @target_cpu@
36705 +target_noncanonical = @target_noncanonical@
36706 target_os = @target_os@
36707 target_vendor = @target_vendor@
36708 +toolexecdir = @toolexecdir@
36709 toolexeclibdir = @toolexeclibdir@
36710 +toolexecmainlibdir = @toolexecmainlibdir@
36711 uudecode = @uudecode@
36712 vm_classes = @vm_classes@
36713 nativeexeclib_LTLIBRARIES = libgjsmalsa.la
36714 --- a/libjava/classpath/native/jni/midi-dssi/Makefile.in
36715 +++ b/libjava/classpath/native/jni/midi-dssi/Makefile.in
36716 @@ -361,9 +361,12 @@ sysconfdir = @sysconfdir@
36718 target_alias = @target_alias@
36719 target_cpu = @target_cpu@
36720 +target_noncanonical = @target_noncanonical@
36721 target_os = @target_os@
36722 target_vendor = @target_vendor@
36723 +toolexecdir = @toolexecdir@
36724 toolexeclibdir = @toolexeclibdir@
36725 +toolexecmainlibdir = @toolexecmainlibdir@
36726 uudecode = @uudecode@
36727 vm_classes = @vm_classes@
36728 nativeexeclib_LTLIBRARIES = libgjsmdssi.la
36729 --- a/libjava/classpath/native/jni/native-lib/Makefile.in
36730 +++ b/libjava/classpath/native/jni/native-lib/Makefile.in
36731 @@ -350,9 +350,12 @@ sysconfdir = @sysconfdir@
36733 target_alias = @target_alias@
36734 target_cpu = @target_cpu@
36735 +target_noncanonical = @target_noncanonical@
36736 target_os = @target_os@
36737 target_vendor = @target_vendor@
36738 +toolexecdir = @toolexecdir@
36739 toolexeclibdir = @toolexeclibdir@
36740 +toolexecmainlibdir = @toolexecmainlibdir@
36741 uudecode = @uudecode@
36742 vm_classes = @vm_classes@
36743 noinst_LTLIBRARIES = libclasspathnative.la
36744 --- a/libjava/classpath/native/jni/qt-peer/Makefile.in
36745 +++ b/libjava/classpath/native/jni/qt-peer/Makefile.in
36746 @@ -376,9 +376,12 @@ sysconfdir = @sysconfdir@
36748 target_alias = @target_alias@
36749 target_cpu = @target_cpu@
36750 +target_noncanonical = @target_noncanonical@
36751 target_os = @target_os@
36752 target_vendor = @target_vendor@
36753 +toolexecdir = @toolexecdir@
36754 toolexeclibdir = @toolexeclibdir@
36755 +toolexecmainlibdir = @toolexecmainlibdir@
36756 uudecode = @uudecode@
36757 vm_classes = @vm_classes@
36758 noinst_LTLIBRARIES = libqtpeer.la
36759 --- a/libjava/classpath/native/jni/xmlj/Makefile.in
36760 +++ b/libjava/classpath/native/jni/xmlj/Makefile.in
36761 @@ -360,9 +360,12 @@ sysconfdir = @sysconfdir@
36763 target_alias = @target_alias@
36764 target_cpu = @target_cpu@
36765 +target_noncanonical = @target_noncanonical@
36766 target_os = @target_os@
36767 target_vendor = @target_vendor@
36768 +toolexecdir = @toolexecdir@
36769 toolexeclibdir = @toolexeclibdir@
36770 +toolexecmainlibdir = @toolexecmainlibdir@
36771 uudecode = @uudecode@
36772 vm_classes = @vm_classes@
36773 nativeexeclib_LTLIBRARIES = libxmlj.la
36774 --- a/libjava/classpath/native/plugin/Makefile.in
36775 +++ b/libjava/classpath/native/plugin/Makefile.in
36776 @@ -358,9 +358,12 @@ sysconfdir = @sysconfdir@
36778 target_alias = @target_alias@
36779 target_cpu = @target_cpu@
36780 +target_noncanonical = @target_noncanonical@
36781 target_os = @target_os@
36782 target_vendor = @target_vendor@
36783 +toolexecdir = @toolexecdir@
36784 toolexeclibdir = @toolexeclibdir@
36785 +toolexecmainlibdir = @toolexecmainlibdir@
36786 uudecode = @uudecode@
36787 vm_classes = @vm_classes@
36788 nativeexeclib_LTLIBRARIES = libgcjwebplugin.la
36789 --- a/libjava/classpath/resource/Makefile.in
36790 +++ b/libjava/classpath/resource/Makefile.in
36791 @@ -343,9 +343,12 @@ sysconfdir = @sysconfdir@
36793 target_alias = @target_alias@
36794 target_cpu = @target_cpu@
36795 +target_noncanonical = @target_noncanonical@
36796 target_os = @target_os@
36797 target_vendor = @target_vendor@
36798 +toolexecdir = @toolexecdir@
36799 toolexeclibdir = @toolexeclibdir@
36800 +toolexecmainlibdir = @toolexecmainlibdir@
36801 uudecode = @uudecode@
36802 vm_classes = @vm_classes@
36803 logging_DATA = java/util/logging/logging.properties
36804 --- a/libjava/classpath/scripts/Makefile.in
36805 +++ b/libjava/classpath/scripts/Makefile.in
36806 @@ -333,9 +333,12 @@ sysconfdir = @sysconfdir@
36808 target_alias = @target_alias@
36809 target_cpu = @target_cpu@
36810 +target_noncanonical = @target_noncanonical@
36811 target_os = @target_os@
36812 target_vendor = @target_vendor@
36813 +toolexecdir = @toolexecdir@
36814 toolexeclibdir = @toolexeclibdir@
36815 +toolexecmainlibdir = @toolexecmainlibdir@
36816 uudecode = @uudecode@
36817 vm_classes = @vm_classes@
36818 EXTRA_DIST = generate-locale-list.sh import-cacerts.sh
36819 --- a/libjava/classpath/tools/Makefile.in
36820 +++ b/libjava/classpath/tools/Makefile.in
36821 @@ -448,9 +448,12 @@ sysconfdir = @sysconfdir@
36823 target_alias = @target_alias@
36824 target_cpu = @target_cpu@
36825 +target_noncanonical = @target_noncanonical@
36826 target_os = @target_os@
36827 target_vendor = @target_vendor@
36828 +toolexecdir = @toolexecdir@
36829 toolexeclibdir = @toolexeclibdir@
36830 +toolexecmainlibdir = @toolexecmainlibdir@
36831 uudecode = @uudecode@
36832 vm_classes = @vm_classes@
36833 @CREATE_GJDOC_TRUE@gjdoc_gendir = ${top_srcdir}/tools/generated
36834 --- a/libjava/configure
36835 +++ b/libjava/configure
36836 @@ -26500,10 +26500,10 @@ gcjsubdir=gcj-$gcjversion-$libgcj_sovers
36837 multi_os_directory=`$CC -print-multi-os-directory`
36838 case $multi_os_directory in
36840 - dbexecdir='$(libdir)/'$gcjsubdir # Avoid /.
36841 + dbexecdir='$(toolexeclibdir)/'$gcjsubdir # Avoid /.
36844 - dbexecdir='$(libdir)/'$multi_os_directory/$gcjsubdir
36845 + dbexecdir='$(toolexeclibdir)/'$multi_os_directory/$gcjsubdir
36849 @@ -27651,6 +27651,74 @@ if { (eval echo "$as_me:$LINENO: \"$ac_l
36851 echo "$as_me:$LINENO: \$? = $ac_status" >&5
36852 (exit $ac_status); }; }; then
36853 + chktls_save_LDFLAGS="$LDFLAGS"
36856 + LDFLAGS="-shared -Wl,--no-undefined $LDFLAGS"
36859 + chktls_save_CFLAGS="$CFLAGS"
36860 + CFLAGS="-fPIC $CFLAGS"
36861 + if test x$gcc_no_link = xyes; then
36862 + { { echo "$as_me:$LINENO: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&5
36863 +echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;}
36864 + { (exit 1); exit 1; }; }
36866 +cat >conftest.$ac_ext <<_ACEOF
36867 +int f() { return 0; }
36869 +rm -f conftest.$ac_objext conftest$ac_exeext
36870 +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
36871 + (eval $ac_link) 2>conftest.er1
36873 + grep -v '^ *+' conftest.er1 >conftest.err
36874 + rm -f conftest.er1
36875 + cat conftest.err >&5
36876 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
36877 + (exit $ac_status); } &&
36878 + { ac_try='test -z "$ac_c_werror_flag"
36879 + || test ! -s conftest.err'
36880 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
36881 + (eval $ac_try) 2>&5
36883 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
36884 + (exit $ac_status); }; } &&
36885 + { ac_try='test -s conftest$ac_exeext'
36886 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
36887 + (eval $ac_try) 2>&5
36889 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
36890 + (exit $ac_status); }; }; then
36891 + if test x$gcc_no_link = xyes; then
36892 + { { echo "$as_me:$LINENO: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&5
36893 +echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;}
36894 + { (exit 1); exit 1; }; }
36896 +cat >conftest.$ac_ext <<_ACEOF
36897 +__thread int a; int b; int f() { return a = b; }
36899 +rm -f conftest.$ac_objext conftest$ac_exeext
36900 +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
36901 + (eval $ac_link) 2>conftest.er1
36903 + grep -v '^ *+' conftest.er1 >conftest.err
36904 + rm -f conftest.er1
36905 + cat conftest.err >&5
36906 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
36907 + (exit $ac_status); } &&
36908 + { ac_try='test -z "$ac_c_werror_flag"
36909 + || test ! -s conftest.err'
36910 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
36911 + (eval $ac_try) 2>&5
36913 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
36914 + (exit $ac_status); }; } &&
36915 + { ac_try='test -s conftest$ac_exeext'
36916 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
36917 + (eval $ac_try) 2>&5
36919 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
36920 + (exit $ac_status); }; }; then
36921 gcc_cv_have_tls=yes
36923 echo "$as_me: failed program was:" >&5
36924 @@ -27660,6 +27728,24 @@ gcc_cv_have_tls=no
36926 rm -f conftest.err conftest.$ac_objext \
36927 conftest$ac_exeext conftest.$ac_ext
36929 + echo "$as_me: failed program was:" >&5
36930 +sed 's/^/| /' conftest.$ac_ext >&5
36932 +gcc_cv_have_tls=yes
36934 +rm -f conftest.err conftest.$ac_objext \
36935 + conftest$ac_exeext conftest.$ac_ext
36936 + CFLAGS="$chktls_save_CFLAGS"
36937 + LDFLAGS="$chktls_save_LDFLAGS"
36939 + echo "$as_me: failed program was:" >&5
36940 +sed 's/^/| /' conftest.$ac_ext >&5
36942 +gcc_cv_have_tls=no
36944 +rm -f conftest.err conftest.$ac_objext \
36945 + conftest$ac_exeext conftest.$ac_ext
36949 --- a/libjava/configure.ac
36950 +++ b/libjava/configure.ac
36951 @@ -1489,10 +1489,10 @@ gcjsubdir=gcj-$gcjversion-$libgcj_sovers
36952 multi_os_directory=`$CC -print-multi-os-directory`
36953 case $multi_os_directory in
36955 - dbexecdir='$(libdir)/'$gcjsubdir # Avoid /.
36956 + dbexecdir='$(toolexeclibdir)/'$gcjsubdir # Avoid /.
36959 - dbexecdir='$(libdir)/'$multi_os_directory/$gcjsubdir
36960 + dbexecdir='$(toolexeclibdir)/'$multi_os_directory/$gcjsubdir
36963 AC_SUBST(dbexecdir)
36964 --- a/libmudflap/configure
36965 +++ b/libmudflap/configure
36966 @@ -12787,6 +12787,64 @@ if { (eval echo "$as_me:$LINENO: \"$ac_l
36968 echo "$as_me:$LINENO: \$? = $ac_status" >&5
36969 (exit $ac_status); }; }; then
36970 + chktls_save_LDFLAGS="$LDFLAGS"
36973 + LDFLAGS="-shared -Wl,--no-undefined $LDFLAGS"
36976 + chktls_save_CFLAGS="$CFLAGS"
36977 + CFLAGS="-fPIC $CFLAGS"
36978 + cat >conftest.$ac_ext <<_ACEOF
36979 +int f() { return 0; }
36981 +rm -f conftest.$ac_objext conftest$ac_exeext
36982 +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
36983 + (eval $ac_link) 2>conftest.er1
36985 + grep -v '^ *+' conftest.er1 >conftest.err
36986 + rm -f conftest.er1
36987 + cat conftest.err >&5
36988 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
36989 + (exit $ac_status); } &&
36990 + { ac_try='test -z "$ac_c_werror_flag"
36991 + || test ! -s conftest.err'
36992 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
36993 + (eval $ac_try) 2>&5
36995 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
36996 + (exit $ac_status); }; } &&
36997 + { ac_try='test -s conftest$ac_exeext'
36998 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
36999 + (eval $ac_try) 2>&5
37001 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37002 + (exit $ac_status); }; }; then
37003 + cat >conftest.$ac_ext <<_ACEOF
37004 +__thread int a; int b; int f() { return a = b; }
37006 +rm -f conftest.$ac_objext conftest$ac_exeext
37007 +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
37008 + (eval $ac_link) 2>conftest.er1
37010 + grep -v '^ *+' conftest.er1 >conftest.err
37011 + rm -f conftest.er1
37012 + cat conftest.err >&5
37013 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37014 + (exit $ac_status); } &&
37015 + { ac_try='test -z "$ac_c_werror_flag"
37016 + || test ! -s conftest.err'
37017 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
37018 + (eval $ac_try) 2>&5
37020 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37021 + (exit $ac_status); }; } &&
37022 + { ac_try='test -s conftest$ac_exeext'
37023 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
37024 + (eval $ac_try) 2>&5
37026 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37027 + (exit $ac_status); }; }; then
37028 gcc_cv_have_tls=yes
37030 echo "$as_me: failed program was:" >&5
37031 @@ -12796,6 +12854,24 @@ gcc_cv_have_tls=no
37033 rm -f conftest.err conftest.$ac_objext \
37034 conftest$ac_exeext conftest.$ac_ext
37036 + echo "$as_me: failed program was:" >&5
37037 +sed 's/^/| /' conftest.$ac_ext >&5
37039 +gcc_cv_have_tls=yes
37041 +rm -f conftest.err conftest.$ac_objext \
37042 + conftest$ac_exeext conftest.$ac_ext
37043 + CFLAGS="$chktls_save_CFLAGS"
37044 + LDFLAGS="$chktls_save_LDFLAGS"
37046 + echo "$as_me: failed program was:" >&5
37047 +sed 's/^/| /' conftest.$ac_ext >&5
37049 +gcc_cv_have_tls=no
37051 +rm -f conftest.err conftest.$ac_objext \
37052 + conftest$ac_exeext conftest.$ac_ext
37056 --- a/libstdc++-v3/Makefile.in
37057 +++ b/libstdc++-v3/Makefile.in
37058 @@ -193,6 +193,8 @@ LIBICONV = @LIBICONV@
37059 LIBOBJS = @LIBOBJS@
37061 LIBSUPCXX_PICFLAGS = @LIBSUPCXX_PICFLAGS@
37062 +LIBSUPCXX_PRONLY_FALSE = @LIBSUPCXX_PRONLY_FALSE@
37063 +LIBSUPCXX_PRONLY_TRUE = @LIBSUPCXX_PRONLY_TRUE@
37064 LIBTOOL = @LIBTOOL@
37067 --- a/libstdc++-v3/config/cpu/sh/atomicity.h
37068 +++ b/libstdc++-v3/config/cpu/sh/atomicity.h
37069 @@ -25,47 +25,48 @@
37073 -#ifndef _GLIBCXX_ATOMICITY_H
37074 -#define _GLIBCXX_ATOMICITY_H 1
37075 +#include <ext/atomicity.h>
37077 -typedef int _Atomic_word;
37078 +_GLIBCXX_BEGIN_NAMESPACE(__gnu_cxx)
37080 -static inline _Atomic_word
37081 -__attribute__ ((__unused__))
37082 -__exchange_and_add (volatile _Atomic_word* __mem, int __val)
37084 - _Atomic_word __result;
37085 + typedef int _Atomic_word;
37087 - __asm__ __volatile__
37089 - "\tmovli.l\t@%2,r0\n"
37092 - "\tmovco.l\tr0,@%2\n"
37094 - : "+m" (*__mem), "=r" (__result)
37095 - : "r" (__mem), "rI08" (__val)
37102 -static inline void
37103 -__attribute__ ((__unused__))
37104 -__atomic_add (volatile _Atomic_word* __mem, int __val)
37107 - "\tmovli.l\t@%1,r0\n"
37109 - "\tmovco.l\tr0,@%1\n"
37112 - : "r" (__mem), "rI08" (__val)
37116 + __attribute__ ((__unused__))
37117 + __exchange_and_add (volatile _Atomic_word* __mem, int __val)
37119 + _Atomic_word __result;
37122 + __asm__ __volatile__
37124 + "\tmovli.l\t@%2,r0\n"
37127 + "\tmovco.l\tr0,@%2\n"
37129 + : "+m" (*__mem), "=&r" (__result)
37130 + : "r" (__mem), "rI08" (__val)
37138 + __attribute__ ((__unused__))
37139 + __atomic_add (volatile _Atomic_word* __mem, int __val)
37142 + "\tmovli.l\t@%1,r0\n"
37144 + "\tmovco.l\tr0,@%1\n"
37147 + : "r" (__mem), "rI08" (__val)
37151 +_GLIBCXX_END_NAMESPACE
37153 #else /* !__SH4A__ */
37155 --- a/libstdc++-v3/configure
37156 +++ b/libstdc++-v3/configure
37157 @@ -458,7 +458,7 @@ ac_includes_default="\
37158 # include <unistd.h>
37161 -ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS libtool_VERSION multi_basedir build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CYGPATH_W PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM mkdir_p AWK SET_MAKE am__leading_dot AMTAR am__tar am__untar glibcxx_builddir glibcxx_srcdir toplevel_srcdir CC ac_ct_CC EXEEXT OBJEXT CXX ac_ct_CXX CFLAGS CXXFLAGS LN_S AS ac_ct_AS AR ac_ct_AR RANLIB ac_ct_RANLIB MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT CPP CPPFLAGS EGREP LIBTOOL SED FGREP GREP LD DUMPBIN ac_ct_DUMPBIN NM OBJDUMP ac_ct_OBJDUMP lt_ECHO DSYMUTIL ac_ct_DSYMUTIL NMEDIT ac_ct_NMEDIT LIPO ac_ct_LIPO OTOOL ac_ct_OTOOL OTOOL64 ac_ct_OTOOL64 LDFLAGS CXXCPP enable_shared enable_static GLIBCXX_HOSTED_TRUE GLIBCXX_HOSTED_FALSE GLIBCXX_BUILD_PCH_TRUE GLIBCXX_BUILD_PCH_FALSE glibcxx_PCHFLAGS glibcxx_thread_h WERROR SECTION_FLAGS CSTDIO_H BASIC_FILE_H BASIC_FILE_CC check_msgfmt glibcxx_MOFILES glibcxx_POFILES glibcxx_localedir USE_NLS CLOCALE_H CMESSAGES_H CCODECVT_CC CCOLLATE_CC CCTYPE_CC CMESSAGES_CC CMONEY_CC CNUMERIC_CC CTIME_H CTIME_CC CLOCALE_CC CLOCALE_INTERNAL_H ALLOCATOR_H ALLOCATOR_NAME C_INCLUDE_DIR GLIBCXX_C_HEADERS_C_TRUE GLIBCXX_C_HEADERS_C_FALSE GLIBCXX_C_HEADERS_C_STD_TRUE GLIBCXX_C_HEADERS_C_STD_FALSE GLIBCXX_C_HEADERS_C_GLOBAL_TRUE GLIBCXX_C_HEADERS_C_GLOBAL_FALSE GLIBCXX_C_HEADERS_COMPATIBILITY_TRUE GLIBCXX_C_HEADERS_COMPATIBILITY_FALSE GLIBCXX_C_HEADERS_EXTRA_TRUE GLIBCXX_C_HEADERS_EXTRA_FALSE DEBUG_FLAGS GLIBCXX_BUILD_DEBUG_TRUE GLIBCXX_BUILD_DEBUG_FALSE ENABLE_PARALLEL_TRUE ENABLE_PARALLEL_FALSE EXTRA_CXX_FLAGS GLIBCXX_LIBS SECTION_LDFLAGS OPT_LDFLAGS LIBICONV LTLIBICONV SYMVER_FILE port_specific_symbol_files ENABLE_SYMVERS_TRUE ENABLE_SYMVERS_FALSE ENABLE_SYMVERS_GNU_TRUE ENABLE_SYMVERS_GNU_FALSE ENABLE_SYMVERS_GNU_NAMESPACE_TRUE ENABLE_SYMVERS_GNU_NAMESPACE_FALSE ENABLE_SYMVERS_DARWIN_TRUE ENABLE_SYMVERS_DARWIN_FALSE ENABLE_VISIBILITY_TRUE ENABLE_VISIBILITY_FALSE GLIBCXX_LDBL_COMPAT_TRUE GLIBCXX_LDBL_COMPAT_FALSE baseline_dir ATOMICITY_SRCDIR ATOMIC_WORD_SRCDIR ATOMIC_FLAGS CPU_DEFINES_SRCDIR ABI_TWEAKS_SRCDIR OS_INC_SRCDIR ERROR_CONSTANTS_SRCDIR glibcxx_prefixdir gxx_include_dir glibcxx_toolexecdir glibcxx_toolexeclibdir GLIBCXX_INCLUDES TOPLEVEL_INCLUDES OPTIMIZE_CXXFLAGS WARN_FLAGS LIBSUPCXX_PICFLAGS LIBOBJS LTLIBOBJS'
37162 +ac_subst_vars='SHELL PATH_SEPARATOR PACKAGE_NAME PACKAGE_TARNAME PACKAGE_VERSION PACKAGE_STRING PACKAGE_BUGREPORT exec_prefix prefix program_transform_name bindir sbindir libexecdir datadir sysconfdir sharedstatedir localstatedir libdir includedir oldincludedir infodir mandir build_alias host_alias target_alias DEFS ECHO_C ECHO_N ECHO_T LIBS libtool_VERSION multi_basedir build build_cpu build_vendor build_os host host_cpu host_vendor host_os target target_cpu target_vendor target_os INSTALL_PROGRAM INSTALL_SCRIPT INSTALL_DATA CYGPATH_W PACKAGE VERSION ACLOCAL AUTOCONF AUTOMAKE AUTOHEADER MAKEINFO install_sh STRIP ac_ct_STRIP INSTALL_STRIP_PROGRAM mkdir_p AWK SET_MAKE am__leading_dot AMTAR am__tar am__untar glibcxx_builddir glibcxx_srcdir toplevel_srcdir CC ac_ct_CC EXEEXT OBJEXT CXX ac_ct_CXX CFLAGS CXXFLAGS LN_S AS ac_ct_AS AR ac_ct_AR RANLIB ac_ct_RANLIB MAINTAINER_MODE_TRUE MAINTAINER_MODE_FALSE MAINT CPP CPPFLAGS EGREP LIBTOOL SED FGREP GREP LD DUMPBIN ac_ct_DUMPBIN NM OBJDUMP ac_ct_OBJDUMP lt_ECHO DSYMUTIL ac_ct_DSYMUTIL NMEDIT ac_ct_NMEDIT LIPO ac_ct_LIPO OTOOL ac_ct_OTOOL OTOOL64 ac_ct_OTOOL64 LDFLAGS CXXCPP enable_shared enable_static GLIBCXX_HOSTED_TRUE GLIBCXX_HOSTED_FALSE GLIBCXX_BUILD_PCH_TRUE GLIBCXX_BUILD_PCH_FALSE glibcxx_PCHFLAGS glibcxx_thread_h WERROR SECTION_FLAGS CSTDIO_H BASIC_FILE_H BASIC_FILE_CC check_msgfmt glibcxx_MOFILES glibcxx_POFILES glibcxx_localedir USE_NLS CLOCALE_H CMESSAGES_H CCODECVT_CC CCOLLATE_CC CCTYPE_CC CMESSAGES_CC CMONEY_CC CNUMERIC_CC CTIME_H CTIME_CC CLOCALE_CC CLOCALE_INTERNAL_H ALLOCATOR_H ALLOCATOR_NAME C_INCLUDE_DIR GLIBCXX_C_HEADERS_C_TRUE GLIBCXX_C_HEADERS_C_FALSE GLIBCXX_C_HEADERS_C_STD_TRUE GLIBCXX_C_HEADERS_C_STD_FALSE GLIBCXX_C_HEADERS_C_GLOBAL_TRUE GLIBCXX_C_HEADERS_C_GLOBAL_FALSE GLIBCXX_C_HEADERS_COMPATIBILITY_TRUE GLIBCXX_C_HEADERS_COMPATIBILITY_FALSE GLIBCXX_C_HEADERS_EXTRA_TRUE GLIBCXX_C_HEADERS_EXTRA_FALSE DEBUG_FLAGS GLIBCXX_BUILD_DEBUG_TRUE GLIBCXX_BUILD_DEBUG_FALSE ENABLE_PARALLEL_TRUE ENABLE_PARALLEL_FALSE EXTRA_CXX_FLAGS GLIBCXX_LIBS SECTION_LDFLAGS OPT_LDFLAGS LIBICONV LTLIBICONV SYMVER_FILE port_specific_symbol_files ENABLE_SYMVERS_TRUE ENABLE_SYMVERS_FALSE ENABLE_SYMVERS_GNU_TRUE ENABLE_SYMVERS_GNU_FALSE ENABLE_SYMVERS_GNU_NAMESPACE_TRUE ENABLE_SYMVERS_GNU_NAMESPACE_FALSE ENABLE_SYMVERS_DARWIN_TRUE ENABLE_SYMVERS_DARWIN_FALSE ENABLE_VISIBILITY_TRUE ENABLE_VISIBILITY_FALSE GLIBCXX_LDBL_COMPAT_TRUE GLIBCXX_LDBL_COMPAT_FALSE baseline_dir ATOMICITY_SRCDIR ATOMIC_WORD_SRCDIR ATOMIC_FLAGS CPU_DEFINES_SRCDIR ABI_TWEAKS_SRCDIR OS_INC_SRCDIR ERROR_CONSTANTS_SRCDIR LIBSUPCXX_PRONLY_TRUE LIBSUPCXX_PRONLY_FALSE glibcxx_prefixdir gxx_include_dir glibcxx_toolexecdir glibcxx_toolexeclibdir GLIBCXX_INCLUDES TOPLEVEL_INCLUDES OPTIMIZE_CXXFLAGS WARN_FLAGS LIBSUPCXX_PICFLAGS LIBOBJS LTLIBOBJS'
37166 @@ -40730,6 +40730,74 @@ if { (eval echo "$as_me:$LINENO: \"$ac_l
37168 echo "$as_me:$LINENO: \$? = $ac_status" >&5
37169 (exit $ac_status); }; }; then
37170 + chktls_save_LDFLAGS="$LDFLAGS"
37173 + LDFLAGS="-shared -Wl,--no-undefined $LDFLAGS"
37176 + chktls_save_CFLAGS="$CFLAGS"
37177 + CFLAGS="-fPIC $CFLAGS"
37178 + if test x$gcc_no_link = xyes; then
37179 + { { echo "$as_me:$LINENO: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&5
37180 +echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;}
37181 + { (exit 1); exit 1; }; }
37183 +cat >conftest.$ac_ext <<_ACEOF
37184 +int f() { return 0; }
37186 +rm -f conftest.$ac_objext conftest$ac_exeext
37187 +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
37188 + (eval $ac_link) 2>conftest.er1
37190 + grep -v '^ *+' conftest.er1 >conftest.err
37191 + rm -f conftest.er1
37192 + cat conftest.err >&5
37193 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37194 + (exit $ac_status); } &&
37195 + { ac_try='test -z "$ac_c_werror_flag"
37196 + || test ! -s conftest.err'
37197 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
37198 + (eval $ac_try) 2>&5
37200 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37201 + (exit $ac_status); }; } &&
37202 + { ac_try='test -s conftest$ac_exeext'
37203 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
37204 + (eval $ac_try) 2>&5
37206 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37207 + (exit $ac_status); }; }; then
37208 + if test x$gcc_no_link = xyes; then
37209 + { { echo "$as_me:$LINENO: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&5
37210 +echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;}
37211 + { (exit 1); exit 1; }; }
37213 +cat >conftest.$ac_ext <<_ACEOF
37214 +__thread int a; int b; int f() { return a = b; }
37216 +rm -f conftest.$ac_objext conftest$ac_exeext
37217 +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
37218 + (eval $ac_link) 2>conftest.er1
37220 + grep -v '^ *+' conftest.er1 >conftest.err
37221 + rm -f conftest.er1
37222 + cat conftest.err >&5
37223 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37224 + (exit $ac_status); } &&
37225 + { ac_try='test -z "$ac_c_werror_flag"
37226 + || test ! -s conftest.err'
37227 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
37228 + (eval $ac_try) 2>&5
37230 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37231 + (exit $ac_status); }; } &&
37232 + { ac_try='test -s conftest$ac_exeext'
37233 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
37234 + (eval $ac_try) 2>&5
37236 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37237 + (exit $ac_status); }; }; then
37238 gcc_cv_have_tls=yes
37240 echo "$as_me: failed program was:" >&5
37241 @@ -40739,6 +40807,24 @@ gcc_cv_have_tls=no
37243 rm -f conftest.err conftest.$ac_objext \
37244 conftest$ac_exeext conftest.$ac_ext
37246 + echo "$as_me: failed program was:" >&5
37247 +sed 's/^/| /' conftest.$ac_ext >&5
37249 +gcc_cv_have_tls=yes
37251 +rm -f conftest.err conftest.$ac_objext \
37252 + conftest$ac_exeext conftest.$ac_ext
37253 + CFLAGS="$chktls_save_CFLAGS"
37254 + LDFLAGS="$chktls_save_LDFLAGS"
37256 + echo "$as_me: failed program was:" >&5
37257 +sed 's/^/| /' conftest.$ac_ext >&5
37259 +gcc_cv_have_tls=no
37261 +rm -f conftest.err conftest.$ac_objext \
37262 + conftest$ac_exeext conftest.$ac_ext
37266 @@ -76926,6 +77012,74 @@ if { (eval echo "$as_me:$LINENO: \"$ac_l
37268 echo "$as_me:$LINENO: \$? = $ac_status" >&5
37269 (exit $ac_status); }; }; then
37270 + chktls_save_LDFLAGS="$LDFLAGS"
37273 + LDFLAGS="-shared -Wl,--no-undefined $LDFLAGS"
37276 + chktls_save_CFLAGS="$CFLAGS"
37277 + CFLAGS="-fPIC $CFLAGS"
37278 + if test x$gcc_no_link = xyes; then
37279 + { { echo "$as_me:$LINENO: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&5
37280 +echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;}
37281 + { (exit 1); exit 1; }; }
37283 +cat >conftest.$ac_ext <<_ACEOF
37284 +int f() { return 0; }
37286 +rm -f conftest.$ac_objext conftest$ac_exeext
37287 +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
37288 + (eval $ac_link) 2>conftest.er1
37290 + grep -v '^ *+' conftest.er1 >conftest.err
37291 + rm -f conftest.er1
37292 + cat conftest.err >&5
37293 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37294 + (exit $ac_status); } &&
37295 + { ac_try='test -z "$ac_c_werror_flag"
37296 + || test ! -s conftest.err'
37297 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
37298 + (eval $ac_try) 2>&5
37300 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37301 + (exit $ac_status); }; } &&
37302 + { ac_try='test -s conftest$ac_exeext'
37303 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
37304 + (eval $ac_try) 2>&5
37306 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37307 + (exit $ac_status); }; }; then
37308 + if test x$gcc_no_link = xyes; then
37309 + { { echo "$as_me:$LINENO: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&5
37310 +echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;}
37311 + { (exit 1); exit 1; }; }
37313 +cat >conftest.$ac_ext <<_ACEOF
37314 +__thread int a; int b; int f() { return a = b; }
37316 +rm -f conftest.$ac_objext conftest$ac_exeext
37317 +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
37318 + (eval $ac_link) 2>conftest.er1
37320 + grep -v '^ *+' conftest.er1 >conftest.err
37321 + rm -f conftest.er1
37322 + cat conftest.err >&5
37323 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37324 + (exit $ac_status); } &&
37325 + { ac_try='test -z "$ac_c_werror_flag"
37326 + || test ! -s conftest.err'
37327 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
37328 + (eval $ac_try) 2>&5
37330 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37331 + (exit $ac_status); }; } &&
37332 + { ac_try='test -s conftest$ac_exeext'
37333 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
37334 + (eval $ac_try) 2>&5
37336 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37337 + (exit $ac_status); }; }; then
37338 gcc_cv_have_tls=yes
37340 echo "$as_me: failed program was:" >&5
37341 @@ -76935,6 +77089,24 @@ gcc_cv_have_tls=no
37343 rm -f conftest.err conftest.$ac_objext \
37344 conftest$ac_exeext conftest.$ac_ext
37346 + echo "$as_me: failed program was:" >&5
37347 +sed 's/^/| /' conftest.$ac_ext >&5
37349 +gcc_cv_have_tls=yes
37351 +rm -f conftest.err conftest.$ac_objext \
37352 + conftest$ac_exeext conftest.$ac_ext
37353 + CFLAGS="$chktls_save_CFLAGS"
37354 + LDFLAGS="$chktls_save_LDFLAGS"
37356 + echo "$as_me: failed program was:" >&5
37357 +sed 's/^/| /' conftest.$ac_ext >&5
37359 +gcc_cv_have_tls=no
37361 +rm -f conftest.err conftest.$ac_objext \
37362 + conftest$ac_exeext conftest.$ac_ext
37366 @@ -94541,6 +94713,74 @@ if { (eval echo "$as_me:$LINENO: \"$ac_l
37368 echo "$as_me:$LINENO: \$? = $ac_status" >&5
37369 (exit $ac_status); }; }; then
37370 + chktls_save_LDFLAGS="$LDFLAGS"
37373 + LDFLAGS="-shared -Wl,--no-undefined $LDFLAGS"
37376 + chktls_save_CFLAGS="$CFLAGS"
37377 + CFLAGS="-fPIC $CFLAGS"
37378 + if test x$gcc_no_link = xyes; then
37379 + { { echo "$as_me:$LINENO: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&5
37380 +echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;}
37381 + { (exit 1); exit 1; }; }
37383 +cat >conftest.$ac_ext <<_ACEOF
37384 +int f() { return 0; }
37386 +rm -f conftest.$ac_objext conftest$ac_exeext
37387 +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
37388 + (eval $ac_link) 2>conftest.er1
37390 + grep -v '^ *+' conftest.er1 >conftest.err
37391 + rm -f conftest.er1
37392 + cat conftest.err >&5
37393 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37394 + (exit $ac_status); } &&
37395 + { ac_try='test -z "$ac_c_werror_flag"
37396 + || test ! -s conftest.err'
37397 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
37398 + (eval $ac_try) 2>&5
37400 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37401 + (exit $ac_status); }; } &&
37402 + { ac_try='test -s conftest$ac_exeext'
37403 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
37404 + (eval $ac_try) 2>&5
37406 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37407 + (exit $ac_status); }; }; then
37408 + if test x$gcc_no_link = xyes; then
37409 + { { echo "$as_me:$LINENO: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&5
37410 +echo "$as_me: error: Link tests are not allowed after GCC_NO_EXECUTABLES." >&2;}
37411 + { (exit 1); exit 1; }; }
37413 +cat >conftest.$ac_ext <<_ACEOF
37414 +__thread int a; int b; int f() { return a = b; }
37416 +rm -f conftest.$ac_objext conftest$ac_exeext
37417 +if { (eval echo "$as_me:$LINENO: \"$ac_link\"") >&5
37418 + (eval $ac_link) 2>conftest.er1
37420 + grep -v '^ *+' conftest.er1 >conftest.err
37421 + rm -f conftest.er1
37422 + cat conftest.err >&5
37423 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37424 + (exit $ac_status); } &&
37425 + { ac_try='test -z "$ac_c_werror_flag"
37426 + || test ! -s conftest.err'
37427 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
37428 + (eval $ac_try) 2>&5
37430 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37431 + (exit $ac_status); }; } &&
37432 + { ac_try='test -s conftest$ac_exeext'
37433 + { (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
37434 + (eval $ac_try) 2>&5
37436 + echo "$as_me:$LINENO: \$? = $ac_status" >&5
37437 + (exit $ac_status); }; }; then
37438 gcc_cv_have_tls=yes
37440 echo "$as_me: failed program was:" >&5
37441 @@ -94550,6 +94790,24 @@ gcc_cv_have_tls=no
37443 rm -f conftest.err conftest.$ac_objext \
37444 conftest$ac_exeext conftest.$ac_ext
37446 + echo "$as_me: failed program was:" >&5
37447 +sed 's/^/| /' conftest.$ac_ext >&5
37449 +gcc_cv_have_tls=yes
37451 +rm -f conftest.err conftest.$ac_objext \
37452 + conftest$ac_exeext conftest.$ac_ext
37453 + CFLAGS="$chktls_save_CFLAGS"
37454 + LDFLAGS="$chktls_save_LDFLAGS"
37456 + echo "$as_me: failed program was:" >&5
37457 +sed 's/^/| /' conftest.$ac_ext >&5
37459 +gcc_cv_have_tls=no
37461 +rm -f conftest.err conftest.$ac_objext \
37462 + conftest$ac_exeext conftest.$ac_ext
37466 @@ -114470,7 +114728,8 @@ _ACEOF
37467 cat confdefs.h >>conftest.$ac_ext
37468 cat >>conftest.$ac_ext <<_ACEOF
37469 /* end confdefs.h. */
37470 -$ac_includes_default
37471 +/* no standard headers */
37476 @@ -114534,7 +114793,8 @@ _ACEOF
37477 cat confdefs.h >>conftest.$ac_ext
37478 cat >>conftest.$ac_ext <<_ACEOF
37479 /* end confdefs.h. */
37480 -$ac_includes_default
37481 +/* no standard headers */
37486 @@ -114575,7 +114835,8 @@ _ACEOF
37487 cat confdefs.h >>conftest.$ac_ext
37488 cat >>conftest.$ac_ext <<_ACEOF
37489 /* end confdefs.h. */
37490 -$ac_includes_default
37491 +/* no standard headers */
37496 @@ -114632,7 +114893,8 @@ _ACEOF
37497 cat confdefs.h >>conftest.$ac_ext
37498 cat >>conftest.$ac_ext <<_ACEOF
37499 /* end confdefs.h. */
37500 -$ac_includes_default
37501 +/* no standard headers */
37506 @@ -114673,7 +114935,8 @@ _ACEOF
37507 cat confdefs.h >>conftest.$ac_ext
37508 cat >>conftest.$ac_ext <<_ACEOF
37509 /* end confdefs.h. */
37510 -$ac_includes_default
37511 +/* no standard headers */
37516 @@ -114738,7 +115001,8 @@ _ACEOF
37517 cat confdefs.h >>conftest.$ac_ext
37518 cat >>conftest.$ac_ext <<_ACEOF
37519 /* end confdefs.h. */
37520 -$ac_includes_default
37521 +/* no standard headers */
37526 @@ -114806,7 +115070,8 @@ _ACEOF
37527 cat confdefs.h >>conftest.$ac_ext
37528 cat >>conftest.$ac_ext <<_ACEOF
37529 /* end confdefs.h. */
37530 -$ac_includes_default
37531 +/* no standard headers */
37533 long longval () { return (long) (sizeof (void *)); }
37534 unsigned long ulongval () { return (long) (sizeof (void *)); }
37536 @@ -114894,7 +115159,8 @@ _ACEOF
37537 cat confdefs.h >>conftest.$ac_ext
37538 cat >>conftest.$ac_ext <<_ACEOF
37539 /* end confdefs.h. */
37540 -$ac_includes_default
37541 +/* no standard headers */
37546 @@ -114958,7 +115224,8 @@ _ACEOF
37547 cat confdefs.h >>conftest.$ac_ext
37548 cat >>conftest.$ac_ext <<_ACEOF
37549 /* end confdefs.h. */
37550 -$ac_includes_default
37551 +/* no standard headers */
37556 @@ -114999,7 +115266,8 @@ _ACEOF
37557 cat confdefs.h >>conftest.$ac_ext
37558 cat >>conftest.$ac_ext <<_ACEOF
37559 /* end confdefs.h. */
37560 -$ac_includes_default
37561 +/* no standard headers */
37566 @@ -115056,7 +115324,8 @@ _ACEOF
37567 cat confdefs.h >>conftest.$ac_ext
37568 cat >>conftest.$ac_ext <<_ACEOF
37569 /* end confdefs.h. */
37570 -$ac_includes_default
37571 +/* no standard headers */
37576 @@ -115097,7 +115366,8 @@ _ACEOF
37577 cat confdefs.h >>conftest.$ac_ext
37578 cat >>conftest.$ac_ext <<_ACEOF
37579 /* end confdefs.h. */
37580 -$ac_includes_default
37581 +/* no standard headers */
37586 @@ -115162,7 +115432,8 @@ _ACEOF
37587 cat confdefs.h >>conftest.$ac_ext
37588 cat >>conftest.$ac_ext <<_ACEOF
37589 /* end confdefs.h. */
37590 -$ac_includes_default
37591 +/* no standard headers */
37596 @@ -115230,7 +115501,8 @@ _ACEOF
37597 cat confdefs.h >>conftest.$ac_ext
37598 cat >>conftest.$ac_ext <<_ACEOF
37599 /* end confdefs.h. */
37600 -$ac_includes_default
37601 +/* no standard headers */
37603 long longval () { return (long) (sizeof (long)); }
37604 unsigned long ulongval () { return (long) (sizeof (long)); }
37606 @@ -115318,7 +115590,8 @@ _ACEOF
37607 cat confdefs.h >>conftest.$ac_ext
37608 cat >>conftest.$ac_ext <<_ACEOF
37609 /* end confdefs.h. */
37610 -$ac_includes_default
37611 +/* no standard headers */
37616 @@ -115382,7 +115655,8 @@ _ACEOF
37617 cat confdefs.h >>conftest.$ac_ext
37618 cat >>conftest.$ac_ext <<_ACEOF
37619 /* end confdefs.h. */
37620 -$ac_includes_default
37621 +/* no standard headers */
37626 @@ -115423,7 +115697,8 @@ _ACEOF
37627 cat confdefs.h >>conftest.$ac_ext
37628 cat >>conftest.$ac_ext <<_ACEOF
37629 /* end confdefs.h. */
37630 -$ac_includes_default
37631 +/* no standard headers */
37636 @@ -115480,7 +115755,8 @@ _ACEOF
37637 cat confdefs.h >>conftest.$ac_ext
37638 cat >>conftest.$ac_ext <<_ACEOF
37639 /* end confdefs.h. */
37640 -$ac_includes_default
37641 +/* no standard headers */
37646 @@ -115521,7 +115797,8 @@ _ACEOF
37647 cat confdefs.h >>conftest.$ac_ext
37648 cat >>conftest.$ac_ext <<_ACEOF
37649 /* end confdefs.h. */
37650 -$ac_includes_default
37651 +/* no standard headers */
37656 @@ -115586,7 +115863,8 @@ _ACEOF
37657 cat confdefs.h >>conftest.$ac_ext
37658 cat >>conftest.$ac_ext <<_ACEOF
37659 /* end confdefs.h. */
37660 -$ac_includes_default
37661 +/* no standard headers */
37666 @@ -115654,7 +115932,8 @@ _ACEOF
37667 cat confdefs.h >>conftest.$ac_ext
37668 cat >>conftest.$ac_ext <<_ACEOF
37669 /* end confdefs.h. */
37670 -$ac_includes_default
37671 +/* no standard headers */
37673 long longval () { return (long) (sizeof (int)); }
37674 unsigned long ulongval () { return (long) (sizeof (int)); }
37676 @@ -115738,7 +116017,8 @@ _ACEOF
37677 cat confdefs.h >>conftest.$ac_ext
37678 cat >>conftest.$ac_ext <<_ACEOF
37679 /* end confdefs.h. */
37680 -$ac_includes_default
37681 +/* no standard headers */
37686 @@ -115802,7 +116082,8 @@ _ACEOF
37687 cat confdefs.h >>conftest.$ac_ext
37688 cat >>conftest.$ac_ext <<_ACEOF
37689 /* end confdefs.h. */
37690 -$ac_includes_default
37691 +/* no standard headers */
37696 @@ -115843,7 +116124,8 @@ _ACEOF
37697 cat confdefs.h >>conftest.$ac_ext
37698 cat >>conftest.$ac_ext <<_ACEOF
37699 /* end confdefs.h. */
37700 -$ac_includes_default
37701 +/* no standard headers */
37706 @@ -115900,7 +116182,8 @@ _ACEOF
37707 cat confdefs.h >>conftest.$ac_ext
37708 cat >>conftest.$ac_ext <<_ACEOF
37709 /* end confdefs.h. */
37710 -$ac_includes_default
37711 +/* no standard headers */
37716 @@ -115941,7 +116224,8 @@ _ACEOF
37717 cat confdefs.h >>conftest.$ac_ext
37718 cat >>conftest.$ac_ext <<_ACEOF
37719 /* end confdefs.h. */
37720 -$ac_includes_default
37721 +/* no standard headers */
37726 @@ -116006,7 +116290,8 @@ _ACEOF
37727 cat confdefs.h >>conftest.$ac_ext
37728 cat >>conftest.$ac_ext <<_ACEOF
37729 /* end confdefs.h. */
37730 -$ac_includes_default
37731 +/* no standard headers */
37736 @@ -116074,7 +116359,8 @@ _ACEOF
37737 cat confdefs.h >>conftest.$ac_ext
37738 cat >>conftest.$ac_ext <<_ACEOF
37739 /* end confdefs.h. */
37740 -$ac_includes_default
37741 +/* no standard headers */
37743 long longval () { return (long) (sizeof (short)); }
37744 unsigned long ulongval () { return (long) (sizeof (short)); }
37746 @@ -116158,7 +116444,8 @@ _ACEOF
37747 cat confdefs.h >>conftest.$ac_ext
37748 cat >>conftest.$ac_ext <<_ACEOF
37749 /* end confdefs.h. */
37750 -$ac_includes_default
37751 +/* no standard headers */
37756 @@ -116222,7 +116509,8 @@ _ACEOF
37757 cat confdefs.h >>conftest.$ac_ext
37758 cat >>conftest.$ac_ext <<_ACEOF
37759 /* end confdefs.h. */
37760 -$ac_includes_default
37761 +/* no standard headers */
37766 @@ -116263,7 +116551,8 @@ _ACEOF
37767 cat confdefs.h >>conftest.$ac_ext
37768 cat >>conftest.$ac_ext <<_ACEOF
37769 /* end confdefs.h. */
37770 -$ac_includes_default
37771 +/* no standard headers */
37776 @@ -116320,7 +116609,8 @@ _ACEOF
37777 cat confdefs.h >>conftest.$ac_ext
37778 cat >>conftest.$ac_ext <<_ACEOF
37779 /* end confdefs.h. */
37780 -$ac_includes_default
37781 +/* no standard headers */
37786 @@ -116361,7 +116651,8 @@ _ACEOF
37787 cat confdefs.h >>conftest.$ac_ext
37788 cat >>conftest.$ac_ext <<_ACEOF
37789 /* end confdefs.h. */
37790 -$ac_includes_default
37791 +/* no standard headers */
37796 @@ -116426,7 +116717,8 @@ _ACEOF
37797 cat confdefs.h >>conftest.$ac_ext
37798 cat >>conftest.$ac_ext <<_ACEOF
37799 /* end confdefs.h. */
37800 -$ac_includes_default
37801 +/* no standard headers */
37806 @@ -116494,7 +116786,8 @@ _ACEOF
37807 cat confdefs.h >>conftest.$ac_ext
37808 cat >>conftest.$ac_ext <<_ACEOF
37809 /* end confdefs.h. */
37810 -$ac_includes_default
37811 +/* no standard headers */
37813 long longval () { return (long) (sizeof (char)); }
37814 unsigned long ulongval () { return (long) (sizeof (char)); }
37816 @@ -118004,6 +118297,24 @@ ABI_TWEAKS_SRCDIR=config/${abi_tweaks_di
37820 +# For SymbianOS, we use a highly cut-down libsupc++. This lets us
37821 +# conditionalise libsupc++'s Makefile.am to include only the necessary sources.
37823 + *arm*-symbianelf)
37824 + LIBSUPCXX_PRONLY=yes;;
37829 +if test x$LIBSUPCXX_PRONLY = xyes; then
37830 + LIBSUPCXX_PRONLY_TRUE=
37831 + LIBSUPCXX_PRONLY_FALSE='#'
37833 + LIBSUPCXX_PRONLY_TRUE='#'
37834 + LIBSUPCXX_PRONLY_FALSE=
37838 # Determine cross-compile flags and AM_CONDITIONALs.
37839 #AC_SUBST(GLIBCXX_IS_NATIVE)
37840 #AM_CONDITIONAL(CANADIAN, test $CANADIAN = yes)
37841 @@ -118582,6 +118893,13 @@ echo "$as_me: error: conditional \"GLIBC
37842 Usually this means the macro was only invoked conditionally." >&2;}
37843 { (exit 1); exit 1; }; }
37845 +if test -z "${LIBSUPCXX_PRONLY_TRUE}" && test -z "${LIBSUPCXX_PRONLY_FALSE}"; then
37846 + { { echo "$as_me:$LINENO: error: conditional \"LIBSUPCXX_PRONLY\" was never defined.
37847 +Usually this means the macro was only invoked conditionally." >&5
37848 +echo "$as_me: error: conditional \"LIBSUPCXX_PRONLY\" was never defined.
37849 +Usually this means the macro was only invoked conditionally." >&2;}
37850 + { (exit 1); exit 1; }; }
37853 : ${CONFIG_STATUS=./config.status}
37854 ac_clean_files_save=$ac_clean_files
37855 @@ -119667,6 +119985,8 @@ s,@CPU_DEFINES_SRCDIR@,$CPU_DEFINES_SRCD
37856 s,@ABI_TWEAKS_SRCDIR@,$ABI_TWEAKS_SRCDIR,;t t
37857 s,@OS_INC_SRCDIR@,$OS_INC_SRCDIR,;t t
37858 s,@ERROR_CONSTANTS_SRCDIR@,$ERROR_CONSTANTS_SRCDIR,;t t
37859 +s,@LIBSUPCXX_PRONLY_TRUE@,$LIBSUPCXX_PRONLY_TRUE,;t t
37860 +s,@LIBSUPCXX_PRONLY_FALSE@,$LIBSUPCXX_PRONLY_FALSE,;t t
37861 s,@glibcxx_prefixdir@,$glibcxx_prefixdir,;t t
37862 s,@gxx_include_dir@,$gxx_include_dir,;t t
37863 s,@glibcxx_toolexecdir@,$glibcxx_toolexecdir,;t t
37864 --- a/libstdc++-v3/configure.ac
37865 +++ b/libstdc++-v3/configure.ac
37866 @@ -329,6 +329,15 @@ AC_SUBST(OS_INC_SRCDIR)
37867 AC_SUBST(ERROR_CONSTANTS_SRCDIR)
37870 +# For SymbianOS, we use a highly cut-down libsupc++. This lets us
37871 +# conditionalise libsupc++'s Makefile.am to include only the necessary sources.
37873 + *arm*-symbianelf)
37874 + LIBSUPCXX_PRONLY=yes;;
37877 +AM_CONDITIONAL(LIBSUPCXX_PRONLY, test x$LIBSUPCXX_PRONLY = xyes)
37879 # Determine cross-compile flags and AM_CONDITIONALs.
37880 #AC_SUBST(GLIBCXX_IS_NATIVE)
37881 #AM_CONDITIONAL(CANADIAN, test $CANADIAN = yes)
37882 --- a/libstdc++-v3/doc/Makefile.in
37883 +++ b/libstdc++-v3/doc/Makefile.in
37884 @@ -161,6 +161,8 @@ LIBICONV = @LIBICONV@
37885 LIBOBJS = @LIBOBJS@
37887 LIBSUPCXX_PICFLAGS = @LIBSUPCXX_PICFLAGS@
37888 +LIBSUPCXX_PRONLY_FALSE = @LIBSUPCXX_PRONLY_FALSE@
37889 +LIBSUPCXX_PRONLY_TRUE = @LIBSUPCXX_PRONLY_TRUE@
37890 LIBTOOL = @LIBTOOL@
37893 --- a/libstdc++-v3/include/Makefile.am
37894 +++ b/libstdc++-v3/include/Makefile.am
37895 @@ -1125,8 +1125,14 @@ ${pch3_output}: ${pch3_source} ${pch2_ou
37897 install-data-local: install-headers
37899 +if LIBSUPCXX_PRONLY
37900 +# Don't install any headers if we're only putting eh_personality in
37901 +# libsupc++ (e.g. on SymbianOS)
37902 +install-data-local:
37904 install-data-local: install-freestanding-headers
37908 # This is a subset of the full install-headers rule. We only need <cstddef>,
37909 # <limits>, <cstdlib>, <cstdarg>, <new>, <typeinfo>, <exception>, and any
37910 --- a/libstdc++-v3/include/Makefile.in
37911 +++ b/libstdc++-v3/include/Makefile.in
37912 @@ -161,6 +161,8 @@ LIBICONV = @LIBICONV@
37913 LIBOBJS = @LIBOBJS@
37915 LIBSUPCXX_PICFLAGS = @LIBSUPCXX_PICFLAGS@
37916 +LIBSUPCXX_PRONLY_FALSE = @LIBSUPCXX_PRONLY_FALSE@
37917 +LIBSUPCXX_PRONLY_TRUE = @LIBSUPCXX_PRONLY_TRUE@
37918 LIBTOOL = @LIBTOOL@
37921 @@ -1527,7 +1529,10 @@ ${pch3_output}: ${pch3_source} ${pch2_ou
37922 # the rest are taken from the original source tree.
37924 @GLIBCXX_HOSTED_TRUE@install-data-local: install-headers
37925 -@GLIBCXX_HOSTED_FALSE@install-data-local: install-freestanding-headers
37926 +# Don't install any headers if we're only putting eh_personality in
37927 +# libsupc++ (e.g. on SymbianOS)
37928 +@GLIBCXX_HOSTED_FALSE@@LIBSUPCXX_PRONLY_TRUE@install-data-local:
37929 +@GLIBCXX_HOSTED_FALSE@@LIBSUPCXX_PRONLY_FALSE@install-data-local: install-freestanding-headers
37931 # This is a subset of the full install-headers rule. We only need <cstddef>,
37932 # <limits>, <cstdlib>, <cstdarg>, <new>, <typeinfo>, <exception>, and any
37933 --- a/libstdc++-v3/include/c_global/cwchar
37934 +++ b/libstdc++-v3/include/c_global/cwchar
37935 @@ -156,14 +156,18 @@ _GLIBCXX_BEGIN_NAMESPACE(std)
37939 +#ifndef _GLIBCXX_HAVE_BROKEN_VSWPRINTF
37945 #if _GLIBCXX_HAVE_VFWSCANF
37948 +#ifndef _GLIBCXX_HAVE_BROKEN_VSWPRINTF
37951 #if _GLIBCXX_HAVE_VSWSCANF
37954 --- a/libstdc++-v3/libsupc++/Makefile.am
37955 +++ b/libstdc++-v3/libsupc++/Makefile.am
37956 @@ -30,6 +30,11 @@ toolexeclib_LTLIBRARIES = libsupc++.la
37957 # 2) integrated libsupc++convenience.la that is to be a part of libstdc++.a
37958 noinst_LTLIBRARIES = libsupc++convenience.la
37960 +if LIBSUPCXX_PRONLY
37962 + eh_personality.cc
37967 exception new typeinfo cxxabi.h cxxabi-forced.h exception_defines.h \
37968 @@ -84,6 +89,7 @@ sources = \
37970 vmi_class_type_info.cc \
37974 libsupc___la_SOURCES = $(sources) $(c_sources)
37975 libsupc__convenience_la_SOURCES = $(sources) $(c_sources)
37976 --- a/libstdc++-v3/libsupc++/Makefile.in
37977 +++ b/libstdc++-v3/libsupc++/Makefile.in
37978 @@ -38,7 +38,7 @@ POST_UNINSTALL = :
37979 build_triplet = @build@
37980 host_triplet = @host@
37981 target_triplet = @target@
37982 -DIST_COMMON = $(glibcxxinstall_HEADERS) $(srcdir)/Makefile.am \
37983 +DIST_COMMON = $(am__glibcxxinstall_HEADERS_DIST) $(srcdir)/Makefile.am \
37984 $(srcdir)/Makefile.in $(top_srcdir)/fragment.am
37986 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
37987 @@ -87,19 +87,29 @@ am__libsupc___la_SOURCES_DIST = array_ty
37988 pmem_type_info.cc pointer_type_info.cc pure.cc \
37989 si_class_type_info.cc tinfo.cc tinfo2.cc vec.cc \
37990 vmi_class_type_info.cc vterminate.cc cp-demangle.c
37991 -am__objects_1 = array_type_info.lo atexit_arm.lo bad_cast.lo \
37992 - bad_typeid.lo class_type_info.lo del_op.lo del_opnt.lo \
37993 - del_opv.lo del_opvnt.lo dyncast.lo eh_alloc.lo eh_arm.lo \
37994 - eh_aux_runtime.lo eh_call.lo eh_catch.lo eh_exception.lo \
37995 - eh_globals.lo eh_personality.lo eh_ptr.lo eh_term_handler.lo \
37996 - eh_terminate.lo eh_throw.lo eh_type.lo eh_unex_handler.lo \
37997 - enum_type_info.lo function_type_info.lo \
37998 - fundamental_type_info.lo guard.lo new_handler.lo new_op.lo \
37999 - new_opnt.lo new_opv.lo new_opvnt.lo pbase_type_info.lo \
38000 - pmem_type_info.lo pointer_type_info.lo pure.lo \
38001 - si_class_type_info.lo tinfo.lo tinfo2.lo vec.lo \
38002 - vmi_class_type_info.lo vterminate.lo
38003 -@GLIBCXX_HOSTED_TRUE@am__objects_2 = cp-demangle.lo
38004 +@LIBSUPCXX_PRONLY_FALSE@am__objects_1 = array_type_info.lo \
38005 +@LIBSUPCXX_PRONLY_FALSE@ atexit_arm.lo bad_cast.lo \
38006 +@LIBSUPCXX_PRONLY_FALSE@ bad_typeid.lo class_type_info.lo \
38007 +@LIBSUPCXX_PRONLY_FALSE@ del_op.lo del_opnt.lo del_opv.lo \
38008 +@LIBSUPCXX_PRONLY_FALSE@ del_opvnt.lo dyncast.lo eh_alloc.lo \
38009 +@LIBSUPCXX_PRONLY_FALSE@ eh_arm.lo eh_aux_runtime.lo eh_call.lo \
38010 +@LIBSUPCXX_PRONLY_FALSE@ eh_catch.lo eh_exception.lo \
38011 +@LIBSUPCXX_PRONLY_FALSE@ eh_globals.lo eh_personality.lo \
38012 +@LIBSUPCXX_PRONLY_FALSE@ eh_ptr.lo eh_term_handler.lo \
38013 +@LIBSUPCXX_PRONLY_FALSE@ eh_terminate.lo eh_throw.lo eh_type.lo \
38014 +@LIBSUPCXX_PRONLY_FALSE@ eh_unex_handler.lo enum_type_info.lo \
38015 +@LIBSUPCXX_PRONLY_FALSE@ function_type_info.lo \
38016 +@LIBSUPCXX_PRONLY_FALSE@ fundamental_type_info.lo guard.lo \
38017 +@LIBSUPCXX_PRONLY_FALSE@ new_handler.lo new_op.lo new_opnt.lo \
38018 +@LIBSUPCXX_PRONLY_FALSE@ new_opv.lo new_opvnt.lo \
38019 +@LIBSUPCXX_PRONLY_FALSE@ pbase_type_info.lo pmem_type_info.lo \
38020 +@LIBSUPCXX_PRONLY_FALSE@ pointer_type_info.lo pure.lo \
38021 +@LIBSUPCXX_PRONLY_FALSE@ si_class_type_info.lo tinfo.lo \
38022 +@LIBSUPCXX_PRONLY_FALSE@ tinfo2.lo vec.lo \
38023 +@LIBSUPCXX_PRONLY_FALSE@ vmi_class_type_info.lo vterminate.lo
38024 +@LIBSUPCXX_PRONLY_TRUE@am__objects_1 = eh_personality.lo
38025 +@GLIBCXX_HOSTED_TRUE@@LIBSUPCXX_PRONLY_FALSE@am__objects_2 = \
38026 +@GLIBCXX_HOSTED_TRUE@@LIBSUPCXX_PRONLY_FALSE@ cp-demangle.lo
38027 am_libsupc___la_OBJECTS = $(am__objects_1) $(am__objects_2)
38028 libsupc___la_OBJECTS = $(am_libsupc___la_OBJECTS)
38029 libsupc__convenience_la_LIBADD =
38030 @@ -132,6 +142,9 @@ CXXLD = $(CXX)
38031 SOURCES = $(libsupc___la_SOURCES) $(libsupc__convenience_la_SOURCES)
38032 DIST_SOURCES = $(am__libsupc___la_SOURCES_DIST) \
38033 $(am__libsupc__convenience_la_SOURCES_DIST)
38034 +am__glibcxxinstall_HEADERS_DIST = exception new typeinfo cxxabi.h \
38035 + cxxabi-forced.h exception_defines.h initializer_list \
38037 glibcxxinstallHEADERS_INSTALL = $(INSTALL_HEADER)
38038 HEADERS = $(glibcxxinstall_HEADERS)
38040 @@ -231,6 +244,8 @@ LIBICONV = @LIBICONV@
38041 LIBOBJS = @LIBOBJS@
38043 LIBSUPCXX_PICFLAGS = @LIBSUPCXX_PICFLAGS@
38044 +LIBSUPCXX_PRONLY_FALSE = @LIBSUPCXX_PRONLY_FALSE@
38045 +LIBSUPCXX_PRONLY_TRUE = @LIBSUPCXX_PRONLY_TRUE@
38046 LIBTOOL = @LIBTOOL@
38049 @@ -365,57 +380,60 @@ AM_CPPFLAGS = $(GLIBCXX_INCLUDES)
38050 toolexeclib_LTLIBRARIES = libsupc++.la
38051 # 2) integrated libsupc++convenience.la that is to be a part of libstdc++.a
38052 noinst_LTLIBRARIES = libsupc++convenience.la
38054 - exception new typeinfo cxxabi.h cxxabi-forced.h exception_defines.h \
38055 - initializer_list exception_ptr.h
38057 -@GLIBCXX_HOSTED_TRUE@c_sources = \
38058 -@GLIBCXX_HOSTED_TRUE@ cp-demangle.c
38061 - array_type_info.cc \
38065 - class_type_info.cc \
38073 - eh_aux_runtime.cc \
38076 - eh_exception.cc \
38078 - eh_personality.cc \
38080 - eh_term_handler.cc \
38081 - eh_terminate.cc \
38084 - eh_unex_handler.cc \
38085 - enum_type_info.cc \
38086 - function_type_info.cc \
38087 - fundamental_type_info.cc \
38094 - pbase_type_info.cc \
38095 - pmem_type_info.cc \
38096 - pointer_type_info.cc \
38098 - si_class_type_info.cc \
38102 - vmi_class_type_info.cc \
38104 +@LIBSUPCXX_PRONLY_FALSE@sources = \
38105 +@LIBSUPCXX_PRONLY_FALSE@ array_type_info.cc \
38106 +@LIBSUPCXX_PRONLY_FALSE@ atexit_arm.cc \
38107 +@LIBSUPCXX_PRONLY_FALSE@ bad_cast.cc \
38108 +@LIBSUPCXX_PRONLY_FALSE@ bad_typeid.cc \
38109 +@LIBSUPCXX_PRONLY_FALSE@ class_type_info.cc \
38110 +@LIBSUPCXX_PRONLY_FALSE@ del_op.cc \
38111 +@LIBSUPCXX_PRONLY_FALSE@ del_opnt.cc \
38112 +@LIBSUPCXX_PRONLY_FALSE@ del_opv.cc \
38113 +@LIBSUPCXX_PRONLY_FALSE@ del_opvnt.cc \
38114 +@LIBSUPCXX_PRONLY_FALSE@ dyncast.cc \
38115 +@LIBSUPCXX_PRONLY_FALSE@ eh_alloc.cc \
38116 +@LIBSUPCXX_PRONLY_FALSE@ eh_arm.cc \
38117 +@LIBSUPCXX_PRONLY_FALSE@ eh_aux_runtime.cc \
38118 +@LIBSUPCXX_PRONLY_FALSE@ eh_call.cc \
38119 +@LIBSUPCXX_PRONLY_FALSE@ eh_catch.cc \
38120 +@LIBSUPCXX_PRONLY_FALSE@ eh_exception.cc \
38121 +@LIBSUPCXX_PRONLY_FALSE@ eh_globals.cc \
38122 +@LIBSUPCXX_PRONLY_FALSE@ eh_personality.cc \
38123 +@LIBSUPCXX_PRONLY_FALSE@ eh_ptr.cc \
38124 +@LIBSUPCXX_PRONLY_FALSE@ eh_term_handler.cc \
38125 +@LIBSUPCXX_PRONLY_FALSE@ eh_terminate.cc \
38126 +@LIBSUPCXX_PRONLY_FALSE@ eh_throw.cc \
38127 +@LIBSUPCXX_PRONLY_FALSE@ eh_type.cc \
38128 +@LIBSUPCXX_PRONLY_FALSE@ eh_unex_handler.cc \
38129 +@LIBSUPCXX_PRONLY_FALSE@ enum_type_info.cc \
38130 +@LIBSUPCXX_PRONLY_FALSE@ function_type_info.cc \
38131 +@LIBSUPCXX_PRONLY_FALSE@ fundamental_type_info.cc \
38132 +@LIBSUPCXX_PRONLY_FALSE@ guard.cc \
38133 +@LIBSUPCXX_PRONLY_FALSE@ new_handler.cc \
38134 +@LIBSUPCXX_PRONLY_FALSE@ new_op.cc \
38135 +@LIBSUPCXX_PRONLY_FALSE@ new_opnt.cc \
38136 +@LIBSUPCXX_PRONLY_FALSE@ new_opv.cc \
38137 +@LIBSUPCXX_PRONLY_FALSE@ new_opvnt.cc \
38138 +@LIBSUPCXX_PRONLY_FALSE@ pbase_type_info.cc \
38139 +@LIBSUPCXX_PRONLY_FALSE@ pmem_type_info.cc \
38140 +@LIBSUPCXX_PRONLY_FALSE@ pointer_type_info.cc \
38141 +@LIBSUPCXX_PRONLY_FALSE@ pure.cc \
38142 +@LIBSUPCXX_PRONLY_FALSE@ si_class_type_info.cc \
38143 +@LIBSUPCXX_PRONLY_FALSE@ tinfo.cc \
38144 +@LIBSUPCXX_PRONLY_FALSE@ tinfo2.cc \
38145 +@LIBSUPCXX_PRONLY_FALSE@ vec.cc \
38146 +@LIBSUPCXX_PRONLY_FALSE@ vmi_class_type_info.cc \
38147 +@LIBSUPCXX_PRONLY_FALSE@ vterminate.cc
38149 +@LIBSUPCXX_PRONLY_TRUE@sources = \
38150 +@LIBSUPCXX_PRONLY_TRUE@ eh_personality.cc
38152 +@LIBSUPCXX_PRONLY_FALSE@headers = \
38153 +@LIBSUPCXX_PRONLY_FALSE@ exception new typeinfo cxxabi.h cxxabi-forced.h exception_defines.h \
38154 +@LIBSUPCXX_PRONLY_FALSE@ initializer_list exception_ptr.h
38156 +@GLIBCXX_HOSTED_TRUE@@LIBSUPCXX_PRONLY_FALSE@c_sources = \
38157 +@GLIBCXX_HOSTED_TRUE@@LIBSUPCXX_PRONLY_FALSE@ cp-demangle.c
38159 libsupc___la_SOURCES = $(sources) $(c_sources)
38160 libsupc__convenience_la_SOURCES = $(sources) $(c_sources)
38161 --- a/libstdc++-v3/libsupc++/eh_arm.cc
38162 +++ b/libstdc++-v3/libsupc++/eh_arm.cc
38163 @@ -38,7 +38,7 @@ using namespace __cxxabiv1;
38164 extern "C" __cxa_type_match_result
38165 __cxa_type_match(_Unwind_Exception* ue_header,
38166 const std::type_info* catch_type,
38167 - bool is_reference __attribute__((__unused__)),
38168 + bool is_reference,
38169 void** thrown_ptr_p)
38171 bool forced_unwind = __is_gxx_forced_unwind_class(ue_header->exception_class);
38172 @@ -68,11 +68,11 @@ __cxa_type_match(_Unwind_Exception* ue_h
38173 if (throw_type->__is_pointer_p())
38174 thrown_ptr = *(void**) thrown_ptr;
38176 - if (catch_type->__do_catch(throw_type, &thrown_ptr, 1))
38177 + if (catch_type->__do_catch (throw_type, &thrown_ptr, 1 + is_reference * 2))
38179 *thrown_ptr_p = thrown_ptr;
38181 - if (typeid(*catch_type) == typeid (typeid(void*)))
38182 + if (typeid (*catch_type) == typeid (typeid(void*)))
38184 const __pointer_type_info *catch_pointer_type =
38185 static_cast<const __pointer_type_info *> (catch_type);
38186 --- a/libstdc++-v3/libsupc++/eh_personality.cc
38187 +++ b/libstdc++-v3/libsupc++/eh_personality.cc
38188 @@ -89,20 +89,22 @@ parse_lsda_header (_Unwind_Context *cont
38189 // Return an element from a type table.
38191 static const std::type_info*
38192 -get_ttype_entry(lsda_header_info* info, _uleb128_t i)
38193 +get_ttype_entry(lsda_header_info* info, _uleb128_t i, bool &is_ref)
38197 ptr = (_Unwind_Ptr) (info->TType - (i * 4));
38198 ptr = _Unwind_decode_target2(ptr);
38200 - return reinterpret_cast<const std::type_info *>(ptr);
38201 + is_ref = ptr & 1;
38203 + return reinterpret_cast<const std::type_info *>(ptr & ~1);
38206 // The ABI provides a routine for matching exception object types.
38207 typedef _Unwind_Control_Block _throw_typet;
38208 -#define get_adjusted_ptr(catch_type, throw_type, thrown_ptr_p) \
38209 - (__cxa_type_match (throw_type, catch_type, false, thrown_ptr_p) \
38210 +#define get_adjusted_ptr(catch_type, throw_type, is_ref, thrown_ptr_p) \
38211 + (__cxa_type_match (throw_type, catch_type, is_ref, thrown_ptr_p) \
38214 // Return true if THROW_TYPE matches one if the filter types.
38215 @@ -118,6 +120,7 @@ check_exception_spec(lsda_header_info* i
38217 const std::type_info* catch_type;
38223 @@ -129,13 +132,14 @@ check_exception_spec(lsda_header_info* i
38224 tmp = _Unwind_decode_target2((_Unwind_Word) e);
38226 // Match a ttype entry.
38227 - catch_type = reinterpret_cast<const std::type_info*>(tmp);
38228 + is_ref = tmp & 1;
38229 + catch_type = reinterpret_cast<const std::type_info*>(tmp & ~1);
38231 // ??? There is currently no way to ask the RTTI code about the
38232 // relationship between two types without reference to a specific
38233 // object. There should be; then we wouldn't need to mess with
38234 // thrown_ptr here.
38235 - if (get_adjusted_ptr(catch_type, throw_type, &thrown_ptr))
38236 + if (get_adjusted_ptr(catch_type, throw_type, is_ref, &thrown_ptr))
38239 // Advance to the next entry.
38240 @@ -207,7 +211,7 @@ typedef const std::type_info _throw_type
38241 // Return an element from a type table.
38243 static const std::type_info *
38244 -get_ttype_entry (lsda_header_info *info, _uleb128_t i)
38245 +get_ttype_entry (lsda_header_info *info, _uleb128_t i, bool &is_ref)
38249 @@ -215,7 +219,9 @@ get_ttype_entry (lsda_header_info *info,
38250 read_encoded_value_with_base (info->ttype_encoding, info->ttype_base,
38251 info->TType - i, &ptr);
38253 - return reinterpret_cast<const std::type_info *>(ptr);
38254 + is_ref = ptr & 1;
38256 + return reinterpret_cast<const std::type_info *>(ptr & ~1);
38259 // Given the thrown type THROW_TYPE, pointer to a variable containing a
38260 @@ -226,6 +232,7 @@ get_ttype_entry (lsda_header_info *info,
38262 get_adjusted_ptr (const std::type_info *catch_type,
38263 const std::type_info *throw_type,
38265 void **thrown_ptr_p)
38267 void *thrown_ptr = *thrown_ptr_p;
38268 @@ -237,7 +244,7 @@ get_adjusted_ptr (const std::type_info *
38269 if (throw_type->__is_pointer_p ())
38270 thrown_ptr = *(void **) thrown_ptr;
38272 - if (catch_type->__do_catch (throw_type, &thrown_ptr, 1))
38273 + if (catch_type->__do_catch (throw_type, &thrown_ptr, 1 + is_ref * 2))
38275 *thrown_ptr_p = thrown_ptr;
38277 @@ -267,13 +274,15 @@ check_exception_spec(lsda_header_info* i
38280 // Match a ttype entry.
38281 - catch_type = get_ttype_entry (info, tmp);
38284 + catch_type = get_ttype_entry (info, tmp, is_ref);
38286 // ??? There is currently no way to ask the RTTI code about the
38287 // relationship between two types without reference to a specific
38288 // object. There should be; then we wouldn't need to mess with
38289 // thrown_ptr here.
38290 - if (get_adjusted_ptr (catch_type, throw_type, &thrown_ptr))
38291 + if (get_adjusted_ptr (catch_type, throw_type, is_ref, &thrown_ptr))
38295 @@ -582,14 +591,16 @@ PERSONALITY_FUNCTION (int version,
38296 else if (ar_filter > 0)
38298 // Positive filter values are handlers.
38299 - catch_type = get_ttype_entry (&info, ar_filter);
38302 + catch_type = get_ttype_entry (&info, ar_filter, is_ref);
38304 // Null catch type is a catch-all handler; we can catch foreign
38305 // exceptions with this. Otherwise we must match types.
38308 && get_adjusted_ptr (catch_type, throw_type,
38310 + is_ref, &thrown_ptr)))
38312 saw_handler = true;
38314 --- a/libstdc++-v3/po/Makefile.in
38315 +++ b/libstdc++-v3/po/Makefile.in
38316 @@ -161,6 +161,8 @@ LIBICONV = @LIBICONV@
38317 LIBOBJS = @LIBOBJS@
38319 LIBSUPCXX_PICFLAGS = @LIBSUPCXX_PICFLAGS@
38320 +LIBSUPCXX_PRONLY_FALSE = @LIBSUPCXX_PRONLY_FALSE@
38321 +LIBSUPCXX_PRONLY_TRUE = @LIBSUPCXX_PRONLY_TRUE@
38322 LIBTOOL = @LIBTOOL@
38325 --- a/libstdc++-v3/src/Makefile.in
38326 +++ b/libstdc++-v3/src/Makefile.in
38327 @@ -221,6 +221,8 @@ LIBICONV = @LIBICONV@
38328 LIBOBJS = @LIBOBJS@
38330 LIBSUPCXX_PICFLAGS = @LIBSUPCXX_PICFLAGS@
38331 +LIBSUPCXX_PRONLY_FALSE = @LIBSUPCXX_PRONLY_FALSE@
38332 +LIBSUPCXX_PRONLY_TRUE = @LIBSUPCXX_PRONLY_TRUE@
38333 LIBTOOL = @LIBTOOL@
38336 --- a/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stod.cc
38337 +++ b/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stod.cc
38339 // { dg-options "-std=gnu++0x" }
38340 +// { dg-require-string-conversions "" }
38341 // 2008-06-15 Paolo Carlini <paolo.carlini@oracle.com>
38343 // Copyright (C) 2008, 2009 Free Software Foundation, Inc.
38344 --- a/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stof.cc
38345 +++ b/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stof.cc
38347 // { dg-options "-std=gnu++0x" }
38348 +// { dg-require-string-conversions "" }
38349 // 2008-06-15 Paolo Carlini <paolo.carlini@oracle.com>
38351 // Copyright (C) 2008, 2009 Free Software Foundation, Inc.
38352 --- a/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stoi.cc
38353 +++ b/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stoi.cc
38355 // { dg-options "-std=gnu++0x" }
38356 +// { dg-require-string-conversions "" }
38357 // 2008-06-15 Paolo Carlini <paolo.carlini@oracle.com>
38359 // Copyright (C) 2008, 2009 Free Software Foundation, Inc.
38360 --- a/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stol.cc
38361 +++ b/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stol.cc
38363 // { dg-options "-std=gnu++0x" }
38364 +// { dg-require-string-conversions "" }
38365 // 2008-06-15 Paolo Carlini <paolo.carlini@oracle.com>
38367 // Copyright (C) 2008, 2009 Free Software Foundation, Inc.
38368 --- a/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stold.cc
38369 +++ b/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stold.cc
38371 // { dg-options "-std=gnu++0x" }
38372 +// { dg-require-string-conversions "" }
38373 // 2008-06-15 Paolo Carlini <paolo.carlini@oracle.com>
38375 // Copyright (C) 2008, 2009 Free Software Foundation, Inc.
38376 --- a/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stoll.cc
38377 +++ b/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stoll.cc
38379 // { dg-options "-std=gnu++0x" }
38380 +// { dg-require-string-conversions "" }
38381 // 2008-06-15 Paolo Carlini <paolo.carlini@oracle.com>
38383 // Copyright (C) 2008, 2009 Free Software Foundation, Inc.
38384 --- a/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stoul.cc
38385 +++ b/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stoul.cc
38387 // { dg-options "-std=gnu++0x" }
38388 +// { dg-require-string-conversions "" }
38389 // 2008-06-15 Paolo Carlini <paolo.carlini@oracle.com>
38391 // Copyright (C) 2008, 2009 Free Software Foundation, Inc.
38392 --- a/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stoull.cc
38393 +++ b/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/stoull.cc
38395 // { dg-options "-std=gnu++0x" }
38396 +// { dg-require-string-conversions "" }
38397 // 2008-06-15 Paolo Carlini <paolo.carlini@oracle.com>
38399 // Copyright (C) 2008, 2009 Free Software Foundation, Inc.
38400 --- a/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/to_wstring.cc
38401 +++ b/libstdc++-v3/testsuite/21_strings/basic_string/numeric_conversions/wchar_t/to_wstring.cc
38403 // { dg-options "-std=gnu++0x" }
38404 +// { dg-require-string-conversions "" }
38405 // 2008-06-15 Paolo Carlini <paolo.carlini@oracle.com>
38407 // Copyright (C) 2008, 2009 Free Software Foundation, Inc.
38408 --- a/libstdc++-v3/testsuite/21_strings/headers/cwchar/functions_std.cc
38409 +++ b/libstdc++-v3/testsuite/21_strings/headers/cwchar/functions_std.cc
38411 // { dg-do compile }
38412 // { dg-require-c-std "" }
38413 +// { dg-require-swprintf "" }
38415 // Copyright (C) 2007, 2009 Free Software Foundation, Inc.
38417 --- a/libstdc++-v3/testsuite/27_io/basic_filebuf/seekoff/char/1-io.cc
38418 +++ b/libstdc++-v3/testsuite/27_io/basic_filebuf/seekoff/char/1-io.cc
38420 // 27.8.1.4 Overridden virtual functions
38422 // { dg-require-fileio "" }
38423 +// { dg-require-binary-io "" }
38426 #include <testsuite_hooks.h>
38427 --- a/libstdc++-v3/testsuite/27_io/basic_filebuf/seekoff/char/2-io.cc
38428 +++ b/libstdc++-v3/testsuite/27_io/basic_filebuf/seekoff/char/2-io.cc
38430 // 27.8.1.4 Overridden virtual functions
38432 // { dg-require-fileio "" }
38433 +// { dg-require-binary-io "" }
38436 #include <testsuite_hooks.h>
38437 --- a/libstdc++-v3/testsuite/27_io/basic_filebuf/sgetn/char/1-in.cc
38438 +++ b/libstdc++-v3/testsuite/27_io/basic_filebuf/sgetn/char/1-in.cc
38440 // 27.8.1.4 Overridden virtual functions
38442 // { dg-require-fileio "" }
38443 +// { dg-require-binary-io "" }
38446 #include <testsuite_hooks.h>
38447 --- a/libstdc++-v3/testsuite/27_io/basic_filebuf/sgetn/char/1-io.cc
38448 +++ b/libstdc++-v3/testsuite/27_io/basic_filebuf/sgetn/char/1-io.cc
38450 // 27.8.1.4 Overridden virtual functions
38452 // { dg-require-fileio "" }
38453 +// { dg-require-binary-io "" }
38456 #include <testsuite_hooks.h>
38457 --- a/libstdc++-v3/testsuite/27_io/basic_filebuf/sgetn/char/2-in.cc
38458 +++ b/libstdc++-v3/testsuite/27_io/basic_filebuf/sgetn/char/2-in.cc
38460 // 27.8.1.4 Overridden virtual functions
38462 // { dg-require-fileio "" }
38463 +// { dg-require-binary-io "" }
38466 #include <testsuite_hooks.h>
38467 --- a/libstdc++-v3/testsuite/27_io/basic_filebuf/sgetn/char/2-io.cc
38468 +++ b/libstdc++-v3/testsuite/27_io/basic_filebuf/sgetn/char/2-io.cc
38470 // 27.8.1.4 Overridden virtual functions
38472 // { dg-require-fileio "" }
38473 +// { dg-require-binary-io "" }
38476 #include <testsuite_hooks.h>
38477 --- a/libstdc++-v3/testsuite/27_io/basic_filebuf/underflow/wchar_t/11603.cc
38478 +++ b/libstdc++-v3/testsuite/27_io/basic_filebuf/underflow/wchar_t/11603.cc
38481 // 27.8.1.4 Overridden virtual functions
38483 +// { dg-require-binary-io "" }
38487 #include <testsuite_hooks.h>
38488 --- a/libstdc++-v3/testsuite/27_io/basic_istream/readsome/char/6746-2.cc
38489 +++ b/libstdc++-v3/testsuite/27_io/basic_istream/readsome/char/6746-2.cc
38491 // @diff@ %-*.tst %-*.txt
38493 // { dg-require-fileio "" }
38494 +// { dg-require-binary-io "" }
38498 --- a/libstdc++-v3/testsuite/27_io/basic_istream/readsome/wchar_t/6746-2.cc
38499 +++ b/libstdc++-v3/testsuite/27_io/basic_istream/readsome/wchar_t/6746-2.cc
38501 // causes "in_avail" to return an incorrect value.
38502 // { dg-do run { xfail arm*-*-elf arm*-*-eabi } }
38504 +// { dg-require-binary-io "" }
38506 // 27.6.1.3 unformatted input functions
38507 // @require@ %-*.tst %-*.txt
38508 // @diff@ %-*.tst %-*.txt
38509 --- a/libstdc++-v3/testsuite/27_io/basic_ostream/inserters_arithmetic/wchar_t/4402.cc
38510 +++ b/libstdc++-v3/testsuite/27_io/basic_ostream/inserters_arithmetic/wchar_t/4402.cc
38512 +// { dg-require-swprintf "" }
38514 // Copyright (C) 2005, 2006, 2007, 2009 Free Software Foundation, Inc.
38516 // This file is part of the GNU ISO C++ Library. This library is free
38517 --- a/libstdc++-v3/testsuite/27_io/basic_ostream/inserters_other/wchar_t/error_code.cc
38518 +++ b/libstdc++-v3/testsuite/27_io/basic_ostream/inserters_other/wchar_t/error_code.cc
38520 // { dg-options "-std=gnu++0x" }
38521 +// { dg-require-swprintf "" }
38523 // Copyright (C) 2007, 2008, 2009 Free Software Foundation
38525 --- a/libstdc++-v3/testsuite/27_io/objects/char/10.cc
38526 +++ b/libstdc++-v3/testsuite/27_io/objects/char/10.cc
38528 // <http://www.gnu.org/licenses/>.
38530 // { dg-require-fileio "" }
38531 +// { dg-require-binary-io "" }
38533 #include <iostream>
38535 --- a/libstdc++-v3/testsuite/Makefile.in
38536 +++ b/libstdc++-v3/testsuite/Makefile.in
38537 @@ -161,6 +161,8 @@ LIBICONV = @LIBICONV@
38538 LIBOBJS = @LIBOBJS@
38540 LIBSUPCXX_PICFLAGS = @LIBSUPCXX_PICFLAGS@
38541 +LIBSUPCXX_PRONLY_FALSE = @LIBSUPCXX_PRONLY_FALSE@
38542 +LIBSUPCXX_PRONLY_TRUE = @LIBSUPCXX_PRONLY_TRUE@
38543 LIBTOOL = @LIBTOOL@
38546 --- a/libstdc++-v3/testsuite/ext/vstring/element_access/char/front_back.cc
38547 +++ b/libstdc++-v3/testsuite/ext/vstring/element_access/char/front_back.cc
38549 // { dg-options "-std=gnu++0x" }
38550 +// { dg-require-string-conversions "" }
38552 // 2007-10-16 Paolo Carlini <pcarlini@suse.de>
38554 --- a/libstdc++-v3/testsuite/ext/vstring/element_access/wchar_t/front_back.cc
38555 +++ b/libstdc++-v3/testsuite/ext/vstring/element_access/wchar_t/front_back.cc
38557 // { dg-options "-std=gnu++0x" }
38558 +// { dg-require-string-conversions "" }
38560 // 2007-10-16 Paolo Carlini <pcarlini@suse.de>
38562 --- a/libstdc++-v3/testsuite/ext/vstring/init-list.cc
38563 +++ b/libstdc++-v3/testsuite/ext/vstring/init-list.cc
38567 // { dg-options "-std=gnu++0x" }
38568 +// { dg-require-string-conversions "" }
38570 #include <ext/vstring.h>
38571 #include <testsuite_hooks.h>
38572 --- a/libstdc++-v3/testsuite/ext/vstring/moveable.cc
38573 +++ b/libstdc++-v3/testsuite/ext/vstring/moveable.cc
38575 // { dg-options "-std=gnu++0x" }
38576 +// { dg-require-string-conversions "" }
38578 // Copyright (C) 2007, 2009 Free Software Foundation, Inc.
38580 --- a/libstdc++-v3/testsuite/ext/vstring/requirements/citerators.cc
38581 +++ b/libstdc++-v3/testsuite/ext/vstring/requirements/citerators.cc
38583 // { dg-options "-std=gnu++0x" }
38584 +// { dg-require-string-conversions "" }
38586 // 2007-10-15 Paolo Carlini <pcarlini@suse.de>
38588 --- a/libstdc++-v3/testsuite/ext/vstring/requirements/explicit_instantiation/char16_t/1.cc
38589 +++ b/libstdc++-v3/testsuite/ext/vstring/requirements/explicit_instantiation/char16_t/1.cc
38591 // { dg-do compile }
38592 // { dg-options "-std=gnu++0x" }
38593 // { dg-require-cstdint "" }
38594 +// { dg-require-string-conversions "" }
38596 // Copyright (C) 2008, 2009 Free Software Foundation, Inc.
38598 --- a/libstdc++-v3/testsuite/ext/vstring/requirements/explicit_instantiation/char32_t/1.cc
38599 +++ b/libstdc++-v3/testsuite/ext/vstring/requirements/explicit_instantiation/char32_t/1.cc
38601 // { dg-do compile }
38602 // { dg-options "-std=gnu++0x" }
38603 // { dg-require-cstdint "" }
38604 +// { dg-require-string-conversions "" }
38606 // Copyright (C) 2008, 2009 Free Software Foundation, Inc.
38608 --- a/libstdc++-v3/testsuite/lib/dg-options.exp
38609 +++ b/libstdc++-v3/testsuite/lib/dg-options.exp
38610 @@ -142,3 +142,21 @@ proc dg-require-string-conversions { arg
38615 +proc dg-require-swprintf { args } {
38616 + if { ![ check_v3_target_swprintf ] } {
38617 + upvar dg-do-what dg-do-what
38618 + set dg-do-what [list [lindex ${dg-do-what} 0] "N" "P"]
38624 +proc dg-require-binary-io { args } {
38625 + if { ![ check_v3_target_binary_io ] } {
38626 + upvar dg-do-what dg-do-what
38627 + set dg-do-what [list [lindex ${dg-do-what} 0] "N" "P"]
38632 --- a/libstdc++-v3/testsuite/lib/libstdc++.exp
38633 +++ b/libstdc++-v3/testsuite/lib/libstdc++.exp
38634 @@ -204,14 +204,23 @@ proc libstdc++_init { testfile } {
38635 # directory, and then add that to the search path.
38636 foreach src [glob "${srcdir}/util/*.h" \
38637 "${srcdir}/util/*.cc" \
38638 - "${srcdir}/util/*/*.hpp" \
38639 + "${srcdir}/util/*.tcc" \
38640 + "${srcdir}/util/*.hpp" \
38641 + "${srcdir}/util/*/*.h" \
38642 "${srcdir}/util/*/*.cc" \
38643 + "${srcdir}/util/*/*.tcc" \
38644 "${srcdir}/util/*/*.hpp" \
38645 + "${srcdir}/util/*/*/*.h" \
38646 "${srcdir}/util/*/*/*.cc" \
38647 + "${srcdir}/util/*/*/*.tcc" \
38648 "${srcdir}/util/*/*/*.hpp" \
38649 + "${srcdir}/util/*/*/*/*.h" \
38650 "${srcdir}/util/*/*/*/*.cc" \
38651 + "${srcdir}/util/*/*/*/*.tcc" \
38652 "${srcdir}/util/*/*/*/*.hpp" \
38653 + "${srcdir}/util/*/*/*/*/*.h" \
38654 "${srcdir}/util/*/*/*/*/*.cc" \
38655 + "${srcdir}/util/*/*/*/*/*.tcc" \
38656 "${srcdir}/util/*/*/*/*/*.hpp" ] {
38657 # Remove everything up to "util/..."
38658 set dst [string range $src [string length "${srcdir}/"] end]
38659 @@ -1374,3 +1383,119 @@ proc check_v3_target_string_conversions
38660 verbose "check_v3_target_string_conversions: $et_string_conversions" 2
38661 return $et_string_conversions
38664 +proc check_v3_target_swprintf { } {
38666 + global DEFAULT_CXXFLAGS
38667 + global et_swprintf
38671 + if { ![info exists et_swprintf_target_name] } {
38672 + set et_swprintf_target_name ""
38675 + # If the target has changed since we set the cached value, clear it.
38676 + set current_target [current_target_name]
38677 + if { $current_target != $et_swprintf_target_name } {
38678 + verbose "check_v3_target_swprintf: `$et_swprintf_target_name'" 2
38679 + set et_swprintf_target_name $current_target
38680 + if [info exists et_swprintf] {
38681 + verbose "check_v3_target_swprintf: removing cached result" 2
38682 + unset et_swprintf
38686 + if [info exists et_swprintf] {
38687 + verbose "check_v3_target_swprintf: using cached result" 2
38689 + set et_swprintf 0
38691 + # Set up and compile a C++0x test program that depends
38692 + # on a standard swprintf function to be available.
38693 + set src swprintf[pid].cc
38694 + set exe swprintf[pid].exe
38696 + set f [open $src "w"]
38697 + puts $f "#include <bits/c++config.h>"
38698 + puts $f "int main()"
38699 + puts $f "#if !defined(_GLIBCXX_HAVE_BROKEN_VSWPRINTF)"
38700 + puts $f "{ return 0; }"
38704 + set cxxflags_saved $cxxflags
38705 + set cxxflags "$cxxflags $DEFAULT_CXXFLAGS -Werror"
38707 + set lines [v3_target_compile $src $exe executable ""]
38708 + set cxxflags $cxxflags_saved
38711 + if [string match "" $lines] {
38712 + # No error message, compilation succeeded.
38713 + set et_swprintf 1
38715 + verbose "check_v3_target_swprintf: compilation failed" 2
38718 + verbose "check_v3_target_swprintf: $et_swprintf" 2
38719 + return $et_swprintf
38722 +proc check_v3_target_binary_io { } {
38724 + global DEFAULT_CXXFLAGS
38725 + global et_binary_io
38729 + if { ![info exists et_binary_io_target_name] } {
38730 + set et_binary_io_target_name ""
38733 + # If the target has changed since we set the cached value, clear it.
38734 + set current_target [current_target_name]
38735 + if { $current_target != $et_binary_io_target_name } {
38736 + verbose "check_v3_target_binary_io: `$et_binary_io_target_name'" 2
38737 + set et_binary_io_target_name $current_target
38738 + if [info exists et_binary_io] {
38739 + verbose "check_v3_target_binary_io: removing cached result" 2
38740 + unset et_binary_io
38744 + if [info exists et_binary_io] {
38745 + verbose "check_v3_target_binary_io: using cached result" 2
38747 + set et_binary_io 0
38749 + # Set up and compile a C++0x test program that depends
38750 + # on text and binary I/O being the same.
38751 + set src binary_io[pid].cc
38752 + set exe binary_io[pid].exe
38754 + set f [open $src "w"]
38755 + puts $f "#include <bits/c++config.h>"
38756 + puts $f "int main()"
38757 + puts $f "#if !defined(_GLIBCXX_HAVE_DOS_BASED_FILESYSTEM)"
38758 + puts $f "{ return 0; }"
38762 + set cxxflags_saved $cxxflags
38763 + set cxxflags "$cxxflags $DEFAULT_CXXFLAGS -Werror"
38765 + set lines [v3_target_compile $src $exe executable ""]
38766 + set cxxflags $cxxflags_saved
38769 + if [string match "" $lines] {
38770 + # No error message, compilation succeeded.
38771 + set et_binary_io 1
38773 + verbose "check_v3_target_binary_io: compilation failed" 2
38776 + verbose "check_v3_target_binary_io: $et_binary_io" 2
38777 + return $et_binary_io
38779 --- a/libstdc++-v3/testsuite/lib/prune.exp
38780 +++ b/libstdc++-v3/testsuite/lib/prune.exp
38781 @@ -30,5 +30,23 @@ proc prune_g++_output { text } {
38782 regsub -all "(^|\n)\[^\n\]*: Additional NOP may be necessary to workaround Itanium processor A/B step errata" $text "" text
38783 regsub -all "(^|\n)\[^\n*\]*: Assembler messages:\[^\n\]*" $text "" text
38785 + if { [ishost "sparc*-*-solaris2*"] } {
38786 + # When testing a compiler built for SPARC Solaris 2.9 (or earlier)
38787 + # on a host running Solaris 2.10 (or later), we get this warning
38788 + # from the static linker when building with g++:
38790 + # libm.so.1, needed by .../libstdc++.so may conflict with
38793 + # The warning is issued because libstdc++ is linked against
38794 + # libm.so.1 (from the Solaris 2.9 sysroot), whereas Solaris 2.10
38795 + # provides both libm.so.2 and libm.so.1. On Solaris 2.10, libc.so
38796 + # depends on libm.so.2, so all programs pull in libm.so.2.
38798 + # Pulling both libraries must in fact be harmless, as, otherwise,
38799 + # programs built for Solaris 2.9 would break on Solaris 2.10.
38800 + regsub -all "(^|\n)\[^\n\]*: warning: libm.so.1, needed by \[^\n\]*, may conflict with libm.so.2" $text "" text