+--- a/drivers/net/wireless/ath/ath5k/mac80211-ops.c
++++ b/drivers/net/wireless/ath/ath5k/mac80211-ops.c
+@@ -210,8 +210,8 @@ ath5k_config(struct ieee80211_hw *hw, u3
+ }
+
+ if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
+- (ah->power_level != conf->power_level)) {
+- ah->power_level = conf->power_level;
++ (ah->ah_txpower.txp_requested != conf->power_level)) {
++ ah->ah_txpower.txp_requested = conf->power_level;
+
+ /* Half dB steps */
+ ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
+@@ -622,7 +622,7 @@ ath5k_conf_tx(struct ieee80211_hw *hw, s
+ qi.tqi_aifs = params->aifs;
+ qi.tqi_cw_min = params->cw_min;
+ qi.tqi_cw_max = params->cw_max;
+- qi.tqi_burst_time = params->txop;
++ qi.tqi_burst_time = params->txop * 32;
+
+ ATH5K_DBG(ah, ATH5K_DEBUG_ANY,
+ "Configure tx [queue %d], "
+--- a/drivers/net/wireless/ath/ath9k/ar9002_hw.c
++++ b/drivers/net/wireless/ath/ath9k/ar9002_hw.c
+@@ -26,106 +26,74 @@
+ static void ar9002_hw_init_mode_regs(struct ath_hw *ah)
+ {
+ if (AR_SREV_9271(ah)) {
+- INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
+- ARRAY_SIZE(ar9271Modes_9271), 5);
+- INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
+- ARRAY_SIZE(ar9271Common_9271), 2);
+- INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
+- ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 5);
++ INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271);
++ INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271);
++ INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg);
+ return;
+ }
+
+ if (ah->config.pcie_clock_req)
+ INIT_INI_ARRAY(&ah->iniPcieSerdes,
+- ar9280PciePhy_clkreq_off_L1_9280,
+- ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280), 2);
++ ar9280PciePhy_clkreq_off_L1_9280);
+ else
+ INIT_INI_ARRAY(&ah->iniPcieSerdes,
+- ar9280PciePhy_clkreq_always_on_L1_9280,
+- ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
++ ar9280PciePhy_clkreq_always_on_L1_9280);
+ #ifdef CONFIG_PM_SLEEP
+ INIT_INI_ARRAY(&ah->iniPcieSerdesWow,
+- ar9280PciePhy_awow,
+- ARRAY_SIZE(ar9280PciePhy_awow), 2);
++ ar9280PciePhy_awow);
+ #endif
+
+ if (AR_SREV_9287_11_OR_LATER(ah)) {
+- INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
+- ARRAY_SIZE(ar9287Modes_9287_1_1), 5);
+- INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
+- ARRAY_SIZE(ar9287Common_9287_1_1), 2);
++ INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1);
++ INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1);
+ } else if (AR_SREV_9285_12_OR_LATER(ah)) {
+- INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
+- ARRAY_SIZE(ar9285Modes_9285_1_2), 5);
+- INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
+- ARRAY_SIZE(ar9285Common_9285_1_2), 2);
++ INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2);
++ INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2);
+ } else if (AR_SREV_9280_20_OR_LATER(ah)) {
+- INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
+- ARRAY_SIZE(ar9280Modes_9280_2), 5);
+- INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
+- ARRAY_SIZE(ar9280Common_9280_2), 2);
++ INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2);
++ INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2);
+
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
+- ar9280Modes_fast_clock_9280_2,
+- ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
++ ar9280Modes_fast_clock_9280_2);
+ } else if (AR_SREV_9160_10_OR_LATER(ah)) {
+- INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
+- ARRAY_SIZE(ar5416Modes_9160), 5);
+- INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
+- ARRAY_SIZE(ar5416Common_9160), 2);
++ INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160);
++ INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160);
+ if (AR_SREV_9160_11(ah)) {
+ INIT_INI_ARRAY(&ah->iniAddac,
+- ar5416Addac_9160_1_1,
+- ARRAY_SIZE(ar5416Addac_9160_1_1), 2);
++ ar5416Addac_9160_1_1);
+ } else {
+- INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
+- ARRAY_SIZE(ar5416Addac_9160), 2);
++ INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160);
+ }
+ } else if (AR_SREV_9100_OR_LATER(ah)) {
+- INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
+- ARRAY_SIZE(ar5416Modes_9100), 5);
+- INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
+- ARRAY_SIZE(ar5416Common_9100), 2);
+- INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
+- ARRAY_SIZE(ar5416Bank6_9100), 3);
+- INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
+- ARRAY_SIZE(ar5416Addac_9100), 2);
++ INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100);
++ INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100);
++ INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100);
++ INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100);
+ } else {
+- INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
+- ARRAY_SIZE(ar5416Modes), 5);
+- INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
+- ARRAY_SIZE(ar5416Common), 2);
+- INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
+- ARRAY_SIZE(ar5416Bank6TPC), 3);
+- INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
+- ARRAY_SIZE(ar5416Addac), 2);
++ INIT_INI_ARRAY(&ah->iniModes, ar5416Modes);
++ INIT_INI_ARRAY(&ah->iniCommon, ar5416Common);
++ INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC);
++ INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac);
+ }
+
+ if (!AR_SREV_9280_20_OR_LATER(ah)) {
+ /* Common for AR5416, AR913x, AR9160 */
+- INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
+- ARRAY_SIZE(ar5416BB_RfGain), 3);
++ INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain);
+
+- INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
+- ARRAY_SIZE(ar5416Bank0), 2);
+- INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
+- ARRAY_SIZE(ar5416Bank1), 2);
+- INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
+- ARRAY_SIZE(ar5416Bank2), 2);
+- INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
+- ARRAY_SIZE(ar5416Bank3), 3);
+- INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
+- ARRAY_SIZE(ar5416Bank7), 2);
++ INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0);
++ INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1);
++ INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2);
++ INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3);
++ INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7);
+
+ /* Common for AR5416, AR9160 */
+ if (!AR_SREV_9100(ah))
+- INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
+- ARRAY_SIZE(ar5416Bank6), 3);
++ INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6);
+
+ /* Common for AR913x, AR9160 */
+ if (!AR_SREV_5416(ah))
+- INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
+- ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
++ INIT_INI_ARRAY(&ah->iniBank6TPC,
++ ar5416Bank6TPC_9100);
+ }
+
+ /* iniAddac needs to be modified for these chips */
+@@ -148,13 +116,9 @@ static void ar9002_hw_init_mode_regs(str
+ }
+ if (AR_SREV_9287_11_OR_LATER(ah)) {
+ INIT_INI_ARRAY(&ah->iniCckfirNormal,
+- ar9287Common_normal_cck_fir_coeff_9287_1_1,
+- ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_9287_1_1),
+- 2);
++ ar9287Common_normal_cck_fir_coeff_9287_1_1);
+ INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
+- ar9287Common_japan_2484_cck_fir_coeff_9287_1_1,
+- ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_9287_1_1),
+- 2);
++ ar9287Common_japan_2484_cck_fir_coeff_9287_1_1);
+ }
+ }
+
+@@ -168,20 +132,16 @@ static void ar9280_20_hw_init_rxgain_ini
+
+ if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9280Modes_backoff_13db_rxgain_9280_2,
+- ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 5);
++ ar9280Modes_backoff_13db_rxgain_9280_2);
+ else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9280Modes_backoff_23db_rxgain_9280_2,
+- ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 5);
++ ar9280Modes_backoff_23db_rxgain_9280_2);
+ else
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9280Modes_original_rxgain_9280_2,
+- ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
++ ar9280Modes_original_rxgain_9280_2);
+ } else {
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9280Modes_original_rxgain_9280_2,
+- ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 5);
++ ar9280Modes_original_rxgain_9280_2);
+ }
+ }
+
+@@ -191,16 +151,13 @@ static void ar9280_20_hw_init_txgain_ini
+ AR5416_EEP_MINOR_VER_19) {
+ if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9280Modes_high_power_tx_gain_9280_2,
+- ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 5);
++ ar9280Modes_high_power_tx_gain_9280_2);
+ else
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9280Modes_original_tx_gain_9280_2,
+- ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
++ ar9280Modes_original_tx_gain_9280_2);
+ } else {
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9280Modes_original_tx_gain_9280_2,
+- ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 5);
++ ar9280Modes_original_tx_gain_9280_2);
+ }
+ }
+
+@@ -208,12 +165,10 @@ static void ar9271_hw_init_txgain_ini(st
+ {
+ if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9271Modes_high_power_tx_gain_9271,
+- ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 5);
++ ar9271Modes_high_power_tx_gain_9271);
+ else
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9271Modes_normal_power_tx_gain_9271,
+- ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 5);
++ ar9271Modes_normal_power_tx_gain_9271);
+ }
+
+ static void ar9002_hw_init_mode_gain_regs(struct ath_hw *ah)
+@@ -222,8 +177,7 @@ static void ar9002_hw_init_mode_gain_reg
+
+ if (AR_SREV_9287_11_OR_LATER(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9287Modes_rx_gain_9287_1_1,
+- ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 5);
++ ar9287Modes_rx_gain_9287_1_1);
+ else if (AR_SREV_9280_20(ah))
+ ar9280_20_hw_init_rxgain_ini(ah);
+
+@@ -231,8 +185,7 @@ static void ar9002_hw_init_mode_gain_reg
+ ar9271_hw_init_txgain_ini(ah, txgain_type);
+ } else if (AR_SREV_9287_11_OR_LATER(ah)) {
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9287Modes_tx_gain_9287_1_1,
+- ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 5);
++ ar9287Modes_tx_gain_9287_1_1);
+ } else if (AR_SREV_9280_20(ah)) {
+ ar9280_20_hw_init_txgain_ini(ah, txgain_type);
+ } else if (AR_SREV_9285_12_OR_LATER(ah)) {
+@@ -240,26 +193,18 @@ static void ar9002_hw_init_mode_gain_reg
+ if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
+ if (AR_SREV_9285E_20(ah)) {
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9285Modes_XE2_0_high_power,
+- ARRAY_SIZE(
+- ar9285Modes_XE2_0_high_power), 5);
++ ar9285Modes_XE2_0_high_power);
+ } else {
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9285Modes_high_power_tx_gain_9285_1_2,
+- ARRAY_SIZE(
+- ar9285Modes_high_power_tx_gain_9285_1_2), 5);
++ ar9285Modes_high_power_tx_gain_9285_1_2);
+ }
+ } else {
+ if (AR_SREV_9285E_20(ah)) {
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9285Modes_XE2_0_normal_power,
+- ARRAY_SIZE(
+- ar9285Modes_XE2_0_normal_power), 5);
++ ar9285Modes_XE2_0_normal_power);
+ } else {
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9285Modes_original_tx_gain_9285_1_2,
+- ARRAY_SIZE(
+- ar9285Modes_original_tx_gain_9285_1_2), 5);
++ ar9285Modes_original_tx_gain_9285_1_2);
+ }
+ }
+ }
+--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
+@@ -131,8 +131,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext1 = {
+@@ -331,8 +332,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0c80c080),
+ .papdRateMaskHt40 = LE32(0x0080c080),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext2 = {
+@@ -704,8 +706,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0c80c080),
+ .papdRateMaskHt40 = LE32(0x0080c080),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext1 = {
+@@ -904,8 +907,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext2 = {
+@@ -1278,8 +1282,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0c80c080),
+ .papdRateMaskHt40 = LE32(0x0080c080),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext1 = {
+@@ -1478,8 +1483,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext2 = {
+@@ -1852,8 +1858,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0c80c080),
+ .papdRateMaskHt40 = LE32(0x0080c080),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext1 = {
+@@ -2052,8 +2059,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext2 = {
+@@ -2425,8 +2433,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0c80C080),
+ .papdRateMaskHt40 = LE32(0x0080C080),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext1 = {
+@@ -2625,8 +2634,9 @@ static const struct ar9300_eeprom ar9300
+ .thresh62 = 28,
+ .papdRateMaskHt20 = LE32(0x0cf0e0e0),
+ .papdRateMaskHt40 = LE32(0x6cf0e0e0),
++ .xlna_bias_strength = 0,
+ .futureModal = {
+- 0, 0, 0, 0, 0, 0, 0, 0,
++ 0, 0, 0, 0, 0, 0, 0,
+ },
+ },
+ .base_ext2 = {
+@@ -2971,14 +2981,6 @@ static u32 ath9k_hw_ar9300_get_eeprom(st
+ return (pBase->txrxMask >> 4) & 0xf;
+ case EEP_RX_MASK:
+ return pBase->txrxMask & 0xf;
+- case EEP_DRIVE_STRENGTH:
+-#define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
+- return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
+- case EEP_INTERNAL_REGULATOR:
+- /* Bit 4 is internal regulator flag */
+- return (pBase->featureEnable & 0x10) >> 4;
+- case EEP_SWREG:
+- return le32_to_cpu(pBase->swreg);
+ case EEP_PAPRD:
+ return !!(pBase->featureEnable & BIT(5));
+ case EEP_CHAIN_MASK_REDUCE:
+@@ -2989,8 +2991,6 @@ static u32 ath9k_hw_ar9300_get_eeprom(st
+ return eep->modalHeader5G.antennaGain;
+ case EEP_ANTENNA_GAIN_2G:
+ return eep->modalHeader2G.antennaGain;
+- case EEP_QUICK_DROP:
+- return pBase->miscConfiguration & BIT(1);
+ default:
+ return 0;
+ }
+@@ -3260,10 +3260,20 @@ static int ar9300_eeprom_restore_interna
+ int it;
+ u16 checksum, mchecksum;
+ struct ath_common *common = ath9k_hw_common(ah);
++ struct ar9300_eeprom *eep;
+ eeprom_read_op read;
+
+- if (ath9k_hw_use_flash(ah))
+- return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
++ if (ath9k_hw_use_flash(ah)) {
++ u8 txrx;
++
++ ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
++
++ /* check if eeprom contains valid data */
++ eep = (struct ar9300_eeprom *) mptr;
++ txrx = eep->baseEepHeader.txrxMask;
++ if (txrx != 0 && txrx != 0xff)
++ return 0;
++ }
+
+ word = kzalloc(2048, GFP_KERNEL);
+ if (!word)
+@@ -3493,19 +3503,20 @@ static int ath9k_hw_ar9300_get_eeprom_re
+ return 0;
+ }
+
+-static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
++static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah,
++ bool is2ghz)
+ {
+ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+
+ if (is2ghz)
+- return eep->modalHeader2G.xpaBiasLvl;
++ return &eep->modalHeader2G;
+ else
+- return eep->modalHeader5G.xpaBiasLvl;
++ return &eep->modalHeader5G;
+ }
+
+ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
+ {
+- int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
++ int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl;
+
+ if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
+ REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
+@@ -3521,57 +3532,26 @@ static void ar9003_hw_xpa_bias_level_app
+ }
+ }
+
+-static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz)
++static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz)
+ {
+- struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+- __le16 val;
+-
+- if (is_2ghz)
+- val = eep->modalHeader2G.switchcomspdt;
+- else
+- val = eep->modalHeader5G.switchcomspdt;
+- return le16_to_cpu(val);
++ return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt);
+ }
+
+
+ static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
+ {
+- struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+- __le32 val;
+-
+- if (is2ghz)
+- val = eep->modalHeader2G.antCtrlCommon;
+- else
+- val = eep->modalHeader5G.antCtrlCommon;
+- return le32_to_cpu(val);
++ return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon);
+ }
+
+ static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
+ {
+- struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+- __le32 val;
+-
+- if (is2ghz)
+- val = eep->modalHeader2G.antCtrlCommon2;
+- else
+- val = eep->modalHeader5G.antCtrlCommon2;
+- return le32_to_cpu(val);
++ return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2);
+ }
+
+-static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
+- int chain,
++static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain,
+ bool is2ghz)
+ {
+- struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+- __le16 val = 0;
+-
+- if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
+- if (is2ghz)
+- val = eep->modalHeader2G.antCtrlChain[chain];
+- else
+- val = eep->modalHeader5G.antCtrlChain[chain];
+- }
+-
++ __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain];
+ return le16_to_cpu(val);
+ }
+
+@@ -3681,11 +3661,12 @@ static void ar9003_hw_ant_ctrl_apply(str
+
+ static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
+ {
++ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
++ struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
+ int drive_strength;
+ unsigned long reg;
+
+- drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
+-
++ drive_strength = pBase->miscConfiguration & BIT(0);
+ if (!drive_strength)
+ return;
+
+@@ -3815,11 +3796,11 @@ static bool is_pmu_set(struct ath_hw *ah
+
+ void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
+ {
+- int internal_regulator =
+- ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
++ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
++ struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
+ u32 reg_val;
+
+- if (internal_regulator) {
++ if (pBase->featureEnable & BIT(4)) {
+ if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
+ int reg_pmu_set;
+
+@@ -3863,11 +3844,11 @@ void ar9003_hw_internal_regulator_apply(
+ if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
+ return;
+ } else if (AR_SREV_9462(ah)) {
+- reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
++ reg_val = le32_to_cpu(pBase->swreg);
+ REG_WRITE(ah, AR_PHY_PMU1, reg_val);
+ } else {
+ /* Internal regulator is ON. Write swreg register. */
+- reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
++ reg_val = le32_to_cpu(pBase->swreg);
+ REG_WRITE(ah, AR_RTC_REG_CONTROL1,
+ REG_READ(ah, AR_RTC_REG_CONTROL1) &
+ (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
+@@ -3909,6 +3890,9 @@ static void ar9003_hw_apply_tuning_caps(
+ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+ u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
+
++ if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
++ return;
++
+ if (eep->baseEepHeader.featureEnable & 0x40) {
+ tuning_caps_param &= 0x7f;
+ REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
+@@ -3921,10 +3905,11 @@ static void ar9003_hw_apply_tuning_caps(
+ static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
+ {
+ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+- int quick_drop = ath9k_hw_ar9300_get_eeprom(ah, EEP_QUICK_DROP);
++ struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
++ int quick_drop;
+ s32 t[3], f[3] = {5180, 5500, 5785};
+
+- if (!quick_drop)
++ if (!(pBase->miscConfiguration & BIT(1)))
+ return;
+
+ if (freq < 4000)
+@@ -3938,13 +3923,11 @@ static void ar9003_hw_quick_drop_apply(s
+ REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
+ }
+
+-static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, u16 freq)
++static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz)
+ {
+- struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+ u32 value;
+
+- value = (freq < 4000) ? eep->modalHeader2G.txEndToXpaOff :
+- eep->modalHeader5G.txEndToXpaOff;
++ value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff;
+
+ REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
+ AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
+@@ -3952,19 +3935,63 @@ static void ar9003_hw_txend_to_xpa_off_a
+ AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
+ }
+
++static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz)
++{
++ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
++ u8 xpa_ctl;
++
++ if (!(eep->baseEepHeader.featureEnable & 0x80))
++ return;
++
++ if (!AR_SREV_9300(ah) && !AR_SREV_9340(ah) && !AR_SREV_9580(ah))
++ return;
++
++ xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn;
++ if (is2ghz)
++ REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
++ AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON, xpa_ctl);
++ else
++ REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
++ AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON, xpa_ctl);
++}
++
++static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz)
++{
++ struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
++ u8 bias;
++
++ if (!(eep->baseEepHeader.featureEnable & 0x40))
++ return;
++
++ if (!AR_SREV_9300(ah))
++ return;
++
++ bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength;
++ REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
++ bias & 0x3);
++ bias >>= 2;
++ REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
++ bias & 0x3);
++ bias >>= 2;
++ REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS,
++ bias & 0x3);
++}
++
+ static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
+ struct ath9k_channel *chan)
+ {
+- ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
+- ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
++ bool is2ghz = IS_CHAN_2GHZ(chan);
++ ar9003_hw_xpa_timing_control_apply(ah, is2ghz);
++ ar9003_hw_xpa_bias_level_apply(ah, is2ghz);
++ ar9003_hw_ant_ctrl_apply(ah, is2ghz);
+ ar9003_hw_drive_strength_apply(ah);
++ ar9003_hw_xlna_bias_strength_apply(ah, is2ghz);
+ ar9003_hw_atten_apply(ah, chan);
+ ar9003_hw_quick_drop_apply(ah, chan->channel);
+ if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
+ ar9003_hw_internal_regulator_apply(ah);
+- if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
+- ar9003_hw_apply_tuning_caps(ah);
+- ar9003_hw_txend_to_xpa_off_apply(ah, chan->channel);
++ ar9003_hw_apply_tuning_caps(ah);
++ ar9003_hw_txend_to_xpa_off_apply(ah, is2ghz);
+ }
+
+ static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
+@@ -5100,14 +5127,9 @@ s32 ar9003_hw_get_rx_gain_idx(struct ath
+ return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
+ }
+
+-u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
++u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz)
+ {
+- struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
+-
+- if (is_2ghz)
+- return eep->modalHeader2G.spurChans;
+- else
+- return eep->modalHeader5G.spurChans;
++ return ar9003_modal_header(ah, is2ghz)->spurChans;
+ }
+
+ unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
+--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
++++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+@@ -231,7 +231,8 @@ struct ar9300_modal_eep_header {
+ __le32 papdRateMaskHt20;
+ __le32 papdRateMaskHt40;
+ __le16 switchcomspdt;
+- u8 futureModal[8];
++ u8 xlna_bias_strength;
++ u8 futureModal[7];
+ } __packed;
+
+ struct ar9300_cal_data_per_freq_op_loop {
+--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+@@ -44,462 +44,310 @@ static void ar9003_hw_init_mode_regs(str
+ ar9462_2p0_baseband_core_txfir_coeff_japan_2484
+ if (AR_SREV_9330_11(ah)) {
+ /* mac */
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+- ar9331_1p1_mac_core,
+- ARRAY_SIZE(ar9331_1p1_mac_core), 2);
++ ar9331_1p1_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar9331_1p1_mac_postamble,
+- ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
++ ar9331_1p1_mac_postamble);
+
+ /* bb */
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar9331_1p1_baseband_core,
+- ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
++ ar9331_1p1_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar9331_1p1_baseband_postamble,
+- ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
++ ar9331_1p1_baseband_postamble);
+
+ /* radio */
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar9331_1p1_radio_core,
+- ARRAY_SIZE(ar9331_1p1_radio_core), 2);
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
++ ar9331_1p1_radio_core);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar9331_1p1_soc_preamble,
+- ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++ ar9331_1p1_soc_preamble);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+- ar9331_1p1_soc_postamble,
+- ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
++ ar9331_1p1_soc_postamble);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9331_common_rx_gain_1p1,
+- ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
++ ar9331_common_rx_gain_1p1);
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_lowest_ob_db_tx_gain_1p1,
+- ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
+- 5);
++ ar9331_modes_lowest_ob_db_tx_gain_1p1);
+
+ /* additional clock settings */
+ if (ah->is_clk_25mhz)
+ INIT_INI_ARRAY(&ah->iniAdditional,
+- ar9331_1p1_xtal_25M,
+- ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
++ ar9331_1p1_xtal_25M);
+ else
+ INIT_INI_ARRAY(&ah->iniAdditional,
+- ar9331_1p1_xtal_40M,
+- ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
++ ar9331_1p1_xtal_40M);
+ } else if (AR_SREV_9330_12(ah)) {
+ /* mac */
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+- ar9331_1p2_mac_core,
+- ARRAY_SIZE(ar9331_1p2_mac_core), 2);
++ ar9331_1p2_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar9331_1p2_mac_postamble,
+- ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
++ ar9331_1p2_mac_postamble);
+
+ /* bb */
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar9331_1p2_baseband_core,
+- ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
++ ar9331_1p2_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar9331_1p2_baseband_postamble,
+- ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
++ ar9331_1p2_baseband_postamble);
+
+ /* radio */
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar9331_1p2_radio_core,
+- ARRAY_SIZE(ar9331_1p2_radio_core), 2);
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
++ ar9331_1p2_radio_core);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar9331_1p2_soc_preamble,
+- ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++ ar9331_1p2_soc_preamble);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+- ar9331_1p2_soc_postamble,
+- ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
++ ar9331_1p2_soc_postamble);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9331_common_rx_gain_1p2,
+- ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
++ ar9331_common_rx_gain_1p2);
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_lowest_ob_db_tx_gain_1p2,
+- ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
+- 5);
++ ar9331_modes_lowest_ob_db_tx_gain_1p2);
+
+ /* additional clock settings */
+ if (ah->is_clk_25mhz)
+ INIT_INI_ARRAY(&ah->iniAdditional,
+- ar9331_1p2_xtal_25M,
+- ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
++ ar9331_1p2_xtal_25M);
+ else
+ INIT_INI_ARRAY(&ah->iniAdditional,
+- ar9331_1p2_xtal_40M,
+- ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
++ ar9331_1p2_xtal_40M);
+ } else if (AR_SREV_9340(ah)) {
+ /* mac */
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+- ar9340_1p0_mac_core,
+- ARRAY_SIZE(ar9340_1p0_mac_core), 2);
++ ar9340_1p0_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar9340_1p0_mac_postamble,
+- ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
++ ar9340_1p0_mac_postamble);
+
+ /* bb */
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar9340_1p0_baseband_core,
+- ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
++ ar9340_1p0_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar9340_1p0_baseband_postamble,
+- ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
++ ar9340_1p0_baseband_postamble);
+
+ /* radio */
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar9340_1p0_radio_core,
+- ARRAY_SIZE(ar9340_1p0_radio_core), 2);
++ ar9340_1p0_radio_core);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+- ar9340_1p0_radio_postamble,
+- ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
++ ar9340_1p0_radio_postamble);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar9340_1p0_soc_preamble,
+- ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++ ar9340_1p0_soc_preamble);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+- ar9340_1p0_soc_postamble,
+- ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
++ ar9340_1p0_soc_postamble);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9340Common_wo_xlna_rx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
+- 5);
+- INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9340Modes_high_ob_db_tx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
+- 5);
++ ar9340Common_wo_xlna_rx_gain_table_1p0);
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar9340Modes_high_ob_db_tx_gain_table_1p0);
+
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
+- ar9340Modes_fast_clock_1p0,
+- ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
+- 3);
++ ar9340Modes_fast_clock_1p0);
+
+ if (!ah->is_clk_25mhz)
+ INIT_INI_ARRAY(&ah->iniAdditional,
+- ar9340_1p0_radio_core_40M,
+- ARRAY_SIZE(ar9340_1p0_radio_core_40M),
+- 2);
++ ar9340_1p0_radio_core_40M);
+ } else if (AR_SREV_9485_11(ah)) {
+ /* mac */
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+- ar9485_1_1_mac_core,
+- ARRAY_SIZE(ar9485_1_1_mac_core), 2);
++ ar9485_1_1_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar9485_1_1_mac_postamble,
+- ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
++ ar9485_1_1_mac_postamble);
+
+ /* bb */
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
+- ARRAY_SIZE(ar9485_1_1), 2);
++ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar9485_1_1_baseband_core,
+- ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
++ ar9485_1_1_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar9485_1_1_baseband_postamble,
+- ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
++ ar9485_1_1_baseband_postamble);
+
+ /* radio */
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar9485_1_1_radio_core,
+- ARRAY_SIZE(ar9485_1_1_radio_core), 2);
++ ar9485_1_1_radio_core);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+- ar9485_1_1_radio_postamble,
+- ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
++ ar9485_1_1_radio_postamble);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar9485_1_1_soc_preamble,
+- ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
++ ar9485_1_1_soc_preamble);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9485Common_wo_xlna_rx_gain_1_1,
+- ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
++ ar9485Common_wo_xlna_rx_gain_1_1);
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9485_modes_lowest_ob_db_tx_gain_1_1,
+- ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
+- 5);
++ ar9485_modes_lowest_ob_db_tx_gain_1_1);
+
+ /* Load PCIE SERDES settings from INI */
+
+ /* Awake Setting */
+
+ INIT_INI_ARRAY(&ah->iniPcieSerdes,
+- ar9485_1_1_pcie_phy_clkreq_disable_L1,
+- ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
+- 2);
++ ar9485_1_1_pcie_phy_clkreq_disable_L1);
+
+ /* Sleep Setting */
+
+ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+- ar9485_1_1_pcie_phy_clkreq_disable_L1,
+- ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
+- 2);
++ ar9485_1_1_pcie_phy_clkreq_disable_L1);
+ } else if (AR_SREV_9462_20(ah)) {
+
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
+- ARRAY_SIZE(ar9462_2p0_mac_core), 2);
++ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar9462_2p0_mac_postamble,
+- ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
++ ar9462_2p0_mac_postamble);
+
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar9462_2p0_baseband_core,
+- ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
++ ar9462_2p0_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar9462_2p0_baseband_postamble,
+- ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
++ ar9462_2p0_baseband_postamble);
+
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar9462_2p0_radio_core,
+- ARRAY_SIZE(ar9462_2p0_radio_core), 2);
++ ar9462_2p0_radio_core);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+- ar9462_2p0_radio_postamble,
+- ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
++ ar9462_2p0_radio_postamble);
+ INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
+- ar9462_2p0_radio_postamble_sys2ant,
+- ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
+- 5);
++ ar9462_2p0_radio_postamble_sys2ant);
+
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar9462_2p0_soc_preamble,
+- ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++ ar9462_2p0_soc_preamble);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+- ar9462_2p0_soc_postamble,
+- ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
++ ar9462_2p0_soc_postamble);
+
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9462_common_rx_gain_table_2p0,
+- ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
++ ar9462_common_rx_gain_table_2p0);
+
+ /* Awake -> Sleep Setting */
+ INIT_INI_ARRAY(&ah->iniPcieSerdes,
+- PCIE_PLL_ON_CREQ_DIS_L1_2P0,
+- ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
+- 2);
++ PCIE_PLL_ON_CREQ_DIS_L1_2P0);
+ /* Sleep -> Awake Setting */
+ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+- PCIE_PLL_ON_CREQ_DIS_L1_2P0,
+- ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
+- 2);
++ PCIE_PLL_ON_CREQ_DIS_L1_2P0);
+
+ /* Fast clock modal settings */
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
+- ar9462_modes_fast_clock_2p0,
+- ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
++ ar9462_modes_fast_clock_2p0);
+
+ INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
+- AR9462_BB_CTX_COEFJ(2p0),
+- ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
++ AR9462_BB_CTX_COEFJ(2p0));
+
+- INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
+- ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
++ INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ);
+ } else if (AR_SREV_9550(ah)) {
+ /* mac */
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+- ar955x_1p0_mac_core,
+- ARRAY_SIZE(ar955x_1p0_mac_core), 2);
++ ar955x_1p0_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar955x_1p0_mac_postamble,
+- ARRAY_SIZE(ar955x_1p0_mac_postamble), 5);
++ ar955x_1p0_mac_postamble);
+
+ /* bb */
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar955x_1p0_baseband_core,
+- ARRAY_SIZE(ar955x_1p0_baseband_core), 2);
++ ar955x_1p0_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar955x_1p0_baseband_postamble,
+- ARRAY_SIZE(ar955x_1p0_baseband_postamble), 5);
++ ar955x_1p0_baseband_postamble);
+
+ /* radio */
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar955x_1p0_radio_core,
+- ARRAY_SIZE(ar955x_1p0_radio_core), 2);
++ ar955x_1p0_radio_core);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+- ar955x_1p0_radio_postamble,
+- ARRAY_SIZE(ar955x_1p0_radio_postamble), 5);
++ ar955x_1p0_radio_postamble);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar955x_1p0_soc_preamble,
+- ARRAY_SIZE(ar955x_1p0_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++ ar955x_1p0_soc_preamble);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+- ar955x_1p0_soc_postamble,
+- ARRAY_SIZE(ar955x_1p0_soc_postamble), 5);
++ ar955x_1p0_soc_postamble);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar955x_1p0_common_wo_xlna_rx_gain_table,
+- ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
+- 2);
++ ar955x_1p0_common_wo_xlna_rx_gain_table);
+ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
+- ar955x_1p0_common_wo_xlna_rx_gain_bounds,
+- ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
+- 5);
+- INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar955x_1p0_modes_xpa_tx_gain_table,
+- ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
+- 9);
++ ar955x_1p0_common_wo_xlna_rx_gain_bounds);
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar955x_1p0_modes_xpa_tx_gain_table);
+
+ /* Fast clock modal settings */
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
+- ar955x_1p0_modes_fast_clock,
+- ARRAY_SIZE(ar955x_1p0_modes_fast_clock), 3);
++ ar955x_1p0_modes_fast_clock);
+ } else if (AR_SREV_9580(ah)) {
+ /* mac */
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+- ar9580_1p0_mac_core,
+- ARRAY_SIZE(ar9580_1p0_mac_core), 2);
++ ar9580_1p0_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar9580_1p0_mac_postamble,
+- ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
++ ar9580_1p0_mac_postamble);
+
+ /* bb */
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar9580_1p0_baseband_core,
+- ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
++ ar9580_1p0_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar9580_1p0_baseband_postamble,
+- ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
++ ar9580_1p0_baseband_postamble);
+
+ /* radio */
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar9580_1p0_radio_core,
+- ARRAY_SIZE(ar9580_1p0_radio_core), 2);
++ ar9580_1p0_radio_core);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+- ar9580_1p0_radio_postamble,
+- ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
++ ar9580_1p0_radio_postamble);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar9580_1p0_soc_preamble,
+- ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++ ar9580_1p0_soc_preamble);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+- ar9580_1p0_soc_postamble,
+- ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
++ ar9580_1p0_soc_postamble);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9580_1p0_rx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
++ ar9580_1p0_rx_gain_table);
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9580_1p0_low_ob_db_tx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
+- 5);
++ ar9580_1p0_low_ob_db_tx_gain_table);
+
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
+- ar9580_1p0_modes_fast_clock,
+- ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
+- 3);
++ ar9580_1p0_modes_fast_clock);
+ } else {
+ /* mac */
+- INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
+- ar9300_2p2_mac_core,
+- ARRAY_SIZE(ar9300_2p2_mac_core), 2);
++ ar9300_2p2_mac_core);
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
+- ar9300_2p2_mac_postamble,
+- ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
++ ar9300_2p2_mac_postamble);
+
+ /* bb */
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
+- ar9300_2p2_baseband_core,
+- ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
++ ar9300_2p2_baseband_core);
+ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
+- ar9300_2p2_baseband_postamble,
+- ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
++ ar9300_2p2_baseband_postamble);
+
+ /* radio */
+- INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
+- ar9300_2p2_radio_core,
+- ARRAY_SIZE(ar9300_2p2_radio_core), 2);
++ ar9300_2p2_radio_core);
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
+- ar9300_2p2_radio_postamble,
+- ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
++ ar9300_2p2_radio_postamble);
+
+ /* soc */
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
+- ar9300_2p2_soc_preamble,
+- ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
+- INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
++ ar9300_2p2_soc_preamble);
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
+- ar9300_2p2_soc_postamble,
+- ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
++ ar9300_2p2_soc_postamble);
+
+ /* rx/tx gain */
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9300Common_rx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
++ ar9300Common_rx_gain_table_2p2);
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
+- 5);
++ ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
+
+ /* Load PCIE SERDES settings from INI */
+
+ /* Awake Setting */
+
+ INIT_INI_ARRAY(&ah->iniPcieSerdes,
+- ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+- ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
+- 2);
++ ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
+
+ /* Sleep Setting */
+
+ INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
+- ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+- ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
+- 2);
++ ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
+
+ /* Fast clock modal settings */
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
+- ar9300Modes_fast_clock_2p2,
+- ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
+- 3);
++ ar9300Modes_fast_clock_2p2);
+ }
+ }
+
+@@ -507,156 +355,110 @@ static void ar9003_tx_gain_table_mode0(s
+ {
+ if (AR_SREV_9330_12(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_lowest_ob_db_tx_gain_1p2,
+- ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
+- 5);
++ ar9331_modes_lowest_ob_db_tx_gain_1p2);
+ else if (AR_SREV_9330_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_lowest_ob_db_tx_gain_1p1,
+- ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
+- 5);
++ ar9331_modes_lowest_ob_db_tx_gain_1p1);
+ else if (AR_SREV_9340(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+- 5);
++ ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
+ else if (AR_SREV_9485_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9485_modes_lowest_ob_db_tx_gain_1_1,
+- ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
+- 5);
++ ar9485_modes_lowest_ob_db_tx_gain_1_1);
+ else if (AR_SREV_9550(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar955x_1p0_modes_xpa_tx_gain_table,
+- ARRAY_SIZE(ar955x_1p0_modes_xpa_tx_gain_table),
+- 9);
++ ar955x_1p0_modes_xpa_tx_gain_table);
+ else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9580_1p0_lowest_ob_db_tx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
+- 5);
++ ar9580_1p0_lowest_ob_db_tx_gain_table);
+ else if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9462_modes_low_ob_db_tx_gain_table_2p0,
+- ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
+- 5);
++ ar9462_modes_low_ob_db_tx_gain_table_2p0);
+ else
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
+- 5);
++ ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
+ }
+
+ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
+ {
+ if (AR_SREV_9330_12(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_high_ob_db_tx_gain_1p2,
+- ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
+- 5);
++ ar9331_modes_high_ob_db_tx_gain_1p2);
+ else if (AR_SREV_9330_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_high_ob_db_tx_gain_1p1,
+- ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
+- 5);
++ ar9331_modes_high_ob_db_tx_gain_1p1);
+ else if (AR_SREV_9340(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+- 5);
++ ar9340Modes_high_ob_db_tx_gain_table_1p0);
+ else if (AR_SREV_9485_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9485Modes_high_ob_db_tx_gain_1_1,
+- ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
+- 5);
++ ar9485Modes_high_ob_db_tx_gain_1_1);
+ else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9580_1p0_high_ob_db_tx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
+- 5);
++ ar9580_1p0_high_ob_db_tx_gain_table);
+ else if (AR_SREV_9550(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar955x_1p0_modes_no_xpa_tx_gain_table,
+- ARRAY_SIZE(ar955x_1p0_modes_no_xpa_tx_gain_table),
+- 9);
++ ar955x_1p0_modes_no_xpa_tx_gain_table);
+ else if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9462_modes_high_ob_db_tx_gain_table_2p0,
+- ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
+- 5);
++ ar9462_modes_high_ob_db_tx_gain_table_2p0);
+ else
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9300Modes_high_ob_db_tx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
+- 5);
++ ar9300Modes_high_ob_db_tx_gain_table_2p2);
+ }
+
+ static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
+ {
+ if (AR_SREV_9330_12(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_low_ob_db_tx_gain_1p2,
+- ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
+- 5);
++ ar9331_modes_low_ob_db_tx_gain_1p2);
+ else if (AR_SREV_9330_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_low_ob_db_tx_gain_1p1,
+- ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
+- 5);
++ ar9331_modes_low_ob_db_tx_gain_1p1);
+ else if (AR_SREV_9340(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+- 5);
++ ar9340Modes_low_ob_db_tx_gain_table_1p0);
+ else if (AR_SREV_9485_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9485Modes_low_ob_db_tx_gain_1_1,
+- ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
+- 5);
++ ar9485Modes_low_ob_db_tx_gain_1_1);
+ else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9580_1p0_low_ob_db_tx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
+- 5);
++ ar9580_1p0_low_ob_db_tx_gain_table);
+ else
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9300Modes_low_ob_db_tx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
+- 5);
++ ar9300Modes_low_ob_db_tx_gain_table_2p2);
+ }
+
+ static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
+ {
+ if (AR_SREV_9330_12(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_high_power_tx_gain_1p2,
+- ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
+- 5);
++ ar9331_modes_high_power_tx_gain_1p2);
+ else if (AR_SREV_9330_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9331_modes_high_power_tx_gain_1p1,
+- ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
+- 5);
++ ar9331_modes_high_power_tx_gain_1p1);
+ else if (AR_SREV_9340(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
+- 5);
++ ar9340Modes_high_power_tx_gain_table_1p0);
+ else if (AR_SREV_9485_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9485Modes_high_power_tx_gain_1_1,
+- ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
+- 5);
++ ar9485Modes_high_power_tx_gain_1_1);
+ else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9580_1p0_high_power_tx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
+- 5);
++ ar9580_1p0_high_power_tx_gain_table);
+ else
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
+- ar9300Modes_high_power_tx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
+- 5);
++ ar9300Modes_high_power_tx_gain_table_2p2);
++}
++
++static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
++{
++ if (AR_SREV_9340(ah))
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
++ else if (AR_SREV_9580(ah))
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
++ ar9580_1p0_mixed_ob_db_tx_gain_table);
+ }
+
+ static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
+@@ -675,6 +477,9 @@ static void ar9003_tx_gain_table_apply(s
+ case 3:
+ ar9003_tx_gain_table_mode3(ah);
+ break;
++ case 4:
++ ar9003_tx_gain_table_mode4(ah);
++ break;
+ }
+ }
+
+@@ -682,104 +487,67 @@ static void ar9003_rx_gain_table_mode0(s
+ {
+ if (AR_SREV_9330_12(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9331_common_rx_gain_1p2,
+- ARRAY_SIZE(ar9331_common_rx_gain_1p2),
+- 2);
++ ar9331_common_rx_gain_1p2);
+ else if (AR_SREV_9330_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9331_common_rx_gain_1p1,
+- ARRAY_SIZE(ar9331_common_rx_gain_1p1),
+- 2);
++ ar9331_common_rx_gain_1p1);
+ else if (AR_SREV_9340(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9340Common_rx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
+- 2);
++ ar9340Common_rx_gain_table_1p0);
+ else if (AR_SREV_9485_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9485Common_wo_xlna_rx_gain_1_1,
+- ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
+- 2);
++ ar9485Common_wo_xlna_rx_gain_1_1);
+ else if (AR_SREV_9550(ah)) {
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar955x_1p0_common_rx_gain_table,
+- ARRAY_SIZE(ar955x_1p0_common_rx_gain_table),
+- 2);
++ ar955x_1p0_common_rx_gain_table);
+ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
+- ar955x_1p0_common_rx_gain_bounds,
+- ARRAY_SIZE(ar955x_1p0_common_rx_gain_bounds),
+- 5);
++ ar955x_1p0_common_rx_gain_bounds);
+ } else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9580_1p0_rx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_rx_gain_table),
+- 2);
++ ar9580_1p0_rx_gain_table);
+ else if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9462_common_rx_gain_table_2p0,
+- ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
+- 2);
++ ar9462_common_rx_gain_table_2p0);
+ else
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9300Common_rx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
+- 2);
++ ar9300Common_rx_gain_table_2p2);
+ }
+
+ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
+ {
+ if (AR_SREV_9330_12(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9331_common_wo_xlna_rx_gain_1p2,
+- ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
+- 2);
++ ar9331_common_wo_xlna_rx_gain_1p2);
+ else if (AR_SREV_9330_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9331_common_wo_xlna_rx_gain_1p1,
+- ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
+- 2);
++ ar9331_common_wo_xlna_rx_gain_1p1);
+ else if (AR_SREV_9340(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9340Common_wo_xlna_rx_gain_table_1p0,
+- ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
+- 2);
++ ar9340Common_wo_xlna_rx_gain_table_1p0);
+ else if (AR_SREV_9485_11(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9485Common_wo_xlna_rx_gain_1_1,
+- ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
+- 2);
++ ar9485Common_wo_xlna_rx_gain_1_1);
+ else if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9462_common_wo_xlna_rx_gain_table_2p0,
+- ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
+- 2);
++ ar9462_common_wo_xlna_rx_gain_table_2p0);
+ else if (AR_SREV_9550(ah)) {
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar955x_1p0_common_wo_xlna_rx_gain_table,
+- ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_table),
+- 2);
++ ar955x_1p0_common_wo_xlna_rx_gain_table);
+ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
+- ar955x_1p0_common_wo_xlna_rx_gain_bounds,
+- ARRAY_SIZE(ar955x_1p0_common_wo_xlna_rx_gain_bounds),
+- 5);
++ ar955x_1p0_common_wo_xlna_rx_gain_bounds);
+ } else if (AR_SREV_9580(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9580_1p0_wo_xlna_rx_gain_table,
+- ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
+- 2);
++ ar9580_1p0_wo_xlna_rx_gain_table);
+ else
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9300Common_wo_xlna_rx_gain_table_2p2,
+- ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
+- 2);
++ ar9300Common_wo_xlna_rx_gain_table_2p2);
+ }
+
+ static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
+ {
+ if (AR_SREV_9462_20(ah))
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
+- ar9462_common_mixed_rx_gain_table_2p0,
+- ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
++ ar9462_common_mixed_rx_gain_table_2p0);
+ }
+
+ static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+@@ -117,8 +117,8 @@ static int ar9003_hw_set_channel(struct
+ ah->is_clk_25mhz) {
+ u32 chan_frac;
+
+- channelSel = (freq * 2) / 75;
+- chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
++ channelSel = freq / 75;
++ chan_frac = ((freq % 75) * 0x20000) / 75;
+ channelSel = (channelSel << 17) | chan_frac;
+ } else {
+ channelSel = CHANSEL_5G(freq);
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h
+@@ -633,6 +633,8 @@
+ #define AR_PHY_65NM_CH0_BIAS2 0x160c4
+ #define AR_PHY_65NM_CH0_BIAS4 0x160cc
+ #define AR_PHY_65NM_CH0_RXTX4 0x1610c
++#define AR_PHY_65NM_CH1_RXTX4 0x1650c
++#define AR_PHY_65NM_CH2_RXTX4 0x1690c
+
+ #define AR_CH0_TOP (AR_SREV_9300(ah) ? 0x16288 : \
+ ((AR_SREV_9462(ah) ? 0x1628c : 0x16280)))
+@@ -876,6 +878,9 @@
+ #define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
+ #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_S 28
+
++#define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000
++#define AR_PHY_65NM_RXTX4_XLNA_BIAS_S 30
++
+ /*
+ * Channel 1 Register Map
+ */
+--- a/drivers/net/wireless/ath/ath9k/ath9k.h
++++ b/drivers/net/wireless/ath/ath9k/ath9k.h
+@@ -297,6 +297,8 @@ struct ath_tx {
+ struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
+ struct ath_descdma txdma;
+ struct ath_txq *txq_map[WME_NUM_AC];
++ u32 txq_max_pending[WME_NUM_AC];
++ u16 max_aggr_framelen[WME_NUM_AC][4][32];
+ };
+
+ struct ath_rx_edma {
+@@ -341,6 +343,7 @@ int ath_tx_init(struct ath_softc *sc, in
+ void ath_tx_cleanup(struct ath_softc *sc);
+ int ath_txq_update(struct ath_softc *sc, int qnum,
+ struct ath9k_tx_queue_info *q);
++void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop);
+ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
+ struct ath_tx_control *txctl);
+ void ath_tx_tasklet(struct ath_softc *sc);
+@@ -360,7 +363,7 @@ void ath_tx_aggr_sleep(struct ieee80211_
+
+ struct ath_vif {
+ int av_bslot;
+- bool is_bslot_active, primary_sta_vif;
++ bool primary_sta_vif;
+ __le64 tsf_adjust; /* TSF adjustment for staggered beacons */
+ struct ath_buf *av_bcbuf;
+ };
+@@ -386,6 +389,7 @@ struct ath_beacon_config {
+ u16 dtim_period;
+ u16 bmiss_timeout;
+ u8 dtim_count;
++ bool enable_beacon;
+ };
+
+ struct ath_beacon {
+@@ -397,7 +401,6 @@ struct ath_beacon {
+
+ u32 beaconq;
+ u32 bmisscnt;
+- u32 ast_be_xmit;
+ u32 bc_tstamp;
+ struct ieee80211_vif *bslot[ATH_BCBUF];
+ int slottime;
+@@ -411,12 +414,14 @@ struct ath_beacon {
+ bool tx_last;
+ };
+
+-void ath_beacon_tasklet(unsigned long data);
+-void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
+-int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif);
+-void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
+-int ath_beaconq_config(struct ath_softc *sc);
+-void ath_set_beacon(struct ath_softc *sc);
++void ath9k_beacon_tasklet(unsigned long data);
++bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
++void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
++ u32 changed);
++void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
++void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif);
++void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif);
++void ath9k_set_beacon(struct ath_softc *sc);
+ void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
+
+ /*******************/
+@@ -442,9 +447,12 @@ void ath_rx_poll(unsigned long data);
+ void ath_start_rx_poll(struct ath_softc *sc, u8 nbeacon);
+ void ath_paprd_calibrate(struct work_struct *work);
+ void ath_ani_calibrate(unsigned long data);
+-void ath_start_ani(struct ath_common *common);
++void ath_start_ani(struct ath_softc *sc);
++void ath_stop_ani(struct ath_softc *sc);
++void ath_check_ani(struct ath_softc *sc);
+ int ath_update_survey_stats(struct ath_softc *sc);
+ void ath_update_survey_nf(struct ath_softc *sc, int channel);
++void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
+
+ /**********/
+ /* BTCOEX */
+@@ -619,7 +627,6 @@ enum sc_op_flags {
+ SC_OP_INVALID,
+ SC_OP_BEACONS,
+ SC_OP_RXFLUSH,
+- SC_OP_TSF_RESET,
+ SC_OP_ANI_RUN,
+ SC_OP_PRIM_STA_VIF,
+ SC_OP_HW_RESET,
+--- a/drivers/net/wireless/ath/ath9k/beacon.c
++++ b/drivers/net/wireless/ath/ath9k/beacon.c
+@@ -30,7 +30,7 @@ static void ath9k_reset_beacon_status(st
+ * the operating mode of the station (AP or AdHoc). Parameters are AIFS
+ * settings and channel width min/max
+ */
+-int ath_beaconq_config(struct ath_softc *sc)
++static void ath9k_beaconq_config(struct ath_softc *sc)
+ {
+ struct ath_hw *ah = sc->sc_ah;
+ struct ath_common *common = ath9k_hw_common(ah);
+@@ -38,6 +38,7 @@ int ath_beaconq_config(struct ath_softc
+ struct ath_txq *txq;
+
+ ath9k_hw_get_txq_props(ah, sc->beacon.beaconq, &qi);
++
+ if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
+ /* Always burst out beacon and CAB traffic. */
+ qi.tqi_aifs = 1;
+@@ -56,12 +57,9 @@ int ath_beaconq_config(struct ath_softc
+ }
+
+ if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
+- ath_err(common,
+- "Unable to update h/w beacon queue parameters\n");
+- return 0;
++ ath_err(common, "Unable to update h/w beacon queue parameters\n");
+ } else {
+ ath9k_hw_resettxqueue(ah, sc->beacon.beaconq);
+- return 1;
+ }
+ }
+
+@@ -70,7 +68,7 @@ int ath_beaconq_config(struct ath_softc
+ * up rate codes, and channel flags. Beacons are always sent out at the
+ * lowest rate, and are not retried.
+ */
+-static void ath_beacon_setup(struct ath_softc *sc, struct ieee80211_vif *vif,
++static void ath9k_beacon_setup(struct ath_softc *sc, struct ieee80211_vif *vif,
+ struct ath_buf *bf, int rateidx)
+ {
+ struct sk_buff *skb = bf->bf_mpdu;
+@@ -81,8 +79,6 @@ static void ath_beacon_setup(struct ath_
+ u8 chainmask = ah->txchainmask;
+ u8 rate = 0;
+
+- ath9k_reset_beacon_status(sc);
+-
+ sband = &sc->sbands[common->hw->conf.channel->band];
+ rate = sband->bitrates[rateidx].hw_value;
+ if (vif->bss_conf.use_short_preamble)
+@@ -111,7 +107,7 @@ static void ath_beacon_setup(struct ath_
+ ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
+ }
+
+-static void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
++static void ath9k_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
+ {
+ struct ath_softc *sc = hw->priv;
+ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+@@ -128,28 +124,22 @@ static void ath_tx_cabq(struct ieee80211
+ }
+ }
+
+-static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
+- struct ieee80211_vif *vif)
++static struct ath_buf *ath9k_beacon_generate(struct ieee80211_hw *hw,
++ struct ieee80211_vif *vif)
+ {
+ struct ath_softc *sc = hw->priv;
+ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+ struct ath_buf *bf;
+- struct ath_vif *avp;
++ struct ath_vif *avp = (void *)vif->drv_priv;
+ struct sk_buff *skb;
+- struct ath_txq *cabq;
++ struct ath_txq *cabq = sc->beacon.cabq;
+ struct ieee80211_tx_info *info;
++ struct ieee80211_mgmt *mgmt_hdr;
+ int cabq_depth;
+
+- ath9k_reset_beacon_status(sc);
+-
+- avp = (void *)vif->drv_priv;
+- cabq = sc->beacon.cabq;
+-
+- if ((avp->av_bcbuf == NULL) || !avp->is_bslot_active)
++ if (avp->av_bcbuf == NULL)
+ return NULL;
+
+- /* Release the old beacon first */
+-
+ bf = avp->av_bcbuf;
+ skb = bf->bf_mpdu;
+ if (skb) {
+@@ -159,14 +149,14 @@ static struct ath_buf *ath_beacon_genera
+ bf->bf_buf_addr = 0;
+ }
+
+- /* Get a new beacon from mac80211 */
+-
+ skb = ieee80211_beacon_get(hw, vif);
+- bf->bf_mpdu = skb;
+ if (skb == NULL)
+ return NULL;
+- ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
+- avp->tsf_adjust;
++
++ bf->bf_mpdu = skb;
++
++ mgmt_hdr = (struct ieee80211_mgmt *)skb->data;
++ mgmt_hdr->u.beacon.timestamp = avp->tsf_adjust;
+
+ info = IEEE80211_SKB_CB(skb);
+ if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
+@@ -212,61 +202,52 @@ static struct ath_buf *ath_beacon_genera
+ }
+ }
+
+- ath_beacon_setup(sc, vif, bf, info->control.rates[0].idx);
++ ath9k_beacon_setup(sc, vif, bf, info->control.rates[0].idx);
+
+ while (skb) {
+- ath_tx_cabq(hw, skb);
++ ath9k_tx_cabq(hw, skb);
+ skb = ieee80211_get_buffered_bc(hw, vif);
+ }
+
+ return bf;
+ }
+
+-int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif)
++void ath9k_beacon_assign_slot(struct ath_softc *sc, struct ieee80211_vif *vif)
+ {
+ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+- struct ath_vif *avp;
+- struct ath_buf *bf;
+- struct sk_buff *skb;
+- struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
+- __le64 tstamp;
++ struct ath_vif *avp = (void *)vif->drv_priv;
++ int slot;
+
+- avp = (void *)vif->drv_priv;
++ avp->av_bcbuf = list_first_entry(&sc->beacon.bbuf, struct ath_buf, list);
++ list_del(&avp->av_bcbuf->list);
+
+- /* Allocate a beacon descriptor if we haven't done so. */
+- if (!avp->av_bcbuf) {
+- /* Allocate beacon state for hostap/ibss. We know
+- * a buffer is available. */
+- avp->av_bcbuf = list_first_entry(&sc->beacon.bbuf,
+- struct ath_buf, list);
+- list_del(&avp->av_bcbuf->list);
+-
+- if (ath9k_uses_beacons(vif->type)) {
+- int slot;
+- /*
+- * Assign the vif to a beacon xmit slot. As
+- * above, this cannot fail to find one.
+- */
+- avp->av_bslot = 0;
+- for (slot = 0; slot < ATH_BCBUF; slot++)
+- if (sc->beacon.bslot[slot] == NULL) {
+- avp->av_bslot = slot;
+- avp->is_bslot_active = false;
+-
+- /* NB: keep looking for a double slot */
+- if (slot == 0 || !sc->beacon.bslot[slot-1])
+- break;
+- }
+- BUG_ON(sc->beacon.bslot[avp->av_bslot] != NULL);
+- sc->beacon.bslot[avp->av_bslot] = vif;
+- sc->nbcnvifs++;
++ for (slot = 0; slot < ATH_BCBUF; slot++) {
++ if (sc->beacon.bslot[slot] == NULL) {
++ avp->av_bslot = slot;
++ break;
+ }
+ }
+
+- /* release the previous beacon frame, if it already exists. */
+- bf = avp->av_bcbuf;
+- if (bf->bf_mpdu != NULL) {
+- skb = bf->bf_mpdu;
++ sc->beacon.bslot[avp->av_bslot] = vif;
++ sc->nbcnvifs++;
++
++ ath_dbg(common, CONFIG, "Added interface at beacon slot: %d\n",
++ avp->av_bslot);
++}
++
++void ath9k_beacon_remove_slot(struct ath_softc *sc, struct ieee80211_vif *vif)
++{
++ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
++ struct ath_vif *avp = (void *)vif->drv_priv;
++ struct ath_buf *bf = avp->av_bcbuf;
++
++ ath_dbg(common, CONFIG, "Removing interface at beacon slot: %d\n",
++ avp->av_bslot);
++
++ tasklet_disable(&sc->bcon_tasklet);
++
++ if (bf && bf->bf_mpdu) {
++ struct sk_buff *skb = bf->bf_mpdu;
+ dma_unmap_single(sc->dev, bf->bf_buf_addr,
+ skb->len, DMA_TO_DEVICE);
+ dev_kfree_skb_any(skb);
+@@ -274,99 +255,74 @@ int ath_beacon_alloc(struct ath_softc *s
+ bf->bf_buf_addr = 0;
+ }
+
+- /* NB: the beacon data buffer must be 32-bit aligned. */
+- skb = ieee80211_beacon_get(sc->hw, vif);
+- if (skb == NULL)
+- return -ENOMEM;
+-
+- tstamp = ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp;
+- sc->beacon.bc_tstamp = (u32) le64_to_cpu(tstamp);
+- /* Calculate a TSF adjustment factor required for staggered beacons. */
+- if (avp->av_bslot > 0) {
+- u64 tsfadjust;
+- int intval;
++ avp->av_bcbuf = NULL;
++ sc->beacon.bslot[avp->av_bslot] = NULL;
++ sc->nbcnvifs--;
++ list_add_tail(&bf->list, &sc->beacon.bbuf);
+
+- intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL;
++ tasklet_enable(&sc->bcon_tasklet);
++}
+
+- /*
+- * Calculate the TSF offset for this beacon slot, i.e., the
+- * number of usecs that need to be added to the timestamp field
+- * in Beacon and Probe Response frames. Beacon slot 0 is
+- * processed at the correct offset, so it does not require TSF
+- * adjustment. Other slots are adjusted to get the timestamp
+- * close to the TBTT for the BSS.
+- */
+- tsfadjust = TU_TO_USEC(intval * avp->av_bslot) / ATH_BCBUF;
+- avp->tsf_adjust = cpu_to_le64(tsfadjust);
++static int ath9k_beacon_choose_slot(struct ath_softc *sc)
++{
++ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
++ struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
++ u16 intval;
++ u32 tsftu;
++ u64 tsf;
++ int slot;
+
+- ath_dbg(common, BEACON,
+- "stagger beacons, bslot %d intval %u tsfadjust %llu\n",
+- avp->av_bslot, intval, (unsigned long long)tsfadjust);
++ if (sc->sc_ah->opmode != NL80211_IFTYPE_AP) {
++ ath_dbg(common, BEACON, "slot 0, tsf: %llu\n",
++ ath9k_hw_gettsf64(sc->sc_ah));
++ return 0;
++ }
+
+- ((struct ieee80211_mgmt *)skb->data)->u.beacon.timestamp =
+- avp->tsf_adjust;
+- } else
+- avp->tsf_adjust = cpu_to_le64(0);
++ intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL;
++ tsf = ath9k_hw_gettsf64(sc->sc_ah);
++ tsf += TU_TO_USEC(sc->sc_ah->config.sw_beacon_response_time);
++ tsftu = TSF_TO_TU((tsf * ATH_BCBUF) >>32, tsf * ATH_BCBUF);
++ slot = (tsftu % (intval * ATH_BCBUF)) / intval;
+
+- bf->bf_mpdu = skb;
+- bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
+- skb->len, DMA_TO_DEVICE);
+- if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
+- dev_kfree_skb_any(skb);
+- bf->bf_mpdu = NULL;
+- bf->bf_buf_addr = 0;
+- ath_err(common, "dma_mapping_error on beacon alloc\n");
+- return -ENOMEM;
+- }
+- avp->is_bslot_active = true;
++ ath_dbg(common, BEACON, "slot: %d tsf: %llu tsftu: %u\n",
++ slot, tsf, tsftu / ATH_BCBUF);
+
+- return 0;
++ return slot;
+ }
+
+-void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp)
++void ath9k_set_tsfadjust(struct ath_softc *sc, struct ieee80211_vif *vif)
+ {
+- if (avp->av_bcbuf != NULL) {
+- struct ath_buf *bf;
++ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
++ struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
++ struct ath_vif *avp = (void *)vif->drv_priv;
++ u64 tsfadjust;
+
+- avp->is_bslot_active = false;
+- if (avp->av_bslot != -1) {
+- sc->beacon.bslot[avp->av_bslot] = NULL;
+- sc->nbcnvifs--;
+- avp->av_bslot = -1;
+- }
++ if (avp->av_bslot == 0)
++ return;
+
+- bf = avp->av_bcbuf;
+- if (bf->bf_mpdu != NULL) {
+- struct sk_buff *skb = bf->bf_mpdu;
+- dma_unmap_single(sc->dev, bf->bf_buf_addr,
+- skb->len, DMA_TO_DEVICE);
+- dev_kfree_skb_any(skb);
+- bf->bf_mpdu = NULL;
+- bf->bf_buf_addr = 0;
+- }
+- list_add_tail(&bf->list, &sc->beacon.bbuf);
++ tsfadjust = cur_conf->beacon_interval * avp->av_bslot / ATH_BCBUF;
++ avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
+
+- avp->av_bcbuf = NULL;
+- }
++ ath_dbg(common, CONFIG, "tsfadjust is: %llu for bslot: %d\n",
++ (unsigned long long)tsfadjust, avp->av_bslot);
+ }
+
+-void ath_beacon_tasklet(unsigned long data)
++void ath9k_beacon_tasklet(unsigned long data)
+ {
+ struct ath_softc *sc = (struct ath_softc *)data;
+- struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
+ struct ath_hw *ah = sc->sc_ah;
+ struct ath_common *common = ath9k_hw_common(ah);
+ struct ath_buf *bf = NULL;
+ struct ieee80211_vif *vif;
+ bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
+ int slot;
+- u32 bfaddr, bc = 0;
+
+- if (work_pending(&sc->hw_reset_work)) {
++ if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
+ ath_dbg(common, RESET,
+ "reset work is pending, skip beaconing now\n");
+ return;
+ }
++
+ /*
+ * Check if the previous beacon has gone out. If
+ * not don't try to post another, skip this period
+@@ -390,55 +346,25 @@ void ath_beacon_tasklet(unsigned long da
+ } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
+ ath_dbg(common, BSTUCK, "beacon is officially stuck\n");
+ sc->beacon.bmisscnt = 0;
+- set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
+- ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
++ ath9k_queue_reset(sc, RESET_TYPE_BEACON_STUCK);
+ }
+
+ return;
+ }
+
+- /*
+- * Generate beacon frames. we are sending frames
+- * staggered so calculate the slot for this frame based
+- * on the tsf to safeguard against missing an swba.
+- */
+-
+-
+- if (ah->opmode == NL80211_IFTYPE_AP) {
+- u16 intval;
+- u32 tsftu;
+- u64 tsf;
+-
+- intval = cur_conf->beacon_interval ? : ATH_DEFAULT_BINTVAL;
+- tsf = ath9k_hw_gettsf64(ah);
+- tsf += TU_TO_USEC(ah->config.sw_beacon_response_time);
+- tsftu = TSF_TO_TU((tsf * ATH_BCBUF) >>32, tsf * ATH_BCBUF);
+- slot = (tsftu % (intval * ATH_BCBUF)) / intval;
+- vif = sc->beacon.bslot[slot];
+-
+- ath_dbg(common, BEACON,
+- "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
+- slot, tsf, tsftu / ATH_BCBUF, intval, vif);
+- } else {
+- slot = 0;
+- vif = sc->beacon.bslot[slot];
+- }
++ slot = ath9k_beacon_choose_slot(sc);
++ vif = sc->beacon.bslot[slot];
+
++ if (!vif || !vif->bss_conf.enable_beacon)
++ return;
+
+- bfaddr = 0;
+- if (vif) {
+- bf = ath_beacon_generate(sc->hw, vif);
+- if (bf != NULL) {
+- bfaddr = bf->bf_daddr;
+- bc = 1;
+- }
++ bf = ath9k_beacon_generate(sc->hw, vif);
++ WARN_ON(!bf);
+
+- if (sc->beacon.bmisscnt != 0) {
+- ath_dbg(common, BSTUCK,
+- "resume beacon xmit after %u misses\n",
+- sc->beacon.bmisscnt);
+- sc->beacon.bmisscnt = 0;
+- }
++ if (sc->beacon.bmisscnt != 0) {
++ ath_dbg(common, BSTUCK, "resume beacon xmit after %u misses\n",
++ sc->beacon.bmisscnt);
++ sc->beacon.bmisscnt = 0;
+ }
+
+ /*
+@@ -458,39 +384,37 @@ void ath_beacon_tasklet(unsigned long da
+ * set to ATH_BCBUF so this check is a noop.
+ */
+ if (sc->beacon.updateslot == UPDATE) {
+- sc->beacon.updateslot = COMMIT; /* commit next beacon */
++ sc->beacon.updateslot = COMMIT;
+ sc->beacon.slotupdate = slot;
+- } else if (sc->beacon.updateslot == COMMIT && sc->beacon.slotupdate == slot) {
++ } else if (sc->beacon.updateslot == COMMIT &&
++ sc->beacon.slotupdate == slot) {
+ ah->slottime = sc->beacon.slottime;
+ ath9k_hw_init_global_settings(ah);
+ sc->beacon.updateslot = OK;
+ }
+- if (bfaddr != 0) {
++
++ if (bf) {
++ ath9k_reset_beacon_status(sc);
++
+ /* NB: cabq traffic should already be queued and primed */
+- ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bfaddr);
++ ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr);
+
+ if (!edma)
+ ath9k_hw_txstart(ah, sc->beacon.beaconq);
+-
+- sc->beacon.ast_be_xmit += bc; /* XXX per-vif? */
+ }
+ }
+
+-static void ath9k_beacon_init(struct ath_softc *sc,
+- u32 next_beacon,
+- u32 beacon_period)
++static void ath9k_beacon_init(struct ath_softc *sc, u32 nexttbtt, u32 intval)
+ {
+- if (test_bit(SC_OP_TSF_RESET, &sc->sc_flags)) {
+- ath9k_ps_wakeup(sc);
+- ath9k_hw_reset_tsf(sc->sc_ah);
+- }
+-
+- ath9k_hw_beaconinit(sc->sc_ah, next_beacon, beacon_period);
++ struct ath_hw *ah = sc->sc_ah;
+
+- if (test_bit(SC_OP_TSF_RESET, &sc->sc_flags)) {
+- ath9k_ps_restore(sc);
+- clear_bit(SC_OP_TSF_RESET, &sc->sc_flags);
+- }
++ ath9k_hw_disable_interrupts(ah);
++ ath9k_hw_reset_tsf(ah);
++ ath9k_beaconq_config(sc);
++ ath9k_hw_beaconinit(ah, nexttbtt, intval);
++ sc->beacon.bmisscnt = 0;
++ ath9k_hw_set_interrupts(ah);
++ ath9k_hw_enable_interrupts(ah);
+ }
+
+ /*
+@@ -498,32 +422,27 @@ static void ath9k_beacon_init(struct ath
+ * burst together. For the former arrange for the SWBA to be delivered for each
+ * slot. Slots that are not occupied will generate nothing.
+ */
+-static void ath_beacon_config_ap(struct ath_softc *sc,
+- struct ath_beacon_config *conf)
++static void ath9k_beacon_config_ap(struct ath_softc *sc,
++ struct ath_beacon_config *conf)
+ {
+ struct ath_hw *ah = sc->sc_ah;
++ struct ath_common *common = ath9k_hw_common(ah);
+ u32 nexttbtt, intval;
+
+ /* NB: the beacon interval is kept internally in TU's */
+ intval = TU_TO_USEC(conf->beacon_interval);
+- intval /= ATH_BCBUF; /* for staggered beacons */
++ intval /= ATH_BCBUF;
+ nexttbtt = intval;
+
+- /*
+- * In AP mode we enable the beacon timers and SWBA interrupts to
+- * prepare beacon frames.
+- */
+- ah->imask |= ATH9K_INT_SWBA;
+- ath_beaconq_config(sc);
++ if (conf->enable_beacon)
++ ah->imask |= ATH9K_INT_SWBA;
++ else
++ ah->imask &= ~ATH9K_INT_SWBA;
+
+- /* Set the computed AP beacon timers */
++ ath_dbg(common, BEACON, "AP nexttbtt: %u intval: %u conf_intval: %u\n",
++ nexttbtt, intval, conf->beacon_interval);
+
+- ath9k_hw_disable_interrupts(ah);
+- set_bit(SC_OP_TSF_RESET, &sc->sc_flags);
+ ath9k_beacon_init(sc, nexttbtt, intval);
+- sc->beacon.bmisscnt = 0;
+- ath9k_hw_set_interrupts(ah);
+- ath9k_hw_enable_interrupts(ah);
+ }
+
+ /*
+@@ -534,8 +453,8 @@ static void ath_beacon_config_ap(struct
+ * we'll receive a BMISS interrupt when we stop seeing beacons from the AP
+ * we've associated with.
+ */
+-static void ath_beacon_config_sta(struct ath_softc *sc,
+- struct ath_beacon_config *conf)
++static void ath9k_beacon_config_sta(struct ath_softc *sc,
++ struct ath_beacon_config *conf)
+ {
+ struct ath_hw *ah = sc->sc_ah;
+ struct ath_common *common = ath9k_hw_common(ah);
+@@ -654,8 +573,8 @@ static void ath_beacon_config_sta(struct
+ ath9k_hw_enable_interrupts(ah);
+ }
+
+-static void ath_beacon_config_adhoc(struct ath_softc *sc,
+- struct ath_beacon_config *conf)
++static void ath9k_beacon_config_adhoc(struct ath_softc *sc,
++ struct ath_beacon_config *conf)
+ {
+ struct ath_hw *ah = sc->sc_ah;
+ struct ath_common *common = ath9k_hw_common(ah);
+@@ -669,82 +588,53 @@ static void ath_beacon_config_adhoc(stru
+ tsf = roundup(ath9k_hw_gettsf32(ah) + TU_TO_USEC(FUDGE), intval);
+ nexttbtt = tsf + intval;
+
+- ath_dbg(common, BEACON, "IBSS nexttbtt %u intval %u (%u)\n",
+- nexttbtt, intval, conf->beacon_interval);
+-
+- /*
+- * In IBSS mode enable the beacon timers but only enable SWBA interrupts
+- * if we need to manually prepare beacon frames. Otherwise we use a
+- * self-linked tx descriptor and let the hardware deal with things.
+- */
+- ah->imask |= ATH9K_INT_SWBA;
+-
+- ath_beaconq_config(sc);
++ if (conf->enable_beacon)
++ ah->imask |= ATH9K_INT_SWBA;
++ else
++ ah->imask &= ~ATH9K_INT_SWBA;
+
+- /* Set the computed ADHOC beacon timers */
++ ath_dbg(common, BEACON, "IBSS nexttbtt: %u intval: %u conf_intval: %u\n",
++ nexttbtt, intval, conf->beacon_interval);
+
+- ath9k_hw_disable_interrupts(ah);
+ ath9k_beacon_init(sc, nexttbtt, intval);
+- sc->beacon.bmisscnt = 0;
+-
+- ath9k_hw_set_interrupts(ah);
+- ath9k_hw_enable_interrupts(ah);
+ }
+
+-static bool ath9k_allow_beacon_config(struct ath_softc *sc,
+- struct ieee80211_vif *vif)
++bool ath9k_allow_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
+ {
+- struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
+ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+- struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+ struct ath_vif *avp = (void *)vif->drv_priv;
+
+- /*
+- * Can not have different beacon interval on multiple
+- * AP interface case
+- */
+- if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
+- (sc->nbcnvifs > 1) &&
+- (vif->type == NL80211_IFTYPE_AP) &&
+- (cur_conf->beacon_interval != bss_conf->beacon_int)) {
+- ath_dbg(common, CONFIG,
+- "Changing beacon interval of multiple AP interfaces !\n");
+- return false;
+- }
+- /*
+- * Can not configure station vif's beacon config
+- * while on AP opmode
+- */
+- if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) &&
+- (vif->type != NL80211_IFTYPE_AP)) {
+- ath_dbg(common, CONFIG,
+- "STA vif's beacon not allowed on AP mode\n");
+- return false;
++ if (sc->sc_ah->opmode == NL80211_IFTYPE_AP) {
++ if ((vif->type != NL80211_IFTYPE_AP) ||
++ (sc->nbcnvifs > 1)) {
++ ath_dbg(common, CONFIG,
++ "An AP interface is already present !\n");
++ return false;
++ }
+ }
+- /*
+- * Do not allow beacon config if HW was already configured
+- * with another STA vif
+- */
+- if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
+- (vif->type == NL80211_IFTYPE_STATION) &&
+- test_bit(SC_OP_BEACONS, &sc->sc_flags) &&
+- !avp->primary_sta_vif) {
+- ath_dbg(common, CONFIG,
+- "Beacon already configured for a station interface\n");
+- return false;
++
++ if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) {
++ if ((vif->type == NL80211_IFTYPE_STATION) &&
++ test_bit(SC_OP_BEACONS, &sc->sc_flags) &&
++ !avp->primary_sta_vif) {
++ ath_dbg(common, CONFIG,
++ "Beacon already configured for a station interface\n");
++ return false;
++ }
+ }
++
+ return true;
+ }
+
+-void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
++static void ath9k_cache_beacon_config(struct ath_softc *sc,
++ struct ieee80211_bss_conf *bss_conf)
+ {
++ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+ struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
+- struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
+
+- if (!ath9k_allow_beacon_config(sc, vif))
+- return;
++ ath_dbg(common, BEACON,
++ "Caching beacon data for BSS: %pM\n", bss_conf->bssid);
+
+- /* Setup the beacon configuration parameters */
+ cur_conf->beacon_interval = bss_conf->beacon_int;
+ cur_conf->dtim_period = bss_conf->dtim_period;
+ cur_conf->listen_interval = 1;
+@@ -769,73 +659,59 @@ void ath_beacon_config(struct ath_softc
+ if (cur_conf->dtim_period == 0)
+ cur_conf->dtim_period = 1;
+
+- ath_set_beacon(sc);
+ }
+
+-static bool ath_has_valid_bslot(struct ath_softc *sc)
++void ath9k_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif,
++ u32 changed)
+ {
+- struct ath_vif *avp;
+- int slot;
+- bool found = false;
++ struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
++ struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
+
+- for (slot = 0; slot < ATH_BCBUF; slot++) {
+- if (sc->beacon.bslot[slot]) {
+- avp = (void *)sc->beacon.bslot[slot]->drv_priv;
+- if (avp->is_bslot_active) {
+- found = true;
+- break;
+- }
++ ath9k_cache_beacon_config(sc, bss_conf);
++
++ if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION) {
++ ath9k_set_beacon(sc);
++ set_bit(SC_OP_BEACONS, &sc->sc_flags);
++ } else {
++ /*
++ * Take care of multiple interfaces when
++ * enabling/disabling SWBA.
++ */
++ if (changed & BSS_CHANGED_BEACON_ENABLED) {
++ if (!bss_conf->enable_beacon &&
++ (sc->nbcnvifs <= 1))
++ cur_conf->enable_beacon = false;
++ else if (bss_conf->enable_beacon)
++ cur_conf->enable_beacon = true;
+ }
++
++ ath9k_set_beacon(sc);
++
++ if (cur_conf->enable_beacon)
++ set_bit(SC_OP_BEACONS, &sc->sc_flags);
++ else
++ clear_bit(SC_OP_BEACONS, &sc->sc_flags);
+ }
+- return found;
+ }
+
+-
+-void ath_set_beacon(struct ath_softc *sc)
++void ath9k_set_beacon(struct ath_softc *sc)
+ {
+ struct ath_common *common = ath9k_hw_common(sc->sc_ah);
+ struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
+
+ switch (sc->sc_ah->opmode) {
+ case NL80211_IFTYPE_AP:
+- if (ath_has_valid_bslot(sc))
+- ath_beacon_config_ap(sc, cur_conf);
++ ath9k_beacon_config_ap(sc, cur_conf);
+ break;
+ case NL80211_IFTYPE_ADHOC:
+ case NL80211_IFTYPE_MESH_POINT:
+- ath_beacon_config_adhoc(sc, cur_conf);
++ ath9k_beacon_config_adhoc(sc, cur_conf);
+ break;
+ case NL80211_IFTYPE_STATION:
+- ath_beacon_config_sta(sc, cur_conf);
++ ath9k_beacon_config_sta(sc, cur_conf);
+ break;
+ default:
+ ath_dbg(common, CONFIG, "Unsupported beaconing mode\n");
+ return;
+ }
+-
+- set_bit(SC_OP_BEACONS, &sc->sc_flags);
+-}
+-
+-void ath9k_set_beaconing_status(struct ath_softc *sc, bool status)
+-{
+- struct ath_hw *ah = sc->sc_ah;
+-
+- if (!ath_has_valid_bslot(sc)) {
+- clear_bit(SC_OP_BEACONS, &sc->sc_flags);
+- return;
+- }
+-
+- ath9k_ps_wakeup(sc);
+- if (status) {
+- /* Re-enable beaconing */
+- ah->imask |= ATH9K_INT_SWBA;
+- ath9k_hw_set_interrupts(ah);
+- } else {
+- /* Disable SWBA interrupt */
+- ah->imask &= ~ATH9K_INT_SWBA;
+- ath9k_hw_set_interrupts(ah);
+- tasklet_kill(&sc->bcon_tasklet);
+- ath9k_hw_stop_dma_queue(ah, sc->beacon.beaconq);
+- }
+- ath9k_ps_restore(sc);
+ }
+--- a/drivers/net/wireless/ath/ath9k/calib.h
++++ b/drivers/net/wireless/ath/ath9k/calib.h
+@@ -30,10 +30,10 @@ struct ar5416IniArray {
+ u32 ia_columns;
+ };
+
+-#define INIT_INI_ARRAY(iniarray, array, rows, columns) do { \
++#define INIT_INI_ARRAY(iniarray, array) do { \
+ (iniarray)->ia_array = (u32 *)(array); \
+- (iniarray)->ia_rows = (rows); \
+- (iniarray)->ia_columns = (columns); \
++ (iniarray)->ia_rows = ARRAY_SIZE(array); \
++ (iniarray)->ia_columns = ARRAY_SIZE(array[0]); \
+ } while (0)
+
+ #define INI_RA(iniarray, row, column) \
+--- a/drivers/net/wireless/ath/ath9k/debug.c
++++ b/drivers/net/wireless/ath/ath9k/debug.c
+@@ -206,10 +206,9 @@ static ssize_t write_file_disable_ani(st
+
+ if (disable_ani) {
+ clear_bit(SC_OP_ANI_RUN, &sc->sc_flags);
+- del_timer_sync(&common->ani.timer);
++ ath_stop_ani(sc);
+ } else {
+- set_bit(SC_OP_ANI_RUN, &sc->sc_flags);
+- ath_start_ani(common);
++ ath_check_ani(sc);
+ }
+
+ return count;
+@@ -1556,6 +1555,14 @@ int ath9k_init_debug(struct ath_hw *ah)
+ &fops_interrupt);
+ debugfs_create_file("xmit", S_IRUSR, sc->debug.debugfs_phy, sc,
+ &fops_xmit);
++ debugfs_create_u32("qlen_bk", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
++ &sc->tx.txq_max_pending[WME_AC_BK]);
++ debugfs_create_u32("qlen_be", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
++ &sc->tx.txq_max_pending[WME_AC_BE]);
++ debugfs_create_u32("qlen_vi", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
++ &sc->tx.txq_max_pending[WME_AC_VI]);
++ debugfs_create_u32("qlen_vo", S_IRUSR | S_IWUSR, sc->debug.debugfs_phy,
++ &sc->tx.txq_max_pending[WME_AC_VO]);
+ debugfs_create_file("stations", S_IRUSR, sc->debug.debugfs_phy, sc,
+ &fops_stations);
+ debugfs_create_file("misc", S_IRUSR, sc->debug.debugfs_phy, sc,
+--- a/drivers/net/wireless/ath/ath9k/debug.h
++++ b/drivers/net/wireless/ath/ath9k/debug.h
+@@ -32,6 +32,19 @@ struct ath_buf;
+ #define RESET_STAT_INC(sc, type) do { } while (0)
+ #endif
+
++enum ath_reset_type {
++ RESET_TYPE_BB_HANG,
++ RESET_TYPE_BB_WATCHDOG,
++ RESET_TYPE_FATAL_INT,
++ RESET_TYPE_TX_ERROR,
++ RESET_TYPE_TX_HANG,
++ RESET_TYPE_PLL_HANG,
++ RESET_TYPE_MAC_HANG,
++ RESET_TYPE_BEACON_STUCK,
++ RESET_TYPE_MCI,
++ __RESET_TYPE_MAX
++};
++
+ #ifdef CONFIG_ATH9K_DEBUGFS
+
+ /**
+@@ -209,17 +222,6 @@ struct ath_rx_stats {
+ u32 rx_frags;
+ };
+
+-enum ath_reset_type {
+- RESET_TYPE_BB_HANG,
+- RESET_TYPE_BB_WATCHDOG,
+- RESET_TYPE_FATAL_INT,
+- RESET_TYPE_TX_ERROR,
+- RESET_TYPE_TX_HANG,
+- RESET_TYPE_PLL_HANG,
+- RESET_TYPE_MAC_HANG,
+- __RESET_TYPE_MAX
+-};
+-
+ struct ath_stats {
+ struct ath_interrupt_stats istats;
+ struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
+--- a/drivers/net/wireless/ath/ath9k/eeprom.h
++++ b/drivers/net/wireless/ath/ath9k/eeprom.h
+@@ -241,16 +241,12 @@ enum eeprom_param {
+ EEP_TEMPSENSE_SLOPE,
+ EEP_TEMPSENSE_SLOPE_PAL_ON,
+ EEP_PWR_TABLE_OFFSET,
+- EEP_DRIVE_STRENGTH,
+- EEP_INTERNAL_REGULATOR,
+- EEP_SWREG,
+ EEP_PAPRD,
+ EEP_MODAL_VER,
+ EEP_ANT_DIV_CTL1,
+ EEP_CHAIN_MASK_REDUCE,
+ EEP_ANTENNA_GAIN_2G,
+ EEP_ANTENNA_GAIN_5G,
+- EEP_QUICK_DROP
+ };
+
+ enum ar5416_rates {