+void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
+{
+ void __iomem *base;
+ u32 t;
+
+ base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
+
+ t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
+ t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
+ if (mac)
+ t |= AR933X_ETH_CFG_SW_PHY_SWAP;
+ if (mdio)
+ t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
+ __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
+
+ iounmap(base);
+}
+
+void __init ath79_setup_ar934x_eth_cfg(u32 mask)
+{
+ void __iomem *base;
+ u32 t;
+
+ base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
+
+ t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
+
+ t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
+ AR934X_ETH_CFG_MII_GMAC0 |
+ AR934X_ETH_CFG_GMII_GMAC0 |
+ AR934X_ETH_CFG_SW_ONLY_MODE |
+ AR934X_ETH_CFG_SW_PHY_SWAP);
+
+ t |= mask;
+
+ __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
+ /* flush write */
+ __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
+
+ iounmap(base);
+}
+
+void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
+ unsigned int rxdv)
+{
+ void __iomem *base;
+ u32 t;
+
+ rxd &= AR934X_ETH_CFG_RXD_DELAY_MASK;
+ rxdv &= AR934X_ETH_CFG_RDV_DELAY_MASK;
+
+ base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
+
+ t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
+
+ t &= ~(AR934X_ETH_CFG_RXD_DELAY_MASK << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
+ AR934X_ETH_CFG_RDV_DELAY_MASK << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
+
+ t |= (rxd << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
+ rxdv << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
+
+ __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
+ /* flush write */
+ __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
+
+ iounmap(base);
+}
+
+void __init ath79_setup_qca955x_eth_cfg(u32 mask)
+{
+ void __iomem *base;
+ u32 t;
+
+ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
+
+ t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
+
+ t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
+
+ t |= mask;
+
+ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
+
+ iounmap(base);
+}
+
+void __init ath79_setup_qca956x_eth_cfg(u32 mask)
+{
+ void __iomem *base;
+ u32 t;
+
+ base = ioremap(QCA956X_GMAC_BASE, QCA956X_GMAC_SIZE);
+
+ t = __raw_readl(base + QCA956X_GMAC_REG_ETH_CFG);
+
+ t &= ~(QCA956X_ETH_CFG_SW_ONLY_MODE |
+ QCA956X_ETH_CFG_SW_PHY_SWAP);
+
+ t |= mask;
+
+ __raw_writel(t, base + QCA956X_GMAC_REG_ETH_CFG);
+ /* flush write */
+ __raw_readl(base + QCA956X_GMAC_REG_ETH_CFG);
+
+ iounmap(base);
+}
+