AArch64: Disable Secure Cycle Counter

[project/bcm63xx/atf.git] / bl1 / aarch64 / bl1_exceptions.S

diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S
index 19a0ac27a77e803a69fb51f1e5afd655ad3307fd..ed7c27a184032a2ea810c2bef6bb1d79b74a8a6a 100644 (file)
--- a/bl1/aarch64/bl1_exceptions.S
+++ b/bl1/aarch64/bl1_exceptions.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -223,6 +223,14 @@ smc_handler:
         */
        bl      save_gp_registers
 
+       /* -----------------------------------------------------
+        * If Secure Cycle Counter is not disabled in MDCR_EL3
+        * when ARMv8.5-PMU is implemented, save PMCR_EL0 and
+        * disable all event counters and cycle counter.
+        * -----------------------------------------------------
+        */
+       bl      save_pmcr_disable_pmu
+
        /* -----------------------------------------------------
         * Populate the parameters for the SMC handler. We
         * already have x0-x4 in place. x5 will point to a