Add Broadcom's code for bcm63xx support
[project/bcm63xx/atf.git] / fdts / rtsm_ve-motherboard.dtsi
index 6aa40ff4bb9ff44324eb537adb846fefbe0c0caf..486f8a985855d9c8b51961c9358a769eb2bd972f 100644 (file)
@@ -1,31 +1,7 @@
 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * Neither the name of ARM nor the names of its contributors may be used
- * to endorse or promote products derived from this software without specific
- * prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
        motherboard {
@@ -33,7 +9,6 @@
                compatible = "arm,vexpress,v2m-p1", "simple-bus";
                #address-cells = <2>; /* SMB chipselect number and offset */
                #size-cells = <1>;
-               #interrupt-cells = <1>;
                ranges;
 
                flash@0,00000000 {
@@ -51,7 +26,7 @@
                ethernet@2,02000000 {
                        compatible = "smsc,lan91c111";
                        reg = <2 0x02000000 0x10000>;
-                       interrupts = <15>;
+                       interrupts = <0 15 4>;
                };
 
                v2m_clk24mhz: clk24mhz {
                        #size-cells = <1>;
                        ranges = <0 3 0 0x200000>;
 
-                       v2m_sysreg: sysreg@010000 {
+                       v2m_sysreg: sysreg@10000 {
                                compatible = "arm,vexpress-sysreg";
                                reg = <0x010000 0x1000>;
                                gpio-controller;
                                #gpio-cells = <2>;
                        };
 
-                       v2m_sysctl: sysctl@020000 {
+                       v2m_sysctl: sysctl@20000 {
                                compatible = "arm,sp810", "arm,primecell";
                                reg = <0x020000 0x1000>;
                                clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
                                clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
                        };
 
-                       aaci@040000 {
+                       aaci@40000 {
                                compatible = "arm,pl041", "arm,primecell";
                                reg = <0x040000 0x1000>;
-                               interrupts = <11>;
+                               interrupts = <0 11 4>;
                                clocks = <&v2m_clk24mhz>;
                                clock-names = "apb_pclk";
                        };
 
-                       mmci@050000 {
+                       mmci@50000 {
                                compatible = "arm,pl180", "arm,primecell";
                                reg = <0x050000 0x1000>;
-                               interrupts = <9 10>;
+                               interrupts = <0 9 4 0 10 4>;
                                cd-gpios = <&v2m_sysreg 0 0>;
                                wp-gpios = <&v2m_sysreg 1 0>;
                                max-frequency = <12000000>;
                                clock-names = "mclk", "apb_pclk";
                        };
 
-                       kmi@060000 {
+                       kmi@60000 {
                                compatible = "arm,pl050", "arm,primecell";
                                reg = <0x060000 0x1000>;
-                               interrupts = <12>;
+                               interrupts = <0 12 4>;
                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
                                clock-names = "KMIREFCLK", "apb_pclk";
                        };
 
-                       kmi@070000 {
+                       kmi@70000 {
                                compatible = "arm,pl050", "arm,primecell";
                                reg = <0x070000 0x1000>;
-                               interrupts = <13>;
+                               interrupts = <0 13 4>;
                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
                                clock-names = "KMIREFCLK", "apb_pclk";
                        };
 
-                       v2m_serial0: uart@090000 {
+                       v2m_serial0: uart@90000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0x090000 0x1000>;
-                               interrupts = <5>;
+                               interrupts = <0 5 4>;
                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
                                clock-names = "uartclk", "apb_pclk";
                        };
 
-                       v2m_serial1: uart@0a0000 {
+                       v2m_serial1: uart@a0000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0x0a0000 0x1000>;
-                               interrupts = <6>;
+                               interrupts = <0 6 4>;
                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
                                clock-names = "uartclk", "apb_pclk";
                        };
 
-                       v2m_serial2: uart@0b0000 {
+                       v2m_serial2: uart@b0000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0x0b0000 0x1000>;
-                               interrupts = <7>;
+                               interrupts = <0 7 4>;
                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
                                clock-names = "uartclk", "apb_pclk";
                        };
 
-                       v2m_serial3: uart@0c0000 {
+                       v2m_serial3: uart@c0000 {
                                compatible = "arm,pl011", "arm,primecell";
                                reg = <0x0c0000 0x1000>;
-                               interrupts = <8>;
+                               interrupts = <0 8 4>;
                                clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
                                clock-names = "uartclk", "apb_pclk";
                        };
 
-                       wdt@0f0000 {
+                       wdt@f0000 {
                                compatible = "arm,sp805", "arm,primecell";
                                reg = <0x0f0000 0x1000>;
-                               interrupts = <0>;
+                               interrupts = <0 0 4>;
                                clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
                                clock-names = "wdogclk", "apb_pclk";
                        };
                        v2m_timer01: timer@110000 {
                                compatible = "arm,sp804", "arm,primecell";
                                reg = <0x110000 0x1000>;
-                               interrupts = <2>;
+                               interrupts = <0 2 4>;
                                clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
                                clock-names = "timclken1", "timclken2", "apb_pclk";
                        };
                        v2m_timer23: timer@120000 {
                                compatible = "arm,sp804", "arm,primecell";
                                reg = <0x120000 0x1000>;
-                               interrupts = <3>;
+                               interrupts = <0 3 4>;
                                clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
                                clock-names = "timclken1", "timclken2", "apb_pclk";
                        };
                        rtc@170000 {
                                compatible = "arm,pl031", "arm,primecell";
                                reg = <0x170000 0x1000>;
-                               interrupts = <4>;
+                               interrupts = <0 4 4>;
                                clocks = <&v2m_clk24mhz>;
                                clock-names = "apb_pclk";
                        };
                        clcd@1f0000 {
                                compatible = "arm,pl111", "arm,primecell";
                                reg = <0x1f0000 0x1000>;
-                               interrupts = <14>;
+                               interrupts = <0 14 4>;
                                clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
                                clock-names = "clcdclk", "apb_pclk";
                                mode = "XVGA";
                                framebuffer = <0x18000000 0x00180000>;
                        };
 
-                       virtio_block@0130000 {
+                       virtio_block@130000 {
                                compatible = "virtio,mmio";
                                reg = <0x130000 0x1000>;
-                               interrupts = <0x2a>;
+                               interrupts = <0 0x2a 4>;
                        };
                };
 
-               v2m_fixed_3v3: fixedregulator@0 {
+               v2m_fixed_3v3: fixedregulator {
                        compatible = "regulator-fixed";
                        regulator-name = "3V3";
                        regulator-min-microvolt = <3300000>;
                        compatible = "arm,vexpress,config-bus", "simple-bus";
                        arm,vexpress,config-bridge = <&v2m_sysreg>;
 
-                       v2m_oscclk1: osc@1 {
+                       v2m_oscclk1: osc {
                                /* CLCD clock */
                                compatible = "arm,vexpress-osc";
                                arm,vexpress-sysreg,func = <1 1>;
                         * };
                         */
 
-                       muxfpga@0 {
+                       muxfpga {
                                compatible = "arm,vexpress-muxfpga";
                                arm,vexpress-sysreg,func = <7 0>;
                        };
                         * };
                         */
 
-                       dvimode@0 {
+                       dvimode {
                                compatible = "arm,vexpress-dvimode";
                                arm,vexpress-sysreg,func = <11 0>;
                        };