uboot-sunxi: update to version 2017.07
[openwrt/staging/stintel.git] / package / boot / uboot-sunxi / patches / 093-sun6i-fix-PLL-LDO-voltselect.patch
index d200633bc20839e027d4331f07344b38bddddc1f..a8e03e2fb2ccf95ee43b9c0130dd67a3fe261b23 100644 (file)
@@ -16,9 +16,9 @@ order of magnitude as Boot1.
 Furthermore, a bit of documentation is added to clarify that the
 required setting for the PLL LDO is 1.37v as per the A31 manual.
 
---- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
-+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
-@@ -24,14 +24,27 @@ void clock_init_safe(void)
+--- a/arch/arm/mach-sunxi/clock_sun6i.c
++++ b/arch/arm/mach-sunxi/clock_sun6i.c
+@@ -26,13 +26,26 @@ void clock_init_safe(void)
        struct sunxi_prcm_reg * const prcm =
                (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
  
@@ -34,9 +34,9 @@ required setting for the PLL LDO is 1.37v as per the A31 manual.
        clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
                PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
 -              PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
-+              PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370) );
++              PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1370));
        clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
++
 +      /* Give the PLL LDO voltage setting some time to take hold.
 +       * Notes:
 +       *   1) We need to use sdelay() as the timers aren't set up yet.
@@ -44,10 +44,9 @@ required setting for the PLL LDO is 1.37v as per the A31 manual.
 +       *      iterations through a loop.
 +       */
 +      sdelay(100000);
-+
-       clock_set_pll1(408000000);
+ #endif
  
-       writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
+ #if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
 --- a/arch/arm/include/asm/arch-sunxi/prcm.h
 +++ b/arch/arm/include/asm/arch-sunxi/prcm.h
 @@ -111,13 +111,13 @@