Sanitise includes across codebase

[project/bcm63xx/atf.git] / plat / arm / common / arm_tzc_dmc500.c

diff --git a/plat/arm/common/arm_tzc_dmc500.c b/plat/arm/common/arm_tzc_dmc500.c
index 8e41391f5d3d6418333dca315e20aa538168c65d..bea3867d37536d1b1f088bd7f22c4a6ed476f971 100644 (file)
--- a/plat/arm/common/arm_tzc_dmc500.c
+++ b/plat/arm/common/arm_tzc_dmc500.c
@@ -1,26 +1,36 @@
 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <arm_def.h>
 #include <assert.h>
-#include <debug.h>
+
 #include <platform_def.h>
-#include <tzc_dmc500.h>
+
+#include <common/debug.h>
+#include <drivers/arm/tzc_dmc500.h>
+
+#include <arm_def.h>
+#include <plat_arm.h>
 
 /*******************************************************************************
  * Initialize the DMC500-TrustZone Controller for ARM standard platforms.
- * Configure both the interfaces on Region 0 with no access, Region 1 with
- * secure access only, and the remaining DRAM regions access from the
- * given Non-Secure masters.
- *
  * When booting an EL3 payload, this is simplified: we configure region 0 with
  * secure access only and do not enable any other region.
  ******************************************************************************/
-void arm_tzc_dmc500_setup(tzc_dmc500_driver_data_t *plat_driver_data)
+void arm_tzc_dmc500_setup(tzc_dmc500_driver_data_t *plat_driver_data,
+                       const arm_tzc_regions_info_t *tzc_regions)
 {
+#ifndef EL3_PAYLOAD_BASE
+       unsigned int region_index = 1U;
+       const arm_tzc_regions_info_t *p;
+       const arm_tzc_regions_info_t init_tzc_regions[] = {
+               ARM_TZC_REGIONS_DEF,
+               {0}
+       };
+#endif
+
        assert(plat_driver_data);
 
        INFO("Configuring DMC-500 TZ Settings\n");
@@ -28,28 +38,23 @@ void arm_tzc_dmc500_setup(tzc_dmc500_driver_data_t *plat_driver_data)
        tzc_dmc500_driver_init(plat_driver_data);
 
 #ifndef EL3_PAYLOAD_BASE
+       if (tzc_regions == NULL)
+               p = init_tzc_regions;
+       else
+               p = tzc_regions;
+
        /* Region 0 set to no access by default */
        tzc_dmc500_configure_region0(TZC_REGION_S_NONE, 0);
 
-       /* Region 1 set to cover Secure part of DRAM */
-       tzc_dmc500_configure_region(1, ARM_AP_TZC_DRAM1_BASE,
-               ARM_EL3_TZC_DRAM1_END,
-               TZC_REGION_S_RDWR,
-               0);
+       /* Rest Regions set according to tzc_regions array */
+       for (; p->base != 0ULL; p++) {
+               tzc_dmc500_configure_region(region_index, p->base, p->end,
+                                           p->sec_attr, p->nsaid_permissions);
+               region_index++;
+       }
 
-       /* Region 2 set to cover Non-Secure access to 1st DRAM address range.*/
-       tzc_dmc500_configure_region(2,
-               ARM_NS_DRAM1_BASE,
-               ARM_NS_DRAM1_END,
-               ARM_TZC_NS_DRAM_S_ACCESS,
-               PLAT_ARM_TZC_NS_DEV_ACCESS);
+       INFO("Total %u regions set.\n", region_index);
 
-       /* Region 3 set to cover Non-Secure access to 2nd DRAM address range */
-       tzc_dmc500_configure_region(3,
-               ARM_DRAM2_BASE,
-               ARM_DRAM2_END,
-               ARM_TZC_NS_DRAM_S_ACCESS,
-               PLAT_ARM_TZC_NS_DEV_ACCESS);
 #else
        /* Allow secure access only to DRAM for EL3 payloads */
        tzc_dmc500_configure_region0(TZC_REGION_S_RDWR, 0);