ar71xx: add AR933x specific glue code for IRQ initialization

[openwrt/staging/yousong.git] / target / linux / ar71xx / files / arch / mips / ar71xx / irq.c

diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c
index 352548c4ef851dd5d0a6c61b20fd3459dcdfb83a..ff4d9ead7edb7c8c2edfe8cb7b366cef62b91487 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/irq.c
@@ -1,10 +1,12 @@
 /*
  *  Atheros AR71xx SoC specific interrupt handling
  *
+ *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  *
- *  Parts of this file are based on Atheros' 2.6.15 BSP
+ *  Parts of this file are based on Atheros 2.6.15 BSP
+ *  Parts of this file are based on Atheros 2.6.31 BSP
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  under the terms of the GNU General Public License version 2 as published
@@ -21,6 +23,8 @@
 
 #include <asm/mach-ar71xx/ar71xx.h>
 
+static int ip2_flush_reg;
+
 static void ar71xx_gpio_irq_dispatch(void)
 {
        void __iomem *base = ar71xx_gpio_base;
@@ -144,6 +148,21 @@ static void ar71xx_misc_irq_dispatch(void)
        else if (pending & MISC_INT_WDOG)
                do_IRQ(AR71XX_MISC_IRQ_WDOG);
 
+       else if (pending & MISC_INT_TIMER2)
+               do_IRQ(AR71XX_MISC_IRQ_TIMER2);
+
+       else if (pending & MISC_INT_TIMER3)
+               do_IRQ(AR71XX_MISC_IRQ_TIMER3);
+
+       else if (pending & MISC_INT_TIMER4)
+               do_IRQ(AR71XX_MISC_IRQ_TIMER4);
+
+       else if (pending & MISC_INT_DDR_PERF)
+               do_IRQ(AR71XX_MISC_IRQ_DDR_PERF);
+
+       else if (pending & MISC_INT_ENET_LINK)
+               do_IRQ(AR71XX_MISC_IRQ_ENET_LINK);
+
        else
                spurious_interrupt();
 }
@@ -209,10 +228,21 @@ static void __init ar71xx_misc_irq_init(void)
        __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
        __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
 
-       if (ar71xx_soc == AR71XX_SOC_AR7240)
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7240:
+       case AR71XX_SOC_AR7241:
+       case AR71XX_SOC_AR7242:
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
                ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
-       else
+               break;
+       default:
                ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
+               break;
+       }
 
        for (i = AR71XX_MISC_IRQ_BASE;
             i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) {
@@ -233,8 +263,17 @@ asmlinkage void plat_irq_dispatch(void)
        if (pending & STATUSF_IP7)
                do_IRQ(AR71XX_CPU_IRQ_TIMER);
 
-       else if (pending & STATUSF_IP2)
+       else if (pending & STATUSF_IP2) {
+               /*
+                * This IRQ is meant for a PCI device. Drivers for PCI devices
+                * typically allocate coherent DMA memory for the descriptor
+                * ring, however the DMA controller may still have some
+                * unsynchronized data in the FIFO.
+                * Issue a flush here to ensure that the driver sees the update.
+                */
+               ar71xx_ddr_flush(ip2_flush_reg);
                do_IRQ(AR71XX_CPU_IRQ_IP2);
+       }
 
        else if (pending & STATUSF_IP4)
                do_IRQ(AR71XX_CPU_IRQ_GE0);
@@ -254,6 +293,39 @@ asmlinkage void plat_irq_dispatch(void)
 
 void __init arch_init_irq(void)
 {
+       switch (ar71xx_soc) {
+       case AR71XX_SOC_AR7130:
+       case AR71XX_SOC_AR7141:
+       case AR71XX_SOC_AR7161:
+               ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
+               break;
+
+       case AR71XX_SOC_AR7240:
+       case AR71XX_SOC_AR7241:
+       case AR71XX_SOC_AR7242:
+               ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
+               break;
+
+       case AR71XX_SOC_AR9130:
+       case AR71XX_SOC_AR9132:
+               ip2_flush_reg = AR91XX_DDR_REG_FLUSH_WMAC;
+               break;
+
+       case AR71XX_SOC_AR9330:
+       case AR71XX_SOC_AR9331:
+               ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
+               break;
+
+       case AR71XX_SOC_AR9341:
+       case AR71XX_SOC_AR9342:
+       case AR71XX_SOC_AR9344:
+               ip2_flush_reg = AR934X_DDR_REG_FLUSH_PCIE;
+               break;
+
+       default:
+               BUG();
+       }
+
        mips_cpu_irq_init();
 
        ar71xx_misc_irq_init();