* by the Free Software Foundation.
*/
-#include <linux/init.h>
-#include <linux/bitops.h>
-#include <linux/input.h>
-#include <linux/platform_device.h>
-
-#include <asm/mips_machine.h>
#include <asm/mach-ar71xx/ar71xx.h>
-#include <asm/mach-ar71xx/pci.h>
+#include "machtype.h"
#include "devices.h"
#include "dev-m25p80.h"
+#include "dev-gpio-buttons.h"
+#include "dev-pb42-pci.h"
+#include "dev-usb.h"
-#define PB42_BUTTONS_POLL_INTERVAL 20
+#define PB42_KEYS_POLL_INTERVAL 20 /* msecs */
+#define PB42_KEYS_DEBOUNCE_INTERVAL (3 * PB42_KEYS_POLL_INTERVAL)
#define PB42_GPIO_BTN_SW4 8
#define PB42_GPIO_BTN_SW5 3
-static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = {
- {
- .slot = 0,
- .pin = 1,
- .irq = AR71XX_PCI_IRQ_DEV0,
- }, {
- .slot = 1,
- .pin = 1,
- .irq = AR71XX_PCI_IRQ_DEV1,
- }, {
- .slot = 2,
- .pin = 1,
- .irq = AR71XX_PCI_IRQ_DEV2,
- }
-};
-
-static struct gpio_button pb42_gpio_buttons[] __initdata = {
+static struct gpio_keys_button pb42_gpio_keys[] __initdata = {
{
.desc = "sw4",
.type = EV_KEY,
.code = BTN_0,
- .threshold = 5,
+ .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL,
.gpio = PB42_GPIO_BTN_SW4,
.active_low = 1,
- } , {
+ }, {
.desc = "sw5",
.type = EV_KEY,
.code = BTN_1,
- .threshold = 5,
+ .debounce_interval = PB42_KEYS_DEBOUNCE_INTERVAL,
.gpio = PB42_GPIO_BTN_SW5,
.active_low = 1,
}
ar71xx_add_device_mdio(~PB42_MDIO_PHYMASK);
+ ar71xx_init_mac(ar71xx_eth0_data.mac_addr, ar71xx_mac_base, 0);
ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ar71xx_eth0_data.phy_mask = PB42_WAN_PHYMASK;
+ ar71xx_init_mac(ar71xx_eth1_data.mac_addr, ar71xx_mac_base, 1);
ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII;
- ar71xx_eth1_data.phy_mask = PB42_LAN_PHYMASK;
ar71xx_eth1_data.speed = SPEED_100;
ar71xx_eth1_data.duplex = DUPLEX_FULL;
ar71xx_add_device_eth(0);
ar71xx_add_device_eth(1);
- ar71xx_add_device_gpio_buttons(-1, PB42_BUTTONS_POLL_INTERVAL,
- ARRAY_SIZE(pb42_gpio_buttons),
- pb42_gpio_buttons);
+ ar71xx_register_gpio_keys_polled(-1, PB42_KEYS_POLL_INTERVAL,
+ ARRAY_SIZE(pb42_gpio_keys),
+ pb42_gpio_keys);
- ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs);
+ pb42_pci_init();
}
-MIPS_MACHINE(AR71XX_MACH_PB42, "Atheros PB42", pb42_init);
+MIPS_MACHINE(AR71XX_MACH_PB42, "PB42", "Atheros PB42", pb42_init);