[ar71xx] ag71xx: introduce SoC specific fuctions for DDR flush and PLL setup

[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / ar71xx / setup.c

diff --git a/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c b/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
index 758f5414235e1d71b24c5fda7f10f509f746a7e3..a5d26e72c6e787aea9754799358d695cd51d6f9c 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
+++ b/target/linux/ar71xx/files/arch/mips/ar71xx/setup.c
@@ -149,7 +149,7 @@ static void __init ar91xx_detect_sys_frequency(void)
        u32 freq;
        u32 div;
 
-       pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
+       pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 
        div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
        freq = div * AR91XX_BASE_FREQ;
@@ -169,7 +169,7 @@ static void __init ar71xx_detect_sys_frequency(void)
        u32 freq;
        u32 div;
 
-       pll = ar71xx_pll_rr(PLL_REG_CPU_PLL_CFG);
+       pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 
        div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
        freq = div * AR71XX_BASE_FREQ;