enum ar71xx_soc_type ar71xx_soc;
EXPORT_SYMBOL_GPL(ar71xx_soc);
+u32 ar71xx_soc_rev;
+EXPORT_SYMBOL_GPL(ar71xx_soc_rev);
+
static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
static void ar71xx_restart(char *command)
}
break;
- case REV_ID_MAJOR_AR9341:
- ar71xx_soc = AR71XX_SOC_AR9341;
- chip = "9341";
- rev = id & AR934X_REV_ID_REVISION_MASK;
+ case REV_ID_MAJOR_AR9330:
+ ar71xx_soc = AR71XX_SOC_AR9330;
+ chip = "9330";
+ rev = id & AR933X_REV_ID_REVISION_MASK;
+ break;
+
+ case REV_ID_MAJOR_AR9331:
+ ar71xx_soc = AR71XX_SOC_AR9331;
+ chip = "9331";
+ rev = id & AR933X_REV_ID_REVISION_MASK;
break;
case REV_ID_MAJOR_AR9342:
panic("ar71xx: unknown chip id:0x%08x\n", id);
}
+ ar71xx_soc_rev = rev;
+
sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
pr_info("SoC: %s\n", ar71xx_sys_type);
}
ar71xx_ahb_freq = ar71xx_cpu_freq / div;
}
+static void __init ar933x_detect_sys_frequency(void)
+{
+ u32 clock_ctrl;
+ u32 cpu_config;
+ u32 freq;
+ u32 t;
+
+ t = ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
+ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
+ ar71xx_ref_freq = (40 * 1000 * 1000);
+ else
+ ar71xx_ref_freq = (25 * 1000 * 1000);
+
+ clock_ctrl = ar71xx_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
+ if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
+ ar71xx_cpu_freq = ar71xx_ref_freq;
+ ar71xx_ahb_freq = ar71xx_ref_freq;
+ ar71xx_ddr_freq = ar71xx_ref_freq;
+ } else {
+ cpu_config = ar71xx_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
+
+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
+ AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
+ freq = ar71xx_ref_freq / t;
+
+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
+ AR933X_PLL_CPU_CONFIG_NINT_MASK;
+ freq *= t;
+
+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
+ AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ if (t == 0)
+ t = 1;
+
+ freq >>= t;
+
+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
+ AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
+ ar71xx_cpu_freq = freq / t;
+
+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
+ AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
+ ar71xx_ddr_freq = freq / t;
+
+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
+ AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
+ ar71xx_ahb_freq = freq / t;
+ }
+}
+
static void __init detect_sys_frequency(void)
{
switch (ar71xx_soc) {
ar91xx_detect_sys_frequency();
break;
+ case AR71XX_SOC_AR9330:
+ case AR71XX_SOC_AR9331:
+ ar933x_detect_sys_frequency();
+ break;
+
case AR71XX_SOC_AR9341:
case AR71XX_SOC_AR9342:
case AR71XX_SOC_AR9344: