ar71xx: fix ethernet device registration for QCA9558

[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 7975464333a930c0ad73f36c35873307e4a5c8ec..043300c18802683561c55fccf6a8dcbfb0b23d83 100644 (file)
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -355,6 +355,26 @@ static void ar934x_set_speed_ge0(int speed)
        iounmap(base);
 }
 
+static void qca955x_set_speed_xmii(int speed)
+{
+       void __iomem *base;
+       u32 val = ath79_get_eth_pll(0, speed);
+
+       base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+       __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
+       iounmap(base);
+}
+
+static void qca955x_set_speed_sgmii(int speed)
+{
+       void __iomem *base;
+       u32 val = ath79_get_eth_pll(1, speed);
+
+       base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
+       __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
+       iounmap(base);
+}
+
 static void ath79_set_speed_dummy(int speed)
 {
 }
@@ -905,7 +925,6 @@ void __init ath79_register_eth(unsigned int id)
        case ATH79_SOC_AR9341:
        case ATH79_SOC_AR9342:
        case ATH79_SOC_AR9344:
-       case ATH79_SOC_QCA9558:
                if (id == 0) {
                        pdata->reset_bit = AR934X_RESET_GE0_MAC |
                                           AR934X_RESET_GE0_MDIO;
@@ -934,6 +953,29 @@ void __init ath79_register_eth(unsigned int id)
                        pdata->fifo_cfg3 = 0x01f00140;
                break;
 
+       case ATH79_SOC_QCA9558:
+               if (id == 0) {
+                       pdata->reset_bit = QCA955X_RESET_GE0_MAC |
+                                          QCA955X_RESET_GE0_MDIO;
+                       pdata->set_speed = qca955x_set_speed_xmii;
+               } else {
+                       pdata->reset_bit = QCA955X_RESET_GE1_MAC |
+                                          QCA955X_RESET_GE1_MDIO;
+                       pdata->set_speed = qca955x_set_speed_sgmii;
+               }
+
+               pdata->ddr_flush = ath79_ddr_no_flush;
+               pdata->has_gbit = 1;
+               pdata->is_ar724x = 1;
+
+               if (!pdata->fifo_cfg1)
+                       pdata->fifo_cfg1 = 0x0010ffff;
+               if (!pdata->fifo_cfg2)
+                       pdata->fifo_cfg2 = 0x015500aa;
+               if (!pdata->fifo_cfg3)
+                       pdata->fifo_cfg3 = 0x01f00140;
+               break;
+
        default:
                BUG();
        }