#define AR7240_MASK_CTRL_REVISION_M BITM(8)
#define AR7240_MASK_CTRL_VERSION_M BITM(8)
#define AR7240_MASK_CTRL_VERSION_S 8
+#define AR7240_MASK_CTRL_VERSION_AR7240 0x01
+#define AR7240_MASK_CTRL_VERSION_AR934X 0x02
#define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
#define AR7240_REG_MAC_ADDR0 0x20
#define AR7240_PHY_ID1 0x004d
#define AR7240_PHY_ID2 0xd041
-#define AR7240_PORT_MASK(_port) BIT((_port))
-#define AR7240_PORT_MASK_ALL BITM(AR7240_NUM_PORTS)
-#define AR7240_PORT_MASK_BUT(_port) (AR7240_PORT_MASK_ALL & ~BIT((_port)))
+#define AR934X_PHY_ID1 0x004d
+#define AR934X_PHY_ID2 0xd042
#define AR7240_MAX_VLANS 16
+#define AR934X_REG_OPER_MODE0 0x04
+#define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
+#define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
+
+#define AR934X_REG_OPER_MODE1 0x08
+#define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
+
#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
struct ar7240sw {
struct mii_bus *mii_bus;
+ struct ag71xx_switch_platform_data *swdata;
struct switch_dev swdev;
+ int num_ports;
+ u8 ver;
bool vlan;
u16 vlan_id[AR7240_MAX_VLANS];
u8 vlan_table[AR7240_MAX_VLANS];
static DEFINE_MUTEX(reg_mutex);
+static inline int sw_is_ar7240(struct ar7240sw *as)
+{
+ return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
+}
+
+static inline int sw_is_ar934x(struct ar7240sw *as)
+{
+ return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
+}
+
+static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
+{
+ return BIT(port);
+}
+
+static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
+{
+ return BIT(as->swdev.ports) - 1;
+}
+
+static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
+{
+ return ar7240sw_port_mask_all(as) & ~BIT(port);
+}
+
static inline u16 mk_phy_addr(u32 reg)
{
return 0x17 & ((reg >> 4) | 0x10);
if (!portmask) {
if (port == AR7240_PORT_CPU)
- portmask = AR7240_PORT_MASK_BUT(AR7240_PORT_CPU);
+ portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
else
- portmask = AR7240_PORT_MASK(AR7240_PORT_CPU);
+ portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
}
/* allow the port to talk to all other ports, but exclude its
* own ID to prevent frames from being reflected back to the
* port that they came from */
- portmask &= AR7240_PORT_MASK_BUT(port);
+ portmask &= ar7240sw_port_mask_but(as, port);
/* set default VID and and destination ports for this VLAN */
vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
int i;
val->len = 0;
- for (i = 0; i < AR7240_NUM_PORTS; i++) {
+ for (i = 0; i < as->swdev.ports; i++) {
struct switch_port *p;
if (!(ports & (1 << i)))
if (!vp)
continue;
- for (i = 0; i < AR7240_NUM_PORTS; i++) {
+ for (i = 0; i < as->swdev.ports; i++) {
u8 mask = (1 << i);
if (vp & mask)
portmask[i] |= vp & ~mask;
} else {
/* vlan disabled:
* isolate all ports, but connect them to the cpu port */
- for (i = 0; i < AR7240_NUM_PORTS; i++) {
+ for (i = 0; i < as->swdev.ports; i++) {
if (i == AR7240_PORT_CPU)
continue;
}
/* update the port destination mask registers and tag settings */
- for (i = 0; i < AR7240_NUM_PORTS; i++)
+ for (i = 0; i < as->swdev.ports; i++)
ar7240sw_setup_port(as, i, portmask[i]);
return 0;
static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
{
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
struct mii_bus *mii = ag->mii_bus;
struct ar7240sw *as;
struct switch_dev *swdev;
u32 ctrl;
u16 phy_id1;
u16 phy_id2;
- u8 ver;
int i;
+ phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
+ phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
+ if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
+ (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
+ pr_err("%s: unknown phy id '%04x:%04x'\n",
+ ag->dev->name, phy_id1, phy_id2);
+ return NULL;
+ }
+
as = kzalloc(sizeof(*as), GFP_KERNEL);
if (!as)
return NULL;
as->mii_bus = mii;
+ as->swdata = pdata->switch_data;
+
+ swdev = &as->swdev;
ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
+ as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
+ AR7240_MASK_CTRL_VERSION_M;
+
+ if (sw_is_ar7240(as)) {
+ swdev->name = "AR7240/AR9330 built-in switch";
+ } else if (sw_is_ar934x(as)) {
+ swdev->name = "AR934X built-in switch";
+
+ if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
+ ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
+ AR934X_OPER_MODE0_MAC_GMII_EN);
+ } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
+ ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
+ AR934X_OPER_MODE0_PHY_MII_EN);
+ } else {
+ pr_err("%s: invalid PHY interface mode\n",
+ ag->dev->name);
+ goto err_free;
+ }
- ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M;
- if (ver != 1) {
+ if (as->swdata->phy4_mii_en)
+ ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
+ AR934X_REG_OPER_MODE1_PHY4_MII_EN);
+ } else {
pr_err("%s: unsupported chip, ctrl=%08x\n",
ag->dev->name, ctrl);
- return NULL;
- }
-
- phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
- phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
- if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) {
- pr_err("%s: unknown phy id '%04x:%04x'\n",
- ag->dev->name, phy_id1, phy_id2);
- return NULL;
+ goto err_free;
}
- swdev = &as->swdev;
- swdev->name = "AR7240 built-in switch";
- swdev->ports = AR7240_NUM_PORTS;
+ swdev->ports = AR7240_NUM_PORTS - 1;
swdev->cpu_port = AR7240_PORT_CPU;
swdev->vlans = AR7240_MAX_VLANS;
swdev->ops = &ar7240_ops;
- if (register_switch(&as->swdev, ag->dev) < 0) {
- kfree(as);
- return NULL;
- }
+ if (register_switch(&as->swdev, ag->dev) < 0)
+ goto err_free;
- pr_info("%s: Found an AR7240 built-in switch\n", ag->dev->name);
+ pr_info("%s: Found an %s\n", ag->dev->name, swdev->name);
/* initialize defaults */
for (i = 0; i < AR7240_MAX_VLANS; i++)
as->vlan_id[i] = i;
- as->vlan_table[0] = AR7240_PORT_MASK_ALL;
+ as->vlan_table[0] = ar7240sw_port_mask_all(as);
return as;
+
+err_free:
+ kfree(as);
+ return NULL;
}
static void link_function(struct work_struct *work) {
projects / openwrt / staging / yousong.git / blobdiff