#define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
#define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
+#define AR7240_PORT_STATUS_SPEED_S 0
#define AR7240_PORT_STATUS_SPEED_M BITM(2)
#define AR7240_PORT_STATUS_SPEED_10 0
#define AR7240_PORT_STATUS_SPEED_100 1
#define AR7240_PHY_ID1 0x004d
#define AR7240_PHY_ID2 0xd041
-#define AR7240_PORT_MASK(_port) BIT((_port))
-#define AR7240_PORT_MASK_ALL BITM(AR7240_NUM_PORTS)
-#define AR7240_PORT_MASK_BUT(_port) (AR7240_PORT_MASK_ALL & ~BIT((_port)))
-
#define AR7240_MAX_VLANS 16
#define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
struct ar7240sw {
struct mii_bus *mii_bus;
+ struct ag71xx_switch_platform_data *swdata;
struct switch_dev swdev;
+ int num_ports;
bool vlan;
u16 vlan_id[AR7240_MAX_VLANS];
u8 vlan_table[AR7240_MAX_VLANS];
u8 vlan_tagged;
u16 pvid[AR7240_NUM_PORTS];
+ char buf[80];
};
struct ar7240sw_hw_stat {
static DEFINE_MUTEX(reg_mutex);
-static inline void ar7240sw_init(struct ar7240sw *as, struct mii_bus *mii)
+static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
{
- as->mii_bus = mii;
+ return BIT(port);
+}
+
+static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
+{
+ return BIT(as->swdev.ports) - 1;
+}
+
+static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
+{
+ return ar7240sw_port_mask_all(as) & ~BIT(port);
}
static inline u16 mk_phy_addr(u32 reg)
return ret;
}
-static int ar7240sw_capture_stats(struct ar7240sw *as)
-{
- struct mii_bus *mii = as->mii_bus;
- int ret;
-
- /* Capture the hardware statistics for all ports */
- ar7240sw_reg_write(mii, AR7240_REG_MIB_FUNCTION0,
- (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
-
- /* Wait for the capturing to complete. */
- ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
- AR7240_MIB_BUSY, 0, 10);
- return ret;
-}
-
static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
{
ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
{
struct mii_bus *mii = as->mii_bus;
u32 ctrl;
- u32 dest_ports;
u32 vlan;
ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
if (!portmask) {
if (port == AR7240_PORT_CPU)
- portmask = AR7240_PORT_MASK_BUT(AR7240_PORT_CPU);
+ portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
else
- portmask = AR7240_PORT_MASK(AR7240_PORT_CPU);
+ portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
}
/* allow the port to talk to all other ports, but exclude its
* own ID to prevent frames from being reflected back to the
* port that they came from */
- dest_ports = AR7240_PORT_MASK_BUT(port);
+ portmask &= ar7240sw_port_mask_but(as, port);
/* set default VID and and destination ports for this VLAN */
vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
int i;
val->len = 0;
- for (i = 0; i < AR7240_NUM_PORTS; i++) {
+ for (i = 0; i < as->swdev.ports; i++) {
struct switch_port *p;
if (!(ports & (1 << i)))
return 0;
}
+static const char *
+ar7240_speed_str(u32 status)
+{
+ u32 speed;
+
+ speed = (status >> AR7240_PORT_STATUS_SPEED_S) &
+ AR7240_PORT_STATUS_SPEED_M;
+ switch (speed) {
+ case AR7240_PORT_STATUS_SPEED_10:
+ return "10baseT";
+ case AR7240_PORT_STATUS_SPEED_100:
+ return "100baseT";
+ case AR7240_PORT_STATUS_SPEED_1000:
+ return "1000baseT";
+ }
+
+ return "unknown";
+}
+
+static int
+ar7240_port_get_link(struct switch_dev *dev, const struct switch_attr *attr,
+ struct switch_val *val)
+{
+ struct ar7240sw *as = sw_to_ar7240(dev);
+ struct mii_bus *mii = as->mii_bus;
+ u32 len;
+ u32 status;
+ int port;
+
+ port = val->port_vlan;
+
+ memset(as->buf, '\0', sizeof(as->buf));
+ status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
+
+ if (status & AR7240_PORT_STATUS_LINK_UP) {
+ len = snprintf(as->buf, sizeof(as->buf),
+ "port:%d link:up speed:%s %s-duplex %s%s%s",
+ port,
+ ar7240_speed_str(status),
+ (status & AR7240_PORT_STATUS_DUPLEX) ?
+ "full" : "half",
+ (status & AR7240_PORT_STATUS_TXFLOW) ?
+ "txflow ": "",
+ (status & AR7240_PORT_STATUS_RXFLOW) ?
+ "rxflow " : "",
+ (status & AR7240_PORT_STATUS_LINK_AUTO) ?
+ "auto ": "");
+ } else {
+ len = snprintf(as->buf, sizeof(as->buf),
+ "port:%d link:down", port);
+ }
+
+ val->value.s = as->buf;
+ val->len = len;
+
+ return 0;
+}
static void
ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
if (!vp)
continue;
- for (i = 0; i < AR7240_NUM_PORTS; i++) {
+ for (i = 0; i < as->swdev.ports; i++) {
u8 mask = (1 << i);
if (vp & mask)
portmask[i] |= vp & ~mask;
} else {
/* vlan disabled:
* isolate all ports, but connect them to the cpu port */
- for (i = 0; i < AR7240_NUM_PORTS; i++) {
+ for (i = 0; i < as->swdev.ports; i++) {
if (i == AR7240_PORT_CPU)
continue;
}
/* update the port destination mask registers and tag settings */
- for (i = 0; i < AR7240_NUM_PORTS; i++)
+ for (i = 0; i < as->swdev.ports; i++)
ar7240sw_setup_port(as, i, portmask[i]);
return 0;
};
static struct switch_attr ar7240_port[] = {
+ {
+ .type = SWITCH_TYPE_STRING,
+ .name = "link",
+ .description = "Get port link information",
+ .max = 1,
+ .set = NULL,
+ .get = ar7240_port_get_link,
+ },
};
static struct switch_attr ar7240_vlan[] = {
static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
{
+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
struct mii_bus *mii = ag->mii_bus;
struct ar7240sw *as;
struct switch_dev *swdev;
u8 ver;
int i;
+ phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
+ phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
+ if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) {
+ pr_err("%s: unknown phy id '%04x:%04x'\n",
+ ag->dev->name, phy_id1, phy_id2);
+ return NULL;
+ }
+
as = kzalloc(sizeof(*as), GFP_KERNEL);
if (!as)
return NULL;
- ar7240sw_init(as, mii);
+ as->mii_bus = mii;
+ as->swdata = pdata->switch_data;
ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
-
ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M;
if (ver != 1) {
pr_err("%s: unsupported chip, ctrl=%08x\n",
return NULL;
}
- phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
- phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
- if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) {
- pr_err("%s: unknown phy id '%04x:%04x'\n",
- ag->dev->name, phy_id1, phy_id2);
- return NULL;
- }
-
swdev = &as->swdev;
swdev->name = "AR7240 built-in switch";
- swdev->ports = AR7240_NUM_PORTS;
+ swdev->ports = AR7240_NUM_PORTS - 1;
swdev->cpu_port = AR7240_PORT_CPU;
swdev->vlans = AR7240_MAX_VLANS;
swdev->ops = &ar7240_ops;
for (i = 0; i < AR7240_MAX_VLANS; i++)
as->vlan_id[i] = i;
- as->vlan_table[0] = AR7240_PORT_MASK_ALL;
+ as->vlan_table[0] = ar7240sw_port_mask_all(as);
return as;
}
projects / openwrt / staging / yousong.git / blobdiff