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dir-825-b1: Fix wholeflash images: Attempting to flash a wholeflash (-openwrt) image...
[openwrt/staging/yousong.git] / target / linux / ar71xx / patches-3.3 / 605-MIPS-ath79-db120-fixes.patch
diff --git a/target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch b/target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch
index 4f9d00bc1d5021d373d2336d7deaef31d5fdd6b2..031198fe48ea767cceb9d9832cae7f3fe5a418bb 100644 (file)
--- a/target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch
+++ b/target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch
@@ -7,14 +7,11 @@
 - * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
 + * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   *
-  * All rights reserved.
-  *
-@@ -37,17 +37,28 @@
-  * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  * Permission to use, copy, modify, and/or distribute this software for any
+  * purpose with or without fee is hereby granted, provided that the above
+@@ -19,16 +19,25 @@
   */
  
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
  #include <linux/pci.h>
 +#include <linux/phy.h>
 +#include <linux/platform_device.h>
@@ -40,7 +37,7 @@
  #define DB120_GPIO_LED_WLAN_5G                12
  #define DB120_GPIO_LED_WLAN_2G                13
  #define DB120_GPIO_LED_STATUS         14
-@@ -58,8 +69,50 @@
+@@ -39,8 +48,10 @@
  #define DB120_KEYS_POLL_INTERVAL      20      /* msecs */
  #define DB120_KEYS_DEBOUNCE_INTERVAL  (3 * DB120_KEYS_POLL_INTERVAL)
  
@@ -50,50 +47,10 @@
 +#define DB120_MAC1_OFFSET             6
 +#define DB120_WMAC_CALDATA_OFFSET     0x1000
 +#define DB120_PCIE_CALDATA_OFFSET     0x5000
-+
-+static struct mtd_partition db120_partitions[] = {
-+      {
-+              .name           = "u-boot",
-+              .offset         = 0,
-+              .size           = 0x040000,
-+              .mask_flags     = MTD_WRITEABLE,
-+      },
-+      {
-+              .name           = "u-boot-env",
-+              .offset         = 0x040000,
-+              .size           = 0x010000,
-+      },
-+      {
-+              .name           = "rootfs",
-+              .offset         = 0x050000,
-+              .size           = 0x630000,
-+      },
-+      {
-+              .name           = "uImage",
-+              .offset         = 0x680000,
-+              .size           = 0x160000,
-+      },
-+      {
-+              .name           = "NVRAM",
-+              .offset         = 0x7E0000,
-+              .size           = 0x010000,
-+      },
-+      {
-+              .name           = "ART",
-+              .offset         = 0x7F0000,
-+              .size           = 0x010000,
-+              .mask_flags     = MTD_WRITEABLE,
-+      }
-+};
-+
-+static struct flash_platform_data db120_flash_data = {
-+      .parts          = db120_partitions,
-+      .nr_parts       = ARRAY_SIZE(db120_partitions),
-+};
  
  static struct gpio_led db120_leds_gpio[] __initdata = {
        {
-@@ -82,6 +135,11 @@ static struct gpio_led db120_leds_gpio[]
+@@ -63,6 +74,11 @@ static struct gpio_led db120_leds_gpio[]
                .gpio           = DB120_GPIO_LED_WLAN_2G,
                .active_low     = 1,
        },
@@ -105,7 +62,7 @@
  };
  
  static struct gpio_keys_button db120_gpio_keys[] __initdata = {
-@@ -95,66 +153,89 @@ static struct gpio_keys_button db120_gpi
+@@ -76,66 +92,99 @@ static struct gpio_keys_button db120_gpi
        },
  };
  
@@ -127,6 +84,18 @@
 -              .max_speed_hz   = 25000000,
 -              .modalias       = "s25sl064a",
 -              .controller_data = &db120_spi0_data,
+-      }
++static struct ar8327_led_cfg db120_ar8327_led_cfg = {
++      .led_ctrl0 = 0x00000000,
++      .led_ctrl1 = 0xc737c737,
++      .led_ctrl2 = 0x00000000,
++      .led_ctrl3 = 0x00c30c00,
++      .open_drain = true,
+ };
+ 
+-static struct ath79_spi_platform_data db120_spi_data = {
+-      .bus_num        = 0,
+-      .num_chipselect = 1,
 +static struct ar8327_platform_data db120_ar8327_data = {
 +      .pad0_cfg = &db120_ar8327_pad0_cfg,
 +      .cpuport_cfg = {
@@ -135,23 +104,20 @@
 +              .duplex = 1,
 +              .txpause = 1,
 +              .rxpause = 1,
-       }
++      },
++      .led_cfg = &db120_ar8327_led_cfg,
  };
  
--static struct ath79_spi_platform_data db120_spi_data = {
--      .bus_num        = 0,
--      .num_chipselect = 1,
+-#ifdef CONFIG_PCI
+-static struct ath9k_platform_data db120_ath9k_data;
 +static struct mdio_board_info db120_mdio0_info[] = {
 +      {
 +              .bus_id = "ag71xx-mdio.0",
 +              .phy_addr = 0,
 +              .platform_data = &db120_ar8327_data,
 +      },
- };
++};
  
--#ifdef CONFIG_PCI
--static struct ath9k_platform_data db120_ath9k_data;
--
 -static int db120_pci_plat_dev_init(struct pci_dev *dev)
 +static void __init db120_gmac_setup(void)
  {
@@ -173,7 +139,7 @@
 -             sizeof(db120_ath9k_data.eeprom_data));
 +      t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
 +      t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
-+             AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
++             AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
 +      t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
 +
 +      __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
@@ -191,7 +157,7 @@
        u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
  
 +      ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
-+      ath79_register_m25p80(&db120_flash_data);
++      ath79_register_m25p80(NULL);
 +
        ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
                                 db120_leds_gpio);
@@ -219,6 +185,7 @@
 +      ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 +      ath79_eth0_data.phy_mask = BIT(0);
 +      ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
++      ath79_eth0_pll_data.pll_1000 = 0x06000000;
 +      ath79_register_eth(0);
 +
 +      /* GMAC1 is connected to the internal switch */
@@ -233,7 +200,7 @@
  MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
 --- a/arch/mips/ath79/Kconfig
 +++ b/arch/mips/ath79/Kconfig
-@@ -31,9 +31,11 @@ config ATH79_MACH_AP81
+@@ -43,9 +43,11 @@ config ATH79_MACH_AP81
  config ATH79_MACH_DB120
        bool "Atheros DB120 reference board"
        select SOC_AR934X
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