ar71xx: dynamically set AR8327's PAD configuration on AP136

[openwrt/staging/dedeckeh.git] / target / linux / ar71xx / patches-3.6 / 609-MIPS-ath79-ap136-fixes.patch

diff --git a/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch b/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch
index b378888bfdc153f0c912e57997cf116f38b07b4d..9b887cbf30b45f7a1f0e5723b7e2c1e2462b7b90 100644 (file)
--- a/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch
+++ b/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch
@@ -56,87 +56,82 @@
  
  static struct gpio_led ap136_leds_gpio[] __initdata = {
        {
-@@ -98,63 +104,91 @@ static struct gpio_keys_button ap136_gpi
+@@ -98,63 +104,103 @@ static struct gpio_keys_button ap136_gpi
        },
  };
  
 -static struct ath79_spi_controller_data ap136_spi0_data = {
 -      .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
 -      .cs_line = 0,
-+static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg = {
-+      .mode = AR8327_PAD_MAC_RGMII,
-+      .txclk_delay_en = true,
-+      .rxclk_delay_en = true,
-+      .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
-+      .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
++static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg;
++static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg;
++
++static struct ar8327_platform_data ap136_ar8327_data = {
++      .pad0_cfg = &ap136_ar8327_pad0_cfg,
++      .pad6_cfg = &ap136_ar8327_pad6_cfg,
++      .port0_cfg = {
++              .force_link = 1,
++              .speed = AR8327_PORT_SPEED_1000,
++              .duplex = 1,
++              .txpause = 1,
++              .rxpause = 1,
++      },
++      .port6_cfg = {
++              .force_link = 1,
++              .speed = AR8327_PORT_SPEED_1000,
++              .duplex = 1,
++              .txpause = 1,
++              .rxpause = 1,
++      },
  };
  
 -static struct spi_board_info ap136_spi_info[] = {
--      {
++static struct mdio_board_info ap136_mdio0_info[] = {
+       {
 -              .bus_num        = 0,
 -              .chip_select    = 0,
 -              .max_speed_hz   = 25000000,
 -              .modalias       = "mx25l6405d",
 -              .controller_data = &ap136_spi0_data,
 -      }
-+static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg = {
-+      .mode = AR8327_PAD_MAC_SGMII,
-+      .txclk_delay_en = false,
-+      .rxclk_delay_en = true,
-+      .txclk_delay_sel = AR8327_CLK_DELAY_SEL0,
-+      .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
++              .bus_id = "ag71xx-mdio.0",
++              .phy_addr = 0,
++              .platform_data = &ap136_ar8327_data,
++      },
  };
  
 -static struct ath79_spi_platform_data ap136_spi_data = {
 -      .bus_num        = 0,
 -      .num_chipselect = 1,
-+static struct ar8327_platform_data ap136_ar8327_data = {
-+      .pad0_cfg = &ap136_ar8327_pad0_cfg,
-+      .pad6_cfg = &ap136_ar8327_pad6_cfg,
-+      .cpuport_cfg = {
-+              .force_link = 1,
-+              .speed = AR8327_PORT_SPEED_1000,
-+              .duplex = 1,
-+              .txpause = 1,
-+              .rxpause = 1,
-+      }
- };
+-};
++static void __init ap136_gmac_setup(void)
++{
++      void __iomem *base;
++      u32 t;
  
 -#ifdef CONFIG_PCI
 -static struct ath9k_platform_data ap136_ath9k_data;
-+static struct mdio_board_info ap136_mdio0_info[] = {
-+      {
-+              .bus_id = "ag71xx-mdio.0",
-+              .phy_addr = 0,
-+              .platform_data = &ap136_ar8327_data,
-+      },
-+};
++      base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
  
 -static int ap136_pci_plat_dev_init(struct pci_dev *dev)
-+static void __init ap136_gmac_setup(void)
- {
+-{
 -      if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
 -              dev->dev.platform_data = &ap136_ath9k_data;
-+      void __iomem *base;
-+      u32 t;
++      t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
  
 -      return 0;
 -}
-+      base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
++      t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
++      t |= QCA955X_ETH_CFG_RGMII_EN;
  
 -static void __init ap136_pci_init(u8 *eeprom)
 -{
 -      memcpy(ap136_ath9k_data.eeprom_data, eeprom,
 -             sizeof(ap136_ath9k_data.eeprom_data));
-+      t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
-+
-+      t &= ~(QCA955X_ETH_CFG_RGMII_GMAC0 | QCA955X_ETH_CFG_SGMII_GMAC0);
-+      t |= QCA955X_ETH_CFG_RGMII_GMAC0;
++      __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
  
 -      ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
 -      ath79_register_pci();
-+      __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
-+
 +      iounmap(base);
  }
 -#else
@@ -172,13 +167,31 @@
 +      mdiobus_register_board_info(ap136_mdio0_info,
 +                                  ARRAY_SIZE(ap136_mdio0_info));
 +
-+      /* GMAC0 is connected to an AR8327 switch */
++      ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
++      ap136_ar8327_pad0_cfg.txclk_delay_en = true;
++      ap136_ar8327_pad0_cfg.rxclk_delay_en = true;
++      ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
++      ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
++
++      ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
++      ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
++      ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
++
++      /* GMAC0 is connected to GMAC0 of the AR8327 switch via RGMII */
 +      ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 +      ath79_eth0_data.phy_mask = BIT(0);
 +      ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 +      ath79_eth0_pll_data.pll_1000 = 0xa6000000;
 +
 +      ath79_register_eth(0);
++
++      /* GMAC1 is connected to GMAC6 of the AR8327 switch via SGMII */
++      ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
++      ath79_eth1_data.speed = SPEED_1000;
++      ath79_eth1_data.duplex = DUPLEX_FULL;
++      ath79_eth1_pll_data.pll_1000 = 0x03000101;
++
++      ath79_register_eth(1);
  }
  
  MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board",