--- a/arch/mips/ath79/common.c
+++ b/arch/mips/ath79/common.c
-@@ -108,6 +108,8 @@ void ath79_device_reset_set(u32 mask)
+@@ -107,6 +107,8 @@ void ath79_device_reset_set(u32 mask)
reg = QCA953X_RESET_REG_RESET_MODULE;
else if (soc_is_qca955x())
reg = QCA955X_RESET_REG_RESET_MODULE;
else
panic("Reset register not defined for this SOC");
-@@ -138,6 +140,8 @@ void ath79_device_reset_clear(u32 mask)
+@@ -137,6 +139,8 @@ void ath79_device_reset_clear(u32 mask)
reg = QCA953X_RESET_REG_RESET_MODULE;
else if (soc_is_qca955x())
reg = QCA955X_RESET_REG_RESET_MODULE;
else
panic("Reset register not defined for this SOC");
-@@ -164,6 +168,8 @@ u32 ath79_device_reset_get(u32 mask)
+@@ -163,6 +167,8 @@ u32 ath79_device_reset_get(u32 mask)
reg = AR933X_RESET_REG_RESET_MODULE;
else if (soc_is_ar934x())
reg = AR934X_RESET_REG_RESET_MODULE;
}
--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
-@@ -189,6 +189,26 @@ static void qca955x_wmac_setup(void)
- ath79_wmac_data.is_clk_25mhz = true;
- }
+@@ -200,6 +200,26 @@ static void qca955x_wmac_setup(void)
+ #define AR93XX_OTP_READ_DATA \
+ (soc_is_ar934x() ? AR934X_OTP_READ_DATA : AR9300_OTP_READ_DATA)
+static void qca956x_wmac_setup(void)
+{
static bool __init
ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
{
-@@ -392,6 +412,8 @@ void __init ath79_register_wmac(u8 *cal_
+@@ -403,6 +423,8 @@ void __init ath79_register_wmac(u8 *cal_
qca953x_wmac_setup();
else if (soc_is_qca955x())
qca955x_wmac_setup();
* DDR_CTRL block
*/
#define AR71XX_DDR_REG_PCI_WIN0 0x7c
-@@ -375,6 +399,49 @@
+@@ -385,6 +409,49 @@
#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
/*
* USB_CONFIG block
*/
-@@ -422,6 +489,11 @@
+@@ -432,6 +499,11 @@
#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
#define MISC_INT_ETHSW BIT(12)
#define MISC_INT_TIMER4 BIT(10)
#define MISC_INT_TIMER3 BIT(9)
-@@ -596,6 +668,8 @@
+@@ -606,6 +678,8 @@
#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
-@@ -663,6 +737,37 @@
+@@ -673,6 +747,37 @@
QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
QCA955X_EXT_INT_PCIE_RC2_INT3)
#define REV_ID_MAJOR_MASK 0xfff0
#define REV_ID_MAJOR_AR71XX 0x00a0
#define REV_ID_MAJOR_AR913X 0x00b0
-@@ -678,6 +783,8 @@
+@@ -688,6 +793,8 @@
#define REV_ID_MAJOR_QCA9533_V2 0x0160
#define REV_ID_MAJOR_QCA9556 0x0130
#define REV_ID_MAJOR_QCA9558 0x1130
#define AR71XX_REV_ID_MINOR_MASK 0x3
#define AR71XX_REV_ID_MINOR_AR7130 0x0
-@@ -702,6 +809,8 @@
+@@ -712,6 +819,8 @@
#define QCA955X_REV_ID_REVISION_MASK 0xf
/*
* SPI block
*/
-@@ -774,6 +883,19 @@
+@@ -784,6 +893,19 @@
#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
#define QCA955X_GPIO_REG_FUNC 0x6c
#define AR71XX_GPIO_COUNT 16
#define AR7240_GPIO_COUNT 18
#define AR7241_GPIO_COUNT 20
-@@ -782,6 +904,7 @@
+@@ -792,6 +914,7 @@
#define AR934X_GPIO_COUNT 23
#define QCA953X_GPIO_COUNT 18
#define QCA955X_GPIO_COUNT 24