ath79: enable UART in SoC DTSI files

[openwrt/staging/jow.git] / target / linux / ath79 / dts / ar9330.dtsi

diff --git a/target/linux/ath79/dts/ar9330.dtsi b/target/linux/ath79/dts/ar9330.dtsi
index 042b70e0bb41019b894a191e8128ec72dd6b8850..7607fede4925d88048dac0d06b7e1574c5f189b1 100644 (file)
--- a/target/linux/ath79/dts/ar9330.dtsi
+++ b/target/linux/ath79/dts/ar9330.dtsi
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-#include <dt-bindings/clock/ath79-clk.h>
+
 #include "ath79.dtsi"
 
 / {
@@ -8,6 +8,10 @@
        #address-cells = <1>;
        #size-cells = <1>;
 
+       aliases {
+               serial0 = &uart;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -41,8 +45,6 @@
 
                                clocks = <&pll ATH79_CLK_REF>;
                                clock-names = "uart";
-
-                               status = "disabled";
                        };
 
                        gpio: gpio@18040000 {
@@ -57,8 +59,6 @@
 
                                interrupt-controller;
                                #interrupt-cells = <2>;
-
-                               status = "disabled";
                        };
 
                        pinmux: pinmux@18040028 {
@@ -119,11 +119,10 @@
                };
 
                spi: spi@1f000000 {
-                       compatible = "qca,ar7100-spi";
-                       reg = <0x1f000000 0x10>;
+                       compatible = "qca,ar934x-spi";
+                       reg = <0x1f000000 0x1c>;
 
                        clocks = <&pll ATH79_CLK_AHB>;
-                       clock-names = "ahb";
 
                        #address-cells = <1>;
                        #size-cells = <0>;