ath79: enable UART in SoC DTSI files

[openwrt/staging/jow.git] / target / linux / ath79 / dts / ar9330.dtsi

diff --git a/target/linux/ath79/dts/ar9330.dtsi b/target/linux/ath79/dts/ar9330.dtsi
index 49c6f698597692356fb9bdb75220c39a462be692..7607fede4925d88048dac0d06b7e1574c5f189b1 100644 (file)
--- a/target/linux/ath79/dts/ar9330.dtsi
+++ b/target/linux/ath79/dts/ar9330.dtsi
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-#include <dt-bindings/clock/ath79-clk.h>
+
 #include "ath79.dtsi"
 
 / {
@@ -8,6 +8,10 @@
        #address-cells = <1>;
        #size-cells = <1>;
 
+       aliases {
+               serial0 = &uart;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -41,8 +45,6 @@
 
                                clocks = <&pll ATH79_CLK_REF>;
                                clock-names = "uart";
-
-                               status = "disabled";
                        };
 
                        gpio: gpio@18040000 {
@@ -57,8 +59,6 @@
 
                                interrupt-controller;
                                #interrupt-cells = <2>;
-
-                               status = "disabled";
                        };
 
                        pinmux: pinmux@18040028 {
@@ -74,8 +74,8 @@
                                        pinctrl-single,bits = <0x0 0x1 0x1>;
                                };
 
-                               switch_led_pins: pinmux_switch_led_pins {
-                                       pinctrl-single,bits = <0x0 0x1f 0xf8>;
+                               switch_led_disable_pins: pinmux_switch_led_disable_pins {
+                                       pinctrl-single,bits = <0x0 0x0 0xf8>;
                                };
                        };
 
@@ -86,6 +86,16 @@
                                #clock-cells = <1>;
                        };
 
+                       wdt: wdt@18060008 {
+                               compatible = "qca,ar7130-wdt";
+                               reg = <0x18060008 0x8>;
+
+                               interrupts = <4>;
+
+                               clocks = <&pll ATH79_CLK_AHB>;
+                               clock-names = "wdt";
+                       };
+
                        rst: reset-controller@1806001c {
                                compatible = "qca,ar7100-reset";
                                reg = <0x1806001c 0x4>;
@@ -109,11 +119,10 @@
                };
 
                spi: spi@1f000000 {
-                       compatible = "qca,ar7100-spi";
-                       reg = <0x1f000000 0x10>;
+                       compatible = "qca,ar934x-spi";
+                       reg = <0x1f000000 0x1c>;
 
                        clocks = <&pll ATH79_CLK_AHB>;
-                       clock-names = "ahb";
 
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -160,7 +169,6 @@
 
        resets = <&rst 9>;
        reset-names = "mac";
-       phy-mode = "mii";
        phy-handle = <&swphy4>;
 };
 
@@ -192,7 +200,7 @@
 };
 
 &eth1 {
-       compatible = "qca,ar9330-eth", "syscon", "simple-mfd";
+       compatible = "qca,ar9330-eth", "syscon";
 
        pll-data = <0x00110000 0x00001099 0x00991099>;
        phy-mode = "gmii";