ath79: enable UART in SoC DTSI files
[openwrt/staging/jow.git] / target / linux / ath79 / dts / ar9342_iodata_etg3-r.dts
index a2d442a5dc6d3c7f8d0f9a9360b6b9df184b16b1..8b354d6015348ea508fdcdc738203aac5d1b39c3 100644 (file)
@@ -1,41 +1,38 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/dts-v1/;
+
+#include "ar9344.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 
-#include "ar9344.dtsi"
-
 / {
        compatible = "iodata,etg3-r", "qca,ar9344";
        model = "I-O DATA ETG3-R";
 
        aliases {
-               led-boot = &power;
-               led-failsafe = &power;
-               led-running = &power;
-               led-upgrade = &power;
+               led-boot = &led_power;
+               led-failsafe = &led_power;
+               led-running = &led_power;
+               led-upgrade = &led_power;
        };
 
        leds {
                compatible = "gpio-leds";
 
-               power: power {
-                       label = "etg3-r:green:power";
+               led_power: power {
+                       label = "green:power";
                        gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
                        default-state = "on";
                };
 
                notification {
-                       label = "etg3-r:green:notification";
+                       label = "green:notification";
                        gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
-                       default-state = "off";
                };
        };
 
        keys {
-               compatible = "gpio-keys-polled";
-               poll-interval = <20>;
+               compatible = "gpio-keys";
 
                reset {
                        label = "reset";
        };
 };
 
+&ref {
+       clock-frequency = <40000000>;
+};
+
 &spi {
-       num-cs = <1>;
        status = "okay";
 
        flash@0 {
@@ -90,7 +90,7 @@
                        };
 
                        partition@7f0000 {
-                               label = "ART";
+                               label = "art";
                                reg = <0x7f0000 0x010000>;
                                read-only;
                        };
 &eth0 {
        status = "okay";
 
-       pll-data = <0x06000000 0x00000101 0x00001616>;
+       pll-data = <0x0e000000 0x00000101 0x00001616>;
 
        phy-mode = "rgmii";
        phy-handle = <&phy0>;
-};
 
-&uart {
-       status = "okay";
+       gmac-config {
+               device = <&gmac>;
+
+               rgmii-gmac0 = <1>;
+               rxd-delay = <3>;
+               rxdv-delay = <3>;
+       };
 };