ath79: enable UART in SoC DTSI files

[openwrt/staging/jow.git] / target / linux / ath79 / dts / ar9342_ubnt_wa.dtsi

diff --git a/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi b/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi
index 30fa299638c49969487502d34d486ce3e523f0c0..ac036ccd851debd1166c2a393bc60aa6d035a14a 100644 (file)
--- a/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi
+++ b/target/linux/ath79/dts/ar9342_ubnt_wa.dtsi
@@ -1,10 +1,10 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "ar9344.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 
-#include "ar9344.dtsi"
-
 / {
        compatible = "ubnt,wa", "qca,ar9342";
        model = "Ubiquiti Networks WA board";
@@ -25,21 +25,12 @@
        clock-frequency = <40000000>;
 };
 
-&uart {
-       status = "okay";
-};
-
-&gpio {
-       status = "okay";
-};
-
 &pcie {
        status = "okay";
 };
 
 &spi {
        status = "okay";
-       num-cs = <1>;
 
        flash@0 {
                compatible = "jedec,spi-nor";
@@ -75,8 +66,8 @@
                                read-only;
                        };
 
-                       eeprom: partition@ff0000 {
-                               label = "EEPROM";
+                       art: partition@ff0000 {
+                               label = "art";
                                reg = <0xff0000 0x010000>;
                                read-only;
                        };
@@ -88,5 +79,5 @@
        status = "okay";
 
        qca,disable-5ghz;
-       mtd-cal-data = <&eeprom 0x1000>;
+       mtd-cal-data = <&art 0x1000>;
 };