ath79: enable UART in SoC DTSI files
[openwrt/staging/jow.git] / target / linux / ath79 / dts / qca9531_dlink_dch-g020-a1.dts
index 5d6aebf92ffc94972be8b56c048309556deab96c..d2fbc09c60f5b311dfdeec776c59e42aa5510fd7 100644 (file)
@@ -1,11 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-/dts-v1/;
+
+#include "qca953x.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 
-#include "qca953x.dtsi"
-
 / {
        compatible = "dlink,dch-g020-a1", "qca,qca9531";
        model = "D-Link DCH-G020 A1";
                compatible = "gpio-export";
 
                usb_power {
-                       label = "d-link:power:usb";
+                       label = "power:usb";
                        gpio-export,name = "d-link:power:usb";
                        gpio-export,output = <0>;
                        gpios = <&gpio_ext 3 GPIO_ACTIVE_LOW>;
                };
 
                zwave_power {
-                       label = "d-link:power:zwave";
+                       label = "power:zwave";
                        gpio-export,name = "d-link:power:zwave";
                        gpio-export,output = <0>;
                        gpios = <&gpio_ext 1 GPIO_ACTIVE_LOW>;
                compatible = "gpio-leds";
 
                led_power: power {
-                       label = "d-link:green:power";
+                       label = "green:power";
                        gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
                };
 
                status {
-                       label = "d-link:red:status";
+                       label = "red:status";
                        gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
                };
        };
@@ -91,8 +90,6 @@
 &spi {
        status = "okay";
 
-       num-cs = <1>;
-
        flash@0 {
                compatible = "jedec,spi-nor";
                reg = <0>;
        };
 };
 
-&uart {
-       status = "okay";
-};
-
 &usb0 {
        status = "okay";
 };