ath79: enable UART in SoC DTSI files
[openwrt/staging/jow.git] / target / linux / ath79 / dts / qca9533_tplink_cpexxx.dtsi
index fb805ff66ab89662f59ffb7a8a77bb8d60844a6e..d5eeec13b7770014081c6de57708d89e8ffb208e 100644 (file)
@@ -1,10 +1,10 @@
 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 
+#include "qca953x.dtsi"
+
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 
-#include "qca953x.dtsi"
-
 / {
        aliases {
                led-boot = &led_link4;
                compatible = "gpio-leds";
 
                link1 {
-                       label = "tp-link:green:link1";
+                       label = "green:link1";
                        gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
                };
 
                link2 {
-                       label = "tp-link:green:link2";
+                       label = "green:link2";
                        gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
                };
 
                link3 {
-                       label = "tp-link:green:link3";
+                       label = "green:link3";
                        gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
                };
 
                led_link4: link4 {
-                       label = "tp-link:green:link4";
+                       label = "green:link4";
                        gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
                };
        };
        };
 };
 
-&uart {
-       status = "okay";
-};
-
 &spi {
        status = "okay";
 
-       num-cs = <1>;
-
        flash@0 {
                #address-cells = <1>;
                #size-cells = <1>;
        };
 };
 
-&wmac {
+&eth0 {
        status = "okay";
 
-       mtd-cal-data = <&art 0x1000>;
+       phy-handle = <&swphy4>;
+
        mtd-mac-address = <&info 0x8>;
 };
 
-&eth0 {
+&wmac {
        status = "okay";
 
-       phy-handle = <&swphy4>;
-
+       mtd-cal-data = <&art 0x1000>;
        mtd-mac-address = <&info 0x8>;
 };