+obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
--- /dev/null
+++ b/arch/mips/ar231x/board.c
-@@ -0,0 +1,259 @@
+@@ -0,0 +1,260 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+#include <linux/random.h>
+#include <linux/etherdevice.h>
+#include <linux/irq.h>
++#include <linux/io.h>
+#include <asm/irq_cpu.h>
+#include <asm/reboot.h>
-+#include <asm/io.h>
+
+#include <ar231x_platform.h>
+#include "devices.h"
+check_radio_magic(u8 *addr)
+{
+ addr += 0x7a; /* offset for flash magic */
-+ if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) {
++ if ((addr[0] == 0x5a) && (addr[1] == 0xa5))
+ return 1;
-+ }
++
+ return 0;
+}
+
+
+ /* AR2316 relocates radio config to new location */
+ if (!found) {
-+ for (radio_config = board_config + 0xf8;
-+ (radio_config < flash_limit - 0x1000 + 0xf8);
-+ radio_config += 0x1000) {
++ for (radio_config = board_config + 0xf8;
++ (radio_config < flash_limit - 0x1000 + 0xf8);
++ radio_config += 0x1000) {
+ if ((*(u32 *)radio_config != 0xffffffff) &&
-+ check_radio_magic(radio_config)) {
++ check_radio_magic(radio_config)) {
+ found = 1;
+ break;
+ }
-+ }
++ }
+ }
+
+ if (!found) {
-+ printk("Could not find Radio Configuration data\n");
++ pr_warn("WARNING: Could not find Radio Configuration data\n");
+ radio_config = 0;
+ }
+
-+ return (u8 *) radio_config;
++ return radio_config;
+}
+
+int __init
+ }
+
+ if (!bcfg) {
-+ printk(KERN_WARNING "WARNING: No board configuration data found!\n");
++ pr_warn("WARNING: No board configuration data found!\n");
+ return -ENODEV;
+ }
+
+ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
-+ ar231x_board.config = (struct ar231x_boarddata *) board_data;
++ ar231x_board.config = (struct ar231x_boarddata *)board_data;
+ memcpy(board_data, bcfg, 0x100);
+ if (broken_boarddata) {
-+ printk(KERN_WARNING "WARNING: broken board data detected\n");
++ pr_warn("WARNING: broken board data detected\n");
+ config = ar231x_board.config;
+ if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
-+ printk(KERN_INFO "Fixing up empty mac addresses\n");
++ pr_info("Fixing up empty mac addresses\n");
+ config->reset_config_gpio = 0xffff;
+ config->sys_led_gpio = 0xffff;
+ random_ether_addr(config->wlan0_mac);
+ * of what the physical layout on the flash chip looks like */
+
+ if (ar231x_board.radio)
-+ rcfg = (u8 *) ar231x_board.radio;
++ rcfg = (u8 *)ar231x_board.radio;
+ else
+ rcfg = find_radio_config(flash_limit, bcfg);
+
+ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
+ ar231x_board.radio = radio_data;
+ offset = radio_data - board_data;
-+ printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset);
++ pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
++ offset);
+ rcfg_size = BOARD_CONFIG_BUFSZ - offset;
+ memcpy(radio_data, rcfg, rcfg_size);
+
+ mac_addr = &radio_data[0x1d * 2];
+ if (is_broadcast_ether_addr(mac_addr)) {
-+ printk(KERN_INFO "Radio MAC is blank; using board-data\n");
++ pr_info("Radio MAC is blank; using board-data\n");
+ memcpy(mac_addr, ar231x_board.config->wlan0_mac, ETH_ALEN);
+ }
+
+ * address(es).
+ */
+struct ar231x_boarddata {
-+ u32 magic; /* board data is valid */
++ u32 magic; /* board data is valid */
+#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
-+ u16 cksum; /* checksum (starting with BD_REV 2) */
-+ u16 rev; /* revision of this struct */
-+#define BD_REV 4
-+ char board_name[64]; /* Name of board */
-+ u16 major; /* Board major number */
-+ u16 minor; /* Board minor number */
-+ u32 flags; /* Board configuration */
++ u16 cksum; /* checksum (starting with BD_REV 2) */
++ u16 rev; /* revision of this struct */
++#define BD_REV 4
++ char board_name[64]; /* Name of board */
++ u16 major; /* Board major number */
++ u16 minor; /* Board minor number */
++ u32 flags; /* Board configuration */
+#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
+#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
+#define BD_UART1 0x00000004 /* UART1 is stuffed */
+#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
+#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
+#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
-+ u16 reset_config_gpio; /* Reset factory GPIO pin */
-+ u16 sys_led_gpio; /* System LED GPIO pin */
++ u16 reset_config_gpio; /* Reset factory GPIO pin */
++ u16 sys_led_gpio; /* System LED GPIO pin */
+
-+ u32 cpu_freq; /* CPU core frequency in Hz */
-+ u32 sys_freq; /* System frequency in Hz */
-+ u32 cnt_freq; /* Calculated C0_COUNT frequency */
++ u32 cpu_freq; /* CPU core frequency in Hz */
++ u32 sys_freq; /* System frequency in Hz */
++ u32 cnt_freq; /* Calculated C0_COUNT frequency */
+
-+ u8 wlan0_mac[6];
-+ u8 enet0_mac[6];
-+ u8 enet1_mac[6];
++ u8 wlan0_mac[6];
++ u8 enet0_mac[6];
++ u8 enet1_mac[6];
+
-+ u16 pci_id; /* Pseudo PCIID for common code */
-+ u16 mem_cap; /* cap bank1 in MB */
++ u16 pci_id; /* Pseudo PCIID for common code */
++ u16 mem_cap; /* cap bank1 in MB */
+
-+ /* version 3 */
-+ u8 wlan1_mac[6]; /* (ar5212) */
++ /* version 3 */
++ u8 wlan1_mac[6]; /* (ar5212) */
+};
+
+#define BOARD_CONFIG_BUFSZ 0x1000
+#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/gpio.h
-@@ -0,0 +1,28 @@
+@@ -0,0 +1,30 @@
+#ifndef _ATHEROS_GPIO_H_
+#define _ATHEROS_GPIO_H_
+
+/* not sure if these are used? */
+
+/* Returns IRQ to attach for gpio. Unchecked function */
-+static inline int gpio_to_irq(unsigned gpio) {
++static inline int gpio_to_irq(unsigned gpio)
++{
+ return AR531X_GPIO_IRQ(gpio);
+}
+
+/* Returns gpio for IRQ attached. Unchecked function */
-+static inline int irq_to_gpio(unsigned irq) {
++static inline int irq_to_gpio(unsigned irq)
++{
+ return irq - AR531X_GPIO_IRQ(0);
+}
+
+#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
+#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
+
-+#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
-+ /* write 1 to clear all bits in ERR0 */
-+#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
-+#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
++#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
++ /* write 1 to clear all bits in ERR0 */
++#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
++#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
+
+#define AR2315_PROCERR_HMAST 0x0000000f
+#define AR2315_PROCERR_HMAST_DFLT 0
+#endif /* __AR2315_REG_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
-@@ -0,0 +1,232 @@
+@@ -0,0 +1,233 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+/* Reset/Timer Block Address Map */
+#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
+#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
-+#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
-+#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
++#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
++#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
+#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
+#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
+#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
+#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
-+#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
++#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
+#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
+#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
+#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
+#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
-+#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
++#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
+#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
+
+/* AR531X_WD_CTRL register bit field definitions */
+#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
+#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
+#define AR531X_ENABLE_WLAN1 \
-+ (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA)
++ (AR531X_ENABLE_UART_AND_WLAN1_PIO |\
++ AR531X_ENABLE_WLAN1_DMA)
+
+/* AR531X_REV register bit field definitions */
+#define AR531X_REV_WMAC_MAJ 0xf000
+#include <asm/reboot.h>
+#include <asm/time.h>
+#include <linux/irq.h>
-+#include <asm/io.h>
++#include <linux/io.h>
+
+#include <ar231x_platform.h>
+#include <ar5312_regs.h>
+ u32 dma1 = ar231x_read_reg(AR531X_DMA1);
+ u32 dma_addr = ar231x_read_reg(AR531X_DMAADDR); /* clears error */
+
-+ printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
-+ proc_addr, proc1, dma_addr, dma1);
++ pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x "
++ "DMAADDR=0x%8.8x DMA1=0x%8.8x\n", proc_addr, proc1, dma_addr,
++ dma1);
+
+ machine_restart("AHB error"); /* Catastrophic failure */
+ return IRQ_HANDLED;
+
+static const struct gpio_led_platform_data ar5312_led_data = {
+ .num_leds = ARRAY_SIZE(ar5312_leds),
-+ .leds = (void *) ar5312_leds,
++ .leds = (void *)ar5312_leds,
+};
+
+static struct platform_device ar5312_gpio_leds = {
+ .name = "leds-gpio",
+ .id = -1,
-+ .dev.platform_data = (void *) &ar5312_led_data,
++ .dev.platform_data = (void *)&ar5312_led_data,
+};
+#endif
+
+ ar231x_write_reg(AR531X_FLASHCTL2,
+ ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
+
-+ return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
++ return (char *)KSEG1ADDR(AR531X_FLASH + 0x800000);
+}
+
+int __init ar5312_init_devices(void)
+ c--;
+ }
+
-+ switch(ar231x_devtype) {
++ switch (ar231x_devtype) {
+ case DEV_TYPE_AR5312:
+ ar5312_eth0_data.macaddr = config->enet0_mac;
+ ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
+{
+ /* reset the system */
+ local_irq_disable();
-+ while(1) {
++ while (1)
+ ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
-+ }
+}
+
+
+static int __init
+ar5312_cpu_frequency(void)
+{
-+ unsigned int result;
++ unsigned int scratch;
+ unsigned int predivide_mask, predivide_shift;
+ unsigned int multiplier_mask, multiplier_shift;
+ unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
+ u16 devid;
+
+ /* Trust the bootrom's idea of cpu frequency. */
-+ if ((result = ar231x_read_reg(AR5312_SCRATCH)))
-+ return result;
++ scratch = ar231x_read_reg(AR5312_SCRATCH);
++ if (scratch)
++ return scratch;
+
+ devid = ar231x_read_reg(AR531X_REV);
+ devid &= AR531X_REV_MAJ;
+ predivisor = clockctl1_predivide_table[predivide_select];
+ multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
+
-+ if (clock_ctl1 & doubler_mask) {
++ if (clock_ctl1 & doubler_mask)
+ multiplier = multiplier << 1;
-+ }
++
+ return (40000000 / predivisor) * multiplier;
+}
+
+ gpch = &ar5312_gpio_chip;
+ ret = gpiochip_add(&gpch->chip);
+ if (ret) {
-+ printk(KERN_ERR "%s: failed to add gpiochip\n",
-+ gpch->chip.label);
++ pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
+ return ret;
+ }
-+ printk(KERN_INFO "%s: registered %d GPIOs\n",
-+ gpch->chip.label, gpch->chip.ngpio);
++ pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
++ gpch->chip.ngpio);
+ return ret;
+}
+
+ memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
+ bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
+ bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
-+ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
-+ + (bank1AC ? (1 << (bank1AC+1)) : 0);
++ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
++ (bank1AC ? (1 << (bank1AC+1)) : 0);
+ memsize <<= 20;
+ add_memory_region(0, memsize, BOOT_MEM_RAM);
+
+#include <asm/reboot.h>
+#include <asm/time.h>
+#include <linux/irq.h>
-+#include <asm/io.h>
++#include <linux/io.h>
+
+#include <ar231x_platform.h>
+#include <ar2315_regs.h>
+#include "devices.h"
+#include "ar2315.h"
+
-+static u32 gpiointmask = 0, gpiointval = 0;
++static u32 gpiointmask, gpiointval;
+
+static inline void ar2315_gpio_irq(void)
+{
+ unsigned int imr;
+
+ imr = ar231x_read_reg(AR2315_IMR);
-+ switch(d->irq) {
++ switch (d->irq) {
+ case AR531X_MISC_IRQ_SPI:
-+ imr |= AR2315_ISR_SPI;
-+ break;
++ imr |= AR2315_ISR_SPI;
++ break;
+ case AR531X_MISC_IRQ_TIMER:
-+ imr |= AR2315_ISR_TIMER;
-+ break;
++ imr |= AR2315_ISR_TIMER;
++ break;
+ case AR531X_MISC_IRQ_AHB_PROC:
-+ imr |= AR2315_ISR_AHB;
-+ break;
++ imr |= AR2315_ISR_AHB;
++ break;
+ case AR531X_MISC_IRQ_GPIO:
-+ imr |= AR2315_ISR_GPIO;
-+ break;
++ imr |= AR2315_ISR_GPIO;
++ break;
+ case AR531X_MISC_IRQ_UART0:
-+ imr |= AR2315_ISR_UART0;
-+ break;
++ imr |= AR2315_ISR_UART0;
++ break;
+ case AR531X_MISC_IRQ_WATCHDOG:
-+ imr |= AR2315_ISR_WD;
-+ break;
++ imr |= AR2315_ISR_WD;
++ break;
+ default:
+ break;
+ }
+ unsigned int imr;
+
+ imr = ar231x_read_reg(AR2315_IMR);
-+ switch(d->irq) {
++ switch (d->irq) {
+ case AR531X_MISC_IRQ_SPI:
-+ imr &= ~AR2315_ISR_SPI;
-+ break;
++ imr &= ~AR2315_ISR_SPI;
++ break;
+ case AR531X_MISC_IRQ_TIMER:
-+ imr &= ~AR2315_ISR_TIMER;
-+ break;
++ imr &= ~AR2315_ISR_TIMER;
++ break;
+ case AR531X_MISC_IRQ_AHB_PROC:
-+ imr &= ~AR2315_ISR_AHB;
-+ break;
++ imr &= ~AR2315_ISR_AHB;
++ break;
+ case AR531X_MISC_IRQ_GPIO:
-+ imr &= ~AR2315_ISR_GPIO;
-+ break;
++ imr &= ~AR2315_ISR_GPIO;
++ break;
+ case AR531X_MISC_IRQ_UART0:
-+ imr &= ~AR2315_ISR_UART0;
-+ break;
++ imr &= ~AR2315_ISR_UART0;
++ break;
+ case AR531X_MISC_IRQ_WATCHDOG:
-+ imr &= ~AR2315_ISR_WD;
-+ break;
++ imr &= ~AR2315_ISR_WD;
++ break;
+ default:
+ break;
+ }
+
+static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
+{
-+ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
-+ ar231x_read_reg(AR2315_AHB_ERR1);
++ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
++ ar231x_read_reg(AR2315_AHB_ERR1);
+
-+ printk(KERN_ERR "AHB fatal error\n");
-+ machine_restart("AHB error"); /* Catastrophic failure */
++ pr_emerg("AHB fatal error\n");
++ machine_restart("AHB error"); /* Catastrophic failure */
+
-+ return IRQ_HANDLED;
++ return IRQ_HANDLED;
+}
+
+static struct irqaction ar2315_ahb_proc_interrupt = {
+ u32 flash_size = 0;
+
+ /* probe the flash chip size */
-+ switch(spiflash_probe()) {
-+ case STM_8MBIT_SIGNATURE:
-+ flash_size = 0x00100000;
-+ break;
-+ case STM_16MBIT_SIGNATURE:
-+ flash_size = 0x00200000;
-+ break;
-+ case STM_32MBIT_SIGNATURE:
-+ flash_size = 0x00400000;
-+ break;
-+ case STM_64MBIT_SIGNATURE:
-+ flash_size = 0x00800000;
-+ break;
-+ case STM_128MBIT_SIGNATURE:
-+ flash_size = 0x01000000;
-+ break;
++ switch (spiflash_probe()) {
++ case STM_8MBIT_SIGNATURE:
++ flash_size = 0x00100000;
++ break;
++ case STM_16MBIT_SIGNATURE:
++ flash_size = 0x00200000;
++ break;
++ case STM_32MBIT_SIGNATURE:
++ flash_size = 0x00400000;
++ break;
++ case STM_64MBIT_SIGNATURE:
++ flash_size = 0x00800000;
++ break;
++ case STM_128MBIT_SIGNATURE:
++ flash_size = 0x01000000;
++ break;
+ }
+
+ ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start +
+ flash_size - 1;
-+ return (u8 *) ar2315_spiflash_res[0].end + 1;
++ return (u8 *)ar2315_spiflash_res[0].end + 1;
+}
+
+#ifdef CONFIG_LEDS_GPIO
+static struct gpio_led ar2315_leds[6];
+static struct gpio_led_platform_data ar2315_led_data = {
-+ .leds = (void *) ar2315_leds,
++ .leds = (void *)ar2315_leds,
+};
+
+static struct platform_device ar2315_gpio_leds = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
-+ .platform_data = (void *) &ar2315_led_data,
++ .platform_data = (void *)&ar2315_led_data,
+ }
+};
+
+ int i, led = 0;
+
+ ar2315_led_data.num_leds = 0;
-+ for(i = 1; i < 8; i++)
-+ {
-+ if((i == AR2315_RESET_GPIO) ||
-+ (i == ar231x_board.config->reset_config_gpio))
++ for (i = 1; i < 8; i++) {
++ if ((i == AR2315_RESET_GPIO) ||
++ (i == ar231x_board.config->reset_config_gpio))
+ continue;
+
+ if (i == ar231x_board.config->sys_led_gpio)
+static void
+ar2315_restart(char *command)
+{
-+ void (*mips_reset_vec)(void) = (void *) 0xbfc00000;
++ void (*mips_reset_vec)(void) = (void *)0xbfc00000;
+
+ local_irq_disable();
+
+ /* try reset the system via reset control */
-+ ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM);
++ ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
+
+ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
+ * give it some time to attempt a gpio based hardware reset
+ divby2 += 1;
+ pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
+
-+ /* clkm input selected */
++ /* clkm input selected */
+ switch (clock_ctl & CPUCLK_CLK_SEL_M) {
-+ case 0:
-+ case 1:
-+ clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
-+ break;
-+ case 2:
-+ clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
-+ break;
-+ default:
-+ pllc_out = 40000000;
-+ clk_div = 1;
-+ break;
++ case 0:
++ case 1:
++ clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
++ PLLC_CLKM_DIV_S];
++ break;
++ case 2:
++ clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
++ PLLC_CLKC_DIV_S];
++ break;
++ default:
++ pllc_out = 40000000;
++ clk_div = 1;
++ break;
+ }
+
+ cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
+static inline unsigned int
+ar2315_cpu_frequency(void)
+{
-+ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
++ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
+}
+
+static inline unsigned int
+ar2315_apb_frequency(void)
+{
-+ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
++ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
+}
+
+void __init
+ gpch = &ar2315_gpio_chip;
+ ret = gpiochip_add(&gpch->chip);
+ if (ret) {
-+ printk(KERN_ERR "%s: failed to add gpiochip\n",
-+ gpch->chip.label);
++ pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
+ return ret;
+ }
-+ printk(KERN_INFO "%s: registered %d GPIOs\n",
-+ gpch->chip.label, gpch->chip.ngpio);
++ pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
++ gpch->chip.ngpio);
+ return ret;
+}
+
+
+ /* Detect the hardware based on the device ID */
+ devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
-+ switch(devid) {
-+ case 0x90:
-+ case 0x91:
-+ ar231x_devtype = DEV_TYPE_AR2317;
-+ break;
-+ default:
-+ ar231x_devtype = DEV_TYPE_AR2315;
-+ break;
++ switch (devid) {
++ case 0x90:
++ case 0x91:
++ ar231x_devtype = DEV_TYPE_AR2317;
++ break;
++ default:
++ ar231x_devtype = DEV_TYPE_AR2315;
++ break;
+ }
+ ar2315_gpio_init();
+ ar231x_board.devid = devid;
+ /* Clear any lingering AHB errors */
+ config = read_c0_config();
+ write_c0_config(config & ~0x3);
-+ ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET);
++ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
+ ar231x_read_reg(AR2315_AHB_ERR1);
+ ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
+
+static inline u32
+ar231x_read_reg(u32 reg)
+{
-+ return __raw_readl((u32 *) KSEG1ADDR(reg));
++ return __raw_readl((u32 *)KSEG1ADDR(reg));
+}
+
+static inline void
+ar231x_write_reg(u32 reg, u32 val)
+{
-+ __raw_writel(val, (u32 *) KSEG1ADDR(reg));
++ __raw_writel(val, (u32 *)KSEG1ADDR(reg));
+}
+
+static inline u32
projects / openwrt / staging / lynxis / omap.git / blobdiff