--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
-@@ -135,6 +135,19 @@ config BCM63XX
+@@ -138,6 +138,19 @@ config BCM63XX
help
Support for BCM63XX based boards
config MIPS_COBALT
bool "Cobalt Server"
select CEVT_R4K
-@@ -836,6 +849,7 @@ config NLM_XLP_BOARD
+@@ -838,6 +851,7 @@ config NLM_XLP_BOARD
endchoice
+obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
--- /dev/null
+++ b/arch/mips/ar231x/board.c
-@@ -0,0 +1,259 @@
+@@ -0,0 +1,260 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+check_radio_magic(u8 *addr)
+{
+ addr += 0x7a; /* offset for flash magic */
-+ if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) {
++ if ((addr[0] == 0x5a) && (addr[1] == 0xa5))
+ return 1;
-+ }
++
+ return 0;
+}
+
+ }
+
+ if (!found) {
-+ printk("Could not find Radio Configuration data\n");
++ pr_warn("WARNING: Could not find Radio Configuration data\n");
+ radio_config = 0;
+ }
+
+ }
+
+ if (!bcfg) {
-+ printk(KERN_WARNING "WARNING: No board configuration data found!\n");
++ pr_warn("WARNING: No board configuration data found!\n");
+ return -ENODEV;
+ }
+
+ ar231x_board.config = (struct ar231x_boarddata *) board_data;
+ memcpy(board_data, bcfg, 0x100);
+ if (broken_boarddata) {
-+ printk(KERN_WARNING "WARNING: broken board data detected\n");
++ pr_warn("WARNING: broken board data detected\n");
+ config = ar231x_board.config;
+ if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
-+ printk(KERN_INFO "Fixing up empty mac addresses\n");
-+ config->resetConfigGpio = 0xffff;
-+ config->sysLedGpio = 0xffff;
++ pr_info("Fixing up empty mac addresses\n");
++ config->reset_config_gpio = 0xffff;
++ config->sys_led_gpio = 0xffff;
+ random_ether_addr(config->wlan0_mac);
+ config->wlan0_mac[0] &= ~0x06;
+ random_ether_addr(config->enet0_mac);
+ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
+ ar231x_board.radio = radio_data;
+ offset = radio_data - board_data;
-+ printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset);
++ pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
++ offset);
+ rcfg_size = BOARD_CONFIG_BUFSZ - offset;
+ memcpy(radio_data, rcfg, rcfg_size);
+
+ mac_addr = &radio_data[0x1d * 2];
+ if (is_broadcast_ether_addr(mac_addr)) {
-+ printk(KERN_INFO "Radio MAC is blank; using board-data\n");
++ pr_info("Radio MAC is blank; using board-data\n");
+ memcpy(mac_addr, ar231x_board.config->wlan0_mac, ETH_ALEN);
+ }
+
+ u16 cksum; /* checksum (starting with BD_REV 2) */
+ u16 rev; /* revision of this struct */
+#define BD_REV 4
-+ char boardName[64]; /* Name of board */
++ char board_name[64]; /* Name of board */
+ u16 major; /* Board major number */
+ u16 minor; /* Board minor number */
+ u32 flags; /* Board configuration */
+#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
+#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
+#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
-+#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */
++#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
+#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
+#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
+#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
+#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
+#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
+#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
-+ u16 resetConfigGpio; /* Reset factory GPIO pin */
-+ u16 sysLedGpio; /* System LED GPIO pin */
++ u16 reset_config_gpio; /* Reset factory GPIO pin */
++ u16 sys_led_gpio; /* System LED GPIO pin */
+
-+ u32 cpuFreq; /* CPU core frequency in Hz */
-+ u32 sysFreq; /* System frequency in Hz */
-+ u32 cntFreq; /* Calculated C0_COUNT frequency */
++ u32 cpu_freq; /* CPU core frequency in Hz */
++ u32 sys_freq; /* System frequency in Hz */
++ u32 cnt_freq; /* Calculated C0_COUNT frequency */
+
+ u8 wlan0_mac[6];
+ u8 enet0_mac[6];
+ u8 enet1_mac[6];
+
-+ u16 pciId; /* Pseudo PCIID for common code */
-+ u16 memCap; /* cap bank1 in MB */
++ u16 pci_id; /* Pseudo PCIID for common code */
++ u16 mem_cap; /* cap bank1 in MB */
+
+ /* version 3 */
+ u8 wlan1_mac[6]; /* (ar5212) */
+#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/gpio.h
-@@ -0,0 +1,28 @@
+@@ -0,0 +1,30 @@
+#ifndef _ATHEROS_GPIO_H_
+#define _ATHEROS_GPIO_H_
+
+/* not sure if these are used? */
+
+/* Returns IRQ to attach for gpio. Unchecked function */
-+static inline int gpio_to_irq(unsigned gpio) {
++static inline int gpio_to_irq(unsigned gpio)
++{
+ return AR531X_GPIO_IRQ(gpio);
+}
+
+/* Returns gpio for IRQ attached. Unchecked function */
-+static inline int irq_to_gpio(unsigned irq) {
-+ return (irq - (AR531X_GPIO_IRQ(0)));
++static inline int irq_to_gpio(unsigned irq)
++{
++ return irq - AR531X_GPIO_IRQ(0);
+}
+
+#include <asm-generic/gpio.h> /* cansleep wrappers */
+/*
+ * IRQs
+ */
-+#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
-+#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
-+#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
-+#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
-+#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
++#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
++#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
++#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
++#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
++#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
+
+/*
+ * Address map
+ * IRQs
+ */
+
-+#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
-+#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
-+#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
-+#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
-+#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
++#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
++#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
++#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
++#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
++#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
+
+
+/* Address Map */
+#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
+
+#define AR531X_RESET_WMAC0_BITS \
-+ AR531X_RESET_WLAN0 |\
-+ AR531X_RESET_WARM_WLAN0_MAC |\
-+ AR531X_RESET_WARM_WLAN0_BB
++ (AR531X_RESET_WLAN0 |\
++ AR531X_RESET_WARM_WLAN0_MAC |\
++ AR531X_RESET_WARM_WLAN0_BB)
+
+#define AR531X_RESERT_WMAC1_BITS \
-+ AR531X_RESET_WLAN1 |\
-+ AR531X_RESET_WARM_WLAN1_MAC |\
-+ AR531X_RESET_WARM_WLAN1_BB
++ (AR531X_RESET_WLAN1 |\
++ AR531X_RESET_WARM_WLAN1_MAC |\
++ AR531X_RESET_WARM_WLAN1_BB)
+
+/* AR5312_CLOCKCTL1 register bit field definitions */
+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
+static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
+{
+ u32 proc1 = ar231x_read_reg(AR531X_PROC1);
-+ u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */
++ u32 proc_addr = ar231x_read_reg(AR531X_PROCADDR); /* clears error */
+ u32 dma1 = ar231x_read_reg(AR531X_DMA1);
-+ u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */
++ u32 dma_addr = ar231x_read_reg(AR531X_DMAADDR); /* clears error */
+
-+ printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
-+ procAddr, proc1, dmaAddr, dma1);
++ pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x "
++ "DMAADDR=0x%8.8x DMA1=0x%8.8x\n", proc_addr, proc1, dma_addr,
++ dma1);
+
+ machine_restart("AHB error"); /* Catastrophic failure */
+ return IRQ_HANDLED;
+ .set = ar5312_gpio_set_value,
+ .get = ar5312_gpio_get_value,
+ .base = 0,
-+ .ngpio = AR531X_GPIO_IRQ_COUNT, // 22
++ .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
+ }
+};
+
-+// end of gpiolib
++/* end of gpiolib */
+
+static struct physmap_flash_data ar5312_flash_data = {
+ .width = 2,
+ platform_device_register(&ar5312_physmap_flash);
+
+#ifdef CONFIG_LEDS_GPIO
-+ ar5312_leds[0].gpio = config->sysLedGpio;
++ ar5312_leds[0].gpio = config->sys_led_gpio;
+ platform_device_register(&ar5312_gpio_leds);
+#endif
+
+{
+ /* reset the system */
+ local_irq_disable();
-+ while(1) {
++ while (1)
+ ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
-+ }
+}
+
+
+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
+ * to determine the predevisor value.
+ */
-+static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
++static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
+
+
+static int __init
+ar5312_cpu_frequency(void)
+{
-+ unsigned int result;
++ unsigned int scratch;
+ unsigned int predivide_mask, predivide_shift;
+ unsigned int multiplier_mask, multiplier_shift;
-+ unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
++ unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
+ unsigned int doubler_mask;
+ u16 devid;
+
+ /* Trust the bootrom's idea of cpu frequency. */
-+ if ((result = ar231x_read_reg(AR5312_SCRATCH)))
-+ return result;
++ scratch = ar231x_read_reg(AR5312_SCRATCH);
++ if (scratch)
++ return scratch;
+
+ devid = ar231x_read_reg(AR531X_REV);
+ devid &= AR531X_REV_MAJ;
+ /*
+ * Clocking is derived from a fixed 40MHz input clock.
+ *
-+ * cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
-+ * sysFreq = cpuFreq / 4 (used for APB clock, serial,
++ * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
++ * sys_freq = cpu_freq / 4 (used for APB clock, serial,
+ * flash, Timer, Watchdog Timer)
+ *
-+ * cntFreq = cpuFreq / 2 (use for CPU count/compare)
++ * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
+ *
+ * So, for example, with a PLL multiplier of 5, we have
+ *
-+ * cpuFreq = 200MHz
-+ * sysFreq = 50MHz
-+ * cntFreq = 100MHz
++ * cpu_freq = 200MHz
++ * sys_freq = 50MHz
++ * cnt_freq = 100MHz
+ *
+ * We compute the CPU frequency, based on PLL settings.
+ */
+
-+ clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
-+ preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift;
-+ preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect];
-+ multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift;
++ clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
++ predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
++ predivisor = clockctl1_predivide_table[predivide_select];
++ multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
+
-+ if (clockCtl1 & doubler_mask) {
++ if (clock_ctl1 & doubler_mask)
+ multiplier = multiplier << 1;
-+ }
-+ return (40000000 / preDivisor) * multiplier;
++
++ return (40000000 / predivisor) * multiplier;
+}
+
+static inline int
+ gpch = &ar5312_gpio_chip;
+ ret = gpiochip_add(&gpch->chip);
+ if (ret) {
-+ printk(KERN_ERR "%s: failed to add gpiochip\n",
-+ gpch->chip.label);
++ pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
+ return ret;
+ }
-+ printk(KERN_INFO "%s: registered %d GPIOs\n",
-+ gpch->chip.label, gpch->chip.ngpio);
++ pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
++ gpch->chip.ngpio);
+ return ret;
+}
+
+
--- /dev/null
+++ b/arch/mips/ar231x/ar2315.c
-@@ -0,0 +1,692 @@
+@@ -0,0 +1,691 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+#include "devices.h"
+#include "ar2315.h"
+
-+static u32 gpiointmask = 0, gpiointval = 0;
++static u32 gpiointmask, gpiointval;
+
+static inline void ar2315_gpio_irq(void)
+{
+ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
+ ar231x_read_reg(AR2315_AHB_ERR1);
+
-+ printk(KERN_ERR "AHB fatal error\n");
++ pr_emerg("AHB fatal error\n");
+ machine_restart("AHB error"); /* Catastrophic failure */
+
+ return IRQ_HANDLED;
+ u32 rett;
+ if (!(gpch->valid_mask & mask))
+ return 0;
-+ rett = ar2315_gpio_get(gpch->valid_mask); // legacy code
++ rett = ar2315_gpio_get(gpch->valid_mask); /* legacy code */
+ return !!(rett & mask);
+}
+
+ u32 mask = 1 << gpio;
+ if (!(gpch->valid_mask & mask))
+ return;
-+ ar2315_gpio_set(mask, (!!value) * mask); // legacy
++ ar2315_gpio_set(mask, (!!value) * mask); /* legacy */
+}
+
+static int
+ u32 mask = 1 << gpio;
+ if (!(gpch->valid_mask & mask))
+ return -ENXIO;
-+ ar2315_gpio_set_output(mask, 0); // legacy
++ ar2315_gpio_set_output(mask, 0); /* legacy */
+ return 0;
+}
+
+ u32 mask = 1 << gpio;
+ if (!(gpch->valid_mask & mask))
+ return -ENXIO;
-+ ar2315_gpio_set_output(mask, mask); // both legacy
++ ar2315_gpio_set_output(mask, mask); /* both legacy */
+ ar2315_gpio_set(mask, (!!value) * mask);
+ return 0;
+}
+ .set = ar2315_gpio_set_value,
+ .get = ar2315_gpio_get_value,
+ .base = 0,
-+ .ngpio = AR531X_GPIO_IRQ_COUNT, // 22
++ .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
+ }
+};
+
-+// end of gpiolib
++/* end of gpiolib */
+
+
+static struct ar231x_eth ar2315_eth_data = {
+ int i, led = 0;
+
+ ar2315_led_data.num_leds = 0;
-+ for(i = 1; i < 8; i++)
-+ {
++ for (i = 1; i < 8; i++) {
+ if((i == AR2315_RESET_GPIO) ||
-+ (i == ar231x_board.config->resetConfigGpio))
++ (i == ar231x_board.config->reset_config_gpio))
+ continue;
+
-+ if(i == ar231x_board.config->sysLedGpio)
++ if (i == ar231x_board.config->sys_led_gpio)
+ strcpy(led_names[led], "wlan");
+ else
+ sprintf(led_names[led], "gpio%d", i);
+ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
+ * give it some time to attempt a gpio based hardware reset
+ * (atheros reference design workaround) */
-+ gpio_direction_output(AR2315_RESET_GPIO, 0);
++ gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
+ mdelay(100);
+
+ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
+ * to determine the predevisor value.
+ */
-+static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = { 1, 2, 4, 5 };
-+static int __initdata PLLC_DIVIDE_TABLE[5] = { 2, 3, 4, 6, 3 };
++static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
++static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
+
+static unsigned int __init
-+ar2315_sys_clk(unsigned int clockCtl)
++ar2315_sys_clk(unsigned int clock_ctl)
+{
-+ unsigned int pllcCtrl,cpuDiv;
-+ unsigned int pllcOut,refdiv,fdiv,divby2;
-+ unsigned int clkDiv;
-+
-+ pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL);
-+ refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
-+ refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
-+ fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
-+ divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
-+ divby2 += 1;
-+ pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
++ unsigned int pllc_ctrl, cpu_div;
++ unsigned int pllc_out, refdiv, fdiv, divby2;
++ unsigned int clk_div;
+
++ pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
++ refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
++ refdiv = clockctl1_predivide_table[refdiv];
++ fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
++ divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
++ divby2 += 1;
++ pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
+
+ /* clkm input selected */
-+ switch(clockCtl & CPUCLK_CLK_SEL_M) {
++ switch (clock_ctl & CPUCLK_CLK_SEL_M) {
+ case 0:
+ case 1:
-+ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
++ clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
+ break;
+ case 2:
-+ clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
++ clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
+ break;
+ default:
-+ pllcOut = 40000000;
-+ clkDiv = 1;
++ pllc_out = 40000000;
++ clk_div = 1;
+ break;
+ }
-+ cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
-+ cpuDiv = cpuDiv * 2 ?: 1;
-+ return (pllcOut/(clkDiv * cpuDiv));
++
++ cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
++ cpu_div = cpu_div * 2 ?: 1;
++
++ return pllc_out / (clk_div * cpu_div);
+}
+
+static inline unsigned int
+ gpch = &ar2315_gpio_chip;
+ ret = gpiochip_add(&gpch->chip);
+ if (ret) {
-+ printk(KERN_ERR "%s: failed to add gpiochip\n",
-+ gpch->chip.label);
++ pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
+ return ret;
+ }
-+ printk(KERN_INFO "%s: registered %d GPIOs\n",
-+ gpch->chip.label, gpch->chip.ngpio);
++ pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
++ gpch->chip.ngpio);
+ return ret;
+}
+
+#define AR531X_GPIO_IRQ_BASE 0x30
+
+/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
-+#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0
-+#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
++#define AR531X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
++#define AR531X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
+
+/* Miscellaneous interrupts, which share IP6 */
-+#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0
-+#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1
-+#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2
-+#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3
-+#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4
-+#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5
-+#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6
-+#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7
-+#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8
-+#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9
++#define AR531X_MISC_IRQ_NONE (AR531X_MISC_IRQ_BASE+0)
++#define AR531X_MISC_IRQ_TIMER (AR531X_MISC_IRQ_BASE+1)
++#define AR531X_MISC_IRQ_AHB_PROC (AR531X_MISC_IRQ_BASE+2)
++#define AR531X_MISC_IRQ_AHB_DMA (AR531X_MISC_IRQ_BASE+3)
++#define AR531X_MISC_IRQ_GPIO (AR531X_MISC_IRQ_BASE+4)
++#define AR531X_MISC_IRQ_UART0 (AR531X_MISC_IRQ_BASE+5)
++#define AR531X_MISC_IRQ_UART0_DMA (AR531X_MISC_IRQ_BASE+6)
++#define AR531X_MISC_IRQ_WATCHDOG (AR531X_MISC_IRQ_BASE+7)
++#define AR531X_MISC_IRQ_LOCAL (AR531X_MISC_IRQ_BASE+8)
++#define AR531X_MISC_IRQ_SPI (AR531X_MISC_IRQ_BASE+9)
+#define AR531X_MISC_IRQ_COUNT 10
+
+/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
-+#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0
-+#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n
++#define AR531X_GPIO_IRQ_NONE (AR531X_GPIO_IRQ_BASE+0)
++#define AR531X_GPIO_IRQ(n) (AR531X_GPIO_IRQ_BASE+n)
+#define AR531X_GPIO_IRQ_COUNT 22
+
+static inline u32
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