+#endif /* __ASM_MACH_AR231X_DMA_COHERENCE_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/gpio.h
-@@ -0,0 +1,30 @@
+@@ -0,0 +1,16 @@
+#ifndef __ASM_MACH_AR231X_GPIO_H
+#define __ASM_MACH_AR231X_GPIO_H
+
-+#include <ar231x.h>
++#include <asm-generic/gpio.h>
+
+#define gpio_get_value __gpio_get_value
+#define gpio_set_value __gpio_set_value
+#define gpio_cansleep __gpio_cansleep
++#define gpio_to_irq __gpio_to_irq
+
-+/*
-+ * Wrappers for the generic GPIO layer
-+ */
-+
-+/* not sure if these are used? */
-+
-+/* Returns IRQ to attach for gpio. Unchecked function */
-+static inline int gpio_to_irq(unsigned gpio)
-+{
-+ return AR231X_GPIO_IRQ(gpio);
-+}
-+
-+/* Returns gpio for IRQ attached. Unchecked function */
+static inline int irq_to_gpio(unsigned irq)
+{
-+ return irq - AR231X_GPIO_IRQ(0);
++ return -EINVAL;
+}
+
-+#include <asm-generic/gpio.h> /* cansleep wrappers */
-+
+#endif /* __ASM_MACH_AR231X_GPIO_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/reset.h
+#endif /* __ASM_MACH_AR231X_WAR_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
-@@ -0,0 +1,631 @@
+@@ -0,0 +1,608 @@
+/*
+ * Register definitions for AR2315+
+ *
+/*
+ * Miscellaneous interrupts, which share IP2.
+ */
-+#define AR2315_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
-+#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+1)
-+#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+2)
-+#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+3)
-+#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+4)
-+#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+5)
-+#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+6)
-+#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+7)
-+#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+8)
-+#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+9)
-+#define AR2315_MISC_IRQ_COUNT 10
++#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+0)
++#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+1)
++#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+2)
++#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+3)
++#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+4)
++#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+5)
++#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+6)
++#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
++#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+8)
++#define AR2315_MISC_IRQ_COUNT 9
+
+/*
+ * PCI interrupts, which share IP5
+#define AMBACLK_CLK_DIV_M 0x0000000c
+#define AMBACLK_CLK_DIV_S 2
+
-+/*
-+ * GPIO
-+ */
-+#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
-+#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
-+#define AR2315_GPIO_DIR (AR2315_DSLBASE + 0x0098)
-+#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
-+
-+#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
-+#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
-+#define AR2315_GPIO_DIR_I(x) (0) /* input */
-+
-+#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
-+#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
-+#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
-+#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
-+
-+#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for
-+ * AR2315_GPIO_INT_* macros */
-+#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
-+#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
-+#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
-+#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
++/* GPIO MMR base address */
++#define AR2315_GPIO (AR2315_DSLBASE + 0x0088)
+
+#define AR2315_RESET_GPIO 5
-+#define AR2315_NUM_GPIO 22
+
+/*
+ * PCI Clock Control
+#endif /* __ASM_MACH_AR231X_AR2315_REGS_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
-@@ -0,0 +1,249 @@
+@@ -0,0 +1,235 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+/*
+ * Miscellaneous interrupts, which share IP6.
+ */
-+#define AR5312_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
-+#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+1)
-+#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+2)
-+#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+3)
-+#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+4)
-+#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+5)
-+#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+6)
-+#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
-+#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+8)
-+#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+9)
-+#define AR5312_MISC_IRQ_COUNT 10
++#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+0)
++#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+1)
++#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+2)
++#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+3)
++#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+4)
++#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+5)
++#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+6)
++#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+7)
++#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+8)
++#define AR5312_MISC_IRQ_COUNT 9
+
+/*
+ * Address Map
+#define AR5312_WD_CTRL_RESET 0x0002
+
+/* AR5312_ISR register bit field definitions */
-+#define AR5312_ISR_NONE 0x0000
+#define AR5312_ISR_TIMER 0x0001
+#define AR5312_ISR_AHBPROC 0x0002
+#define AR5312_ISR_AHBDMA 0x0004
+#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
+#define MEM_CFG1_AC1_S 12
+
-+/* GPIO Address Map */
+#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
-+#define AR5312_GPIO_DO (AR5312_GPIO + 0x00) /* output register */
-+#define AR5312_GPIO_DI (AR5312_GPIO + 0x04) /* intput register */
-+#define AR5312_GPIO_CR (AR5312_GPIO + 0x08) /* control register */
-+
-+/* GPIO Control Register bit field definitions */
-+#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
-+#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
-+#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
-+#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/
-+#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
-+#define AR5312_NUM_GPIO 8
+
+#endif /* __ASM_MACH_AR231X_AR5312_REGS_H */
--- /dev/null
+++ b/arch/mips/ar231x/ar5312.c
-@@ -0,0 +1,534 @@
+@@ -0,0 +1,476 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ ar231x_read_reg(AR5312_IMR);
+
+ if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
-+ do_IRQ(AR5312_MISC_IRQ_TIMER);
++ generic_handle_irq(AR5312_MISC_IRQ_TIMER);
+ (void)ar231x_read_reg(AR5312_TIMER);
+ } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
-+ do_IRQ(AR5312_MISC_IRQ_AHB_PROC);
++ generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
+ else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
-+ do_IRQ(AR5312_MISC_IRQ_UART0);
++ generic_handle_irq(AR5312_MISC_IRQ_UART0);
+ else if (ar231x_misc_intrs & AR5312_ISR_WD)
-+ do_IRQ(AR5312_MISC_IRQ_WATCHDOG);
++ generic_handle_irq(AR5312_MISC_IRQ_WATCHDOG);
+ else
-+ do_IRQ(AR5312_MISC_IRQ_NONE);
++ spurious_interrupt();
+}
+
+static asmlinkage void
+ do_IRQ(AR5312_IRQ_MISC_INTRS);
+ else if (pending & CAUSEF_IP7)
+ do_IRQ(AR231X_IRQ_CPU_CLOCK);
++ else
++ spurious_interrupt();
+}
+
+/* Enable the specified AR5312_MISC_IRQ interrupt */
+ unsigned int imr;
+
+ imr = ar231x_read_reg(AR5312_IMR);
-+ imr |= (1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
++ imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
+ ar231x_write_reg(AR5312_IMR, imr);
+}
+
+ unsigned int imr;
+
+ imr = ar231x_read_reg(AR5312_IMR);
-+ imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
++ imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
+ ar231x_write_reg(AR5312_IMR, imr);
+ ar231x_read_reg(AR5312_IMR); /* flush write buffer */
+}
+ irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
+}
+
-+/*
-+ * gpiolib implementations
-+ */
-+static int
-+ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
-+{
-+ return (ar231x_read_reg(AR5312_GPIO_DI) >> gpio) & 1;
-+}
-+
-+static void
-+ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
-+{
-+ u32 reg = ar231x_read_reg(AR5312_GPIO_DO);
-+
-+ reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
-+ ar231x_write_reg(AR5312_GPIO_DO, reg);
-+}
-+
-+static int
-+ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
-+{
-+ ar231x_mask_reg(AR5312_GPIO_CR, 0, 1 << gpio);
-+ return 0;
-+}
-+
-+static int
-+ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
-+{
-+ ar231x_mask_reg(AR5312_GPIO_CR, 1 << gpio, 0);
-+ ar5312_gpio_set_value(chip, gpio, value);
-+ return 0;
-+}
-+
-+static struct gpio_chip ar5312_gpio_chip = {
-+ .label = "ar5312-gpio",
-+ .direction_input = ar5312_gpio_direction_input,
-+ .direction_output = ar5312_gpio_direction_output,
-+ .set = ar5312_gpio_set_value,
-+ .get = ar5312_gpio_get_value,
-+ .base = 0,
-+ .ngpio = AR5312_NUM_GPIO, /* 8 */
-+};
-+
-+/* end of gpiolib */
-+
+static void ar5312_device_reset_set(u32 mask)
+{
+ u32 val;
+ mips_hpt_frequency = ar5312_cpu_frequency() / 2;
+}
+
-+static int __init
-+ar5312_gpio_init(void)
-+{
-+ int ret = gpiochip_add(&ar5312_gpio_chip);
-+
-+ if (ret) {
-+ pr_err("%s: failed to add gpiochip\n", ar5312_gpio_chip.label);
-+ return ret;
-+ }
-+ pr_info("%s: registered %d GPIOs\n", ar5312_gpio_chip.label,
-+ ar5312_gpio_chip.ngpio);
-+ return ret;
-+}
-+
+void __init
+ar5312_prom_init(void)
+{
+ devid >>= AR5312_REV_WMAC_MIN_S;
+ devid &= AR5312_REV_CHIP;
+ ar231x_board.devid = (u16)devid;
-+ ar5312_gpio_init();
+}
+
+void __init
+
--- /dev/null
+++ b/arch/mips/ar231x/ar2315.c
-@@ -0,0 +1,562 @@
+@@ -0,0 +1,431 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+#include "devices.h"
+#include "ar2315.h"
+
-+static u32 gpiointmask, gpiointval;
-+
-+static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
-+{
-+ u32 pend;
-+ int bit = -1;
-+
-+ /* only do one gpio interrupt at a time */
-+ pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
-+
-+ if (pend) {
-+ bit = fls(pend) - 1;
-+ pend &= ~(1 << bit);
-+ gpiointval ^= (1 << bit);
-+ }
-+
-+ if (!pend)
-+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
-+
-+ /* Enable interrupt with edge detection */
-+ if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
-+ AR2315_GPIO_DIR_I(bit))
-+ return;
-+
-+ if (bit >= 0)
-+ do_IRQ(AR231X_GPIO_IRQ_BASE + bit);
-+}
-+
+static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
+{
+ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
+ ar231x_read_reg(AR2315_IMR);
+
+ if (misc_intr & AR2315_ISR_SPI)
-+ do_IRQ(AR2315_MISC_IRQ_SPI);
++ generic_handle_irq(AR2315_MISC_IRQ_SPI);
+ else if (misc_intr & AR2315_ISR_TIMER)
-+ do_IRQ(AR2315_MISC_IRQ_TIMER);
++ generic_handle_irq(AR2315_MISC_IRQ_TIMER);
+ else if (misc_intr & AR2315_ISR_AHB)
-+ do_IRQ(AR2315_MISC_IRQ_AHB);
-+ else if (misc_intr & AR2315_ISR_GPIO)
-+ do_IRQ(AR2315_MISC_IRQ_GPIO);
-+ else if (misc_intr & AR2315_ISR_UART0)
-+ do_IRQ(AR2315_MISC_IRQ_UART0);
++ generic_handle_irq(AR2315_MISC_IRQ_AHB);
++ else if (misc_intr & AR2315_ISR_GPIO) {
++ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
++ generic_handle_irq(AR2315_MISC_IRQ_GPIO);
++ } else if (misc_intr & AR2315_ISR_UART0)
++ generic_handle_irq(AR2315_MISC_IRQ_UART0);
+ else if (misc_intr & AR2315_ISR_WD) {
+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
-+ do_IRQ(AR2315_MISC_IRQ_WATCHDOG);
++ generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
+ } else
-+ do_IRQ(AR2315_MISC_IRQ_NONE);
++ spurious_interrupt();
+}
+
+/*
+ do_IRQ(AR2315_IRQ_MISC_INTRS);
+ else if (pending & CAUSEF_IP7)
+ do_IRQ(AR231X_IRQ_CPU_CLOCK);
++ else
++ spurious_interrupt();
+}
+
-+static void ar2315_set_gpiointmask(int gpio, int level)
-+{
-+ u32 reg;
-+
-+ reg = ar231x_read_reg(AR2315_GPIO_INT);
-+ reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
-+ reg |= gpio | AR2315_GPIO_INT_LVL(level);
-+ ar231x_write_reg(AR2315_GPIO_INT, reg);
-+}
-+
-+static void ar2315_gpio_irq_unmask(struct irq_data *d)
-+{
-+ unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
-+
-+ /* Enable interrupt with edge detection */
-+ if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(gpio)) !=
-+ AR2315_GPIO_DIR_I(gpio))
-+ return;
-+
-+ gpiointmask |= (1 << gpio);
-+ ar2315_set_gpiointmask(gpio, 3);
-+}
-+
-+static void ar2315_gpio_irq_mask(struct irq_data *d)
-+{
-+ unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
-+
-+ /* Disable interrupt */
-+ gpiointmask &= ~(1 << gpio);
-+ ar2315_set_gpiointmask(gpio, 0);
-+}
-+
-+static struct irq_chip ar2315_gpio_irq_chip = {
-+ .name = "AR2315-GPIO",
-+ .irq_unmask = ar2315_gpio_irq_unmask,
-+ .irq_mask = ar2315_gpio_irq_mask,
-+};
-+
+static void
+ar2315_misc_irq_unmask(struct irq_data *d)
+{
+ unsigned int imr;
+
+ imr = ar231x_read_reg(AR2315_IMR);
-+ imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE - 1);
++ imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
+ ar231x_write_reg(AR2315_IMR, imr);
+}
+
+ unsigned int imr;
+
+ imr = ar231x_read_reg(AR2315_IMR);
-+ imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
++ imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
+ ar231x_write_reg(AR2315_IMR, imr);
+}
+
+ return;
+
+ ar231x_irq_dispatch = ar2315_irq_dispatch;
-+ gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
+ for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
+ int irq = AR231X_MISC_IRQ_BASE + i;
+
+ irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
+ handle_level_irq);
+ }
-+ for (i = 0; i < AR2315_NUM_GPIO; i++) {
-+ int irq = AR231X_GPIO_IRQ_BASE + i;
-+
-+ irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
-+ handle_level_irq);
-+ }
-+ irq_set_chained_handler(AR2315_MISC_IRQ_GPIO, ar2315_gpio_irq_handler);
+ setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
+ irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
+}
+
-+/*
-+ * gpiolib implementation
-+ */
-+static int
-+ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
-+{
-+ return (ar231x_read_reg(AR2315_GPIO_DI) >> gpio) & 1;
-+}
-+
-+static void
-+ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
-+{
-+ u32 reg = ar231x_read_reg(AR2315_GPIO_DO);
-+
-+ reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
-+ ar231x_write_reg(AR2315_GPIO_DO, reg);
-+}
-+
-+static int
-+ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
-+{
-+ ar231x_mask_reg(AR2315_GPIO_DIR, 1 << gpio, 0);
-+ return 0;
-+}
-+
-+static int
-+ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
-+{
-+ ar231x_mask_reg(AR2315_GPIO_DIR, 0, 1 << gpio);
-+ ar2315_gpio_set_value(chip, gpio, value);
-+ return 0;
-+}
-+
-+static struct gpio_chip ar2315_gpio_chip = {
-+ .label = "ar2315-gpio",
-+ .direction_input = ar2315_gpio_direction_input,
-+ .direction_output = ar2315_gpio_direction_output,
-+ .set = ar2315_gpio_set_value,
-+ .get = ar2315_gpio_get_value,
-+ .base = 0,
-+ .ngpio = AR2315_NUM_GPIO, /* 22 */
-+};
-+
-+/* end of gpiolib */
-+
+static void ar2315_device_reset_set(u32 mask)
+{
+ u32 val;
+ mips_hpt_frequency = ar2315_cpu_frequency() / 2;
+}
+
-+static int __init
-+ar2315_gpio_init(void)
-+{
-+ int ret = gpiochip_add(&ar2315_gpio_chip);
-+
-+ if (ret) {
-+ pr_err("%s: failed to add gpiochip\n", ar2315_gpio_chip.label);
-+ return ret;
-+ }
-+ pr_info("%s: registered %d GPIOs\n", ar2315_gpio_chip.label,
-+ ar2315_gpio_chip.ngpio);
-+ return ret;
-+}
-+
+void __init
+ar2315_prom_init(void)
+{
+ ar231x_devtype = DEV_TYPE_AR2315;
+ break;
+ }
-+ ar2315_gpio_init();
+ ar231x_board.devid = devid;
+}
+
+#endif
--- /dev/null
+++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
-@@ -0,0 +1,43 @@
+@@ -0,0 +1,38 @@
+#ifndef __ASM_MACH_AR231X_H
+#define __ASM_MACH_AR231X_H
+
+#define AR231X_GPIO_IRQ_BASE 0x30
+
+/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
-+#define AR231X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
+#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
+
-+/* GPIO Interrupts, share ARXXXX_MISC_IRQ_GPIO */
-+#define AR231X_GPIO_IRQ_NONE (AR231X_GPIO_IRQ_BASE+0)
-+#define AR231X_GPIO_IRQ(n) (AR231X_GPIO_IRQ_BASE+n)
-+
+static inline u32
+ar231x_read_reg(u32 reg)
+{