family: TNETD7100, 7200 and 7300.
+config ATH25
-+ bool "Atheros 231x/531x SoC support"
++ bool "Atheros AR231x/AR531x SoC support"
+ select CEVT_R4K
+ select CSRC_R4K
+ select DMA_NONCOHERENT
+ select IRQ_CPU
++ select IRQ_DOMAIN
+ select SYS_HAS_CPU_MIPS32_R1
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_SUPPORTS_32BIT_KERNEL
-+ select ARCH_REQUIRE_GPIOLIB
+ help
-+ Support for AR231x and AR531x based boards
++ Support for Atheros AR231x and Atheros AR531x based boards
+
config ATH79
bool "Atheros AR71XX/AR724X/AR913X based boards"
select ARCH_REQUIRE_GPIOLIB
-@@ -834,6 +847,7 @@ config MIPS_PARAVIRT
-
+@@ -835,6 +848,7 @@ config MIPS_PARAVIRT
endchoice
-+source "arch/mips/ath25/Kconfig"
source "arch/mips/alchemy/Kconfig"
++source "arch/mips/ath25/Kconfig"
source "arch/mips/ath79/Kconfig"
source "arch/mips/bcm47xx/Kconfig"
+ source "arch/mips/bcm63xx/Kconfig"
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -2,6 +2,7 @@
+++ b/arch/mips/ath25/Kconfig
@@ -0,0 +1,9 @@
+config SOC_AR5312
-+ bool "Atheros 5312/2312+ support"
++ bool "Atheros AR5312/AR2312+ SoC support"
+ depends on ATH25
+ default y
+
+config SOC_AR2315
-+ bool "Atheros 2315+ support"
++ bool "Atheros AR2315+ SoC support"
+ depends on ATH25
+ default y
--- /dev/null
+obj-$(CONFIG_SOC_AR2315) += ar2315.o
--- /dev/null
+++ b/arch/mips/ath25/board.c
-@@ -0,0 +1,244 @@
+@@ -0,0 +1,234 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
+ */
+
-+#include <generated/autoconf.h>
+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/string.h>
-+#include <linux/platform_device.h>
-+#include <linux/kernel.h>
-+#include <linux/random.h>
-+#include <linux/etherdevice.h>
-+#include <linux/irq.h>
-+#include <linux/io.h>
++#include <linux/interrupt.h>
+#include <asm/irq_cpu.h>
+#include <asm/reboot.h>
+#include <asm/bootinfo.h>
+static void ath25_halt(void)
+{
+ local_irq_disable();
-+ while (1)
-+ ;
++ unreachable();
+}
+
+void __init plat_mem_setup(void)
+ */
+
+/*
-+ * Prom setup file for ar231x
++ * Prom setup file for AR5312/AR231x SoCs
+ */
+
+#include <linux/init.h>
+}
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
-@@ -0,0 +1,84 @@
+@@ -0,0 +1,73 @@
+#ifndef __ASM_MACH_ATH25_PLATFORM_H
+#define __ASM_MACH_ATH25_PLATFORM_H
+
+ const char *radio;
+};
+
-+/*
-+ * Platform device information for the Ethernet MAC
-+ */
-+struct ar231x_eth {
-+ void (*reset_set)(u32);
-+ void (*reset_clear)(u32);
-+ u32 reset_mac;
-+ u32 reset_phy;
-+ char *macaddr;
-+};
-+
+#endif /* __ASM_MACH_ATH25_PLATFORM_H */
--- /dev/null
+++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
+#endif /* __ASM_MACH_ATH25_WAR_H */
--- /dev/null
+++ b/arch/mips/ath25/ar2315_regs.h
-@@ -0,0 +1,479 @@
+@@ -0,0 +1,410 @@
+/*
+ * Register definitions for AR2315+
+ *
+/*
+ * Miscellaneous interrupts, which share IP2.
+ */
-+#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+0)
-+#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+1)
-+#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+2)
-+#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+3)
-+#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+4)
-+#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+5)
-+#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+6)
-+#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
-+#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+8)
++#define AR2315_MISC_IRQ_UART0 0
++#define AR2315_MISC_IRQ_I2C_RSVD 1
++#define AR2315_MISC_IRQ_SPI 2
++#define AR2315_MISC_IRQ_AHB 3
++#define AR2315_MISC_IRQ_APB 4
++#define AR2315_MISC_IRQ_TIMER 5
++#define AR2315_MISC_IRQ_GPIO 6
++#define AR2315_MISC_IRQ_WATCHDOG 7
++#define AR2315_MISC_IRQ_IR_RSVD 8
+#define AR2315_MISC_IRQ_COUNT 9
+
+/*
+#define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
+#define AR2315_PCI_EXT_SIZE 0x40000000
+
-+/* MII registers offset inside Ethernet MMR region */
-+#define AR2315_ENET0_MII_BASE (AR2315_ENET0_BASE + 0x14)
-+
+/*
-+ * Cold reset register
++ * Configuration registers
+ */
++
++/* Cold reset register */
+#define AR2315_COLD_RESET 0x0000
+
-+#define AR2315_RESET_COLD_AHB 0x00000001
-+#define AR2315_RESET_COLD_APB 0x00000002
-+#define AR2315_RESET_COLD_CPU 0x00000004
-+#define AR2315_RESET_COLD_CPUWARM 0x00000008
-+#define AR2315_RESET_SYSTEM \
-+ (RESET_COLD_CPU |\
-+ RESET_COLD_APB |\
-+ RESET_COLD_AHB) /* full system */
-+#define AR2317_RESET_SYSTEM 0x00000010
++#define AR2315_RESET_COLD_AHB 0x00000001
++#define AR2315_RESET_COLD_APB 0x00000002
++#define AR2315_RESET_COLD_CPU 0x00000004
++#define AR2315_RESET_COLD_CPUWARM 0x00000008
++#define AR2315_RESET_SYSTEM (RESET_COLD_CPU |\
++ RESET_COLD_APB |\
++ RESET_COLD_AHB) /* full system */
++#define AR2317_RESET_SYSTEM 0x00000010
+
-+/*
-+ * Reset register
-+ */
++/* Reset register */
+#define AR2315_RESET 0x0004
+
-+/* warm reset WLAN0 MAC */
-+#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
-+/* warm reset WLAN0 BaseBand */
-+#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
-+/* warm reset MPEG-TS */
-+#define AR2315_RESET_MPEGTS_RSVD 0x00000004
-+/* warm reset PCI ahb/dma */
-+#define AR2315_RESET_PCIDMA 0x00000008
-+/* warm reset memory controller */
-+#define AR2315_RESET_MEMCTL 0x00000010
-+/* warm reset local bus */
-+#define AR2315_RESET_LOCAL 0x00000020
-+/* warm reset I2C bus */
-+#define AR2315_RESET_I2C_RSVD 0x00000040
-+/* warm reset SPI interface */
-+#define AR2315_RESET_SPI 0x00000080
-+/* warm reset UART0 */
-+#define AR2315_RESET_UART0 0x00000100
-+/* warm reset IR interface */
-+#define AR2315_RESET_IR_RSVD 0x00000200
-+/* cold reset ENET0 phy */
-+#define AR2315_RESET_EPHY0 0x00000400
-+/* cold reset ENET0 mac */
-+#define AR2315_RESET_ENET0 0x00000800
-+
-+/*
-+ * AHB master arbitration control
-+ */
++#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
++#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BB */
++#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
++#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
++#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset mem control */
++#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
++#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
++#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI iface */
++#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
++#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR iface */
++#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
++#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 MAC */
++
++/* AHB master arbitration control */
+#define AR2315_AHB_ARB_CTL 0x0008
+
-+/* CPU, default */
-+#define AR2315_ARB_CPU 0x00000001
-+/* WLAN */
-+#define AR2315_ARB_WLAN 0x00000002
-+/* MPEG-TS */
-+#define AR2315_ARB_MPEGTS_RSVD 0x00000004
-+/* LOCAL */
-+#define AR2315_ARB_LOCAL 0x00000008
-+/* PCI */
-+#define AR2315_ARB_PCI 0x00000010
-+/* Ethernet */
-+#define AR2315_ARB_ETHERNET 0x00000020
-+/* retry policy, debug only */
-+#define AR2315_ARB_RETRY 0x00000100
++#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
++#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
++#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
++#define AR2315_ARB_LOCAL 0x00000008 /* Local bus */
++#define AR2315_ARB_PCI 0x00000010 /* PCI bus */
++#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
++#define AR2315_ARB_RETRY 0x00000100 /* Retry policy (debug) */
+
-+/*
-+ * Config Register
-+ */
++/* Config Register */
+#define AR2315_ENDIAN_CTL 0x000c
+
-+/* EC - AHB bridge endianess */
-+#define AR2315_CONFIG_AHB 0x00000001
-+/* WLAN byteswap */
-+#define AR2315_CONFIG_WLAN 0x00000002
-+/* MPEG-TS byteswap */
-+#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
-+/* PCI byteswap */
-+#define AR2315_CONFIG_PCI 0x00000008
-+/* Memory controller endianess */
-+#define AR2315_CONFIG_MEMCTL 0x00000010
-+/* Local bus byteswap */
-+#define AR2315_CONFIG_LOCAL 0x00000020
-+/* Ethernet byteswap */
-+#define AR2315_CONFIG_ETHERNET 0x00000040
-+
-+/* CPU write buffer merge */
-+#define AR2315_CONFIG_MERGE 0x00000200
-+/* CPU big endian */
-+#define AR2315_CONFIG_CPU 0x00000400
-+#define AR2315_CONFIG_PCIAHB 0x00000800
-+#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
-+/* SPI byteswap */
-+#define AR2315_CONFIG_SPI 0x00008000
-+#define AR2315_CONFIG_CPU_DRAM 0x00010000
-+#define AR2315_CONFIG_CPU_PCI 0x00020000
-+#define AR2315_CONFIG_CPU_MMR 0x00040000
-+#define AR2315_CONFIG_BIG 0x00000400
-+
-+/*
-+ * NMI control
-+ */
++#define AR2315_CONFIG_AHB 0x00000001 /* EC-AHB bridge endian */
++#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
++#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
++#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
++#define AR2315_CONFIG_MEMCTL 0x00000010 /* Mem controller endian */
++#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
++#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
++#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
++#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
++#define AR2315_CONFIG_BIG 0x00000400
++#define AR2315_CONFIG_PCIAHB 0x00000800
++#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
++#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
++#define AR2315_CONFIG_CPU_DRAM 0x00010000
++#define AR2315_CONFIG_CPU_PCI 0x00020000
++#define AR2315_CONFIG_CPU_MMR 0x00040000
++
++/* NMI control */
+#define AR2315_NMI_CTL 0x0010
+
-+#define AR2315_NMI_EN 1
++#define AR2315_NMI_EN 1
+
-+/*
-+ * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
-+ */
++/* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */
+#define AR2315_SREV 0x0014
+
-+#define AR2315_REV_MAJ 0x00f0
-+#define AR2315_REV_MAJ_S 4
-+#define AR2315_REV_MIN 0x000f
-+#define AR2315_REV_MIN_S 0
-+#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
++#define AR2315_REV_MAJ 0x000000f0
++#define AR2315_REV_MAJ_S 4
++#define AR2315_REV_MIN 0x0000000f
++#define AR2315_REV_MIN_S 0
++#define AR2315_REV_CHIP (AR2315_REV_MAJ | AR2315_REV_MIN)
+
-+/*
-+ * Interface Enable
-+ */
++/* Interface Enable */
+#define AR2315_IF_CTL 0x0018
+
-+#define AR2315_IF_MASK 0x00000007
-+#define AR2315_IF_DISABLED 0
-+#define AR2315_IF_PCI 1
-+#define AR2315_IF_TS_LOCAL 2
-+/* only for emulation with separate pins */
-+#define AR2315_IF_ALL 3
-+#define AR2315_IF_LOCAL_HOST 0x00000008
-+#define AR2315_IF_PCI_HOST 0x00000010
-+#define AR2315_IF_PCI_INTR 0x00000020
-+#define AR2315_IF_PCI_CLK_MASK 0x00030000
-+#define AR2315_IF_PCI_CLK_INPUT 0
-+#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
-+#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
-+#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
-+#define AR2315_IF_PCI_CLK_SHIFT 16
-+
-+/*
-+ * APB Interrupt control
-+ */
-+
++#define AR2315_IF_MASK 0x00000007
++#define AR2315_IF_DISABLED 0 /* Disable all */
++#define AR2315_IF_PCI 1 /* PCI */
++#define AR2315_IF_TS_LOCAL 2 /* Local bus */
++#define AR2315_IF_ALL 3 /* Emulation only */
++#define AR2315_IF_LOCAL_HOST 0x00000008
++#define AR2315_IF_PCI_HOST 0x00000010
++#define AR2315_IF_PCI_INTR 0x00000020
++#define AR2315_IF_PCI_CLK_MASK 0x00030000
++#define AR2315_IF_PCI_CLK_INPUT 0
++#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
++#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
++#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
++#define AR2315_IF_PCI_CLK_SHIFT 16
++
++/* APB Interrupt control */
+#define AR2315_ISR 0x0020
+#define AR2315_IMR 0x0024
+#define AR2315_GISR 0x0028
+
-+#define AR2315_ISR_UART0 0x0001 /* high speed UART */
-+#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
-+#define AR2315_ISR_SPI 0x0004 /* SPI bus */
-+#define AR2315_ISR_AHB 0x0008 /* AHB error */
-+#define AR2315_ISR_APB 0x0010 /* APB error */
-+#define AR2315_ISR_TIMER 0x0020 /* timer */
-+#define AR2315_ISR_GPIO 0x0040 /* GPIO */
-+#define AR2315_ISR_WD 0x0080 /* watchdog */
-+#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
-+
-+#define AR2315_GISR_MISC 0x0001
-+#define AR2315_GISR_WLAN0 0x0002
-+#define AR2315_GISR_MPEGTS_RSVD 0x0004
-+#define AR2315_GISR_LOCALPCI 0x0008
-+#define AR2315_GISR_WMACPOLL 0x0010
-+#define AR2315_GISR_TIMER 0x0020
-+#define AR2315_GISR_ETHERNET 0x0040
-+
-+/*
-+ * Timers
-+ */
++#define AR2315_ISR_UART0 0x00000001 /* high speed UART */
++#define AR2315_ISR_I2C_RSVD 0x00000002 /* I2C bus */
++#define AR2315_ISR_SPI 0x00000004 /* SPI bus */
++#define AR2315_ISR_AHB 0x00000008 /* AHB error */
++#define AR2315_ISR_APB 0x00000010 /* APB error */
++#define AR2315_ISR_TIMER 0x00000020 /* Timer */
++#define AR2315_ISR_GPIO 0x00000040 /* GPIO */
++#define AR2315_ISR_WD 0x00000080 /* Watchdog */
++#define AR2315_ISR_IR_RSVD 0x00000100 /* IR */
++
++#define AR2315_GISR_MISC 0x00000001 /* Misc */
++#define AR2315_GISR_WLAN0 0x00000002 /* WLAN0 */
++#define AR2315_GISR_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
++#define AR2315_GISR_LOCALPCI 0x00000008 /* Local/PCI bus */
++#define AR2315_GISR_WMACPOLL 0x00000010
++#define AR2315_GISR_TIMER 0x00000020
++#define AR2315_GISR_ETHERNET 0x00000040 /* Ethernet */
++
++/* Generic timer */
+#define AR2315_TIMER 0x0030
+#define AR2315_RELOAD 0x0034
+
++/* Watchdog timer */
+#define AR2315_WDT_TIMER 0x0038
+#define AR2315_WDT_CTRL 0x003c
+
+#define AR2315_WDT_CTRL_NMI 0x00000001 /* NMI on watchdog */
+#define AR2315_WDT_CTRL_RESET 0x00000002 /* reset on watchdog */
+
-+/*
-+ * CPU Performance Counters
-+ */
++/* CPU Performance Counters */
+#define AR2315_PERFCNT0 0x0048
+#define AR2315_PERFCNT1 0x004c
+
-+#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
-+#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
-+#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
-+#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
-+#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
-+#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
-+#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
-+
-+#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
-+#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
-+#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
-+#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
-+#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
-+#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
-+#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
-+
-+/*
-+ * AHB Error Reporting.
-+ */
++#define AR2315_PERF0_DATAHIT 0x00000001 /* Count Data Cache Hits */
++#define AR2315_PERF0_DATAMISS 0x00000002 /* Count Data Cache Misses */
++#define AR2315_PERF0_INSTHIT 0x00000004 /* Count Instruction Cache Hits */
++#define AR2315_PERF0_INSTMISS 0x00000008 /* Count Instruction Cache Misses */
++#define AR2315_PERF0_ACTIVE 0x00000010 /* Count Active Processor Cycles */
++#define AR2315_PERF0_WBHIT 0x00000020 /* Count CPU Write Buffer Hits */
++#define AR2315_PERF0_WBMISS 0x00000040 /* Count CPU Write Buffer Misses */
++
++#define AR2315_PERF1_EB_ARDY 0x00000001 /* Count EB_ARdy signal */
++#define AR2315_PERF1_EB_AVALID 0x00000002 /* Count EB_AValid signal */
++#define AR2315_PERF1_EB_WDRDY 0x00000004 /* Count EB_WDRdy signal */
++#define AR2315_PERF1_EB_RDVAL 0x00000008 /* Count EB_RdVal signal */
++#define AR2315_PERF1_VRADDR 0x00000010 /* Count valid read address cycles*/
++#define AR2315_PERF1_VWADDR 0x00000020 /* Count valid write address cycl.*/
++#define AR2315_PERF1_VWDATA 0x00000040 /* Count valid write data cycles */
++
++/* AHB Error Reporting */
+#define AR2315_AHB_ERR0 0x0050 /* error */
+#define AR2315_AHB_ERR1 0x0054 /* haddr */
+#define AR2315_AHB_ERR2 0x0058 /* hwdata */
+#define AR2315_AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
+#define AR2315_AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
+
-+#define AR2315_PROCERR_HMAST 0x0000000f
-+#define AR2315_PROCERR_HMAST_DFLT 0
-+#define AR2315_PROCERR_HMAST_WMAC 1
-+#define AR2315_PROCERR_HMAST_ENET 2
-+#define AR2315_PROCERR_HMAST_PCIENDPT 3
-+#define AR2315_PROCERR_HMAST_LOCAL 4
-+#define AR2315_PROCERR_HMAST_CPU 5
-+#define AR2315_PROCERR_HMAST_PCITGT 6
-+
-+#define AR2315_PROCERR_HMAST_S 0
-+#define AR2315_PROCERR_HWRITE 0x00000010
-+#define AR2315_PROCERR_HSIZE 0x00000060
-+#define AR2315_PROCERR_HSIZE_S 5
-+#define AR2315_PROCERR_HTRANS 0x00000180
-+#define AR2315_PROCERR_HTRANS_S 7
-+#define AR2315_PROCERR_HBURST 0x00000e00
-+#define AR2315_PROCERR_HBURST_S 9
-+
-+/*
-+ * Clock Control
-+ */
++#define AR2315_PROCERR_HMAST 0x0000000f
++#define AR2315_PROCERR_HMAST_DFLT 0
++#define AR2315_PROCERR_HMAST_WMAC 1
++#define AR2315_PROCERR_HMAST_ENET 2
++#define AR2315_PROCERR_HMAST_PCIENDPT 3
++#define AR2315_PROCERR_HMAST_LOCAL 4
++#define AR2315_PROCERR_HMAST_CPU 5
++#define AR2315_PROCERR_HMAST_PCITGT 6
++#define AR2315_PROCERR_HMAST_S 0
++#define AR2315_PROCERR_HWRITE 0x00000010
++#define AR2315_PROCERR_HSIZE 0x00000060
++#define AR2315_PROCERR_HSIZE_S 5
++#define AR2315_PROCERR_HTRANS 0x00000180
++#define AR2315_PROCERR_HTRANS_S 7
++#define AR2315_PROCERR_HBURST 0x00000e00
++#define AR2315_PROCERR_HBURST_S 9
++
++/* Clock Control */
+#define AR2315_PLLC_CTL 0x0064
+#define AR2315_PLLV_CTL 0x0068
+#define AR2315_CPUCLK 0x006c
+#define AR2315_AMBACLK_CLK_DIV_M 0x0000000c
+#define AR2315_AMBACLK_CLK_DIV_S 2
+
-+/* GPIO MMR base address */
-+#define AR2315_GPIO 0x0088
-+
-+#define AR2315_RESET_GPIO 5
-+
-+/*
-+ * PCI Clock Control
-+ */
++/* PCI Clock Control */
+#define AR2315_PCICLK 0x00a4
+
-+#define AR2315_PCICLK_INPUT_M 0x3
-+#define AR2315_PCICLK_INPUT_S 0
-+
-+#define AR2315_PCICLK_PLLC_CLKM 0
-+#define AR2315_PCICLK_PLLC_CLKM1 1
-+#define AR2315_PCICLK_PLLC_CLKC 2
-+#define AR2315_PCICLK_REF_CLK 3
-+
-+#define AR2315_PCICLK_DIV_M 0xc
-+#define AR2315_PCICLK_DIV_S 2
-+
-+#define AR2315_PCICLK_IN_FREQ 0
-+#define AR2315_PCICLK_IN_FREQ_DIV_6 1
-+#define AR2315_PCICLK_IN_FREQ_DIV_8 2
-+#define AR2315_PCICLK_IN_FREQ_DIV_10 3
-+
-+/*
-+ * Observation Control Register
-+ */
++#define AR2315_PCICLK_INPUT_M 0x00000003
++#define AR2315_PCICLK_INPUT_S 0
++#define AR2315_PCICLK_PLLC_CLKM 0
++#define AR2315_PCICLK_PLLC_CLKM1 1
++#define AR2315_PCICLK_PLLC_CLKC 2
++#define AR2315_PCICLK_REF_CLK 3
++#define AR2315_PCICLK_DIV_M 0x0000000c
++#define AR2315_PCICLK_DIV_S 2
++#define AR2315_PCICLK_IN_FREQ 0
++#define AR2315_PCICLK_IN_FREQ_DIV_6 1
++#define AR2315_PCICLK_IN_FREQ_DIV_8 2
++#define AR2315_PCICLK_IN_FREQ_DIV_10 3
++
++/* Observation Control Register */
+#define AR2315_OCR 0x00b0
+
+#define AR2315_OCR_GPIO0_IRIN 0x00000040
+#define AR2315_OCR_GPIO1_IROUT 0x00000080
+#define AR2315_OCR_GPIO3_RXCLR 0x00000200
+
-+/*
-+ * General Clock Control
-+ */
++/* General Clock Control */
+#define AR2315_MISCCLK 0x00b4
+
+#define AR2315_MISCCLK_PLLBYPASS_EN 0x00000001
+ */
+#define AR2315_LB_CONFIG 0x0000
+
-+#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
-+#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
-+#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
-+#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
-+#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
-+#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
-+#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
-+#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
-+#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
-+#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
-+#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
-+#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
-+#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
-+#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
-+#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
-+#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
-+#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
-+#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
-+#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
-+#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
-+#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
-+#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
-+#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
-+#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
-+#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
++#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
++#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
++#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
++#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
++#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
++#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
++#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
++#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
++#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
++#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
++#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
++#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
++#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
++#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
++#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
++#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
++#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
++#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
++#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
++#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
++#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
++#define AR2315_LBCONF_INT_CTR3 0x000c0000 /* GND drive, Vdd drive */
++#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
++#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
++#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
+
+#define AR2315_LB_CLKSEL 0x0004
+
-+#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
++#define AR2315_LBCLK_EXT 0x00000001 /* use external clk for lb */
+
+#define AR2315_LB_1MS 0x0008
+
-+#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
++#define AR2315_LB1MS_MASK 0x0003ffff /* # of AHB clk cycles in 1ms */
+
+#define AR2315_LB_MISCCFG 0x000c
-+#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
-+#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
-+#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
-+#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
-+#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
++
++#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
++#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
++#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
++#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
++#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
+#define AR2315_LBM_TIMEOUT_M 0x00ffff80
+#define AR2315_LBM_TIMEOUT_S 7
-+#define AR2315_LBM_PORTMUX 0x07000000
++#define AR2315_LBM_PORTMUX 0x07000000
+
+#define AR2315_LB_RXTSOFF 0x0010
+
+#define AR2315_LB_TX_CHAIN_EN 0x0100
+
-+#define AR2315_LB_TXEN_0 0x01
-+#define AR2315_LB_TXEN_1 0x02
-+#define AR2315_LB_TXEN_2 0x04
-+#define AR2315_LB_TXEN_3 0x08
++#define AR2315_LB_TXEN_0 0x00000001
++#define AR2315_LB_TXEN_1 0x00000002
++#define AR2315_LB_TXEN_2 0x00000004
++#define AR2315_LB_TXEN_3 0x00000008
+
+#define AR2315_LB_TX_CHAIN_DIS 0x0104
+#define AR2315_LB_TX_DESC_PTR 0x0200
+
+#define AR2315_LB_RX_CHAIN_EN 0x0400
+
-+#define AR2315_LB_RXEN 0x01
++#define AR2315_LB_RXEN 0x00000001
+
+#define AR2315_LB_RX_CHAIN_DIS 0x0404
+#define AR2315_LB_RX_DESC_PTR 0x0408
+#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
--- /dev/null
+++ b/arch/mips/ath25/ar5312_regs.h
-@@ -0,0 +1,229 @@
+@@ -0,0 +1,224 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
+#define __ASM_MACH_ATH25_AR5312_REGS_H
+
-+#include <asm/addrspace.h>
-+
+/*
+ * IRQs
+ */
+/*
+ * Miscellaneous interrupts, which share IP6.
+ */
-+#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+0)
-+#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+1)
-+#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+2)
-+#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+3)
-+#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+4)
-+#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+5)
-+#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+6)
-+#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+7)
-+#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+8)
++#define AR5312_MISC_IRQ_TIMER 0
++#define AR5312_MISC_IRQ_AHB_PROC 1
++#define AR5312_MISC_IRQ_AHB_DMA 2
++#define AR5312_MISC_IRQ_GPIO 3
++#define AR5312_MISC_IRQ_UART0 4
++#define AR5312_MISC_IRQ_UART0_DMA 5
++#define AR5312_MISC_IRQ_WATCHDOG 6
++#define AR5312_MISC_IRQ_LOCAL 7
++#define AR5312_MISC_IRQ_SPI 8
+#define AR5312_MISC_IRQ_COUNT 9
+
+/*
+/*
+ * Need these defines to determine true number of ethernet MACs
+ */
-+#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
-+#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
-+#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
-+
-+/* MII registers offset inside Ethernet MMR region */
-+#define AR5312_ENET0_MII_BASE (AR5312_ENET0_BASE + 0x14)
-+#define AR5312_ENET1_MII_BASE (AR5312_ENET1_BASE + 0x14)
++#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
++#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
++#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
+
+/* Reset/Timer Block Address Map */
+#define AR5312_TIMER 0x0000 /* countdown timer */
+#define AR5312_WDT_CTRL_RESET 0x00000002
+
+/* AR5312_ISR register bit field definitions */
-+#define AR5312_ISR_TIMER 0x0001
-+#define AR5312_ISR_AHBPROC 0x0002
-+#define AR5312_ISR_AHBDMA 0x0004
-+#define AR5312_ISR_GPIO 0x0008
-+#define AR5312_ISR_UART0 0x0010
-+#define AR5312_ISR_UART0DMA 0x0020
-+#define AR5312_ISR_WD 0x0040
-+#define AR5312_ISR_LOCAL 0x0080
++#define AR5312_ISR_TIMER 0x00000001
++#define AR5312_ISR_AHBPROC 0x00000002
++#define AR5312_ISR_AHBDMA 0x00000004
++#define AR5312_ISR_GPIO 0x00000008
++#define AR5312_ISR_UART0 0x00000010
++#define AR5312_ISR_UART0DMA 0x00000020
++#define AR5312_ISR_WD 0x00000040
++#define AR5312_ISR_LOCAL 0x00000080
+
+/* AR5312_RESET register bit field definitions */
-+#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
-+#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
-+#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
-+#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
-+#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
-+#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
-+#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
-+#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
-+#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
-+#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
-+#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
-+#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
-+#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
-+#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
-+#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
-+#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
-+#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
-+#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
-+
-+#define AR5312_RESET_WMAC0_BITS \
-+ (AR5312_RESET_WLAN0 |\
-+ AR5312_RESET_WARM_WLAN0_MAC |\
-+ AR5312_RESET_WARM_WLAN0_BB)
-+
-+#define AR5312_RESET_WMAC1_BITS \
-+ (AR5312_RESET_WLAN1 |\
-+ AR5312_RESET_WARM_WLAN1_MAC |\
-+ AR5312_RESET_WARM_WLAN1_BB)
++#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
++#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
++#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC/BB */
++#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
++#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
++#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 MAC */
++#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 MAC */
++#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 */
++#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
++#define AR5312_RESET_APB 0x00000400 /* cold reset APB ar5312 */
++#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
++#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
++#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BB */
++#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the CPU */
++#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 MAC */
++#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 BB */
++#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
++#define AR5312_RESET_WDOG 0x00100000 /* last reset was a wdt */
++
++#define AR5312_RESET_WMAC0_BITS (AR5312_RESET_WLAN0 |\
++ AR5312_RESET_WARM_WLAN0_MAC |\
++ AR5312_RESET_WARM_WLAN0_BB)
++
++#define AR5312_RESET_WMAC1_BITS (AR5312_RESET_WLAN1 |\
++ AR5312_RESET_WARM_WLAN1_MAC |\
++ AR5312_RESET_WARM_WLAN1_BB)
+
+/* AR5312_CLOCKCTL1 register bit field definitions */
-+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
-+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
-+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
-+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
-+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
+
+/* Valid for AR5312 and AR2312 */
-+#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
-+#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
-+#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
-+#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
-+#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
++#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
++#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
++#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
++#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
++#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
+
+/* Valid for AR2313 */
-+#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
-+#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
-+#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
-+#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
-+#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
++#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
++#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
++#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
++#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
++#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
+
+/* AR5312_ENABLE register bit field definitions */
-+#define AR5312_ENABLE_WLAN0 0x0001
-+#define AR5312_ENABLE_ENET0 0x0002
-+#define AR5312_ENABLE_ENET1 0x0004
-+#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
-+#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
-+#define AR5312_ENABLE_WLAN1 \
-+ (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
-+ AR5312_ENABLE_WLAN1_DMA)
++#define AR5312_ENABLE_WLAN0 0x00000001
++#define AR5312_ENABLE_ENET0 0x00000002
++#define AR5312_ENABLE_ENET1 0x00000004
++#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x00000008/* UART & WLAN1 PIO */
++#define AR5312_ENABLE_WLAN1_DMA 0x00000010/* WLAN1 DMAs */
++#define AR5312_ENABLE_WLAN1 (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
++ AR5312_ENABLE_WLAN1_DMA)
+
+/* AR5312_REV register bit field definitions */
-+#define AR5312_REV_WMAC_MAJ 0xf000
-+#define AR5312_REV_WMAC_MAJ_S 12
-+#define AR5312_REV_WMAC_MIN 0x0f00
-+#define AR5312_REV_WMAC_MIN_S 8
-+#define AR5312_REV_MAJ 0x00f0
-+#define AR5312_REV_MAJ_S 4
-+#define AR5312_REV_MIN 0x000f
-+#define AR5312_REV_MIN_S 0
-+#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
++#define AR5312_REV_WMAC_MAJ 0x0000f000
++#define AR5312_REV_WMAC_MAJ_S 12
++#define AR5312_REV_WMAC_MIN 0x00000f00
++#define AR5312_REV_WMAC_MIN_S 8
++#define AR5312_REV_MAJ 0x000000f0
++#define AR5312_REV_MAJ_S 4
++#define AR5312_REV_MIN 0x0000000f
++#define AR5312_REV_MIN_S 0
++#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
+
+/* Major revision numbers, bits 7..4 of Revision ID register */
-+#define AR5312_REV_MAJ_AR5312 0x4
-+#define AR5312_REV_MAJ_AR2313 0x5
++#define AR5312_REV_MAJ_AR5312 0x4
++#define AR5312_REV_MAJ_AR2313 0x5
+
+/* Minor revision numbers, bits 3..0 of Revision ID register */
-+#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
-+#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
++#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
++#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
+
-+/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
++/*
++ * ARM Flash Controller -- 3 flash banks with either x8 or x16 devices
++ */
+#define AR5312_FLASHCTL0 0x0000
+#define AR5312_FLASHCTL1 0x0004
+#define AR5312_FLASHCTL2 0x0008
+#define AR5312_FLASHCTL_ATR 0x80000000 /* Access == retry every */
+#define AR5312_FLASHCTL_ATR4 0xc0000000 /* Access == retry every 4 */
+
-+/* ARM SDRAM Controller -- just enough to determine memory size */
++/*
++ * ARM SDRAM Controller -- just enough to determine memory size
++ */
+#define AR5312_MEM_CFG1 0x0004
+
+#define AR5312_MEM_CFG1_AC0_M 0x00000700 /* bank 0: SDRAM addr check */
+#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
--- /dev/null
+++ b/arch/mips/ath25/ar5312.c
-@@ -0,0 +1,474 @@
+@@ -0,0 +1,393 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ */
+
+/*
-+ * Platform devices for Atheros SoCs
++ * Platform devices for Atheros AR5312 SoCs
+ */
+
-+#include <generated/autoconf.h>
+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/string.h>
-+#include <linux/mtd/physmap.h>
-+#include <linux/platform_device.h>
+#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/irqdomain.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
++#include <linux/mtd/physmap.h>
+#include <linux/reboot.h>
-+#include <linux/leds.h>
-+#include <linux/gpio.h>
+#include <asm/bootinfo.h>
+#include <asm/reboot.h>
+#include <asm/time.h>
-+#include <linux/irq.h>
-+#include <linux/io.h>
+
+#include <ath25_platform.h>
+
+#include "ar5312_regs.h"
+
+static void __iomem *ar5312_rst_base;
++static struct irq_domain *ar5312_misc_irq_domain;
+
+static inline u32 ar5312_rst_reg_read(u32 reg)
+{
+
+static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
+{
-+ unsigned int ar231x_misc_intrs = ar5312_rst_reg_read(AR5312_ISR) &
-+ ar5312_rst_reg_read(AR5312_IMR);
-+
-+ if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
-+ generic_handle_irq(AR5312_MISC_IRQ_TIMER);
-+ (void)ar5312_rst_reg_read(AR5312_TIMER);
-+ } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
-+ generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
-+ else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
-+ generic_handle_irq(AR5312_MISC_IRQ_UART0);
-+ else if (ar231x_misc_intrs & AR5312_ISR_WD)
-+ generic_handle_irq(AR5312_MISC_IRQ_WATCHDOG);
-+ else
++ u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
++ ar5312_rst_reg_read(AR5312_IMR);
++ unsigned nr, misc_irq = 0;
++
++ if (pending) {
++ struct irq_domain *domain = irq_get_handler_data(irq);
++
++ nr = __ffs(pending);
++ misc_irq = irq_find_mapping(domain, nr);
++ }
++
++ if (misc_irq) {
++ generic_handle_irq(misc_irq);
++ if (nr == AR5312_MISC_IRQ_TIMER)
++ ar5312_rst_reg_read(AR5312_TIMER);
++ } else {
+ spurious_interrupt();
++ }
+}
+
+/* Enable the specified AR5312_MISC_IRQ interrupt */
+static void ar5312_misc_irq_unmask(struct irq_data *d)
+{
-+ unsigned int imr;
-+
-+ imr = ar5312_rst_reg_read(AR5312_IMR);
-+ imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
-+ ar5312_rst_reg_write(AR5312_IMR, imr);
++ ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
+}
+
+/* Disable the specified AR5312_MISC_IRQ interrupt */
+static void ar5312_misc_irq_mask(struct irq_data *d)
+{
-+ unsigned int imr;
-+
-+ imr = ar5312_rst_reg_read(AR5312_IMR);
-+ imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
-+ ar5312_rst_reg_write(AR5312_IMR, imr);
++ ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
+ ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
+}
+
+ .irq_mask = ar5312_misc_irq_mask,
+};
+
++static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
++ irq_hw_number_t hw)
++{
++ irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
++ return 0;
++}
++
++static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
++ .map = ar5312_misc_irq_map,
++};
++
+static void ar5312_irq_dispatch(void)
+{
-+ int pending = read_c0_status() & read_c0_cause();
++ u32 pending = read_c0_status() & read_c0_cause();
+
+ if (pending & CAUSEF_IP2)
+ do_IRQ(AR5312_IRQ_WLAN0);
-+ else if (pending & CAUSEF_IP3)
-+ do_IRQ(AR5312_IRQ_ENET0);
-+ else if (pending & CAUSEF_IP4)
-+ do_IRQ(AR5312_IRQ_ENET1);
+ else if (pending & CAUSEF_IP5)
+ do_IRQ(AR5312_IRQ_WLAN1);
+ else if (pending & CAUSEF_IP6)
+
+void __init ar5312_arch_init_irq(void)
+{
-+ int i;
++ struct irq_domain *domain;
++ unsigned irq;
+
+ ath25_irq_dispatch = ar5312_irq_dispatch;
-+ for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
-+ int irq = AR231X_MISC_IRQ_BASE + i;
-+
-+ irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
-+ handle_level_irq);
-+ }
-+ setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_err_interrupt);
-+ irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler);
-+}
+
-+static void ar5312_device_reset_set(u32 mask)
-+{
-+ u32 val;
++ domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
++ &ar5312_misc_irq_domain_ops, NULL);
++ if (!domain)
++ panic("Failed to add IRQ domain");
+
-+ val = ar5312_rst_reg_read(AR5312_RESET);
-+ ar5312_rst_reg_write(AR5312_RESET, val | mask);
-+}
++ irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
++ setup_irq(irq, &ar5312_ahb_err_interrupt);
+
-+static void ar5312_device_reset_clear(u32 mask)
-+{
-+ u32 val;
++ irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler);
++ irq_set_handler_data(AR5312_IRQ_MISC, domain);
+
-+ val = ar5312_rst_reg_read(AR5312_RESET);
-+ ar5312_rst_reg_write(AR5312_RESET, val & ~mask);
++ ar5312_misc_irq_domain = domain;
+}
+
+static struct physmap_flash_data ar5312_flash_data = {
+ .flags = IORESOURCE_MEM,
+};
+
-+static struct ar231x_eth ar5312_eth0_data = {
-+ .reset_set = ar5312_device_reset_set,
-+ .reset_clear = ar5312_device_reset_clear,
-+ .reset_mac = AR5312_RESET_ENET0,
-+ .reset_phy = AR5312_RESET_EPHY0,
-+};
-+
-+static struct ar231x_eth ar5312_eth1_data = {
-+ .reset_set = ar5312_device_reset_set,
-+ .reset_clear = ar5312_device_reset_clear,
-+ .reset_mac = AR5312_RESET_ENET1,
-+ .reset_phy = AR5312_RESET_EPHY1,
-+};
-+
+static struct platform_device ar5312_physmap_flash = {
+ .name = "physmap-flash",
+ .id = 0,
+ .num_resources = 1,
+};
+
-+#ifdef CONFIG_LEDS_GPIO
-+static struct gpio_led ar5312_leds[] = {
-+ { .name = "wlan", .gpio = 0, .active_low = 1, },
-+};
-+
-+static const struct gpio_led_platform_data ar5312_led_data = {
-+ .num_leds = ARRAY_SIZE(ar5312_leds),
-+ .leds = (void *)ar5312_leds,
-+};
-+
-+static struct platform_device ar5312_gpio_leds = {
-+ .name = "leds-gpio",
-+ .id = -1,
-+ .dev.platform_data = (void *)&ar5312_led_data,
-+};
-+#endif
-+
+static void __init ar5312_flash_init(void)
+{
+ void __iomem *flashctl_base;
+void __init ar5312_init_devices(void)
+{
+ struct ath25_boarddata *config;
-+ u8 *c;
+
+ ar5312_flash_init();
+
+
+ platform_device_register(&ar5312_physmap_flash);
+
-+#ifdef CONFIG_LEDS_GPIO
-+ ar5312_leds[0].gpio = config->sys_led_gpio;
-+ platform_device_register(&ar5312_gpio_leds);
-+#endif
-+
-+ /* Fix up MAC addresses if necessary */
-+ if (is_broadcast_ether_addr(config->enet0_mac))
-+ ether_addr_copy(config->enet0_mac, config->enet1_mac);
-+
-+ /* If ENET0 and ENET1 have the same mac address,
-+ * increment the one from ENET1 */
-+ if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
-+ c = config->enet1_mac + 5;
-+ while ((c >= config->enet1_mac) && !(++(*c)))
-+ c--;
-+ }
-+
+ switch (ath25_soc) {
+ case ATH25_SOC_AR5312:
-+ ar5312_eth0_data.macaddr = config->enet0_mac;
-+ ath25_add_ethernet(0, AR5312_ENET0_BASE, "eth0_mii",
-+ AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET0,
-+ &ar5312_eth0_data);
-+
-+ ar5312_eth1_data.macaddr = config->enet1_mac;
-+ ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth1_mii",
-+ AR5312_ENET1_MII_BASE, AR5312_IRQ_ENET1,
-+ &ar5312_eth1_data);
-+
+ if (!ath25_board.radio)
+ return;
+
+
+ ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
+ break;
-+ /*
-+ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
-+ * of ENET1. Atheros calls it 'twisted' for a reason :)
-+ */
+ case ATH25_SOC_AR2312:
+ case ATH25_SOC_AR2313:
-+ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
-+ ar5312_eth1_data.macaddr = config->enet0_mac;
-+ ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth0_mii",
-+ AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET1,
-+ &ar5312_eth1_data);
-+
+ if (!ath25_board.radio)
+ return;
+ break;
+
+static unsigned __init ar5312_cpu_frequency(void)
+{
-+ unsigned int scratch;
-+ unsigned int predivide_mask, predivide_shift;
-+ unsigned int multiplier_mask, multiplier_shift;
-+ unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
-+ unsigned int doubler_mask;
-+ u16 devid;
++ u32 scratch, devid, clock_ctl1;
++ u32 predivide_mask, multiplier_mask, doubler_mask;
++ unsigned predivide_shift, multiplier_shift;
++ unsigned predivide_select, predivisor, multiplier;
+
+ /* Trust the bootrom's idea of cpu frequency. */
+ scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
+ return scratch;
+
+ devid = ar5312_rst_reg_read(AR5312_REV);
-+ devid &= AR5312_REV_MAJ;
-+ devid >>= AR5312_REV_MAJ_S;
++ devid = (devid & AR5312_REV_MAJ) >> AR5312_REV_MAJ_S;
+ if (devid == AR5312_REV_MAJ_AR2313) {
+ predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
+ predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
+ * sys_freq = cpu_freq / 4 (used for APB clock, serial,
+ * flash, Timer, Watchdog Timer)
+ *
-+ * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
++ * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
+ *
+ * So, for example, with a PLL multiplier of 5, we have
+ *
+ multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
+
+ if (clock_ctl1 & doubler_mask)
-+ multiplier = multiplier << 1;
++ multiplier <<= 1;
+
+ return (40000000 / predivisor) * multiplier;
+}
+
+void __init ar5312_arch_init(void)
+{
-+ ath25_serial_setup(AR5312_UART0_BASE, AR5312_MISC_IRQ_UART0,
-+ ar5312_sys_frequency());
++ unsigned irq = irq_create_mapping(ar5312_misc_irq_domain,
++ AR5312_MISC_IRQ_UART0);
++
++ ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency());
+}
--- /dev/null
+++ b/arch/mips/ath25/ar2315.c
-@@ -0,0 +1,418 @@
+@@ -0,0 +1,308 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ */
+
+/*
-+ * Platform devices for Atheros SoCs
++ * Platform devices for Atheros AR2315 SoCs
+ */
+
-+#include <generated/autoconf.h>
+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/types.h>
-+#include <linux/string.h>
-+#include <linux/platform_device.h>
+#include <linux/kernel.h>
++#include <linux/bitops.h>
++#include <linux/irqdomain.h>
++#include <linux/interrupt.h>
++#include <linux/platform_device.h>
+#include <linux/reboot.h>
-+#include <linux/delay.h>
-+#include <linux/leds.h>
-+#include <linux/gpio.h>
+#include <asm/bootinfo.h>
+#include <asm/reboot.h>
+#include <asm/time.h>
-+#include <linux/irq.h>
-+#include <linux/io.h>
+
+#include <ath25_platform.h>
+
+#include "ar2315_regs.h"
+
+static void __iomem *ar2315_rst_base;
++static struct irq_domain *ar2315_misc_irq_domain;
+
+static inline u32 ar2315_rst_reg_read(u32 reg)
+{
+
+static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
+{
-+ unsigned int misc_intr = ar2315_rst_reg_read(AR2315_ISR) &
-+ ar2315_rst_reg_read(AR2315_IMR);
-+
-+ if (misc_intr & AR2315_ISR_SPI)
-+ generic_handle_irq(AR2315_MISC_IRQ_SPI);
-+ else if (misc_intr & AR2315_ISR_TIMER)
-+ generic_handle_irq(AR2315_MISC_IRQ_TIMER);
-+ else if (misc_intr & AR2315_ISR_AHB)
-+ generic_handle_irq(AR2315_MISC_IRQ_AHB);
-+ else if (misc_intr & AR2315_ISR_GPIO) {
-+ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
-+ generic_handle_irq(AR2315_MISC_IRQ_GPIO);
-+ } else if (misc_intr & AR2315_ISR_UART0)
-+ generic_handle_irq(AR2315_MISC_IRQ_UART0);
-+ else if (misc_intr & AR2315_ISR_WD) {
-+ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
-+ generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
-+ } else
++ u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
++ ar2315_rst_reg_read(AR2315_IMR);
++ unsigned nr, misc_irq = 0;
++
++ if (pending) {
++ struct irq_domain *domain = irq_get_handler_data(irq);
++
++ nr = __ffs(pending);
++ misc_irq = irq_find_mapping(domain, nr);
++ }
++
++ if (misc_irq) {
++ if (nr == AR2315_MISC_IRQ_GPIO)
++ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
++ else if (nr == AR2315_MISC_IRQ_WATCHDOG)
++ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
++ generic_handle_irq(misc_irq);
++ } else {
+ spurious_interrupt();
++ }
+}
+
+static void ar2315_misc_irq_unmask(struct irq_data *d)
+{
-+ unsigned int imr;
-+
-+ imr = ar2315_rst_reg_read(AR2315_IMR);
-+ imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
-+ ar2315_rst_reg_write(AR2315_IMR, imr);
++ ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
+}
+
+static void ar2315_misc_irq_mask(struct irq_data *d)
+{
-+ unsigned int imr;
-+
-+ imr = ar2315_rst_reg_read(AR2315_IMR);
-+ imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
-+ ar2315_rst_reg_write(AR2315_IMR, imr);
++ ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
+}
+
+static struct irq_chip ar2315_misc_irq_chip = {
+ .irq_mask = ar2315_misc_irq_mask,
+};
+
++static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
++ irq_hw_number_t hw)
++{
++ irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
++ return 0;
++}
++
++static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
++ .map = ar2315_misc_irq_map,
++};
++
+/*
+ * Called when an interrupt is received, this function
+ * determines exactly which interrupt it was, and it
+ */
+static void ar2315_irq_dispatch(void)
+{
-+ int pending = read_c0_status() & read_c0_cause();
++ u32 pending = read_c0_status() & read_c0_cause();
+
+ if (pending & CAUSEF_IP3)
+ do_IRQ(AR2315_IRQ_WLAN0);
-+ else if (pending & CAUSEF_IP4)
-+ do_IRQ(AR2315_IRQ_ENET0);
+ else if (pending & CAUSEF_IP2)
+ do_IRQ(AR2315_IRQ_MISC);
+ else if (pending & CAUSEF_IP7)
+
+void __init ar2315_arch_init_irq(void)
+{
-+ int i;
++ struct irq_domain *domain;
++ unsigned irq;
+
+ ath25_irq_dispatch = ar2315_irq_dispatch;
-+ for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
-+ int irq = AR231X_MISC_IRQ_BASE + i;
-+
-+ irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
-+ handle_level_irq);
-+ }
-+ setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_err_interrupt);
-+ irq_set_chained_handler(AR2315_IRQ_MISC, ar2315_misc_irq_handler);
-+}
-+
-+static void ar2315_device_reset_set(u32 mask)
-+{
-+ u32 val;
-+
-+ val = ar2315_rst_reg_read(AR2315_RESET);
-+ ar2315_rst_reg_write(AR2315_RESET, val | mask);
-+}
-+
-+static void ar2315_device_reset_clear(u32 mask)
-+{
-+ u32 val;
-+
-+ val = ar2315_rst_reg_read(AR2315_RESET);
-+ ar2315_rst_reg_write(AR2315_RESET, val & ~mask);
-+}
-+
-+static struct ar231x_eth ar2315_eth_data = {
-+ .reset_set = ar2315_device_reset_set,
-+ .reset_clear = ar2315_device_reset_clear,
-+ .reset_mac = AR2315_RESET_ENET0,
-+ .reset_phy = AR2315_RESET_EPHY0,
-+};
-+
-+static struct resource ar2315_spiflash_res[] = {
-+ {
-+ .name = "spiflash_read",
-+ .flags = IORESOURCE_MEM,
-+ .start = AR2315_SPI_READ_BASE,
-+ .end = AR2315_SPI_READ_BASE + AR2315_SPI_READ_SIZE - 1,
-+ },
-+ {
-+ .name = "spiflash_mmr",
-+ .flags = IORESOURCE_MEM,
-+ .start = AR2315_SPI_MMR_BASE,
-+ .end = AR2315_SPI_MMR_BASE + AR2315_SPI_MMR_SIZE - 1,
-+ },
-+};
-+
-+static struct platform_device ar2315_spiflash = {
-+ .id = 0,
-+ .name = "ar2315-spiflash",
-+ .resource = ar2315_spiflash_res,
-+ .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
-+};
-+
-+static struct resource ar2315_wdt_res[] = {
-+ {
-+ .flags = IORESOURCE_MEM,
-+ .start = AR2315_RST_BASE + AR2315_WDT_TIMER,
-+ .end = AR2315_RST_BASE + AR2315_WDT_TIMER + 8 - 1,
-+ },
-+ {
-+ .flags = IORESOURCE_IRQ,
-+ .start = AR2315_MISC_IRQ_WATCHDOG,
-+ .end = AR2315_MISC_IRQ_WATCHDOG,
-+ }
-+};
-+
-+static struct platform_device ar2315_wdt = {
-+ .id = 0,
-+ .name = "ar2315-wdt",
-+ .resource = ar2315_wdt_res,
-+ .num_resources = ARRAY_SIZE(ar2315_wdt_res)
-+};
-+
-+#ifdef CONFIG_LEDS_GPIO
-+static struct gpio_led ar2315_leds[6];
-+static struct gpio_led_platform_data ar2315_led_data = {
-+ .leds = (void *)ar2315_leds,
-+};
+
-+static struct platform_device ar2315_gpio_leds = {
-+ .name = "leds-gpio",
-+ .id = -1,
-+ .dev = {
-+ .platform_data = (void *)&ar2315_led_data,
-+ }
-+};
-+
-+static void __init ar2315_init_gpio_leds(void)
-+{
-+ static char led_names[6][6];
-+ int i, led = 0;
++ domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
++ &ar2315_misc_irq_domain_ops, NULL);
++ if (!domain)
++ panic("Failed to add IRQ domain");
+
-+ ar2315_led_data.num_leds = 0;
-+ for (i = 1; i < 8; i++) {
-+ if ((i == AR2315_RESET_GPIO) ||
-+ (i == ath25_board.config->reset_config_gpio))
-+ continue;
++ irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
++ setup_irq(irq, &ar2315_ahb_err_interrupt);
+
-+ if (i == ath25_board.config->sys_led_gpio)
-+ strcpy(led_names[led], "wlan");
-+ else
-+ sprintf(led_names[led], "gpio%d", i);
++ irq_set_chained_handler(AR2315_IRQ_MISC, ar2315_misc_irq_handler);
++ irq_set_handler_data(AR2315_IRQ_MISC, domain);
+
-+ ar2315_leds[led].name = led_names[led];
-+ ar2315_leds[led].gpio = i;
-+ ar2315_leds[led].active_low = 0;
-+ led++;
-+ }
-+ ar2315_led_data.num_leds = led;
-+ platform_device_register(&ar2315_gpio_leds);
++ ar2315_misc_irq_domain = domain;
+}
-+#else
-+static inline void ar2315_init_gpio_leds(void)
-+{
-+}
-+#endif
+
+void __init ar2315_init_devices(void)
+{
+ /* Find board configuration */
+ ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
-+ ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
-+
-+ ar2315_init_gpio_leds();
-+ platform_device_register(&ar2315_wdt);
-+ platform_device_register(&ar2315_spiflash);
-+ ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii",
-+ AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0,
-+ &ar2315_eth_data);
++
+ ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
+}
+
+ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
+ * a workaround. Give it some time to attempt a gpio based hardware
+ * reset (atheros reference design workaround) */
-+ gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
-+ mdelay(100);
++
++ /* TODO: implement the GPIO reset workaround */
+
+ /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
+ * workaround. Attempt to jump to the mips reset location -
+ refdiv = clockctl1_predivide_table[refdiv];
+ fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
+ divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
-+ pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
++ pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv;
+
+ /* clkm input selected */
+ switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
+ u32 devid;
+ u32 config;
+
++ /* Detect memory size */
+ sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE,
+ AR2315_SDRAMCTL_SIZE);
+ memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
+
+void __init ar2315_arch_init(void)
+{
-+ ath25_serial_setup(AR2315_UART0_BASE, AR2315_MISC_IRQ_UART0,
-+ ar2315_apb_frequency());
++ unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
++ AR2315_MISC_IRQ_UART0);
++
++ ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
+}
--- /dev/null
+++ b/arch/mips/ath25/ar2315.h
-@@ -0,0 +1,36 @@
+@@ -0,0 +1,22 @@
+#ifndef __AR2315_H
+#define __AR2315_H
+
+
+#else
+
-+static inline void ar2315_arch_init_irq(void)
-+{
-+}
-+
-+static inline void ar2315_init_devices(void)
-+{
-+}
-+
-+static inline void ar2315_plat_time_init(void)
-+{
-+}
-+
-+static inline void ar2315_plat_mem_setup(void)
-+{
-+}
-+
-+static inline void ar2315_arch_init(void)
-+{
-+}
++static inline void ar2315_arch_init_irq(void) {}
++static inline void ar2315_init_devices(void) {}
++static inline void ar2315_plat_time_init(void) {}
++static inline void ar2315_plat_mem_setup(void) {}
++static inline void ar2315_arch_init(void) {}
+
+#endif
+
-+#endif
++#endif /* __AR2315_H */
--- /dev/null
+++ b/arch/mips/ath25/ar5312.h
-@@ -0,0 +1,36 @@
+@@ -0,0 +1,22 @@
+#ifndef __AR5312_H
+#define __AR5312_H
+
+
+#else
+
-+static inline void ar5312_arch_init_irq(void)
-+{
-+}
-+
-+static inline void ar5312_init_devices(void)
-+{
-+}
-+
-+static inline void ar5312_plat_time_init(void)
-+{
-+}
-+
-+static inline void ar5312_plat_mem_setup(void)
-+{
-+}
-+
-+static inline void ar5312_arch_init(void)
-+{
-+}
++static inline void ar5312_arch_init_irq(void) {}
++static inline void ar5312_init_devices(void) {}
++static inline void ar5312_plat_time_init(void) {}
++static inline void ar5312_plat_mem_setup(void) {}
++static inline void ar5312_arch_init(void) {}
+
+#endif
+
-+#endif
++#endif /* __AR5312_H */
--- /dev/null
+++ b/arch/mips/ath25/devices.h
-@@ -0,0 +1,46 @@
+@@ -0,0 +1,43 @@
+#ifndef __ATH25_DEVICES_H
+#define __ATH25_DEVICES_H
+
-+#define AR231X_MISC_IRQ_BASE 0x20
-+#define AR231X_GPIO_IRQ_BASE 0x30
++#include <linux/cpu.h>
+
+#define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
+
-+#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
++#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
+
+enum ath25_soc_type {
+ /* handled by ar5312.c */
+extern void (*ath25_irq_dispatch)(void);
+
+int ath25_find_config(phys_addr_t offset, unsigned long size);
-+int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
-+ int irq, void *pdata);
+void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
+int ath25_add_wmac(int nr, u32 base, int irq);
+
+#endif
--- /dev/null
+++ b/arch/mips/ath25/devices.c
-@@ -0,0 +1,191 @@
+@@ -0,0 +1,125 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
-+#include <linux/serial.h>
-+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+#include <linux/platform_device.h>
+#include <asm/bootinfo.h>
+struct ar231x_board_config ath25_board;
+enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
+
-+static struct resource ath25_eth0_res[] = {
-+ {
-+ .name = "eth0_membase",
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .name = "eth0_mii",
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .name = "eth0_irq",
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct resource ath25_eth1_res[] = {
-+ {
-+ .name = "eth1_membase",
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .name = "eth1_mii",
-+ .flags = IORESOURCE_MEM,
-+ },
-+ {
-+ .name = "eth1_irq",
-+ .flags = IORESOURCE_IRQ,
-+ }
-+};
-+
-+static struct platform_device ath25_eth[] = {
-+ {
-+ .id = 0,
-+ .name = "ar231x-eth",
-+ .resource = ath25_eth0_res,
-+ .num_resources = ARRAY_SIZE(ath25_eth0_res)
-+ },
-+ {
-+ .id = 1,
-+ .name = "ar231x-eth",
-+ .resource = ath25_eth1_res,
-+ .num_resources = ARRAY_SIZE(ath25_eth1_res)
-+ }
-+};
-+
+static struct resource ath25_wmac0_res[] = {
+ {
+ .name = "wmac0_membase",
+ return soc_type_strings[ath25_soc];
+}
+
-+int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name,
-+ u32 mii_base, int irq, void *pdata)
-+{
-+ struct resource *res;
-+
-+ ath25_eth[nr].dev.platform_data = pdata;
-+ res = &ath25_eth[nr].resource[0];
-+ res->start = base;
-+ res->end = base + 0x2000 - 1;
-+ res++;
-+ res->name = mii_name;
-+ res->start = mii_base;
-+ res->end = mii_base + 8 - 1;
-+ res++;
-+ res->start = irq;
-+ res->end = irq;
-+ return platform_device_register(&ath25_eth[nr]);
-+}
-+
+void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
+{
+ struct uart_port s;
projects / openwrt / staging / chunkeey.git / blobdiff