endchoice
-+source "arch/mips/ar231x/Kconfig"
++source "arch/mips/ath25/Kconfig"
source "arch/mips/alchemy/Kconfig"
source "arch/mips/ath79/Kconfig"
source "arch/mips/bcm47xx/Kconfig"
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
-@@ -6,6 +6,7 @@ platforms += ath79
+@@ -2,6 +2,7 @@
+
+ platforms += alchemy
+ platforms += ar7
++platforms += ath25
+ platforms += ath79
platforms += bcm47xx
platforms += bcm63xx
- platforms += cavium-octeon
-+platforms += ar231x
- platforms += cobalt
- platforms += dec
- platforms += emma
--- /dev/null
-+++ b/arch/mips/ar231x/Platform
++++ b/arch/mips/ath25/Platform
@@ -0,0 +1,6 @@
+#
+# Atheros AR531X/AR231X WiSoC
+#
-+platform-$(CONFIG_ATH25) += ar231x/
-+cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
++platform-$(CONFIG_ATH25) += ath25/
++cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
+load-$(CONFIG_ATH25) += 0xffffffff80041000
--- /dev/null
-+++ b/arch/mips/ar231x/Kconfig
++++ b/arch/mips/ath25/Kconfig
@@ -0,0 +1,9 @@
+config SOC_AR5312
+ bool "Atheros 5312/2312+ support"
+ depends on ATH25
+ default y
--- /dev/null
-+++ b/arch/mips/ar231x/Makefile
++++ b/arch/mips/ath25/Makefile
@@ -0,0 +1,13 @@
+#
+# This file is subject to the terms and conditions of the GNU General Public
+obj-$(CONFIG_SOC_AR5312) += ar5312.o
+obj-$(CONFIG_SOC_AR2315) += ar2315.o
--- /dev/null
-+++ b/arch/mips/ar231x/board.c
-@@ -0,0 +1,229 @@
++++ b/arch/mips/ath25/board.c
+@@ -0,0 +1,234 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+#include <asm/bootinfo.h>
+#include <asm/time.h>
+
-+#include <ar231x_platform.h>
++#include <ath25_platform.h>
+#include "devices.h"
+#include "ar5312.h"
+#include "ar2315.h"
+
-+void (*ar231x_irq_dispatch)(void);
++void (*ath25_irq_dispatch)(void);
+
+static inline bool check_radio_magic(u8 *addr)
+{
+static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
+{
+ /* config magic found */
-+ if (*((u32 *)addr) == AR231X_BD_MAGIC)
++ if (*((u32 *)addr) == ATH25_BD_MAGIC)
+ return true;
+
+ if (!broken)
+ return false;
+
+ if (check_radio_magic(addr + 0xf8))
-+ ar231x_board.radio = addr + 0xf8;
++ ath25_board.radio = addr + 0xf8;
+ if ((addr < flash_limit + 0x10000) &&
+ check_radio_magic(addr + 0x10000))
-+ ar231x_board.radio = addr + 0x10000;
++ ath25_board.radio = addr + 0x10000;
+
-+ if (ar231x_board.radio) {
++ if (ath25_board.radio) {
+ /* broken board data detected, use radio data to find the
+ * offset, user will fix this */
+ return true;
+ return NULL;
+}
+
-+int __init ar231x_find_config(u8 *flash_limit)
++int __init ath25_find_config(u8 *flash_limit)
+{
-+ struct ar231x_boarddata *config;
++ struct ath25_boarddata *config;
+ unsigned int rcfg_size;
+ int broken_boarddata = 0;
+ u8 *bcfg, *rcfg;
+ u8 *mac_addr;
+ u32 offset;
+
-+ ar231x_board.config = NULL;
-+ ar231x_board.radio = NULL;
++ ath25_board.config = NULL;
++ ath25_board.radio = NULL;
+ /* Copy the board and radio data to RAM, because accessing the mapped
+ * memory of the flash directly after booting is not safe */
+
+ }
+
+ board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
-+ ar231x_board.config = (struct ar231x_boarddata *)board_data;
++ ath25_board.config = (struct ath25_boarddata *)board_data;
+ memcpy(board_data, bcfg, 0x100);
+ if (broken_boarddata) {
+ pr_warn("WARNING: broken board data detected\n");
-+ config = ar231x_board.config;
++ config = ath25_board.config;
+ if (is_zero_ether_addr(config->enet0_mac)) {
+ pr_info("Fixing up empty mac addresses\n");
+ config->reset_config_gpio = 0xffff;
+ /* Radio config starts 0x100 bytes after board config, regardless
+ * of what the physical layout on the flash chip looks like */
+
-+ if (ar231x_board.radio)
-+ rcfg = (u8 *)ar231x_board.radio;
++ if (ath25_board.radio)
++ rcfg = (u8 *)ath25_board.radio;
+ else
+ rcfg = find_radio_config(flash_limit, bcfg);
+
+ return -ENODEV;
+
+ radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
-+ ar231x_board.radio = radio_data;
++ ath25_board.radio = radio_data;
+ offset = radio_data - board_data;
+ pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
+ offset);
+ mac_addr = &radio_data[0x1d * 2];
+ if (is_broadcast_ether_addr(mac_addr)) {
+ pr_info("Radio MAC is blank; using board-data\n");
-+ ether_addr_copy(mac_addr, ar231x_board.config->wlan0_mac);
++ ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
+ }
+
+ return 0;
+}
+
-+static void ar231x_halt(void)
++static void ath25_halt(void)
+{
+ local_irq_disable();
+ while (1)
+
+void __init plat_mem_setup(void)
+{
-+ _machine_halt = ar231x_halt;
-+ pm_power_off = ar231x_halt;
++ _machine_halt = ath25_halt;
++ pm_power_off = ath25_halt;
+
-+ ar5312_plat_setup();
-+ ar2315_plat_setup();
++ if (is_ar5312())
++ ar5312_plat_mem_setup();
++ else
++ ar2315_plat_mem_setup();
+
+ /* Disable data watchpoints */
+ write_c0_watchlo0(0);
+
+asmlinkage void plat_irq_dispatch(void)
+{
-+ ar231x_irq_dispatch();
++ ath25_irq_dispatch();
+}
+
+void __init plat_time_init(void)
+{
-+ ar5312_time_init();
-+ ar2315_time_init();
++ if (is_ar5312())
++ ar5312_plat_time_init();
++ else
++ ar2315_plat_time_init();
+}
+
+unsigned int __cpuinit get_c0_compare_int(void)
+ mips_cpu_irq_init();
+
+ /* Initialize interrupt controllers */
-+ ar5312_irq_init();
-+ ar2315_irq_init();
++ if (is_ar5312())
++ ar5312_arch_init_irq();
++ else
++ ar2315_arch_init_irq();
+}
-+
--- /dev/null
-+++ b/arch/mips/ar231x/prom.c
-@@ -0,0 +1,37 @@
++++ b/arch/mips/ath25/prom.c
+@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ */
+
+#include <linux/init.h>
-+#include <generated/autoconf.h>
-+#include <linux/kernel.h>
-+#include <linux/string.h>
-+#include <linux/mm.h>
-+#include <linux/bootmem.h>
-+
+#include <asm/bootinfo.h>
-+#include <asm/addrspace.h>
-+#include "ar5312.h"
-+#include "ar2315.h"
+
+void __init prom_init(void)
+{
-+ ar5312_prom_init();
-+ ar2315_prom_init();
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
--- /dev/null
-+++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
-@@ -0,0 +1,85 @@
-+#ifndef __ASM_MACH_AR231X_PLATFORM_H
-+#define __ASM_MACH_AR231X_PLATFORM_H
++++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
+@@ -0,0 +1,84 @@
++#ifndef __ASM_MACH_ATH25_PLATFORM_H
++#define __ASM_MACH_ATH25_PLATFORM_H
+
+#include <linux/etherdevice.h>
+
+ * The main reason we need it is in order to extract the ethernet MAC
+ * address(es).
+ */
-+struct ar231x_boarddata {
++struct ath25_boarddata {
+ u32 magic; /* board data is valid */
-+#define AR231X_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
++#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
+ u16 cksum; /* checksum (starting with BD_REV 2) */
+ u16 rev; /* revision of this struct */
+#define BD_REV 4
+ u16 devid;
+
+ /* board config data */
-+ struct ar231x_boarddata *config;
++ struct ath25_boarddata *config;
+
+ /* radio calibration data */
+ const char *radio;
+ void (*reset_clear)(u32);
+ u32 reset_mac;
+ u32 reset_phy;
-+ struct ar231x_board_config *config;
+ char *macaddr;
+};
+
-+#endif /* __ASM_MACH_AR231X_PLATFORM_H */
++#endif /* __ASM_MACH_ATH25_PLATFORM_H */
--- /dev/null
-+++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
-@@ -0,0 +1,84 @@
++++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
+@@ -0,0 +1,64 @@
+/*
+ * Atheros AR231x/AR531x SoC specific CPU feature overrides
+ *
+ * by the Free Software Foundation.
+ *
+ */
-+#ifndef __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
-+#define __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
++#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
++#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
+#define cpu_has_fpu 0
+#define cpu_has_32fpr 0
+#define cpu_has_counter 1
-+/* #define cpu_has_watch ? */
-+/* #define cpu_has_divec ? */
-+/* #define cpu_has_vce ? */
-+/* #define cpu_has_cache_cdex_p ? */
-+/* #define cpu_has_cache_cdex_s ? */
-+/* #define cpu_has_prefetch ? */
-+/* #define cpu_has_mcheck ? */
+#define cpu_has_ejtag 1
+
+#if !defined(CONFIG_SOC_AR5312)
+#define cpu_has_mips3d 0
+#define cpu_has_smartmips 0
+
-+/* #define cpu_has_vtag_icache ? */
-+/* #define cpu_has_dc_aliases ? */
-+/* #define cpu_has_ic_fills_f_dc ? */
-+/* #define cpu_has_pindexed_dcache ? */
-+
-+/* #define cpu_icache_snoops_remote_store ? */
-+
+#define cpu_has_mips32r1 1
+
+#if !defined(CONFIG_SOC_AR5312)
+#define cpu_has_dsp 0
+#define cpu_has_mipsmt 0
+
-+/* #define cpu_has_nofpuex ? */
+#define cpu_has_64bits 0
+#define cpu_has_64bit_zero_reg 0
+#define cpu_has_64bit_gp_regs 0
+#define cpu_has_64bit_addresses 0
+
-+/* #define cpu_has_inclusive_pcaches ? */
-+
-+/* #define cpu_dcache_line_size() ? */
-+/* #define cpu_icache_line_size() ? */
-+
-+#endif /* __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H */
++#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
--- /dev/null
-+++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
-@@ -0,0 +1,76 @@
++++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
+@@ -0,0 +1,82 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
+ *
+ */
-+#ifndef __ASM_MACH_AR231X_DMA_COHERENCE_H
-+#define __ASM_MACH_AR231X_DMA_COHERENCE_H
++#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
++#define __ASM_MACH_ATH25_DMA_COHERENCE_H
+
+#include <linux/device.h>
-+#include <ar2315_regs.h>
+
-+static inline dma_addr_t ar231x_dev_offset(struct device *dev)
++/*
++ * We need some arbitrary non-zero value to be programmed to the BAR1 register
++ * of PCI host controller to enable DMA. The same value should be used as the
++ * offset to calculate the physical address of DMA buffer for PCI devices.
++ */
++#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
++
++static inline dma_addr_t ath25_dev_offset(struct device *dev)
+{
+#ifdef CONFIG_PCI
+ extern struct bus_type pci_bus_type;
+static inline dma_addr_t
+plat_map_dma_mem(struct device *dev, void *addr, size_t size)
+{
-+ return virt_to_phys(addr) + ar231x_dev_offset(dev);
++ return virt_to_phys(addr) + ath25_dev_offset(dev);
+}
+
+static inline dma_addr_t
+plat_map_dma_mem_page(struct device *dev, struct page *page)
+{
-+ return page_to_phys(page) + ar231x_dev_offset(dev);
++ return page_to_phys(page) + ath25_dev_offset(dev);
+}
+
+static inline unsigned long
+plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
+{
-+ return dma_addr - ar231x_dev_offset(dev);
++ return dma_addr - ath25_dev_offset(dev);
+}
+
+static inline void
+#endif
+}
+
-+#endif /* __ASM_MACH_AR231X_DMA_COHERENCE_H */
++#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
--- /dev/null
-+++ b/arch/mips/include/asm/mach-ar231x/gpio.h
++++ b/arch/mips/include/asm/mach-ath25/gpio.h
@@ -0,0 +1,16 @@
-+#ifndef __ASM_MACH_AR231X_GPIO_H
-+#define __ASM_MACH_AR231X_GPIO_H
++#ifndef __ASM_MACH_ATH25_GPIO_H
++#define __ASM_MACH_ATH25_GPIO_H
+
+#include <asm-generic/gpio.h>
+
+ return -EINVAL;
+}
+
-+#endif /* __ASM_MACH_AR231X_GPIO_H */
---- /dev/null
-+++ b/arch/mips/include/asm/mach-ar231x/reset.h
-@@ -0,0 +1,6 @@
-+#ifndef __ASM_MACH_AR231X_RESET_H
-+#define __ASM_MACH_AR231X_RESET_H
-+
-+void ar231x_disable_reset_button(void);
-+
-+#endif /* __ASM_MACH_AR231X_RESET_H */
++#endif /* __ASM_MACH_ATH25_GPIO_H */
--- /dev/null
-+++ b/arch/mips/include/asm/mach-ar231x/war.h
++++ b/arch/mips/include/asm/mach-ath25/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ *
+ * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
+ */
-+#ifndef __ASM_MACH_AR231X_WAR_H
-+#define __ASM_MACH_AR231X_WAR_H
++#ifndef __ASM_MACH_ATH25_WAR_H
++#define __ASM_MACH_ATH25_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR 0
+#define R4600_V1_HIT_CACHEOP_WAR 0
+#define R10000_LLSC_WAR 0
+#define MIPS34K_MISSED_ITLB_WAR 0
+
-+#endif /* __ASM_MACH_AR231X_WAR_H */
++#endif /* __ASM_MACH_ATH25_WAR_H */
--- /dev/null
-+++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
-@@ -0,0 +1,608 @@
++++ b/arch/mips/ath25/ar2315_regs.h
+@@ -0,0 +1,480 @@
+/*
+ * Register definitions for AR2315+
+ *
+ * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
+ */
+
-+#ifndef __ASM_MACH_AR231X_AR2315_REGS_H
-+#define __ASM_MACH_AR231X_AR2315_REGS_H
++#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
++#define __ASM_MACH_ATH25_AR2315_REGS_H
+
+/*
+ * IRQs
+#define AR2315_MISC_IRQ_COUNT 9
+
+/*
-+ * PCI interrupts, which share IP5
-+ * Keep ordered according to AR2315_PCI_INT_XXX bits
-+ */
-+#define AR2315_PCI_IRQ_BASE 0x50
-+#define AR2315_PCI_IRQ_EXT (AR2315_PCI_IRQ_BASE+0)
-+#define AR2315_PCI_IRQ_ABORT (AR2315_PCI_IRQ_BASE+1)
-+#define AR2315_PCI_IRQ_COUNT 2
-+#define AR2315_PCI_IRQ_SHIFT 25 /* in AR2315_PCI_INT_STATUS */
-+
-+/*
+ * Address map
+ */
+#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
+#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
+#define AR2315_PCI 0x10100000 /* PCI MMR */
-+#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
-+#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
++#define AR2315_PCI_SIZE 0x00001000
++#define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */
++#define AR2315_SDRAMCTL_SIZE 0x00000020
++#define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */
+#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
-+#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
++#define AR2315_RST_BASE 0x11000000 /* Reset control MMR */
++#define AR2315_RST_SIZE 0x00000100
+#define AR2315_UART0 0x11100000 /* UART MMR */
+#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
+#define AR2315_PCIEXT 0x80000000 /* pci external */
+/*
+ * Cold reset register
+ */
-+#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
++#define AR2315_COLD_RESET 0x0000
+
+#define AR2315_RESET_COLD_AHB 0x00000001
+#define AR2315_RESET_COLD_APB 0x00000002
+/*
+ * Reset register
+ */
-+#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
++#define AR2315_RESET 0x0004
+
+/* warm reset WLAN0 MAC */
+#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
+/*
+ * AHB master arbitration control
+ */
-+#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
++#define AR2315_AHB_ARB_CTL 0x0008
+
+/* CPU, default */
+#define AR2315_ARB_CPU 0x00000001
+/*
+ * Config Register
+ */
-+#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
++#define AR2315_ENDIAN_CTL 0x000c
+
+/* EC - AHB bridge endianess */
+#define AR2315_CONFIG_AHB 0x00000001
+/*
+ * NMI control
+ */
-+#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
++#define AR2315_NMI_CTL 0x0010
+
+#define AR2315_NMI_EN 1
+
+/*
+ * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
+ */
-+#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
++#define AR2315_SREV 0x0014
+
+#define AR2315_REV_MAJ 0x00f0
+#define AR2315_REV_MAJ_S 4
+/*
+ * Interface Enable
+ */
-+#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
++#define AR2315_IF_CTL 0x0018
+
+#define AR2315_IF_MASK 0x00000007
+#define AR2315_IF_DISABLED 0
+ * APB Interrupt control
+ */
+
-+#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
-+#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
-+#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
++#define AR2315_ISR 0x0020
++#define AR2315_IMR 0x0024
++#define AR2315_GISR 0x0028
+
+#define AR2315_ISR_UART0 0x0001 /* high speed UART */
+#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
+#define AR2315_GISR_ETHERNET 0x0040
+
+/*
-+ * Interrupt routing from IO to the processor IP bits
-+ * Define our inter mask and level
-+ */
-+#define AR2315_INTR_MISCIO SR_IBIT3
-+#define AR2315_INTR_WLAN0 SR_IBIT4
-+#define AR2315_INTR_ENET0 SR_IBIT5
-+#define AR2315_INTR_LOCALPCI SR_IBIT6
-+#define AR2315_INTR_WMACPOLL SR_IBIT7
-+#define AR2315_INTR_COMPARE SR_IBIT8
-+
-+/*
+ * Timers
+ */
-+#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
-+#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
-+#define AR2315_WD (AR2315_DSLBASE + 0x0038)
-+#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
++#define AR2315_TIMER 0x0030
++#define AR2315_RELOAD 0x0034
++
++#define AR2315_WD 0x0038
++#define AR2315_WDC 0x003c
+
+#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
+#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
+/*
+ * CPU Performance Counters
+ */
-+#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
-+#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
++#define AR2315_PERFCNT0 0x0048
++#define AR2315_PERFCNT1 0x004c
+
+#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
+#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
+/*
+ * AHB Error Reporting.
+ */
-+#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
-+#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
-+#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
-+#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
-+#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
++#define AR2315_AHB_ERR0 0x0050 /* error */
++#define AR2315_AHB_ERR1 0x0054 /* haddr */
++#define AR2315_AHB_ERR2 0x0058 /* hwdata */
++#define AR2315_AHB_ERR3 0x005c /* hrdata */
++#define AR2315_AHB_ERR4 0x0060 /* status */
+
+#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
+ /* write 1 to clear all bits in ERR0 */
+/*
+ * Clock Control
+ */
-+#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
-+#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
-+#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
-+#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
-+#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
-+#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
-+#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
++#define AR2315_PLLC_CTL 0x0064
++#define AR2315_PLLV_CTL 0x0068
++#define AR2315_CPUCLK 0x006c
++#define AR2315_AMBACLK 0x0070
++#define AR2315_SYNCCLK 0x0074
++#define AR2315_DSL_SLEEP_CTL 0x0080
++#define AR2315_DSL_SLEEP_DUR 0x0084
+
+/* PLLc Control fields */
+#define PLLC_REF_DIV_M 0x00000003
+#define AMBACLK_CLK_DIV_S 2
+
+/* GPIO MMR base address */
-+#define AR2315_GPIO (AR2315_DSLBASE + 0x0088)
++#define AR2315_GPIO 0x0088
+
+#define AR2315_RESET_GPIO 5
+
+/*
+ * PCI Clock Control
+ */
-+#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
++#define AR2315_PCICLK 0x00a4
+
+#define AR2315_PCICLK_INPUT_M 0x3
+#define AR2315_PCICLK_INPUT_S 0
+/*
+ * Observation Control Register
+ */
-+#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
++#define AR2315_OCR 0x00b0
++
+#define OCR_GPIO0_IRIN 0x0040
+#define OCR_GPIO1_IROUT 0x0080
+#define OCR_GPIO3_RXCLR 0x0200
+/*
+ * General Clock Control
+ */
++#define AR2315_MISCCLK 0x00b4
+
-+#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
+#define MISCCLK_PLLBYPASS_EN 0x00000001
+#define MISCCLK_PROCREFCLK 0x00000002
+
+ * SDRAM Controller
+ * - No read or write buffers are included.
+ */
-+#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
-+#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
-+#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
++#define AR2315_MEM_CFG 0x0000
++#define AR2315_MEM_CTRL 0x000c
++#define AR2315_MEM_REF 0x0010
+
+#define SDRAM_DATA_WIDTH_M 0x00006000
+#define SDRAM_DATA_WIDTH_S 13
+#define SDRAM_BANKADDR_BITS_S 3
+
+/*
-+ * PCI Bus Interface Registers
-+ */
-+#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
-+#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
-+
-+#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
-+#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
-+#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
-+#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
-+#define AR2315_PCIMISC_RST_MODE 0x00000030
-+#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
-+#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
-+#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
-+#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
-+#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
-+#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
-+#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
-+#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
-+ * disable */
-+
-+#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
-+
-+#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
-+
-+#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
-+#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
-+#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
-+#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
-+#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
-+
-+#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
-+#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
-+#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
-+#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
-+#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
-+
-+#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
-+
-+#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
-+#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
-+
-+#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
-+#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
-+
-+#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
-+
-+#define AR2315_PCI_ISR (AR2315_PCI + 0x0500) /* write one to clr */
-+#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
-+#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
-+#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
-+#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
-+#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
-+#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
-+#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
-+#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
-+#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
-+#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
-+#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
-+#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
-+
-+#define AR2315_PCI_IMR (AR2315_PCI + 0x0504) /* mask _PCI_ISR bits */
-+
-+#define AR2315_PCI_IER (AR2315_PCI + 0x0508) /* global PCI int en */
-+#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
-+#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
-+
-+#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
-+#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
-+#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
-+#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
-+#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
-+#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
-+
-+/*
+ * Local Bus Interface Registers
+ */
-+#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
++#define AR2315_LB_CONFIG 0x0000
++
+#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
+#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
+#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
+#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
+#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
+
-+#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
++#define AR2315_LB_CLKSEL 0x0004
++
+#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
+
-+#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
++#define AR2315_LB_1MS 0x0008
++
+#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
+
-+#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
++#define AR2315_LB_MISCCFG 0x000c
+#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
+#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
+#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
+#define AR2315_LBM_TIMEOUT_SHFT 7
+#define AR2315_LBM_PORTMUX 0x07000000
+
-+#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
++#define AR2315_LB_RXTSOFF 0x0010
++
++#define AR2315_LB_TX_CHAIN_EN 0x0100
+
-+#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
+#define AR2315_LB_TXEN_0 0x01
+#define AR2315_LB_TXEN_1 0x02
+#define AR2315_LB_TXEN_2 0x04
+#define AR2315_LB_TXEN_3 0x08
+
-+#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
-+#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
++#define AR2315_LB_TX_CHAIN_DIS 0x0104
++#define AR2315_LB_TX_DESC_PTR 0x0200
++
++#define AR2315_LB_RX_CHAIN_EN 0x0400
+
-+#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
+#define AR2315_LB_RXEN 0x01
+
-+#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
-+#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
++#define AR2315_LB_RX_CHAIN_DIS 0x0404
++#define AR2315_LB_RX_DESC_PTR 0x0408
++
++#define AR2315_LB_INT_STATUS 0x0500
+
-+#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
+#define AR2315_INT_TX_DESC 0x0001
+#define AR2315_INT_TX_OK 0x0002
+#define AR2315_INT_TX_ERR 0x0004
+#define AR2315_INT_MBOX_RD 0x2000
+
+/* Bit definitions for INT MASK are the same as INT_STATUS */
-+#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
-+
-+#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
-+#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
-+
-+/*
-+ * IR Interface Registers
-+ */
-+#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
-+
-+#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
-+
-+#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
-+#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
-+#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
-+#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
-+#define AR2315_IRCTL_SAMPLECLK_SHFT 1
-+#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
-+#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
-+
-+#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
-+#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
-+#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
-+
-+#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
-+#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
-+#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
-+#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
-+#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
-+#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
-+#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
-+#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
-+#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
-+#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
-+
-+/*
-+ * We need some arbitrary non-zero value to be programmed to the BAR1 register
-+ * of PCI host controller to enable DMA. The same value should be used as the
-+ * offset to calculate the physical address of DMA buffer for PCI devices.
-+ */
-+#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
++#define AR2315_LB_INT_MASK 0x0504
+
-+/* ??? access BAR */
-+#define AR2315_PCI_HOST_MBAR0 0x10000000
-+/* RAM access BAR */
-+#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
-+/* ??? access BAR */
-+#define AR2315_PCI_HOST_MBAR2 0x30000000
++#define AR2315_LB_INT_EN 0x0508
++#define AR2315_LB_MBOX 0x0600
+
-+#endif /* __ASM_MACH_AR231X_AR2315_REGS_H */
++#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
--- /dev/null
-+++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
-@@ -0,0 +1,235 @@
++++ b/arch/mips/ath25/ar5312_regs.h
+@@ -0,0 +1,227 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
+ */
+
-+#ifndef __ASM_MACH_AR231X_AR5312_REGS_H
-+#define __ASM_MACH_AR231X_AR5312_REGS_H
++#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
++#define __ASM_MACH_ATH25_AR5312_REGS_H
+
+#include <asm/addrspace.h>
+
+
+/*
+ * Address Map
++ *
++ * The AR5312 supports 2 enet MACS, even though many reference boards only
++ * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
++ * PHY or PHY switch. The AR2312 supports 1 enet MAC.
+ */
+#define AR5312_WLAN0 0x18000000
+#define AR5312_WLAN1 0x18500000
+#define AR5312_ENET0 0x18100000
+#define AR5312_ENET1 0x18200000
-+#define AR5312_SDRAMCTL 0x18300000
-+#define AR5312_FLASHCTL 0x18400000
-+#define AR5312_APBBASE 0x1c000000
++#define AR5312_SDRAMCTL_BASE 0x18300000
++#define AR5312_SDRAMCTL_SIZE 0x00000010
++#define AR5312_FLASHCTL_BASE 0x18400000
++#define AR5312_FLASHCTL_SIZE 0x00000010
+#define AR5312_UART0 0x1c000000 /* UART MMR */
++#define AR5312_GPIO_BASE 0x1c002000
++#define AR5312_RST_BASE 0x1c003000
++#define AR5312_RST_SIZE 0x00000100
+#define AR5312_FLASH 0x1e000000
+
+/*
-+ * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
-+ * should be considered available. The AR5312 supports 2 enet MACS,
-+ * even though many reference boards only actually use 1 of them
-+ * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
-+ * The AR2312 supports 1 enet MAC.
-+ */
-+#define AR5312_NUM_ENET_MAC 2
-+
-+/*
+ * Need these defines to determine true number of ethernet MACs
+ */
+#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
+#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
+#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
+
-+/*
-+ * AR5312_NUM_WMAC defines the number of Wireless MACs that\
-+ * should be considered available.
-+ */
-+#define AR5312_NUM_WMAC 2
-+
+/* Reset/Timer Block Address Map */
-+#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
-+#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
-+#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
-+#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
-+#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
-+#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
-+#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
-+#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
-+#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
-+#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
-+#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
-+#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
-+#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
-+#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
-+#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
++#define AR5312_TIMER 0x0000 /* countdown timer */
++#define AR5312_RELOAD 0x0004 /* timer reload value */
++#define AR5312_WD_CTRL 0x0008 /* watchdog cntrl */
++#define AR5312_WD_TIMER 0x000c /* watchdog timer */
++#define AR5312_ISR 0x0010 /* Intr Status Reg */
++#define AR5312_IMR 0x0014 /* Intr Mask Reg */
++#define AR5312_RESET 0x0020
++#define AR5312_CLOCKCTL1 0x0064
++#define AR5312_SCRATCH 0x006c
++#define AR5312_PROCADDR 0x0070
++#define AR5312_PROC1 0x0074
++#define AR5312_DMAADDR 0x0078
++#define AR5312_DMA1 0x007c
++#define AR5312_ENABLE 0x0080 /* interface enb */
++#define AR5312_REV 0x0090 /* revision */
+
+/* AR5312_WD_CTRL register bit field definitions */
+#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
+#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
+#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
+
++/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
++#define AR5312_FLASHCTL0 0x0000
++#define AR5312_FLASHCTL1 0x0004
++#define AR5312_FLASHCTL2 0x0008
++
+/* AR5312_FLASHCTL register bit field definitions */
+#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
+#define FLASHCTL_IDCY_S 0
+#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
+#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
+
-+/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
-+#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
-+#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
-+#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
-+
+/* ARM SDRAM Controller -- just enough to determine memory size */
-+#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
++#define AR5312_MEM_CFG1 0x0004
++
+#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
+#define MEM_CFG1_AC0_S 8
+#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
+#define MEM_CFG1_AC1_S 12
+
-+#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
-+
-+#endif /* __ASM_MACH_AR231X_AR5312_REGS_H */
++#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
--- /dev/null
-+++ b/arch/mips/ar231x/ar5312.c
-@@ -0,0 +1,476 @@
++++ b/arch/mips/ath25/ar5312.c
+@@ -0,0 +1,483 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+#include <linux/irq.h>
+#include <linux/io.h>
+
-+#include <ar231x_platform.h>
-+#include <ar5312_regs.h>
-+#include <ar231x.h>
++#include <ath25_platform.h>
++
+#include "devices.h"
+#include "ar5312.h"
++#include "ar5312_regs.h"
++
++static void __iomem *ar5312_rst_base;
++
++static inline u32 ar5312_rst_reg_read(u32 reg)
++{
++ return __raw_readl(ar5312_rst_base + reg);
++}
++
++static inline void ar5312_rst_reg_write(u32 reg, u32 val)
++{
++ __raw_writel(val, ar5312_rst_base + reg);
++}
++
++static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
++{
++ u32 ret = ar5312_rst_reg_read(reg);
++
++ ret &= ~mask;
++ ret |= val;
++ ar5312_rst_reg_write(reg, ret);
++}
++
++static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
++{
++ u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
++ u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
++ u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
++ u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
++
++ pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
++ proc_addr, proc1, dma_addr, dma1);
++
++ machine_restart("AHB error"); /* Catastrophic failure */
++ return IRQ_HANDLED;
++}
++
++static struct irqaction ar5312_ahb_err_interrupt = {
++ .handler = ar5312_ahb_err_handler,
++ .name = "ar5312-ahb-error",
++};
+
+static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
+{
-+ unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
-+ ar231x_read_reg(AR5312_IMR);
++ unsigned int ar231x_misc_intrs = ar5312_rst_reg_read(AR5312_ISR) &
++ ar5312_rst_reg_read(AR5312_IMR);
+
+ if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
+ generic_handle_irq(AR5312_MISC_IRQ_TIMER);
-+ (void)ar231x_read_reg(AR5312_TIMER);
++ (void)ar5312_rst_reg_read(AR5312_TIMER);
+ } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
+ generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
+ else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
+ spurious_interrupt();
+}
+
-+static asmlinkage void
-+ar5312_irq_dispatch(void)
-+{
-+ int pending = read_c0_status() & read_c0_cause();
-+
-+ if (pending & CAUSEF_IP2)
-+ do_IRQ(AR5312_IRQ_WLAN0_INTRS);
-+ else if (pending & CAUSEF_IP3)
-+ do_IRQ(AR5312_IRQ_ENET0_INTRS);
-+ else if (pending & CAUSEF_IP4)
-+ do_IRQ(AR5312_IRQ_ENET1_INTRS);
-+ else if (pending & CAUSEF_IP5)
-+ do_IRQ(AR5312_IRQ_WLAN1_INTRS);
-+ else if (pending & CAUSEF_IP6)
-+ do_IRQ(AR5312_IRQ_MISC_INTRS);
-+ else if (pending & CAUSEF_IP7)
-+ do_IRQ(AR231X_IRQ_CPU_CLOCK);
-+ else
-+ spurious_interrupt();
-+}
-+
+/* Enable the specified AR5312_MISC_IRQ interrupt */
-+static void
-+ar5312_misc_irq_unmask(struct irq_data *d)
++static void ar5312_misc_irq_unmask(struct irq_data *d)
+{
+ unsigned int imr;
+
-+ imr = ar231x_read_reg(AR5312_IMR);
++ imr = ar5312_rst_reg_read(AR5312_IMR);
+ imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
-+ ar231x_write_reg(AR5312_IMR, imr);
++ ar5312_rst_reg_write(AR5312_IMR, imr);
+}
+
+/* Disable the specified AR5312_MISC_IRQ interrupt */
-+static void
-+ar5312_misc_irq_mask(struct irq_data *d)
++static void ar5312_misc_irq_mask(struct irq_data *d)
+{
+ unsigned int imr;
+
-+ imr = ar231x_read_reg(AR5312_IMR);
++ imr = ar5312_rst_reg_read(AR5312_IMR);
+ imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
-+ ar231x_write_reg(AR5312_IMR, imr);
-+ ar231x_read_reg(AR5312_IMR); /* flush write buffer */
++ ar5312_rst_reg_write(AR5312_IMR, imr);
++ ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
+}
+
+static struct irq_chip ar5312_misc_irq_chip = {
-+ .name = "AR5312-MISC",
++ .name = "ar5312-misc",
+ .irq_unmask = ar5312_misc_irq_unmask,
+ .irq_mask = ar5312_misc_irq_mask,
+};
+
-+static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
++static void ar5312_irq_dispatch(void)
+{
-+ u32 proc1 = ar231x_read_reg(AR5312_PROC1);
-+ u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
-+ u32 dma1 = ar231x_read_reg(AR5312_DMA1);
-+ u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
-+
-+ pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
-+ proc_addr, proc1, dma_addr, dma1);
++ int pending = read_c0_status() & read_c0_cause();
+
-+ machine_restart("AHB error"); /* Catastrophic failure */
-+ return IRQ_HANDLED;
++ if (pending & CAUSEF_IP2)
++ do_IRQ(AR5312_IRQ_WLAN0_INTRS);
++ else if (pending & CAUSEF_IP3)
++ do_IRQ(AR5312_IRQ_ENET0_INTRS);
++ else if (pending & CAUSEF_IP4)
++ do_IRQ(AR5312_IRQ_ENET1_INTRS);
++ else if (pending & CAUSEF_IP5)
++ do_IRQ(AR5312_IRQ_WLAN1_INTRS);
++ else if (pending & CAUSEF_IP6)
++ do_IRQ(AR5312_IRQ_MISC_INTRS);
++ else if (pending & CAUSEF_IP7)
++ do_IRQ(AR231X_IRQ_CPU_CLOCK);
++ else
++ spurious_interrupt();
+}
+
-+static struct irqaction ar5312_ahb_proc_interrupt = {
-+ .handler = ar5312_ahb_proc_handler,
-+ .name = "ar5312_ahb_proc_interrupt",
-+};
-+
-+void __init ar5312_irq_init(void)
++void __init ar5312_arch_init_irq(void)
+{
+ int i;
+
-+ if (!is_5312())
-+ return;
-+
-+ ar231x_irq_dispatch = ar5312_irq_dispatch;
++ ath25_irq_dispatch = ar5312_irq_dispatch;
+ for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
+ int irq = AR231X_MISC_IRQ_BASE + i;
+
+ irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
+ handle_level_irq);
+ }
-+ setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
++ setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_err_interrupt);
+ irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
+}
+
+{
+ u32 val;
+
-+ val = ar231x_read_reg(AR5312_RESET);
-+ ar231x_write_reg(AR5312_RESET, val | mask);
++ val = ar5312_rst_reg_read(AR5312_RESET);
++ ar5312_rst_reg_write(AR5312_RESET, val | mask);
+}
+
+static void ar5312_device_reset_clear(u32 mask)
+{
+ u32 val;
+
-+ val = ar231x_read_reg(AR5312_RESET);
-+ ar231x_write_reg(AR5312_RESET, val & ~mask);
++ val = ar5312_rst_reg_read(AR5312_RESET);
++ ar5312_rst_reg_write(AR5312_RESET, val & ~mask);
+}
+
+static struct physmap_flash_data ar5312_flash_data = {
+ .reset_clear = ar5312_device_reset_clear,
+ .reset_mac = AR5312_RESET_ENET0,
+ .reset_phy = AR5312_RESET_EPHY0,
-+ .config = &ar231x_board,
+};
+
+static struct ar231x_eth ar5312_eth1_data = {
+ .reset_clear = ar5312_device_reset_clear,
+ .reset_mac = AR5312_RESET_ENET1,
+ .reset_phy = AR5312_RESET_EPHY1,
-+ .config = &ar231x_board,
+};
+
+static struct platform_device ar5312_physmap_flash = {
+ */
+static char __init *ar5312_flash_limit(void)
+{
++ void __iomem *flashctl_base;
+ u32 ctl;
++
++ flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE,
++ AR5312_FLASHCTL_SIZE);
++
++ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
++ ctl &= FLASHCTL_MW;
++
++ /* fixup flash width */
++ switch (ctl) {
++ case FLASHCTL_MW16:
++ ar5312_flash_data.width = 2;
++ break;
++ case FLASHCTL_MW8:
++ default:
++ ar5312_flash_data.width = 1;
++ break;
++ }
++
+ /*
+ * Configure flash bank 0.
+ * Assume 8M window size. Flash will be aliased if it's smaller
+ (0x01 << FLASHCTL_IDCY_S) |
+ (0x07 << FLASHCTL_WST1_S) |
+ (0x07 << FLASHCTL_WST2_S) |
-+ (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
++ ctl;
+
-+ ar231x_write_reg(AR5312_FLASHCTL0, ctl);
++ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
+
+ /* Disable other flash banks */
-+ ar231x_write_reg(AR5312_FLASHCTL1,
-+ ar231x_read_reg(AR5312_FLASHCTL1) &
-+ ~(FLASHCTL_E | FLASHCTL_AC));
++ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
++ ctl &= ~(FLASHCTL_E | FLASHCTL_AC);
++ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
++ ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
++ ctl &= ~(FLASHCTL_E | FLASHCTL_AC);
++ __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
+
-+ ar231x_write_reg(AR5312_FLASHCTL2,
-+ ar231x_read_reg(AR5312_FLASHCTL2) &
-+ ~(FLASHCTL_E | FLASHCTL_AC));
++ iounmap(flashctl_base);
+
+ return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
+}
+
-+int __init ar5312_init_devices(void)
++void __init ar5312_init_devices(void)
+{
-+ struct ar231x_boarddata *config;
-+ u32 fctl = 0;
++ struct ath25_boarddata *config;
+ u8 *c;
+
-+ if (!is_5312())
-+ return 0;
-+
+ /* Locate board/radio config data */
-+ ar231x_find_config(ar5312_flash_limit());
-+ config = ar231x_board.config;
++ ath25_find_config(ar5312_flash_limit());
++ config = ath25_board.config;
+
+ /* AR2313 has CPU minor rev. 10 */
+ if ((current_cpu_data.processor_id & 0xff) == 0x0a)
-+ ar231x_devtype = DEV_TYPE_AR2313;
++ ath25_soc = ATH25_SOC_AR2313;
+
+ /* AR2312 shares the same Silicon ID as AR5312 */
+ else if (config->flags & BD_ISCASPER)
-+ ar231x_devtype = DEV_TYPE_AR2312;
++ ath25_soc = ATH25_SOC_AR2312;
+
+ /* Everything else is probably AR5312 or compatible */
+ else
-+ ar231x_devtype = DEV_TYPE_AR5312;
-+
-+ /* fixup flash width */
-+ fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
-+ switch (fctl) {
-+ case FLASHCTL_MW16:
-+ ar5312_flash_data.width = 2;
-+ break;
-+ case FLASHCTL_MW8:
-+ default:
-+ ar5312_flash_data.width = 1;
-+ break;
-+ }
++ ath25_soc = ATH25_SOC_AR5312;
+
+ platform_device_register(&ar5312_physmap_flash);
+
+ c--;
+ }
+
-+ switch (ar231x_devtype) {
-+ case DEV_TYPE_AR5312:
++ switch (ath25_soc) {
++ case ATH25_SOC_AR5312:
+ ar5312_eth0_data.macaddr = config->enet0_mac;
-+ ar231x_add_ethernet(0, AR5312_ENET0, "eth0_mii",
-+ AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
-+ &ar5312_eth0_data);
++ ath25_add_ethernet(0, AR5312_ENET0, "eth0_mii",
++ AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
++ &ar5312_eth0_data);
+
+ ar5312_eth1_data.macaddr = config->enet1_mac;
-+ ar231x_add_ethernet(1, AR5312_ENET1, "eth1_mii",
-+ AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
-+ &ar5312_eth1_data);
++ ath25_add_ethernet(1, AR5312_ENET1, "eth1_mii",
++ AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
++ &ar5312_eth1_data);
+
-+ if (!ar231x_board.radio)
-+ return 0;
++ if (!ath25_board.radio)
++ return;
+
+ if (!(config->flags & BD_WLAN0))
+ break;
+
-+ ar231x_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
++ ath25_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
+ break;
+ /*
+ * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
+ * of ENET1. Atheros calls it 'twisted' for a reason :)
+ */
-+ case DEV_TYPE_AR2312:
-+ case DEV_TYPE_AR2313:
++ case ATH25_SOC_AR2312:
++ case ATH25_SOC_AR2313:
+ ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
+ ar5312_eth1_data.macaddr = config->enet0_mac;
-+ ar231x_add_ethernet(1, AR5312_ENET1, "eth0_mii",
-+ AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
-+ &ar5312_eth1_data);
++ ath25_add_ethernet(1, AR5312_ENET1, "eth0_mii",
++ AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
++ &ar5312_eth1_data);
+
-+ if (!ar231x_board.radio)
-+ return 0;
++ if (!ath25_board.radio)
++ return;
+ break;
+ default:
+ break;
+ }
+
+ if (config->flags & BD_WLAN1)
-+ ar231x_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
-+
-+ return 0;
++ ath25_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
+}
+
+static void ar5312_restart(char *command)
+ /* reset the system */
+ local_irq_disable();
+ while (1)
-+ ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
++ ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
+}
+
+/*
+ * This table is indexed by bits 5..4 of the CLOCKCTL1 register
+ * to determine the predevisor value.
+ */
-+static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
++static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
+
-+static int __init
-+ar5312_cpu_frequency(void)
++static unsigned __init ar5312_cpu_frequency(void)
+{
+ unsigned int scratch;
+ unsigned int predivide_mask, predivide_shift;
+ u16 devid;
+
+ /* Trust the bootrom's idea of cpu frequency. */
-+ scratch = ar231x_read_reg(AR5312_SCRATCH);
++ scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
+ if (scratch)
+ return scratch;
+
-+ devid = ar231x_read_reg(AR5312_REV);
++ devid = ar5312_rst_reg_read(AR5312_REV);
+ devid &= AR5312_REV_MAJ;
+ devid >>= AR5312_REV_MAJ_S;
+ if (devid == AR5312_REV_MAJ_AR2313) {
+ * We compute the CPU frequency, based on PLL settings.
+ */
+
-+ clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
++ clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
+ predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
+ predivisor = clockctl1_predivide_table[predivide_select];
+ multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
+ return (40000000 / predivisor) * multiplier;
+}
+
-+static inline int
-+ar5312_sys_frequency(void)
++static inline unsigned ar5312_sys_frequency(void)
+{
+ return ar5312_cpu_frequency() / 4;
+}
+
-+void __init
-+ar5312_time_init(void)
++void __init ar5312_plat_time_init(void)
+{
-+ if (!is_5312())
-+ return;
-+
+ mips_hpt_frequency = ar5312_cpu_frequency() / 2;
+}
+
-+void __init
-+ar5312_prom_init(void)
++void __init ar5312_plat_mem_setup(void)
+{
++ void __iomem *sdram_base;
+ u32 memsize, memcfg, bank0AC, bank1AC;
+ u32 devid;
+
-+ if (!is_5312())
-+ return;
-+
+ /* Detect memory size */
-+ memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
++ sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
++ AR5312_SDRAMCTL_SIZE);
++ memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
+ bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
+ bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
+ memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
+ (bank1AC ? (1 << (bank1AC+1)) : 0);
+ memsize <<= 20;
+ add_memory_region(0, memsize, BOOT_MEM_RAM);
++ iounmap(sdram_base);
+
-+ devid = ar231x_read_reg(AR5312_REV);
++ ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);
++
++ devid = ar5312_rst_reg_read(AR5312_REV);
+ devid >>= AR5312_REV_WMAC_MIN_S;
+ devid &= AR5312_REV_CHIP;
-+ ar231x_board.devid = (u16)devid;
-+}
-+
-+void __init
-+ar5312_plat_setup(void)
-+{
-+ if (!is_5312())
-+ return;
++ ath25_board.devid = (u16)devid;
+
+ /* Clear any lingering AHB errors */
-+ ar231x_read_reg(AR5312_PROCADDR);
-+ ar231x_read_reg(AR5312_DMAADDR);
-+ ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
++ ar5312_rst_reg_read(AR5312_PROCADDR);
++ ar5312_rst_reg_read(AR5312_DMAADDR);
++ ar5312_rst_reg_write(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
+
+ _machine_restart = ar5312_restart;
-+ ar231x_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
-+ ar5312_sys_frequency());
+}
+
++void __init ar5312_arch_init(void)
++{
++ ath25_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
++ ar5312_sys_frequency());
++}
--- /dev/null
-+++ b/arch/mips/ar231x/ar2315.c
-@@ -0,0 +1,431 @@
++++ b/arch/mips/ath25/ar2315.c
+@@ -0,0 +1,428 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+#include <linux/irq.h>
+#include <linux/io.h>
+
-+#include <ar231x_platform.h>
-+#include <ar2315_regs.h>
-+#include <ar231x.h>
++#include <ath25_platform.h>
++
+#include "devices.h"
+#include "ar2315.h"
++#include "ar2315_regs.h"
++
++static void __iomem *ar2315_rst_base;
++
++static inline u32 ar2315_rst_reg_read(u32 reg)
++{
++ return __raw_readl(ar2315_rst_base + reg);
++}
++
++static inline void ar2315_rst_reg_write(u32 reg, u32 val)
++{
++ __raw_writel(val, ar2315_rst_base + reg);
++}
++
++static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
++{
++ u32 ret = ar2315_rst_reg_read(reg);
++
++ ret &= ~mask;
++ ret |= val;
++ ar2315_rst_reg_write(reg, ret);
++}
++
++static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
++{
++ ar2315_rst_reg_write(AR2315_AHB_ERR0, AHB_ERROR_DET);
++ ar2315_rst_reg_read(AR2315_AHB_ERR1);
++
++ pr_emerg("AHB fatal error\n");
++ machine_restart("AHB error"); /* Catastrophic failure */
++
++ return IRQ_HANDLED;
++}
++
++static struct irqaction ar2315_ahb_err_interrupt = {
++ .handler = ar2315_ahb_err_handler,
++ .name = "ar2315-ahb-error",
++};
+
+static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
+{
-+ unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
-+ ar231x_read_reg(AR2315_IMR);
++ unsigned int misc_intr = ar2315_rst_reg_read(AR2315_ISR) &
++ ar2315_rst_reg_read(AR2315_IMR);
+
+ if (misc_intr & AR2315_ISR_SPI)
+ generic_handle_irq(AR2315_MISC_IRQ_SPI);
+ else if (misc_intr & AR2315_ISR_AHB)
+ generic_handle_irq(AR2315_MISC_IRQ_AHB);
+ else if (misc_intr & AR2315_ISR_GPIO) {
-+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
++ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
+ generic_handle_irq(AR2315_MISC_IRQ_GPIO);
+ } else if (misc_intr & AR2315_ISR_UART0)
+ generic_handle_irq(AR2315_MISC_IRQ_UART0);
+ else if (misc_intr & AR2315_ISR_WD) {
-+ ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
++ ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
+ generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
+ } else
+ spurious_interrupt();
+}
+
++static void ar2315_misc_irq_unmask(struct irq_data *d)
++{
++ unsigned int imr;
++
++ imr = ar2315_rst_reg_read(AR2315_IMR);
++ imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
++ ar2315_rst_reg_write(AR2315_IMR, imr);
++}
++
++static void ar2315_misc_irq_mask(struct irq_data *d)
++{
++ unsigned int imr;
++
++ imr = ar2315_rst_reg_read(AR2315_IMR);
++ imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
++ ar2315_rst_reg_write(AR2315_IMR, imr);
++}
++
++static struct irq_chip ar2315_misc_irq_chip = {
++ .name = "ar2315-misc",
++ .irq_unmask = ar2315_misc_irq_unmask,
++ .irq_mask = ar2315_misc_irq_mask,
++};
++
+/*
+ * Called when an interrupt is received, this function
+ * determines exactly which interrupt it was, and it
+ * Implicitly, we also define interrupt priority by
+ * choosing which to dispatch first.
+ */
-+static asmlinkage void
-+ar2315_irq_dispatch(void)
++static void ar2315_irq_dispatch(void)
+{
+ int pending = read_c0_status() & read_c0_cause();
+
+ spurious_interrupt();
+}
+
-+static void
-+ar2315_misc_irq_unmask(struct irq_data *d)
-+{
-+ unsigned int imr;
-+
-+ imr = ar231x_read_reg(AR2315_IMR);
-+ imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
-+ ar231x_write_reg(AR2315_IMR, imr);
-+}
-+
-+static void
-+ar2315_misc_irq_mask(struct irq_data *d)
-+{
-+ unsigned int imr;
-+
-+ imr = ar231x_read_reg(AR2315_IMR);
-+ imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
-+ ar231x_write_reg(AR2315_IMR, imr);
-+}
-+
-+static struct irq_chip ar2315_misc_irq_chip = {
-+ .name = "AR2315-MISC",
-+ .irq_unmask = ar2315_misc_irq_unmask,
-+ .irq_mask = ar2315_misc_irq_mask,
-+};
-+
-+static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
-+{
-+ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
-+ ar231x_read_reg(AR2315_AHB_ERR1);
-+
-+ pr_emerg("AHB fatal error\n");
-+ machine_restart("AHB error"); /* Catastrophic failure */
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static struct irqaction ar2315_ahb_proc_interrupt = {
-+ .handler = ar2315_ahb_proc_handler,
-+ .name = "ar2315_ahb_proc_interrupt",
-+};
-+
-+void
-+ar2315_irq_init(void)
++void __init ar2315_arch_init_irq(void)
+{
+ int i;
+
-+ if (!is_2315())
-+ return;
-+
-+ ar231x_irq_dispatch = ar2315_irq_dispatch;
++ ath25_irq_dispatch = ar2315_irq_dispatch;
+ for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
+ int irq = AR231X_MISC_IRQ_BASE + i;
+
+ irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
+ handle_level_irq);
+ }
-+ setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
++ setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_err_interrupt);
+ irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
+}
+
+{
+ u32 val;
+
-+ val = ar231x_read_reg(AR2315_RESET);
-+ ar231x_write_reg(AR2315_RESET, val | mask);
++ val = ar2315_rst_reg_read(AR2315_RESET);
++ ar2315_rst_reg_write(AR2315_RESET, val | mask);
+}
+
+static void ar2315_device_reset_clear(u32 mask)
+{
+ u32 val;
+
-+ val = ar231x_read_reg(AR2315_RESET);
-+ ar231x_write_reg(AR2315_RESET, val & ~mask);
++ val = ar2315_rst_reg_read(AR2315_RESET);
++ ar2315_rst_reg_write(AR2315_RESET, val & ~mask);
+}
+
+static struct ar231x_eth ar2315_eth_data = {
+ .reset_clear = ar2315_device_reset_clear,
+ .reset_mac = AR2315_RESET_ENET0,
+ .reset_phy = AR2315_RESET_EPHY0,
-+ .config = &ar231x_board,
+};
+
+static struct resource ar2315_spiflash_res[] = {
+static struct resource ar2315_wdt_res[] = {
+ {
+ .flags = IORESOURCE_MEM,
-+ .start = AR2315_WD,
-+ .end = AR2315_WD + 8 - 1,
++ .start = AR2315_RST_BASE + AR2315_WD,
++ .end = AR2315_RST_BASE + AR2315_WD + 8 - 1,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
-+static void __init
-+ar2315_init_gpio_leds(void)
++static void __init ar2315_init_gpio_leds(void)
+{
+ static char led_names[6][6];
+ int i, led = 0;
+ ar2315_led_data.num_leds = 0;
+ for (i = 1; i < 8; i++) {
+ if ((i == AR2315_RESET_GPIO) ||
-+ (i == ar231x_board.config->reset_config_gpio))
++ (i == ath25_board.config->reset_config_gpio))
+ continue;
+
-+ if (i == ar231x_board.config->sys_led_gpio)
++ if (i == ath25_board.config->sys_led_gpio)
+ strcpy(led_names[led], "wlan");
+ else
+ sprintf(led_names[led], "gpio%d", i);
+}
+#endif
+
-+int __init
-+ar2315_init_devices(void)
++void __init ar2315_init_devices(void)
+{
-+ if (!is_2315())
-+ return 0;
-+
+ /* Find board configuration */
-+ ar231x_find_config(ar2315_flash_limit());
-+ ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
++ ath25_find_config(ar2315_flash_limit());
++ ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
+
+ ar2315_init_gpio_leds();
+ platform_device_register(&ar2315_wdt);
+ platform_device_register(&ar2315_spiflash);
-+ ar231x_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
-+ AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
-+ ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
-+
-+ return 0;
++ ath25_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
++ AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
++ ath25_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
+}
+
-+static void
-+ar2315_restart(char *command)
++static void ar2315_restart(char *command)
+{
+ void (*mips_reset_vec)(void) = (void *)0xbfc00000;
+
+ local_irq_disable();
+
+ /* try reset the system via reset control */
-+ ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
++ ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
+
+ /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
+ * a workaround. Give it some time to attempt a gpio based hardware
+static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
+static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
+
-+static unsigned int __init
-+ar2315_sys_clk(unsigned int clock_ctl)
++static unsigned __init ar2315_sys_clk(u32 clock_ctl)
+{
+ unsigned int pllc_ctrl, cpu_div;
+ unsigned int pllc_out, refdiv, fdiv, divby2;
+ unsigned int clk_div;
+
-+ pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
++ pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
+ refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
+ refdiv = clockctl1_predivide_table[refdiv];
+ fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
+ return pllc_out / (clk_div * cpu_div);
+}
+
-+static inline unsigned int
-+ar2315_cpu_frequency(void)
++static inline unsigned ar2315_cpu_frequency(void)
+{
-+ return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
++ return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
+}
+
-+static inline unsigned int
-+ar2315_apb_frequency(void)
++static inline unsigned ar2315_apb_frequency(void)
+{
-+ return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
++ return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
+}
+
-+void __init
-+ar2315_time_init(void)
++void __init ar2315_plat_time_init(void)
+{
-+ if (!is_2315())
-+ return;
-+
+ mips_hpt_frequency = ar2315_cpu_frequency() / 2;
+}
+
-+void __init
-+ar2315_prom_init(void)
++void __init ar2315_plat_mem_setup(void)
+{
-+ u32 memsize, memcfg, devid;
-+
-+ if (!is_2315())
-+ return;
++ void __iomem *sdram_base;
++ u32 memsize, memcfg;
++ u32 devid;
++ u32 config;
+
-+ memcfg = ar231x_read_reg(AR2315_MEM_CFG);
++ sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE,
++ AR2315_SDRAMCTL_SIZE);
++ memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
+ memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
+ memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
+ memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
+ memsize <<= 3;
+ add_memory_region(0, memsize, BOOT_MEM_RAM);
++ iounmap(sdram_base);
++
++ ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE);
+
+ /* Detect the hardware based on the device ID */
-+ devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
++ devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
+ switch (devid) {
+ case 0x91: /* Need to check */
-+ ar231x_devtype = DEV_TYPE_AR2318;
++ ath25_soc = ATH25_SOC_AR2318;
+ break;
+ case 0x90:
-+ ar231x_devtype = DEV_TYPE_AR2317;
++ ath25_soc = ATH25_SOC_AR2317;
+ break;
+ case 0x87:
-+ ar231x_devtype = DEV_TYPE_AR2316;
++ ath25_soc = ATH25_SOC_AR2316;
+ break;
+ case 0x86:
+ default:
-+ ar231x_devtype = DEV_TYPE_AR2315;
++ ath25_soc = ATH25_SOC_AR2315;
+ break;
+ }
-+ ar231x_board.devid = devid;
-+}
-+
-+void __init
-+ar2315_plat_setup(void)
-+{
-+ u32 config;
-+
-+ if (!is_2315())
-+ return;
++ ath25_board.devid = devid;
+
+ /* Clear any lingering AHB errors */
+ config = read_c0_config();
+ write_c0_config(config & ~0x3);
-+ ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
-+ ar231x_read_reg(AR2315_AHB_ERR1);
-+ ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
++ ar2315_rst_reg_write(AR2315_AHB_ERR0, AHB_ERROR_DET);
++ ar2315_rst_reg_read(AR2315_AHB_ERR1);
++ ar2315_rst_reg_write(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
+
+ _machine_restart = ar2315_restart;
-+ ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
-+ ar2315_apb_frequency());
++}
++
++void __init ar2315_arch_init(void)
++{
++ ath25_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
++ ar2315_apb_frequency());
+}
--- /dev/null
-+++ b/arch/mips/ar231x/ar2315.h
-@@ -0,0 +1,37 @@
++++ b/arch/mips/ath25/ar2315.h
+@@ -0,0 +1,36 @@
+#ifndef __AR2315_H
+#define __AR2315_H
+
+#ifdef CONFIG_SOC_AR2315
+
-+void ar2315_irq_init(void);
-+int ar2315_init_devices(void);
-+void ar2315_prom_init(void);
-+void ar2315_plat_setup(void);
-+void ar2315_time_init(void);
++void ar2315_arch_init_irq(void);
++void ar2315_init_devices(void);
++void ar2315_plat_time_init(void);
++void ar2315_plat_mem_setup(void);
++void ar2315_arch_init(void);
+
+#else
+
-+static inline void ar2315_irq_init(void)
++static inline void ar2315_arch_init_irq(void)
+{
+}
+
-+static inline int ar2315_init_devices(void)
++static inline void ar2315_init_devices(void)
+{
-+ return 0;
+}
+
-+static inline void ar2315_prom_init(void)
++static inline void ar2315_plat_time_init(void)
+{
+}
+
-+static inline void ar2315_plat_setup(void)
++static inline void ar2315_plat_mem_setup(void)
+{
+}
+
-+static inline void ar2315_time_init(void)
++static inline void ar2315_arch_init(void)
+{
+}
+
+
+#endif
--- /dev/null
-+++ b/arch/mips/ar231x/ar5312.h
-@@ -0,0 +1,37 @@
++++ b/arch/mips/ath25/ar5312.h
+@@ -0,0 +1,36 @@
+#ifndef __AR5312_H
+#define __AR5312_H
+
+#ifdef CONFIG_SOC_AR5312
+
-+void ar5312_irq_init(void);
-+int ar5312_init_devices(void);
-+void ar5312_prom_init(void);
-+void ar5312_plat_setup(void);
-+void ar5312_time_init(void);
++void ar5312_arch_init_irq(void);
++void ar5312_init_devices(void);
++void ar5312_plat_time_init(void);
++void ar5312_plat_mem_setup(void);
++void ar5312_arch_init(void);
+
+#else
+
-+static inline void ar5312_irq_init(void)
++static inline void ar5312_arch_init_irq(void)
+{
+}
+
-+static inline int ar5312_init_devices(void)
++static inline void ar5312_init_devices(void)
+{
-+ return 0;
+}
+
-+static inline void ar5312_prom_init(void)
++static inline void ar5312_plat_time_init(void)
+{
+}
+
-+static inline void ar5312_plat_setup(void)
++static inline void ar5312_plat_mem_setup(void)
+{
+}
+
-+static inline void ar5312_time_init(void)
++static inline void ar5312_arch_init(void)
+{
+}
+
+
+#endif
--- /dev/null
-+++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
-@@ -0,0 +1,38 @@
-+#ifndef __ASM_MACH_AR231X_H
-+#define __ASM_MACH_AR231X_H
-+
-+#include <linux/types.h>
-+#include <linux/io.h>
++++ b/arch/mips/ath25/devices.h
+@@ -0,0 +1,44 @@
++#ifndef __ATH25_DEVICES_H
++#define __ATH25_DEVICES_H
+
+#define AR231X_MISC_IRQ_BASE 0x20
+#define AR231X_GPIO_IRQ_BASE 0x30
+
-+/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
-+#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
-+
-+static inline u32
-+ar231x_read_reg(u32 reg)
-+{
-+ return __raw_readl((void __iomem *)KSEG1ADDR(reg));
-+}
-+
-+static inline void
-+ar231x_write_reg(u32 reg, u32 val)
-+{
-+ __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
-+}
++#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
+
-+static inline u32
-+ar231x_mask_reg(u32 reg, u32 mask, u32 val)
-+{
-+ u32 ret;
-+
-+ ret = ar231x_read_reg(reg);
-+ ret &= ~mask;
-+ ret |= val;
-+ ar231x_write_reg(reg, ret);
-+
-+ return ret;
-+}
-+
-+#endif /* __ASM_MACH_AR231X_H */
---- /dev/null
-+++ b/arch/mips/ar231x/devices.h
-@@ -0,0 +1,39 @@
-+#ifndef __AR231X_DEVICES_H
-+#define __AR231X_DEVICES_H
-+
-+enum {
++enum ath25_soc_type {
+ /* handled by ar5312.c */
-+ DEV_TYPE_AR2312,
-+ DEV_TYPE_AR2313,
-+ DEV_TYPE_AR5312,
++ ATH25_SOC_AR2312,
++ ATH25_SOC_AR2313,
++ ATH25_SOC_AR5312,
+
+ /* handled by ar2315.c */
-+ DEV_TYPE_AR2315,
-+ DEV_TYPE_AR2316,
-+ DEV_TYPE_AR2317,
-+ DEV_TYPE_AR2318,
++ ATH25_SOC_AR2315,
++ ATH25_SOC_AR2316,
++ ATH25_SOC_AR2317,
++ ATH25_SOC_AR2318,
+
-+ DEV_TYPE_UNKNOWN
++ ATH25_SOC_UNKNOWN
+};
+
-+extern int ar231x_devtype;
-+extern struct ar231x_board_config ar231x_board;
-+extern asmlinkage void (*ar231x_irq_dispatch)(void);
++extern enum ath25_soc_type ath25_soc;
++extern struct ar231x_board_config ath25_board;
++extern void (*ath25_irq_dispatch)(void);
+
-+int ar231x_find_config(u8 *flash_limit);
-+void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
-+int ar231x_add_wmac(int nr, u32 base, int irq);
-+int ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
-+ int irq, void *pdata);
++int ath25_find_config(u8 *flash_limit);
++int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
++ int irq, void *pdata);
++void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
++int ath25_add_wmac(int nr, u32 base, int irq);
+
-+static inline bool is_2315(void)
++static inline bool is_ar2315(void)
+{
+ return (current_cpu_data.cputype == CPU_4KEC);
+}
+
-+static inline bool is_5312(void)
++static inline bool is_ar5312(void)
+{
-+ return !is_2315();
++ return !is_ar2315();
+}
+
+#endif
--- /dev/null
-+++ b/arch/mips/ar231x/devices.c
-@@ -0,0 +1,181 @@
++++ b/arch/mips/ath25/devices.c
+@@ -0,0 +1,191 @@
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/platform_device.h>
+#include <asm/bootinfo.h>
+
-+#include <ar231x_platform.h>
-+#include <ar231x.h>
++#include <ath25_platform.h>
+#include "devices.h"
+#include "ar5312.h"
+#include "ar2315.h"
+
-+struct ar231x_board_config ar231x_board;
-+int ar231x_devtype = DEV_TYPE_UNKNOWN;
++struct ar231x_board_config ath25_board;
++enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
+
-+static struct resource ar231x_eth0_res[] = {
++static struct resource ath25_eth0_res[] = {
+ {
+ .name = "eth0_membase",
+ .flags = IORESOURCE_MEM,
+ }
+};
+
-+static struct resource ar231x_eth1_res[] = {
++static struct resource ath25_eth1_res[] = {
+ {
+ .name = "eth1_membase",
+ .flags = IORESOURCE_MEM,
+ }
+};
+
-+static struct platform_device ar231x_eth[] = {
++static struct platform_device ath25_eth[] = {
+ {
+ .id = 0,
+ .name = "ar231x-eth",
-+ .resource = ar231x_eth0_res,
-+ .num_resources = ARRAY_SIZE(ar231x_eth0_res)
++ .resource = ath25_eth0_res,
++ .num_resources = ARRAY_SIZE(ath25_eth0_res)
+ },
+ {
+ .id = 1,
+ .name = "ar231x-eth",
-+ .resource = ar231x_eth1_res,
-+ .num_resources = ARRAY_SIZE(ar231x_eth1_res)
++ .resource = ath25_eth1_res,
++ .num_resources = ARRAY_SIZE(ath25_eth1_res)
+ }
+};
+
-+static struct resource ar231x_wmac0_res[] = {
++static struct resource ath25_wmac0_res[] = {
+ {
+ .name = "wmac0_membase",
+ .flags = IORESOURCE_MEM,
+ }
+};
+
-+static struct resource ar231x_wmac1_res[] = {
++static struct resource ath25_wmac1_res[] = {
+ {
+ .name = "wmac1_membase",
+ .flags = IORESOURCE_MEM,
+ }
+};
+
-+static struct platform_device ar231x_wmac[] = {
++static struct platform_device ath25_wmac[] = {
+ {
+ .id = 0,
+ .name = "ar231x-wmac",
-+ .resource = ar231x_wmac0_res,
-+ .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
-+ .dev.platform_data = &ar231x_board,
++ .resource = ath25_wmac0_res,
++ .num_resources = ARRAY_SIZE(ath25_wmac0_res),
++ .dev.platform_data = &ath25_board,
+ },
+ {
+ .id = 1,
+ .name = "ar231x-wmac",
-+ .resource = ar231x_wmac1_res,
-+ .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
-+ .dev.platform_data = &ar231x_board,
++ .resource = ath25_wmac1_res,
++ .num_resources = ARRAY_SIZE(ath25_wmac1_res),
++ .dev.platform_data = &ath25_board,
+ },
+};
+
-+static const char * const devtype_strings[] = {
-+ [DEV_TYPE_AR5312] = "Atheros AR5312",
-+ [DEV_TYPE_AR2312] = "Atheros AR2312",
-+ [DEV_TYPE_AR2313] = "Atheros AR2313",
-+ [DEV_TYPE_AR2315] = "Atheros AR2315",
-+ [DEV_TYPE_AR2316] = "Atheros AR2316",
-+ [DEV_TYPE_AR2317] = "Atheros AR2317",
-+ [DEV_TYPE_AR2318] = "Atheros AR2318",
-+ [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
++static const char * const soc_type_strings[] = {
++ [ATH25_SOC_AR5312] = "Atheros AR5312",
++ [ATH25_SOC_AR2312] = "Atheros AR2312",
++ [ATH25_SOC_AR2313] = "Atheros AR2313",
++ [ATH25_SOC_AR2315] = "Atheros AR2315",
++ [ATH25_SOC_AR2316] = "Atheros AR2316",
++ [ATH25_SOC_AR2317] = "Atheros AR2317",
++ [ATH25_SOC_AR2318] = "Atheros AR2318",
++ [ATH25_SOC_UNKNOWN] = "Atheros (unknown)",
+};
+
+const char *get_system_type(void)
+{
-+ if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
-+ !devtype_strings[ar231x_devtype])
-+ return devtype_strings[DEV_TYPE_UNKNOWN];
-+ return devtype_strings[ar231x_devtype];
++ if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) ||
++ !soc_type_strings[ath25_soc])
++ return soc_type_strings[ATH25_SOC_UNKNOWN];
++ return soc_type_strings[ath25_soc];
+}
+
-+int __init
-+ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
-+ int irq, void *pdata)
++int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name,
++ u32 mii_base, int irq, void *pdata)
+{
+ struct resource *res;
+
-+ ar231x_eth[nr].dev.platform_data = pdata;
-+ res = &ar231x_eth[nr].resource[0];
++ ath25_eth[nr].dev.platform_data = pdata;
++ res = &ath25_eth[nr].resource[0];
+ res->start = base;
+ res->end = base + 0x2000 - 1;
+ res++;
+ res++;
+ res->start = irq;
+ res->end = irq;
-+ return platform_device_register(&ar231x_eth[nr]);
++ return platform_device_register(&ath25_eth[nr]);
+}
+
-+void __init
-+ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
++void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
+{
+ struct uart_port s;
+
+ early_serial_setup(&s);
+}
+
-+int __init
-+ar231x_add_wmac(int nr, u32 base, int irq)
++int __init ath25_add_wmac(int nr, u32 base, int irq)
+{
+ struct resource *res;
+
-+ ar231x_wmac[nr].dev.platform_data = &ar231x_board;
-+ res = &ar231x_wmac[nr].resource[0];
++ ath25_wmac[nr].dev.platform_data = &ath25_board;
++ res = &ath25_wmac[nr].resource[0];
+ res->start = base;
+ res->end = base + 0x10000 - 1;
+ res++;
+ res->start = irq;
+ res->end = irq;
-+ return platform_device_register(&ar231x_wmac[nr]);
++ return platform_device_register(&ath25_wmac[nr]);
+}
+
-+static int __init ar231x_register_devices(void)
++static int __init ath25_register_devices(void)
+{
-+ ar5312_init_devices();
-+ ar2315_init_devices();
++ if (is_ar5312())
++ ar5312_init_devices();
++ else
++ ar2315_init_devices();
++
++ return 0;
++}
++
++device_initcall(ath25_register_devices);
++
++static int __init ath25_arch_init(void)
++{
++ if (is_ar5312())
++ ar5312_arch_init();
++ else
++ ar2315_arch_init();
+
+ return 0;
+}
+
-+device_initcall(ar231x_register_devices);
++arch_initcall(ath25_arch_init);
projects / openwrt / staging / dedeckeh.git / blobdiff