enable start-stop-daemon by default, i want to use this to clean up a few init script...

[openwrt/staging/wigyori.git] / target / linux / atheros-2.6 / files / arch / mips / atheros / ar531x.h

diff --git a/target/linux/atheros-2.6/files/arch/mips/atheros/ar531x.h b/target/linux/atheros-2.6/files/arch/mips/atheros/ar531x.h
index 208b0101a2e3d05ff6fe02684a2b9093d61ad97f..5256a548ce6c49bfe8c5abaf43e73631321f4f64 100644 (file)
--- a/target/linux/atheros-2.6/files/arch/mips/atheros/ar531x.h
+++ b/target/linux/atheros-2.6/files/arch/mips/atheros/ar531x.h
@@ -1,14 +1,58 @@
 #ifndef __AR531X_H
 #define __AR531X_H
 
+#include <asm/cpu-info.h>
 #include <ar531x_platform.h>
-#include "ar5312.h"
-#include "ar5315.h"
+#include "ar5312/ar5312.h"
+#include "ar5315/ar5315.h"
+
+
+/*
+ * C access to CLZ instruction
+ * (count leading zeroes).
+ */
+static inline int clz(unsigned long val)
+{
+       int ret;
+
+       __asm__ volatile (
+               ".set\tnoreorder\n\t"
+               ".set\tnoat\n\t"
+               ".set\tmips32\n\t"
+               "clz\t%0,%1\n\t"
+               ".set\tmips0\n\t"
+               ".set\tat\n\t"
+               ".set\treorder"
+               : "=r" (ret)
+               : "r" (val)
+       );
+       
+       return ret;
+}
+
+/*                                                                             
+ * Atheros CPUs before the AR2315 are using MIPS 4Kc core, later designs are
+ * using MIPS 4KEc R2 core. This makes it easy to determine the board at runtime.
+ */
+#ifdef CONFIG_ATHEROS_AR5312
+#define DO_AR5312(...) \
+       if (current_cpu_data.cputype != CPU_4KEC) { \
+               __VA_ARGS__ \
+       }
+#else
+#define DO_AR5312(...)
+#endif
+#ifdef CONFIG_ATHEROS_AR5315
+#define DO_AR5315(...) \
+       if (current_cpu_data.cputype == CPU_4KEC) { \
+               __VA_ARGS__ \
+       }
+#else
+#define DO_AR5315(...)
+#endif
 
-#define MIPS_CPU_IRQ_BASE              0x00
-#define AR531X_HIGH_PRIO                0x10
 #define AR531X_MISC_IRQ_BASE           0x20
-#define AR531X_GPIO_IRQ_BASE            0x30
+#define AR531X_GPIO_IRQ_BASE           0x30
 
 /* Software's idea of interrupts handled by "CPU Interrupt Controller" */
 #define AR531X_IRQ_NONE                MIPS_CPU_IRQ_BASE+0
@@ -24,7 +68,8 @@
 #define AR531X_MISC_IRQ_UART0_DMA      AR531X_MISC_IRQ_BASE+6
 #define AR531X_MISC_IRQ_WATCHDOG       AR531X_MISC_IRQ_BASE+7
 #define AR531X_MISC_IRQ_LOCAL          AR531X_MISC_IRQ_BASE+8
-#define AR531X_MISC_IRQ_COUNT          9
+#define AR531X_MISC_IRQ_SPI            AR531X_MISC_IRQ_BASE+9
+#define AR531X_MISC_IRQ_COUNT          10
 
 /* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
 #define AR531X_GPIO_IRQ_NONE            AR531X_MISC_IRQ_BASE+0
@@ -89,18 +134,33 @@ struct ar531x_boarddata {
     u8  wlan1Mac[6];                 /* (ar5212) */
 };
 
+#define BOARD_CONFIG_BUFSZ             0x1000
 
-extern char *board_config;
-extern char *radio_config;
+extern char *board_config, *radio_config;
 extern void serial_setup(unsigned long mapbase, unsigned int uartclk);
 extern int ar531x_find_config(char *flash_limit);
 
+extern void ar5312_prom_init(void);
 extern void ar5312_misc_intr_init(int irq_base);
-extern void ar5312_irq_dispatch(void);
 extern void ar5312_plat_setup(void);
+extern asmlinkage void ar5312_irq_dispatch(void);
 
+extern void ar5315_prom_init(void);
 extern void ar5315_misc_intr_init(int irq_base);
-extern asmlinkage void ar5315_irq_dispatch(void);
 extern void ar5315_plat_setup(void);
+extern asmlinkage void ar5315_irq_dispatch(void);
+extern void ar5315_pci_irq(int irq);
+static inline u32 sysRegMask(u32 phys, u32 mask, u32 value)
+{
+       u32 reg;
+       
+       reg = sysRegRead(phys);
+       reg &= ~mask;
+       reg |= value & mask;
+       sysRegWrite(phys, reg);
+       reg = sysRegRead(phys); /* flush write to the hardware */
+
+       return reg;
+}
 
 #endif