clk_disable_unprepare(vc4_hdmi->pixel_clock);
ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
-@@ -852,9 +855,9 @@ static void vc4_hdmi_encoder_pre_crtc_co
+@@ -853,9 +856,9 @@ static void vc4_hdmi_encoder_pre_crtc_co
* pixel clock, but HSM ends up being the limiting factor.
*/
hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
return;
}
-@@ -866,10 +869,12 @@ static void vc4_hdmi_encoder_pre_crtc_co
+@@ -867,10 +870,12 @@ static void vc4_hdmi_encoder_pre_crtc_co
* FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
* at 300MHz.
*/
clk_disable_unprepare(vc4_hdmi->pixel_clock);
return;
}
-@@ -877,6 +882,9 @@ static void vc4_hdmi_encoder_pre_crtc_co
+@@ -878,6 +883,9 @@ static void vc4_hdmi_encoder_pre_crtc_co
ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
if (ret) {
DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);