}
static u32 vc5_hdmi_calc_hsm_clock(struct vc4_hdmi *vc4_hdmi, unsigned long pixel_rate)
-@@ -1399,6 +1399,7 @@ static int vc4_hdmi_cec_init(struct vc4_
+@@ -1400,6 +1400,7 @@ static int vc4_hdmi_cec_init(struct vc4_
struct cec_connector_info conn_info;
struct platform_device *pdev = vc4_hdmi->pdev;
u32 value;
int ret;
if (!vc4_hdmi->variant->cec_available)
-@@ -1423,8 +1424,9 @@ static int vc4_hdmi_cec_init(struct vc4_
+@@ -1424,8 +1425,9 @@ static int vc4_hdmi_cec_init(struct vc4_
* divider: the hsm_clock rate and this divider setting will
* give a 40 kHz CEC clock.
*/
HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
vc4_cec_irq_handler,
-@@ -1769,6 +1771,7 @@ static int vc4_hdmi_dev_remove(struct pl
+@@ -1770,6 +1772,7 @@ static int vc4_hdmi_dev_remove(struct pl
static const struct vc4_hdmi_variant bcm2835_variant = {
.max_pixel_clock = 162000000,
.audio_available = true,
.cec_available = true,
.registers = vc4_hdmi_fields,
-@@ -1793,6 +1796,7 @@ static const struct vc4_hdmi_variant bcm
+@@ -1794,6 +1797,7 @@ static const struct vc4_hdmi_variant bcm
.id = 0,
.audio_available = true,
.max_pixel_clock = 297000000,
.registers = vc5_hdmi_hdmi0_fields,
.num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
.phy_lane_mapping = {
-@@ -1820,6 +1824,7 @@ static const struct vc4_hdmi_variant bcm
+@@ -1821,6 +1825,7 @@ static const struct vc4_hdmi_variant bcm
.id = 1,
.audio_available = true,
.max_pixel_clock = 297000000,