kernel: update bcma and ssb to wireless-testing master-2014-12-05

[openwrt/staging/wigyori.git] / target / linux / bcm53xx / patches-3.14 / 130-ARM-BCM5301X-register-bcma-bus.patch

diff --git a/target/linux/bcm53xx/patches-3.14/130-ARM-BCM5301X-register-bcma-bus.patch b/target/linux/bcm53xx/patches-3.14/130-ARM-BCM5301X-register-bcma-bus.patch
index 9d01f3311a5d29014a89820e1b5dbaa159c5648c..4044b44ff2c6dcd22ee5ac89216e4889c9cf6c7a 100644 (file)
--- a/target/linux/bcm53xx/patches-3.14/130-ARM-BCM5301X-register-bcma-bus.patch
+++ b/target/linux/bcm53xx/patches-3.14/130-ARM-BCM5301X-register-bcma-bus.patch
@@ -1,74 +1,66 @@
-From 23bcd5e7cb2aaee48ba8b2351f032a230d948b6f Mon Sep 17 00:00:00 2001
+From 414f0ad9b3a8e8ee6eaf09c6d79d5f448ac28630 Mon Sep 17 00:00:00 2001
 From: Hauke Mehrtens <hauke@hauke-m.de>
 Date: Sat, 25 Jan 2014 17:03:07 +0100
-Subject: [PATCH 08/15] ARM: BCM5301X: register bcma bus
+Subject: [PATCH 07/17] ARM: BCM5301X: register bcma bus
 
 ---
  arch/arm/boot/dts/bcm4708.dtsi | 58 ++++++++++++++++++++++++++++++++++++++++++
  1 file changed, 58 insertions(+)
 
---- a/arch/arm/boot/dts/bcm4708.dtsi
-+++ b/arch/arm/boot/dts/bcm4708.dtsi
-@@ -31,4 +31,62 @@
+--- a/arch/arm/boot/dts/bcm5301x.dtsi
++++ b/arch/arm/boot/dts/bcm5301x.dtsi
+@@ -95,12 +95,23 @@
                };
        };
  
-+      nvram0: nvram@0 {
++      nvram0: nvram@1c000000 {
 +              compatible = "brcm,bcm47xx-nvram";
 +              reg = <0x1c000000 0x01000000>;
 +      };
 +
 +      sprom0: sprom@0 {
-+              compatible = "brcm,bcm53xx-sprom";
++              compatible = "brcm,bcm47xx-sprom";
 +              nvram = <&nvram0>;
 +      };
 +
-+      aix@18000000 {
-+              compatible = "brcm,bus-aix";
-+              reg = <0x18000000 0x1000>;
-+              ranges = <0x00000000 0x18000000 0x00100000>;
-+              #address-cells = <1>;
-+              #size-cells = <1>;
+       axi@18000000 {
+               compatible = "brcm,bus-axi";
+               reg = <0x18000000 0x1000>;
+               ranges = <0x00000000 0x18000000 0x00100000>;
+               #address-cells = <1>;
+               #size-cells = <1>;
 +              sprom = <&sprom0>;
+ 
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0x000fffff 0xffff>;
+@@ -108,6 +119,30 @@
+                       /* ChipCommon */
+                       <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ 
++                      /* PCIe Controller 0 */
++                      <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 +
-+              usb2@0 {
-+                      reg = <0x18021000 0x1000>;
-+                      interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-+              };
-+
-+              usb3@0 {
-+                      reg = <0x18023000 0x1000>;
-+                      interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-+              };
-+
-+              gmac@0 {
-+                      reg = <0x18024000 0x1000>;
-+                      interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
-+              };
-+
-+              gmac@1 {
-+                      reg = <0x18025000 0x1000>;
-+                      interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
-+              };
-+
-+              gmac@2 {
-+                      reg = <0x18026000 0x1000>;
-+                      interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
-+              };
-+
-+              gmac@3 {
-+                      reg = <0x18027000 0x1000>;
-+                      interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
-+              };
++                      /* PCIe Controller 1 */
++                      <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
 +
-+              pcie@0 {
-+                      reg = <0x18012000 0x1000>;
-+                      interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
-+              };
++                      /* PCIe Controller 2 */
++                      <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
++                      <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
 +
-+              pcie@1 {
-+                      reg = <0x18013000 0x1000>;
-+                      interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-+              };
-+      };
- };
+                       /* USB 2.0 Controller */
+                       <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+