--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
-@@ -52,6 +52,18 @@ static void bcm_hwclock_set(u32 mask, in
- bcm_perf_writel(reg, PERF_CKCTL_REG);
+@@ -64,6 +64,18 @@ static void bcm_gpiorobosw_set(u32 mask,
+ bcm_gpio_writel(reg, GPIO_ROBOSW_SW_CTRL_REG);
}
+static void bcm_ub_hwclock_set(u32 mask, int enable)
/*
* Ethernet MAC "misc" clock: dma clocks and main clock on 6348
*/
-@@ -362,12 +374,17 @@ static struct clk clk_ipsec = {
+@@ -376,12 +388,17 @@ static struct clk clk_ipsec = {
static void pcie_set(struct clk *clk, int enable)
{
#define BCM_PCIE_MEM_END_PA_6328 (BCM_PCIE_MEM_BASE_PA_6328 + \
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
-@@ -1530,6 +1530,17 @@
+@@ -1535,6 +1535,17 @@
* _REG relative to RSET_PCIE
*************************************************************************/
#define PCIE_CONFIG2_REG 0x408
#define CONFIG2_BAR1_SIZE_EN 1
#define CONFIG2_BAR1_SIZE_MASK 0xf
-@@ -1575,7 +1586,54 @@
+@@ -1580,7 +1591,54 @@
#define PCIE_RC_INT_C (1 << 2)
#define PCIE_RC_INT_D (1 << 3)