u32 ctl_reg;
u32 div_reg;
-@@ -1021,10 +1024,60 @@ bcm2835_clk_is_pllc(struct clk_hw *hw)
+@@ -1023,10 +1026,60 @@ bcm2835_clk_is_pllc(struct clk_hw *hw)
return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0;
}
struct clk_hw *parent, *best_parent = NULL;
bool current_parent_is_pllc;
unsigned long rate, best_rate = 0;
-@@ -1052,9 +1105,8 @@ static int bcm2835_clock_determine_rate(
+@@ -1054,9 +1107,8 @@ static int bcm2835_clock_determine_rate(
if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc)
continue;
if (rate > best_rate && rate <= req->rate) {
best_parent = parent;
best_prate = prate;
-@@ -1275,6 +1327,13 @@ static struct clk_hw *bcm2835_register_c
+@@ -1277,6 +1329,13 @@ static struct clk_hw *bcm2835_register_c
if ((cprman_read(cprman, data->ctl_reg) & CM_ENABLE) == 0)
init.flags &= ~CLK_IS_CRITICAL;