/* Must be last */
struct clk_hw_onecell_data onecell;
-@@ -907,6 +928,9 @@ static long bcm2835_clock_rate_from_divi
+@@ -911,6 +932,9 @@ static long bcm2835_clock_rate_from_divi
const struct bcm2835_clock_data *data = clock->data;
u64 temp;
/*
* The divisor is a 12.12 fixed point field, but only some of
* the bits are populated in any given clock.
-@@ -930,7 +954,12 @@ static unsigned long bcm2835_clock_get_r
+@@ -934,7 +958,12 @@ static unsigned long bcm2835_clock_get_r
struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
struct bcm2835_cprman *cprman = clock->cprman;
const struct bcm2835_clock_data *data = clock->data;
return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
}
-@@ -1209,7 +1238,7 @@ static struct clk_hw *bcm2835_register_p
+@@ -1213,7 +1242,7 @@ static struct clk_hw *bcm2835_register_p
memset(&init, 0, sizeof(init));
/* All of the PLLs derive from the external oscillator. */
init.num_parents = 1;
init.name = data->name;
init.ops = &bcm2835_pll_clk_ops;
-@@ -1295,18 +1324,22 @@ static struct clk_hw *bcm2835_register_c
+@@ -1299,18 +1328,22 @@ static struct clk_hw *bcm2835_register_c
struct bcm2835_clock *clock;
struct clk_init_data init;
const char *parents[1 << CM_SRC_BITS];
}
memset(&init, 0, sizeof(init));
-@@ -1442,6 +1475,47 @@ static const char *const bcm2835_clock_v
+@@ -1446,6 +1479,47 @@ static const char *const bcm2835_clock_v
__VA_ARGS__)
/*
* the real definition of all the pll, pll_dividers and clocks
* these make use of the above REGISTER_* macros
*/
-@@ -1904,6 +1978,18 @@ static const struct bcm2835_clk_desc clk
+@@ -1908,6 +1982,18 @@ static const struct bcm2835_clk_desc clk
.div_reg = CM_DSI1EDIV,
.int_bits = 4,
.frac_bits = 8),
/* the gates */
-@@ -1962,8 +2048,19 @@ static int bcm2835_clk_probe(struct plat
+@@ -1966,8 +2052,19 @@ static int bcm2835_clk_probe(struct plat
if (IS_ERR(cprman->regs))
return PTR_ERR(cprman->regs);