#define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4
#define AR8216_GLOBAL_CPUPORT_EN BIT(8)
+#define AR8216_REG_MDIO_CTRL 0x98
+#define AR8216_MDIO_CTRL_DATA_M BITS(0, 16)
+#define AR8216_MDIO_CTRL_REG_ADDR_S 16
+#define AR8216_MDIO_CTRL_PHY_ADDR_S 21
+#define AR8216_MDIO_CTRL_CMD_WRITE 0
+#define AR8216_MDIO_CTRL_CMD_READ BIT(27)
+#define AR8216_MDIO_CTRL_MASTER_EN BIT(30)
+#define AR8216_MDIO_CTRL_BUSY BIT(31)
+
#define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1))
#define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000)
#define AR8216_PORT_STATUS_SPEED BITS(0,2)