+config SSB_SFLASH
+ bool "SSB serial flash support"
-+ depends on SSB_DRIVER_MIPS && BROKEN
++ depends on SSB_DRIVER_MIPS
+ default y
+
# Assumption: We are on embedded, if we compile the MIPS core.
}
if (updown_tab) {
-@@ -516,8 +524,8 @@ void ssb_pmu_init(struct ssb_chipcommon
+@@ -516,8 +524,8 @@ void ssb_pmu_init(struct ssb_chipcommon
pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
+EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
--- /dev/null
+++ b/drivers/ssb/driver_chipcommon_sflash.c
-@@ -0,0 +1,166 @@
+@@ -0,0 +1,164 @@
+/*
+ * Sonics Silicon Backplane
+ * ChipCommon serial flash interface
+ sflash->size = sflash->blocksize * sflash->numblocks;
+ sflash->present = true;
+
-+ pr_info("Found %s serial flash (blocksize: 0x%X, blocks: %d)\n",
-+ e->name, e->blocksize, e->numblocks);
++ pr_info("Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
++ e->name, sflash->size / 1024, e->blocksize, e->numblocks);
+
+ /* Prepare platform device, but don't register it yet. It's too early,
+ * malloc (required by device_private_init) is not available yet. */
+ sflash->size;
+ ssb_sflash_dev.dev.platform_data = sflash;
+
-+ pr_err("Serial flash support is not implemented yet!\n");
-+
-+ return -ENOTSUPP;
++ return 0;
+}
--- a/drivers/ssb/driver_extif.c
+++ b/drivers/ssb/driver_extif.c
}
static void dump_irq(struct ssb_bus *bus)
-@@ -178,9 +199,9 @@ static void ssb_mips_serial_init(struct
+@@ -178,9 +199,9 @@ static void ssb_mips_serial_init(struct
{
struct ssb_bus *bus = mcore->dev->bus;
mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
else
mcore->nr_serial_ports = 0;
-@@ -189,17 +210,42 @@ static void ssb_mips_serial_init(struct
+@@ -189,17 +210,42 @@ static void ssb_mips_serial_init(struct
static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
{
struct ssb_bus *bus = mcore->dev->bus;
sprom_extract_r458(out, in);
/* TODO - get remaining rev 8 stuff needed */
-@@ -641,7 +753,7 @@ static int sprom_extract(struct ssb_bus
+@@ -641,7 +753,7 @@ static int sprom_extract(struct ssb_bus
memset(out, 0, sizeof(*out));
out->revision = in[size - 1] & 0x00FF;
memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
memset(out->et1mac, 0xFF, 6);
-@@ -650,7 +762,7 @@ static int sprom_extract(struct ssb_bus
+@@ -650,7 +762,7 @@ static int sprom_extract(struct ssb_bus
* number stored in the SPROM.
* Always extract r1. */
out->revision = 1;
}
switch (out->revision) {
-@@ -667,9 +779,8 @@ static int sprom_extract(struct ssb_bus
+@@ -667,9 +779,8 @@ static int sprom_extract(struct ssb_bus
sprom_extract_r8(out, in);
break;
default:
#include <linux/ssb/ssb_regs.h>
-@@ -16,19 +18,28 @@ struct pcmcia_device;
+@@ -16,19 +18,29 @@ struct pcmcia_device;
struct ssb_bus;
struct ssb_driver;
u8 et1phyaddr; /* MII address for enet1 */
u8 et0mdcport; /* MDIO for enet0 */
u8 et1mdcport; /* MDIO for enet1 */
++ u16 dev_id; /* Device ID overriding e.g. PCI ID */
u16 board_rev; /* Board revision number from SPROM. */
+ u16 board_num; /* Board number from SPROM. */
+ u16 board_type; /* Board type from SPROM. */
u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
u16 pa0b0;
-@@ -47,10 +58,10 @@ struct ssb_sprom {
+@@ -47,10 +59,10 @@ struct ssb_sprom {
u8 gpio1; /* GPIO pin 1 */
u8 gpio2; /* GPIO pin 2 */
u8 gpio3; /* GPIO pin 3 */
u8 itssi_a; /* Idle TSSI Target for A-PHY */
u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
u8 tri2g; /* 2.4GHz TX isolation */
-@@ -61,8 +72,8 @@ struct ssb_sprom {
+@@ -61,8 +73,8 @@ struct ssb_sprom {
u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
u8 rssisav2g; /* 2GHz RSSI params */
u8 rssismc2g;
u8 rssismf2g;
-@@ -82,16 +93,13 @@ struct ssb_sprom {
+@@ -82,16 +94,13 @@ struct ssb_sprom {
u16 boardflags2_hi; /* Board flags (bits 48-63) */
/* TODO store board flags in a single u64 */
} antenna_gain;
struct {
-@@ -103,14 +111,85 @@ struct ssb_sprom {
+@@ -103,14 +112,85 @@ struct ssb_sprom {
} ghz5;
} fem;
};
-@@ -166,6 +245,7 @@ struct ssb_bus_ops {
+@@ -166,6 +246,7 @@ struct ssb_bus_ops {
#define SSB_DEV_MINI_MACPHY 0x823
#define SSB_DEV_ARM_1176 0x824
#define SSB_DEV_ARM_7TDMI 0x825
/* Vendor-ID values */
#define SSB_VENDOR_BROADCOM 0x4243
-@@ -260,13 +340,61 @@ enum ssb_bustype {
+@@ -260,13 +341,61 @@ enum ssb_bustype {
#define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */
#define SSB_BOARDVENDOR_HP 0x0E11 /* HP */
/* board_type */
/* chip_package */
#define SSB_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */
#define SSB_CHIPPACK_BCM4712M 2 /* Medium 225pin 4712 */
-@@ -354,7 +482,11 @@ struct ssb_bus {
+@@ -354,7 +483,11 @@ struct ssb_bus {
#ifdef CONFIG_SSB_EMBEDDED
/* Lock for GPIO register access. */
spinlock_t gpio_lock;