kernel: backport MIPS changes introducing a separate IRQ stack

[openwrt/staging/hauke.git] / target / linux / generic / patches-4.4 / 132-mips_inline_dma_ops.patch

diff --git a/target/linux/generic/patches-4.4/132-mips_inline_dma_ops.patch b/target/linux/generic/patches-4.4/132-mips_inline_dma_ops.patch
index bf7dca6a334e693da3ebbacfd8e61f82164e6371..143b0bb3ff49e371763715e64e5cb5dd97dae0a5 100644 (file)
--- a/target/linux/generic/patches-4.4/132-mips_inline_dma_ops.patch
+++ b/target/linux/generic/patches-4.4/132-mips_inline_dma_ops.patch
@@ -19,7 +19,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/arch/mips/Kconfig
 +++ b/arch/mips/Kconfig
-@@ -1618,6 +1618,7 @@ config CPU_CAVIUM_OCTEON
+@@ -1619,6 +1619,7 @@ config CPU_CAVIUM_OCTEON
        select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
        select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
        select MIPS_L1_CACHE_SHIFT_7
@@ -27,7 +27,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
        help
          The Cavium Octeon processor is a highly integrated chip containing
          many ethernet hardware widgets for networking tasks. The processor
-@@ -1913,6 +1914,9 @@ config MIPS_MALTA_PM
+@@ -1914,6 +1915,9 @@ config MIPS_MALTA_PM
        bool
        default y