/* PIO registers base address and register offsets */
#define PIO_BASE_ADDR 0x4000
#define PIO_CTRL (PIO_BASE_ADDR + 0x0)
-@@ -959,7 +955,7 @@ static int advk_sw_pci_bridge_init(struc
+@@ -961,7 +957,7 @@ static int advk_sw_pci_bridge_init(struc
bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
/* Support interrupt A for MSI feature */