lots of ifxmips fixes and features

[openwrt/staging/yousong.git] / target / linux / ifxmips / files / include / asm-mips / ifxmips / ifxmips.h

diff --git a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
index 3ab53aebb08825dcdcc4d1605134fbacfcd7742c..8389611895fa8adf013716c2f7274fa109d78aaf 100644 (file)
--- a/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
+++ b/target/linux/ifxmips/files/include/asm-mips/ifxmips/ifxmips.h
@@ -15,13 +15,13 @@
  *
  *   Copyright (C) 2005 infineon
  *   Copyright (C) 2007 John Crispin <blogic@openwrt.org> 
- *
  */
 #ifndef _IFXMIPS_H__
 #define _IFXMIPS_H__
 
 #define ifxmips_r32(reg) __raw_readl(reg)
 #define ifxmips_w32(val,reg) __raw_writel(val,reg)
+#define ifxmips_w32_mask(clear,set,reg)        ifxmips_w32((ifxmips_r32(reg) & ~clear) | set, reg)
 
 /*------------ GENERAL */
 
@@ -70,8 +70,41 @@
 #define ASCOPT_STOPB                   0x8
 #define ASCOPT_PARODD                  0x0
 #define ASCOPT_CREAD                   0x20
-#define ASCFSTAT_TXFFLMASK             0x3F00
-#define ASCFSTAT_TXFFLOFF              8
+#define TXFIFO_FL                              1
+#define RXFIFO_FL                              1
+#define TXFIFO_FULL                            16
+#define ASCCLC_RMCMASK                 0x0000FF00
+#define ASCCLC_RMCOFFSET               8
+#define ASCCON_M_8ASYNC                        0x0
+#define ASCCON_M_7ASYNC                        0x2
+#define ASCCON_ODD                             0x00000020
+#define ASCCON_STP                             0x00000080
+#define ASCCON_BRS                             0x00000100
+#define ASCCON_FDE                             0x00000200
+#define ASCCON_R                               0x00008000
+#define ASCCON_FEN                             0x00020000
+#define ASCCON_ROEN                            0x00080000
+#define ASCCON_TOEN                            0x00100000
+#define ASCSTATE_PE                            0x00010000
+#define ASCSTATE_FE                            0x00020000
+#define ASCSTATE_ROE                   0x00080000
+#define ASCSTATE_ANY                   (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
+#define ASCWHBSTATE_CLRREN             0x00000001
+#define ASCWHBSTATE_SETREN             0x00000002
+#define ASCWHBSTATE_CLRPE              0x00000004
+#define ASCWHBSTATE_CLRFE              0x00000008
+#define ASCWHBSTATE_CLRROE             0x00000020
+#define ASCTXFCON_TXFEN                        0x0001
+#define ASCTXFCON_TXFFLU               0x0002
+#define ASCTXFCON_TXFITLMASK    0x3F00
+#define ASCTXFCON_TXFITLOFF     8
+#define ASCRXFCON_RXFEN         0x0001
+#define ASCRXFCON_RXFFLU        0x0002
+#define ASCRXFCON_RXFITLMASK    0x3F00
+#define ASCRXFCON_RXFITLOFF     8
+#define ASCFSTAT_RXFFLMASK      0x003F
+#define ASCFSTAT_TXFFLMASK      0x3F00
+#define ASCFSTAT_TXFFLOFF       8
 
 
 
@@ -87,13 +120,6 @@
 #define IFXMIPS_RCU_RST_REQ_AFE        (1 << 11)
 #define IFXMIPS_RCU_RST_REQ_ARC_JTAG   (1 << 20)
 
-/*------------ MCD */
-
-#define IFXMIPS_MCD_BASE_ADDR  (KSEG1 + 0x1F106000)
-
-/* chip id */
-#define IFXMIPS_MCD_CHIPID             ((u32*)(IFXMIPS_MCD_BASE_ADDR + 0x0028))
-
 
 /*------------ GPTU */
 
@@ -188,7 +214,8 @@
 #define REV_MII_MODE 2
 
 /* mdio access */
-#define IFXMIPS_PPE32_MDIO_ACC ((u32*)(IFXMIPS_PPE32_MEM_MAP + 0x1804))
+#define IFXMIPS_PPE32_MDIO_CFG ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11800))
+#define IFXMIPS_PPE32_MDIO_ACC ((u32*)(IFXMIPS_PPE32_BASE_ADDR + 0x11804))
 
 #define MDIO_ACC_REQUEST               0x80000000
 #define MDIO_ACC_READ                  0x40000000
@@ -339,7 +366,7 @@
 #define IFXMIPS_SSC_IRN                        ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x00F4))
 #define IFXMIPS_SSC_SFCON              ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0060))
 #define IFXMIPS_SSC_WHBGPOSTAT ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0078))
-#define IFXMIPS_SSC_STATE      ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
+#define IFXMIPS_SSC_STATE              ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0014))
 #define IFXMIPS_SSC_WHBSTATE   ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0018))
 #define IFXMIPS_SSC_FSTAT              ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0038))
 #define IFXMIPS_SSC_ID                 ((u32*)(IFXMIPS_SSC_BASE_ADDR + 0x0008))
@@ -477,7 +504,7 @@
 #define IFXMIPS_MPS_AD0ENR             ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x0058))
 #define IFXMIPS_MPS_AD1ENR             ((u32*)(IFXMIPS_MPS_BASE_ADDR + 0x005C))
 
-#define IFXMIPS_MPS_CHIPID_VERSION_GET(value)   (((value) >> 28) & ((1 << 4) - 1))
+#define IFXMIPS_MPS_CHIPID_VERSION_GET(value)  (((value) >> 28) & ((1 << 4) - 1))
 #define IFXMIPS_MPS_CHIPID_VERSION_SET(value)  (((( 1 << 4) - 1) & (value)) << 28)
 #define IFXMIPS_MPS_CHIPID_PARTNUM_GET(value)  (((value) >> 12) & ((1 << 16) - 1))
 #define IFXMIPS_MPS_CHIPID_PARTNUM_SET(value)  (((( 1 << 16) - 1) & (value)) << 12)