#define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0
#define PCIE_CORE_LINK_L0S_ENTRY BIT(0)
#define PCIE_CORE_LINK_TRAINING BIT(5)
-@@ -299,7 +301,8 @@ static void advk_pcie_setup_hw(struct ad
+@@ -300,7 +302,8 @@ static void advk_pcie_setup_hw(struct ad
/* Set PCIe Device Control and Status 1 PF0 register */
reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |
(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<
PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);
-@@ -922,6 +925,58 @@ out_release_res:
+@@ -968,6 +971,58 @@ out_release_res:
return err;
}
static int advk_pcie_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
-@@ -996,6 +1051,9 @@ static int advk_pcie_probe(struct platfo
+@@ -1042,6 +1097,9 @@ static int advk_pcie_probe(struct platfo
list_for_each_entry(child, &bus->children, node)
pcie_bus_configure_settings(child);