#define PCIE_CORE_LINK_WIDTH_SHIFT 20
#define PCIE_CORE_ERR_CAPCTL_REG 0x118
#define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
-@@ -201,6 +202,7 @@ struct advk_pcie {
+@@ -202,6 +203,7 @@ struct advk_pcie {
struct mutex msi_used_lock;
u16 msi_msg;
int root_bus_nr;
struct pci_bridge_emul bridge;
};
-@@ -225,20 +227,16 @@ static int advk_pcie_link_up(struct advk
+@@ -226,20 +228,16 @@ static int advk_pcie_link_up(struct advk
static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
{
return -ETIMEDOUT;
}
-@@ -253,6 +251,85 @@ static void advk_pcie_wait_for_retrain(s
+@@ -254,6 +252,85 @@ static void advk_pcie_wait_for_retrain(s
}
}
static void advk_pcie_setup_hw(struct advk_pcie *pcie)
{
u32 reg;
-@@ -288,12 +365,6 @@ static void advk_pcie_setup_hw(struct ad
+@@ -299,12 +376,6 @@ static void advk_pcie_setup_hw(struct ad
PCIE_CORE_CTRL2_TD_ENABLE;
advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
/* Set lane X1 */
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
reg &= ~LANE_CNT_MSK;
-@@ -341,20 +412,7 @@ static void advk_pcie_setup_hw(struct ad
+@@ -352,20 +423,7 @@ static void advk_pcie_setup_hw(struct ad
*/
msleep(PCI_PM_D3COLD_WAIT);
reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
-@@ -1066,6 +1124,12 @@ static int advk_pcie_probe(struct platfo
+@@ -1077,6 +1135,12 @@ static int advk_pcie_probe(struct platfo
return ret;
}