/*
* PCIe driver for PLX NAS782X SoCs
*
+ * Author: Ma Haijun <mahaijuns@gmail.com>
+ *
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/mbus.h>
+#include <linux/mfd/syscon.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/of_address.h>
-#include <linux/of_pci.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
#include <linux/of_irq.h>
+#include <linux/of_pci.h>
#include <linux/of_platform.h>
-#include <linux/of_gpio.h>
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/clk.h>
+#include <linux/phy.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
#include <linux/reset.h>
-#include <mach/iomap.h>
-#include <mach/hardware.h>
-#include <mach/utils.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+
+#define SYS_CTRL_HCSL_CTRL_REGOFFSET 0x114
+
+static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
+{
+ u32 val = readl_relaxed(p);
+
+ val &= ~mask;
+ writel_relaxed(val, p);
+}
+
+static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
+{
+ u32 val = readl_relaxed(p);
+
+ val |= mask;
+ writel_relaxed(val, p);
+}
+
+static inline void oxnas_register_value_mask(void __iomem *p,
+ unsigned mask, unsigned new_value)
+{
+ /* TODO sanity check mask & new_value = new_value */
+ u32 val = readl_relaxed(p);
+
+ val &= ~mask;
+ val |= new_value;
+ writel_relaxed(val, p);
+}
#define VERSION_ID_MAGIC 0x082510b5
#define LINK_UP_TIMEOUT_SECONDS 1
PCIE_OBTRANS = BIT(12),
};
-enum {
- HCSL_BIAS_ON = BIT(0),
- HCSL_PCIE_EN = BIT(1),
- HCSL_PCIEA_EN = BIT(2),
- HCSL_PCIEB_EN = BIT(3),
-};
-
-enum {
- /* pcie phy reg offset */
- PHY_ADDR = 0,
- PHY_DATA = 4,
- /* phy data reg bits */
- READ_EN = BIT(16),
- WRITE_EN = BIT(17),
- CAP_DATA = BIT(18),
-};
-
/* core config registers */
enum {
PCI_CONFIG_VERSION_DEVICEID = 0,
PCIE_SLAVE_BE_SHIFT = 22,
};
-#define ADDR_VAL(val) ((val) & 0xFFFF)
-#define DATA_VAL(val) ((val) & 0xFFFF)
-
#define PCIE_SLAVE_BE(val) ((val) << PCIE_SLAVE_BE_SHIFT)
#define PCIE_SLAVE_BE_MASK PCIE_SLAVE_BE(0xF)
void __iomem *cfgbase;
void __iomem *base;
void __iomem *inbound;
- void __iomem *outbound;
- void __iomem *pcie_ctrl;
-
+ struct regmap *sys_ctrl;
+ unsigned int outbound_offset;
+ unsigned int pcie_ctrl_offset;
+ struct phy *phy;
int haslink;
struct platform_device *pdev;
struct resource io;
static inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes)
{
- oxnas_register_value_mask(pcie->outbound + PCIE_AHB_SLAVE_CTRL,
+ regmap_update_bits(pcie->sys_ctrl, pcie->outbound_offset + PCIE_AHB_SLAVE_CTRL,
PCIE_SLAVE_BE_MASK, PCIE_SLAVE_BE(lanes));
wmb();
}
static int oxnas_pcie_link_up(struct oxnas_pcie *pcie)
{
unsigned long end;
+ unsigned int val;
/* Poll for PCIE link up */
end = jiffies + (LINK_UP_TIMEOUT_SECONDS * HZ);
while (!time_after(jiffies, end)) {
- if (readl(pcie->pcie_ctrl) & PCIE_LINK_UP)
+ regmap_read(pcie->sys_ctrl, pcie->pcie_ctrl_offset, &val);
+ if (val & PCIE_LINK_UP)
return 1;
}
return 0;
}
-static void __init oxnas_pcie_setup_hw(struct oxnas_pcie *pcie)
+static void oxnas_pcie_setup_hw(struct oxnas_pcie *pcie)
{
/* We won't have any inbound address translation. This allows PCI
* devices to access anywhere in the AHB address map. Might be regarded
*/
/* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */
- writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_IN0_MEM_ADDR);
- writel_relaxed(pcie->non_mem.end, pcie->outbound + PCIE_IN0_MEM_LIMIT);
- writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_POM0_MEM_ADDR);
+ regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_ADDR, pcie->non_mem.start);
+ regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_LIMIT, pcie->non_mem.end);
+ regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM0_MEM_ADDR, pcie->non_mem.start);
/* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */
- writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_IN1_MEM_ADDR);
- writel_relaxed(pcie->pre_mem.end, pcie->outbound + PCIE_IN1_MEM_LIMIT);
- writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_POM1_MEM_ADDR);
+ regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_ADDR, pcie->pre_mem.start);
+ regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_LIMIT, pcie->pre_mem.end);
+ regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM1_MEM_ADDR, pcie->pre_mem.start);
/* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/
- writel_relaxed(pcie->io.start, pcie->outbound + PCIE_IN_IO_ADDR);
- writel_relaxed(pcie->io.end, pcie->outbound + PCIE_IN_IO_LIMIT);
+ regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_ADDR, pcie->io.start);
+ regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_LIMIT, pcie->io.end);
+
/* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/
- writel_relaxed(pcie->cfg.start, pcie->outbound + PCIE_IN_CFG0_ADDR);
- writel_relaxed(pcie->cfg.end, pcie->outbound + PCIE_IN_CFG0_LIMIT);
+ regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_ADDR, pcie->cfg.start);
+ regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_LIMIT, pcie->cfg.end);
wmb();
/* Enable outbound address translation */
- oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_OBTRANS);
+ regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset, PCIE_OBTRANS, PCIE_OBTRANS);
wmb();
/*
.write = oxnas_pcie_wr_conf,
};
-static int __init oxnas_pcie_setup(int nr, struct pci_sys_data *sys)
+static int oxnas_pcie_setup(int nr, struct pci_sys_data *sys)
{
struct oxnas_pcie *pcie = sys_to_pcie(sys);
return 1;
}
-static void __init oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie)
+static void oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie)
{
struct hw_pci hw;
int i;
pci_common_init_dev(dev, &hw);
}
-void oxnas_pcie_init_shared_hw(struct platform_device *pdev,
- void __iomem *phybase)
-{
- struct reset_control *rstc;
- int ret;
-
- /* generate clocks from HCSL buffers, shared parts */
- writel(HCSL_BIAS_ON|HCSL_PCIE_EN, SYS_CTRL_HCSL_CTRL);
-
- /* Ensure PCIe PHY is properly reset */
- rstc = reset_control_get(&pdev->dev, "phy");
- if (IS_ERR(rstc)) {
- ret = PTR_ERR(rstc);
- } else {
- ret = reset_control_reset(rstc);
- reset_control_put(rstc);
- }
-
- if (ret) {
- dev_err(&pdev->dev, "phy reset failed %d\n", ret);
- return;
- }
-
- /* Enable PCIe Pre-Emphasis: What these value means? */
-
- writel(ADDR_VAL(0x0014), phybase + PHY_ADDR);
- writel(DATA_VAL(0xce10) | CAP_DATA, phybase + PHY_DATA);
- writel(DATA_VAL(0xce10) | WRITE_EN, phybase + PHY_DATA);
-
- writel(ADDR_VAL(0x2004), phybase + PHY_ADDR);
- writel(DATA_VAL(0x82c7) | CAP_DATA, phybase + PHY_DATA);
- writel(DATA_VAL(0x82c7) | WRITE_EN, phybase + PHY_DATA);
-}
-
-static int oxnas_pcie_shared_init(struct platform_device *pdev)
+static int oxnas_pcie_shared_init(struct platform_device *pdev, struct oxnas_pcie *pcie)
{
if (++pcie_shared.refcount == 1) {
- /* we are the first */
- struct device_node *np = pdev->dev.of_node;
- void __iomem *phy = of_iomap(np, 2);
- if (!phy) {
- --pcie_shared.refcount;
- return -ENOMEM;
- }
- oxnas_pcie_init_shared_hw(pdev, phy);
- iounmap(phy);
+ phy_init(pcie->phy);
+ phy_power_on(pcie->phy);
return 0;
} else {
return 0;
}
#endif
-static int __init
+static int
oxnas_pcie_map_registers(struct platform_device *pdev,
struct device_node *np,
struct oxnas_pcie *pcie)
u32 outbound_ctrl_offset;
u32 pcie_ctrl_offset;
- /* 2 is reserved for shared phy */
ret = of_address_to_resource(np, 0, ®s);
if (ret)
return -EINVAL;
if (!pcie->inbound)
return -ENOMEM;
+ pcie->phy = devm_of_phy_get(&pdev->dev, np, NULL);
+ if (IS_ERR(pcie->phy)) {
+ if (PTR_ERR(pcie->phy) == -EPROBE_DEFER)
+ return PTR_ERR(pcie->phy);
+ pcie->phy = NULL;
+ }
if (of_property_read_u32(np, "plxtech,pcie-outbound-offset",
&outbound_ctrl_offset))
return -EINVAL;
- /* SYSCRTL is shared by too many drivers, so is mapped by board file */
- pcie->outbound = IOMEM(OXNAS_SYSCRTL_BASE_VA + outbound_ctrl_offset);
+ pcie->outbound_offset = outbound_ctrl_offset;
if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset",
&pcie_ctrl_offset))
return -EINVAL;
- pcie->pcie_ctrl = IOMEM(OXNAS_SYSCRTL_BASE_VA + pcie_ctrl_offset);
+ pcie->pcie_ctrl_offset = pcie_ctrl_offset;
return 0;
}
-static int __init oxnas_pcie_init_res(struct platform_device *pdev,
+static int oxnas_pcie_init_res(struct platform_device *pdev,
struct oxnas_pcie *pcie,
struct device_node *np)
{
mdelay(100);
}
- oxnas_register_set_mask(SYS_CTRL_HCSL_CTRL, BIT(pcie->hcsl_en));
+ /* ToDo: use phy power-on port... */
+ regmap_update_bits(pcie->sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET,
+ BIT(pcie->hcsl_en), BIT(pcie->hcsl_en));
/* core */
ret = device_reset(&pdev->dev);
}
/* allow entry to L23 state */
- oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_READY_ENTR_L23);
+ regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
+ PCIE_READY_ENTR_L23, PCIE_READY_ENTR_L23);
/* Set PCIe core into RootCore mode */
- oxnas_register_value_mask(pcie->pcie_ctrl, PCIE_DEVICE_TYPE_MASK,
- PCIE_DEVICE_TYPE_ROOT);
+ regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
+ PCIE_DEVICE_TYPE_MASK, PCIE_DEVICE_TYPE_ROOT);
wmb();
/* Bring up the PCI core */
- oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_LTSSM);
+ regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
+ PCIE_LTSSM, PCIE_LTSSM);
wmb();
}
-static int __init oxnas_pcie_probe(struct platform_device *pdev)
+static int oxnas_pcie_probe(struct platform_device *pdev)
{
struct oxnas_pcie *pcie;
struct device_node *np = pdev->dev.of_node;
pcie->haslink = 1;
spin_lock_init(&pcie->lock);
+ pcie->sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
+ if (IS_ERR(pcie->sys_ctrl))
+ return PTR_ERR(pcie->sys_ctrl);
+
ret = oxnas_pcie_init_res(pdev, pcie, np);
if (ret)
return ret;
goto err_free_gpio;
}
- ret = oxnas_pcie_shared_init(pdev);
+ ret = oxnas_pcie_shared_init(pdev, pcie);
if (ret)
goto err_free_gpio;
{ .compatible = "plxtech,nas782x-pcie", },
{},
};
-MODULE_DEVICE_TABLE(of, oxnas_pcie_of_match_table);
static struct platform_driver oxnas_pcie_driver = {
.driver = {
- .owner = THIS_MODULE,
.name = "oxnas-pcie",
- .of_match_table =
- of_match_ptr(oxnas_pcie_of_match_table),
+ .suppress_bind_attrs = true,
+ .of_match_table = oxnas_pcie_of_match_table,
},
+ .probe = oxnas_pcie_probe,
};
-static int __init oxnas_pcie_init(void)
-{
- return platform_driver_probe(&oxnas_pcie_driver,
- oxnas_pcie_probe);
-}
-
-subsys_initcall(oxnas_pcie_init);
-
-MODULE_AUTHOR("Ma Haijun <mahaijuns@gmail.com>");
-MODULE_DESCRIPTION("NAS782x PCIe driver");
-MODULE_LICENSE("GPLv2");
+builtin_platform_driver(oxnas_pcie_driver);
projects / openwrt / staging / wigyori.git / blobdiff