-/dts-v1/;
-
#include "mt7620a.dtsi"
#include <dt-bindings/gpio/gpio.h>
compatible = "gpio-leds";
lan {
- label = "archer-mr200:white:lan";
+ label = "white:lan";
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
};
wan {
- label = "archer-mr200:white:wan";
+ label = "white:wan";
gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
};
led_power: power {
- label = "archer-mr200:white:power";
+ label = "white:power";
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
};
4g {
- label = "archer-mr200:white:4g";
+ label = "white:4g";
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
};
wps {
- label = "archer-mr200:white:wps";
+ label = "white:wps";
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
signal1 {
- label = "archer-mr200:white:signal1";
+ label = "white:signal1";
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
};
signal2 {
- label = "archer-mr200:white:signal2";
+ label = "white:signal2";
gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
};
signal3 {
- label = "archer-mr200:white:signal3";
+ label = "white:signal3";
gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
};
signal4 {
- label = "archer-mr200:white:signal4";
+ label = "white:signal4";
gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
};
wlan {
- label = "archer-mr200:white:wlan";
+ label = "white:wlan";
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
&spi0 {
status = "okay";
- m25p80@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
- spi-max-frequency = <10000000>;
+ spi-max-frequency = <30000000>;
partitions {
compatible = "fixed-partitions";
&state_default {
gpio {
- ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd", "ephy", "spi refclk";
- ralink,function = "gpio";
+ groups = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd", "ephy", "spi refclk";
+ function = "gpio";
};
};
ðernet {
- mtd-mac-address = <&rom 0xf100>;
- mediatek,portmap = "llll";
- };
+ nvmem-cells = <&macaddr_rom_f100>;
+ nvmem-cell-names = "mac-address";
+};
&ehci {
status = "okay";
status = "okay";
};
-&gsw {
- mediatek,port4 = "ephy";
-};
-
&wmac {
ralink,mtd-eeprom = <&radio 0x0>;
};
mediatek,mtd-eeprom = <&radio 0x8000>;
};
};
+
+&rom {
+ compatible = "nvmem-cells";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_rom_f100: macaddr@f100 {
+ reg = <0xf100 0x6>;
+ };
+};