ramips: mt7621-dts: remove ethsys node

[openwrt/staging/thess.git] / target / linux / ramips / dts / mt7621.dtsi

diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
index 2db238f57fcfefdb069122f3b42c8d7706a134eb..4cb339bcae63939f4b7662b2b78a672831e92c5b 100644 (file)
--- a/target/linux/ramips/dts/mt7621.dtsi
+++ b/target/linux/ramips/dts/mt7621.dtsi
@@ -1,3 +1,5 @@
+/dts-v1/;
+
 #include <dt-bindings/interrupt-controller/mips-gic.h>
 #include <dt-bindings/clock/mt7621-clk.h>
 #include <dt-bindings/gpio/gpio.h>
@@ -7,6 +9,10 @@
        #size-cells = <1>;
        compatible = "mediatek,mt7621-soc";
 
+       aliases {
+               serial0 = &uartlite;
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -31,8 +37,8 @@
                compatible = "mti,cpu-interrupt-controller";
        };
 
-       aliases {
-               serial0 = &uartlite;
+       chosen {
+               bootargs = "console=ttyS0,57600";
        };
 
        pll: pll {
@@ -50,10 +56,10 @@
                clock-frequency = <50000000>;
        };
 
-       palmbus: palmbus@1E000000 {
+       palmbus: palmbus@1e000000 {
                compatible = "palmbus";
-               reg = <0x1E000000 0x100000>;
-               ranges = <0x0 0x1E000000 0x0FFFFF>;
+               reg = <0x1e000000 0x100000>;
+               ranges = <0x0 0x1e000000 0x0fffff>;
 
                #address-cells = <1>;
                #size-cells = <1>;
@@ -135,16 +141,6 @@
                        reg = <0x5000 0x1000>;
                };
 
-               cpc: cpc@1fbf0000 {
-                       compatible = "mtk,mt7621-cpc";
-                       reg = <0x1fbf0000 0x8000>;
-               };
-
-               mc: mc@1fbf8000 {
-                       compatible = "mtk,mt7621-mc";
-                       reg = <0x1fbf8000 0x8000>;
-               };
-
                uartlite: uartlite@c00 {
                        compatible = "ns16550a";
                        reg = <0xc00 0x100>;
@@ -221,7 +217,7 @@
                        reset-names = "dma";
 
                        interrupt-parent = <&gic>;
-                       interrupts = <0 13 4>;
+                       interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
 
                        #dma-cells = <1>;
                        #dma-channels = <16>;
@@ -238,7 +234,7 @@
                        reset-names = "hsdma";
 
                        interrupt-parent = <&gic>;
-                       interrupts = <0 11 4>;
+                       interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 
                        #dma-cells = <1>;
                        #dma-channels = <1>;
@@ -315,7 +311,7 @@
                pcie_pins: pcie {
                        pcie {
                                groups = "pcie";
-                               function = "pcie rst";
+                               function = "gpio";
                        };
                };
 
@@ -349,11 +345,11 @@
                #clock-cells = <1>;
        };
 
-       sdhci: sdhci@1E130000 {
+       sdhci: sdhci@1e130000 {
                status = "disabled";
 
                compatible = "ralink,mt7620-sdhci";
-               reg = <0x1E130000 0x4000>;
+               reg = <0x1e130000 0x4000>;
 
                interrupt-parent = <&gic>;
                interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -362,10 +358,9 @@
                pinctrl-0 = <&sdhci_pins>;
        };
 
-       xhci: xhci@1E1C0000 {
+       xhci: xhci@1e1c0000 {
                #address-cells = <1>;
                #size-cells = <0>;
-               status = "okay";
 
                compatible = "mediatek,mt8173-xhci";
                reg = <0x1e1c0000 0x1000
@@ -414,20 +409,33 @@
                };
        };
 
+       nficlock: nficlock {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+
+               clock-frequency = <125000000>;
+       };
+
+       cpc: cpc@1fbf0000 {
+               compatible = "mti,mips-cpc";
+               reg = <0x1fbf0000 0x8000>;
+       };
+
+       mc: mc@1fbf8000 {
+               compatible = "mti,mips-cdmm";
+               reg = <0x1fbf8000 0x8000>;
+       };
+
        nand: nand@1e003000 {
                status = "disabled";
 
-               compatible = "mtk,mt7621-nand";
-               bank-width = <2>;
+               compatible = "mediatek,mt7621-nfc";
                reg = <0x1e003000 0x800
                        0x1e003800 0x800>;
-       };
+               reg-names = "nfi", "ecc";
 
-       ethsys: syscon@1e000000 {
-               compatible = "mediatek,mt7621-ethsys",
-                            "syscon";
-               reg = <0x1e000000 0x1000>;
-               #clock-cells = <1>;
+               clocks = <&nficlock>;
+               clock-names = "nfi_clk";
        };
 
        ethernet: ethernet@1e100000 {
@@ -446,7 +454,7 @@
                interrupt-parent = <&gic>;
                interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 
-               mediatek,ethsys = <&ethsys>;
+               mediatek,ethsys = <&sysc>;
 
                gmac0: mac@0 {
                        compatible = "mediatek,eth-mac";
@@ -531,18 +539,12 @@
                };
        };
 
-       gsw: gsw@1e110000 {
-               compatible = "mediatek,mt7621-gsw";
-               reg = <0x1e110000 0x8000>;
-               interrupt-parent = <&gic>;
-               interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
-       };
-
        pcie: pcie@1e140000 {
                compatible = "mediatek,mt7621-pci";
-               reg = <0x1e140000 0x100
-                       0x1e142000 0x100>;
-
+               reg = <0x1e140000 0x100     /* host-pci bridge registers */
+                       0x1e142000 0x100    /* pcie port 0 RC control registers */
+                       0x1e143000 0x100    /* pcie port 1 RC control registers */
+                       0x1e144000 0x100>;  /* pcie port 2 RC control registers */
                #address-cells = <3>;
                #size-cells = <2>;
 
@@ -568,32 +570,45 @@
                reset-names = "pcie0", "pcie1", "pcie2";
                clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
                clock-names = "pcie0", "pcie1", "pcie2";
+               phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
+               phy-names = "pcie-phy0", "pcie-phy2";
+
+               reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 
                pcie0: pcie@0,0 {
                        reg = <0x0000 0 0 0 0>;
-
                        #address-cells = <3>;
                        #size-cells = <2>;
-
                        ranges;
+                       bus-range = <0x00 0xff>;
                };
 
                pcie1: pcie@1,0 {
                        reg = <0x0800 0 0 0 0>;
-
                        #address-cells = <3>;
                        #size-cells = <2>;
-
                        ranges;
+                       bus-range = <0x00 0xff>;
                };
 
                pcie2: pcie@2,0 {
                        reg = <0x1000 0 0 0 0>;
-
                        #address-cells = <3>;
                        #size-cells = <2>;
-
                        ranges;
+                       bus-range = <0x00 0xff>;
                };
        };
+
+       pcie0_phy: pcie-phy@1e149000 {
+               compatible = "mediatek,mt7621-pci-phy";
+               reg = <0x1e149000 0x0700>;
+               #phy-cells = <1>;
+       };
+
+       pcie2_phy: pcie-phy@1e14a000 {
+               compatible = "mediatek,mt7621-pci-phy";
+               reg = <0x1e14a000 0x0700>;
+               #phy-cells = <1>;
+       };
 };