clock-frequency = <50000000>;
};
- palmbus: palmbus@1E000000 {
+ palmbus: palmbus@1e000000 {
compatible = "palmbus";
- reg = <0x1E000000 0x100000>;
- ranges = <0x0 0x1E000000 0x0FFFFF>;
+ reg = <0x1e000000 0x100000>;
+ ranges = <0x0 0x1e000000 0x0fffff>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x5000 0x1000>;
};
- cpc: cpc@1fbf0000 {
- compatible = "mtk,mt7621-cpc";
- reg = <0x1fbf0000 0x8000>;
- };
-
- mc: mc@1fbf8000 {
- compatible = "mtk,mt7621-mc";
- reg = <0x1fbf8000 0x8000>;
- };
-
uartlite: uartlite@c00 {
compatible = "ns16550a";
reg = <0xc00 0x100>;
#clock-cells = <1>;
};
- sdhci: sdhci@1E130000 {
+ sdhci: sdhci@1e130000 {
status = "disabled";
compatible = "ralink,mt7620-sdhci";
- reg = <0x1E130000 0x4000>;
+ reg = <0x1e130000 0x4000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-0 = <&sdhci_pins>;
};
- xhci: xhci@1E1C0000 {
+ xhci: xhci@1e1c0000 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <125000000>;
};
+ cpc: cpc@1fbf0000 {
+ compatible = "mti,mips-cpc";
+ reg = <0x1fbf0000 0x8000>;
+ };
+
+ mc: mc@1fbf8000 {
+ compatible = "mti,mips-cdmm";
+ reg = <0x1fbf8000 0x8000>;
+ };
+
nand: nand@1e003000 {
status = "disabled";
clock-names = "nfi_clk";
};
- ethsys: syscon@1e000000 {
- compatible = "mediatek,mt7621-ethsys",
- "syscon";
- reg = <0x1e000000 0x1000>;
- #clock-cells = <1>;
- };
-
ethernet: ethernet@1e100000 {
compatible = "mediatek,mt7621-eth";
reg = <0x1e100000 0x10000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
- mediatek,ethsys = <ðsys>;
+ mediatek,ethsys = <&sysc>;
gmac0: mac@0 {
compatible = "mediatek,eth-mac";
};
};
- gsw: gsw@1e110000 {
- compatible = "mediatek,mt7621-gsw";
- reg = <0x1e110000 0x8000>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
- };
-
pcie: pcie@1e140000 {
compatible = "mediatek,mt7621-pci";
reg = <0x1e140000 0x100 /* host-pci bridge registers */