ramips: mt7621: add new NAND driver

[openwrt/staging/dedeckeh.git] / target / linux / ramips / dts / mt7621.dtsi

diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi
index 28ee0902cc64aef75f404a5d1ea897a0dc248eef..63befa1fdcfa8b2b45dc795af0947d1704275bac 100644 (file)
--- a/target/linux/ramips/dts/mt7621.dtsi
+++ b/target/linux/ramips/dts/mt7621.dtsi
@@ -258,83 +258,83 @@
 
                i2c_pins: i2c_pins {
                        i2c_pins {
-                               ralink,group = "i2c";
-                               ralink,function = "i2c";
+                               groups = "i2c";
+                               function = "i2c";
                        };
                };
 
                spi_pins: spi_pins {
                        spi_pins {
-                               ralink,group = "spi";
-                               ralink,function = "spi";
+                               groups = "spi";
+                               function = "spi";
                        };
                };
 
                uart1_pins: uart1 {
                        uart1 {
-                               ralink,group = "uart1";
-                               ralink,function = "uart1";
+                               groups = "uart1";
+                               function = "uart1";
                        };
                };
 
                uart2_pins: uart2 {
                        uart2 {
-                               ralink,group = "uart2";
-                               ralink,function = "uart2";
+                               groups = "uart2";
+                               function = "uart2";
                        };
                };
 
                uart3_pins: uart3 {
                        uart3 {
-                               ralink,group = "uart3";
-                               ralink,function = "uart3";
+                               groups = "uart3";
+                               function = "uart3";
                        };
                };
 
                rgmii1_pins: rgmii1 {
                        rgmii1 {
-                               ralink,group = "rgmii1";
-                               ralink,function = "rgmii1";
+                               groups = "rgmii1";
+                               function = "rgmii1";
                        };
                };
 
                rgmii2_pins: rgmii2 {
                        rgmii2 {
-                               ralink,group = "rgmii2";
-                               ralink,function = "rgmii2";
+                               groups = "rgmii2";
+                               function = "rgmii2";
                        };
                };
 
                mdio_pins: mdio {
                        mdio {
-                               ralink,group = "mdio";
-                               ralink,function = "mdio";
+                               groups = "mdio";
+                               function = "mdio";
                        };
                };
 
                pcie_pins: pcie {
                        pcie {
-                               ralink,group = "pcie";
-                               ralink,function = "pcie rst";
+                               groups = "pcie";
+                               function = "gpio";
                        };
                };
 
                nand_pins: nand {
                        spi-nand {
-                               ralink,group = "spi";
-                               ralink,function = "nand1";
+                               groups = "spi";
+                               function = "nand1";
                        };
 
                        sdhci-nand {
-                               ralink,group = "sdhci";
-                               ralink,function = "nand2";
+                               groups = "sdhci";
+                               function = "nand2";
                        };
                };
 
                sdhci_pins: sdhci {
                        sdhci {
-                               ralink,group = "sdhci";
-                               ralink,function = "sdhci";
+                               groups = "sdhci";
+                               function = "sdhci";
                        };
                };
        };
@@ -414,13 +414,23 @@
                };
        };
 
+       nficlock: nficlock {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+
+               clock-frequency = <125000000>;
+       };
+
        nand: nand@1e003000 {
                status = "disabled";
 
-               compatible = "mtk,mt7621-nand";
-               bank-width = <2>;
+               compatible = "mediatek,mt7621-nfc";
                reg = <0x1e003000 0x800
                        0x1e003800 0x800>;
+               reg-names = "nfi", "ecc";
+
+               clocks = <&nficlock>;
+               clock-names = "nfi_clk";
        };
 
        ethsys: syscon@1e000000 {
@@ -540,9 +550,10 @@
 
        pcie: pcie@1e140000 {
                compatible = "mediatek,mt7621-pci";
-               reg = <0x1e140000 0x100
-                       0x1e142000 0x100>;
-
+               reg = <0x1e140000 0x100     /* host-pci bridge registers */
+                       0x1e142000 0x100    /* pcie port 0 RC control registers */
+                       0x1e143000 0x100    /* pcie port 1 RC control registers */
+                       0x1e144000 0x100>;  /* pcie port 2 RC control registers */
                #address-cells = <3>;
                #size-cells = <2>;
 
@@ -557,10 +568,11 @@
                        0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
                >;
 
-               interrupt-parent = <&gic>;
-               interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
-                               GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
-                               GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+               #interrupt-cells = <1>;
+               interrupt-map-mask = <0xF0000 0 0 1>;
+               interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
+                               <0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
+                               <0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 
                status = "disabled";
 
@@ -568,32 +580,45 @@
                reset-names = "pcie0", "pcie1", "pcie2";
                clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
                clock-names = "pcie0", "pcie1", "pcie2";
+               phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
+               phy-names = "pcie-phy0", "pcie-phy2";
+
+               reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 
                pcie0: pcie@0,0 {
                        reg = <0x0000 0 0 0 0>;
-
                        #address-cells = <3>;
                        #size-cells = <2>;
-
                        ranges;
+                       bus-range = <0x00 0xff>;
                };
 
                pcie1: pcie@1,0 {
                        reg = <0x0800 0 0 0 0>;
-
                        #address-cells = <3>;
                        #size-cells = <2>;
-
                        ranges;
+                       bus-range = <0x00 0xff>;
                };
 
                pcie2: pcie@2,0 {
                        reg = <0x1000 0 0 0 0>;
-
                        #address-cells = <3>;
                        #size-cells = <2>;
-
                        ranges;
+                       bus-range = <0x00 0xff>;
                };
        };
+
+       pcie0_phy: pcie-phy@1e149000 {
+               compatible = "mediatek,mt7621-pci-phy";
+               reg = <0x1e149000 0x0700>;
+               #phy-cells = <1>;
+       };
+
+       pcie2_phy: pcie-phy@1e14a000 {
+               compatible = "mediatek,mt7621-pci-phy";
+               reg = <0x1e14a000 0x0700>;
+               #phy-cells = <1>;
+       };
 };