#include <dt-bindings/interrupt-controller/mips-gic.h>
#include <dt-bindings/clock/mt7621-clk.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <1>;
clock-frequency = <50000000>;
};
-
-
palmbus: palmbus@1E000000 {
compatible = "palmbus";
reg = <0x1E000000 0x100000>;
reg = <0x100 0x100>;
};
- gpio@600 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- compatible = "mtk,mt7621-gpio";
+ gpio: gpio@600 {
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "mediatek,mt7621-gpio";
+ gpio-controller;
+ interrupt-controller;
reg = <0x600 0x100>;
-
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
-
- gpio0: bank@0 {
- reg = <0>;
- compatible = "mtk,mt7621-gpio-bank";
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio1: bank@1 {
- reg = <1>;
- compatible = "mtk,mt7621-gpio-bank";
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpio2: bank@2 {
- reg = <2>;
- compatible = "mtk,mt7621-gpio-bank";
- gpio-controller;
- #gpio-cells = <2>;
- };
};
i2c: i2c@900 {
i2c_pins: i2c_pins {
i2c_pins {
- ralink,group = "i2c";
- ralink,function = "i2c";
+ groups = "i2c";
+ function = "i2c";
};
};
spi_pins: spi_pins {
spi_pins {
- ralink,group = "spi";
- ralink,function = "spi";
+ groups = "spi";
+ function = "spi";
};
};
uart1_pins: uart1 {
uart1 {
- ralink,group = "uart1";
- ralink,function = "uart1";
+ groups = "uart1";
+ function = "uart1";
};
};
uart2_pins: uart2 {
uart2 {
- ralink,group = "uart2";
- ralink,function = "uart2";
+ groups = "uart2";
+ function = "uart2";
};
};
uart3_pins: uart3 {
uart3 {
- ralink,group = "uart3";
- ralink,function = "uart3";
+ groups = "uart3";
+ function = "uart3";
};
};
rgmii1_pins: rgmii1 {
rgmii1 {
- ralink,group = "rgmii1";
- ralink,function = "rgmii1";
+ groups = "rgmii1";
+ function = "rgmii1";
};
};
rgmii2_pins: rgmii2 {
rgmii2 {
- ralink,group = "rgmii2";
- ralink,function = "rgmii2";
+ groups = "rgmii2";
+ function = "rgmii2";
};
};
mdio_pins: mdio {
mdio {
- ralink,group = "mdio";
- ralink,function = "mdio";
+ groups = "mdio";
+ function = "mdio";
};
};
pcie_pins: pcie {
pcie {
- ralink,group = "pcie";
- ralink,function = "pcie rst";
+ groups = "pcie";
+ function = "gpio";
};
};
nand_pins: nand {
spi-nand {
- ralink,group = "spi";
- ralink,function = "nand1";
+ groups = "spi";
+ function = "nand1";
};
sdhci-nand {
- ralink,group = "sdhci";
- ralink,function = "nand2";
+ groups = "sdhci";
+ function = "nand2";
};
};
sdhci_pins: sdhci {
sdhci {
- ralink,group = "sdhci";
- ralink,function = "sdhci";
+ groups = "sdhci";
+ function = "sdhci";
};
};
};
0x1e003800 0x800>;
};
+ ethsys: syscon@1e000000 {
+ compatible = "mediatek,mt7621-ethsys",
+ "syscon";
+ reg = <0x1e000000 0x1000>;
+ #clock-cells = <1>;
+ };
+
ethernet: ethernet@1e100000 {
compatible = "mediatek,mt7621-eth";
reg = <0x1e100000 0x10000>;
+ clocks = <&sysclock>;
+ clock-names = "ethif";
+
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
resets = <&rstctrl 6 &rstctrl 23>;
reset-names = "fe", "eth";
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
- mediatek,switch = <&gsw>;
+ mediatek,ethsys = <ðsys>;
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ pause;
+ };
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ status = "disabled";
+ phy-mode = "rgmii-rxid";
+ };
- mdio-bus {
+ mdio: mdio-bus {
#address-cells = <1>;
#size-cells = <0>;
- phy1f: ethernet-phy@1f {
+ switch0: switch@1f {
+ compatible = "mediatek,mt7621";
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x1f>;
- phy-mode = "rgmii";
+ mediatek,mcm;
+ resets = <&rstctrl 2>;
+ reset-names = "mcm";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ port@0 {
+ status = "disabled";
+ reg = <0>;
+ label = "lan0";
+ };
+
+ port@1 {
+ status = "disabled";
+ reg = <1>;
+ label = "lan1";
+ };
+
+ port@2 {
+ status = "disabled";
+ reg = <2>;
+ label = "lan2";
+ };
+
+ port@3 {
+ status = "disabled";
+ reg = <3>;
+ label = "lan3";
+ };
+
+ port@4 {
+ status = "disabled";
+ reg = <4>;
+ label = "lan4";
+ };
+
+ port@6 {
+ reg = <6>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
};
};
-
- hnat: hnat@0 {
- compatible = "mediatek,mt7623-hnat";
- reg = <0 0x10000>;
- mtketh-ppd = "eth0";
- mtketh-lan = "eth0";
- mtketh-wan = "eth0";
- resets = <&rstctrl 0>;
- reset-names = "mtketh";
- };
};
gsw: gsw@1e110000 {
pcie: pcie@1e140000 {
compatible = "mediatek,mt7621-pci";
- reg = <0x1e140000 0x100
- 0x1e142000 0x100>;
-
+ reg = <0x1e140000 0x100 /* host-pci bridge registers */
+ 0x1e142000 0x100 /* pcie port 0 RC control registers */
+ 0x1e143000 0x100 /* pcie port 1 RC control registers */
+ 0x1e144000 0x100>; /* pcie port 2 RC control registers */
#address-cells = <3>;
#size-cells = <2>;
0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
- GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
- GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xF0000 0 0 1>;
+ interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
+ <0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
+ <0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
reset-names = "pcie0", "pcie1", "pcie2";
clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
clock-names = "pcie0", "pcie1", "pcie2";
+ phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
+ phy-names = "pcie-phy0", "pcie-phy2";
+
+ reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
pcie0: pcie@0,0 {
reg = <0x0000 0 0 0 0>;
-
#address-cells = <3>;
#size-cells = <2>;
-
ranges;
+ bus-range = <0x00 0xff>;
};
pcie1: pcie@1,0 {
reg = <0x0800 0 0 0 0>;
-
#address-cells = <3>;
#size-cells = <2>;
-
ranges;
+ bus-range = <0x00 0xff>;
};
pcie2: pcie@2,0 {
reg = <0x1000 0 0 0 0>;
-
#address-cells = <3>;
#size-cells = <2>;
-
ranges;
+ bus-range = <0x00 0xff>;
};
};
+
+ pcie0_phy: pcie-phy@1e149000 {
+ compatible = "mediatek,mt7621-pci-phy";
+ reg = <0x1e149000 0x0700>;
+ #phy-cells = <1>;
+ };
+
+ pcie2_phy: pcie-phy@1e14a000 {
+ compatible = "mediatek,mt7621-pci-phy";
+ reg = <0x1e14a000 0x0700>;
+ #phy-cells = <1>;
+ };
};
projects / openwrt / staging / jow.git / blobdiff