#include <linux/mtd/physmap.h>
#include <linux/spi/spi.h>
#include <linux/rt2x00_platform.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/usb/ehci_pdriver.h>
+#include <linux/usb/ohci_pdriver.h>
#include <asm/addrspace.h>
static void rt305x_fe_reset(void)
{
- rt305x_sysc_wr(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
+ u32 reset_bits = RT305X_RESET_FE;
+
+ if (soc_is_rt5350())
+ reset_bits |= RT305X_RESET_ESW;
+ rt305x_sysc_wr(reset_bits, SYSC_REG_RESET_CTRL);
rt305x_sysc_wr(0, SYSC_REG_RESET_CTRL);
}
};
struct rt305x_esw_platform_data rt305x_esw_data = {
+ /* All ports are LAN ports. */
.vlan_config = RT305X_ESW_VLAN_CONFIG_NONE,
.reg_initval_fct2 = 0x00d6500c,
+ /*
+ * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
+ * turbo mii off, rgmi 3.3v off
+ * port5: disabled
+ * port6: enabled, gige, full-duplex, rx/tx-flow-control
+ */
.reg_initval_fpa2 = 0x3f502b28,
};
void __init rt305x_register_wifi(void)
{
- rt305x_wifi_data.eeprom_file_name = "RT305X.eeprom";
+ u32 t;
+
+ rt305x_wifi_data.eeprom_file_name = "soc_wmac.eeprom";
+
+ if (soc_is_rt3352() || soc_is_rt5350()) {
+ t = rt305x_sysc_rr(SYSC_REG_SYSTEM_CONFIG);
+ t &= RT3352_SYSCFG0_XTAL_SEL;
+ if (!t)
+ rt305x_wifi_data.clk_is_20mhz = 1;
+ }
platform_device_register(&rt305x_wifi_device);
}
platform_device_register(&rt305x_spi_device);
}
-static struct resource rt305x_usb_resources[] = {
+static struct resource rt305x_dwc_otg_resources[] = {
{
.start = RT305X_OTG_BASE,
.end = RT305X_OTG_BASE + 0x3FFFF,
},
};
-static struct platform_device rt305x_usb_device = {
+static struct platform_device rt305x_dwc_otg_device = {
.name = "dwc_otg",
- .resource = rt305x_usb_resources,
- .num_resources = ARRAY_SIZE(rt305x_usb_resources),
+ .resource = rt305x_dwc_otg_resources,
+ .num_resources = ARRAY_SIZE(rt305x_dwc_otg_resources),
.dev = {
.platform_data = NULL,
}
};
+static atomic_t rt3352_usb_pwr_ref = ATOMIC_INIT(0);
+
+static int rt3352_usb_power_on(struct platform_device *pdev)
+{
+
+ if (atomic_inc_return(&rt3352_usb_pwr_ref) == 1) {
+ u32 t;
+
+ t = rt305x_sysc_rr(RT3352_SYSC_REG_USB_PS);
+
+ /* enable clock for port0's and port1's phys */
+ t = rt305x_sysc_rr(RT3352_SYSC_REG_CLKCFG1);
+ t |= RT3352_CLKCFG1_UPHY0_CLK_EN | RT3352_CLKCFG1_UPHY1_CLK_EN;
+ rt305x_sysc_wr(t, RT3352_SYSC_REG_CLKCFG1);
+ mdelay(500);
+
+ /* pull USBHOST and USBDEV out from reset */
+ t = rt305x_sysc_rr(RT3352_SYSC_REG_RSTCTRL);
+ t &= ~(RT3352_RSTCTRL_UHST | RT3352_RSTCTRL_UDEV);
+ rt305x_sysc_wr(t, RT3352_SYSC_REG_RSTCTRL);
+ mdelay(500);
+
+ /* enable host mode */
+ t = rt305x_sysc_rr(RT3352_SYSC_REG_SYSCFG1);
+ t |= RT3352_SYSCFG1_USB0_HOST_MODE;
+ rt305x_sysc_wr(t, RT3352_SYSC_REG_SYSCFG1);
+
+ t = rt305x_sysc_rr(RT3352_SYSC_REG_USB_PS);
+ }
+
+ return 0;
+}
+
+static void rt3352_usb_power_off(struct platform_device *pdev)
+{
+
+ if (atomic_dec_return(&rt3352_usb_pwr_ref) == 0) {
+ u32 t;
+
+ /* put USBHOST and USBDEV into reset */
+ t = rt305x_sysc_rr(RT3352_SYSC_REG_RSTCTRL);
+ t |= RT3352_RSTCTRL_UHST | RT3352_RSTCTRL_UDEV;
+ rt305x_sysc_wr(t, RT3352_SYSC_REG_RSTCTRL);
+ udelay(10000);
+
+ /* disable clock for port0's and port1's phys*/
+ t = rt305x_sysc_rr(RT3352_SYSC_REG_CLKCFG1);
+ t &= ~(RT3352_CLKCFG1_UPHY0_CLK_EN | RT3352_CLKCFG1_UPHY1_CLK_EN);
+ rt305x_sysc_wr(t, RT3352_SYSC_REG_CLKCFG1);
+ udelay(10000);
+ }
+}
+
+static struct usb_ehci_pdata rt3352_ehci_data = {
+ .port_power_off = 1,
+ .power_on = rt3352_usb_power_on,
+ .power_off = rt3352_usb_power_off,
+};
+
+static struct resource rt3352_ehci_resources[] = {
+ {
+ .start = RT3352_EHCI_BASE,
+ .end = RT3352_EHCI_BASE + RT3352_EHCI_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = RT305X_INTC_IRQ_OTG,
+ .end = RT305X_INTC_IRQ_OTG,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 rt3352_ehci_dmamask = DMA_BIT_MASK(32);
+static struct platform_device rt3352_ehci_device = {
+ .name = "ehci-platform",
+ .id = -1,
+ .resource = rt3352_ehci_resources,
+ .num_resources = ARRAY_SIZE(rt3352_ehci_resources),
+ .dev = {
+ .dma_mask = &rt3352_ehci_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &rt3352_ehci_data,
+ },
+};
+
+static struct resource rt3352_ohci_resources[] = {
+ {
+ .start = RT3352_OHCI_BASE,
+ .end = RT3352_OHCI_BASE + RT3352_OHCI_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = RT305X_INTC_IRQ_OTG,
+ .end = RT305X_INTC_IRQ_OTG,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct usb_ohci_pdata rt3352_ohci_data = {
+ .power_on = rt3352_usb_power_on,
+ .power_off = rt3352_usb_power_off,
+};
+
+static u64 rt3352_ohci_dmamask = DMA_BIT_MASK(32);
+static struct platform_device rt3352_ohci_device = {
+ .name = "ohci-platform",
+ .id = -1,
+ .resource = rt3352_ohci_resources,
+ .num_resources = ARRAY_SIZE(rt3352_ohci_resources),
+ .dev = {
+ .dma_mask = &rt3352_ohci_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &rt3352_ohci_data,
+ },
+};
+
void __init rt305x_register_usb(void)
{
- platform_device_register(&rt305x_usb_device);
+ if (soc_is_rt305x() || soc_is_rt3350()) {
+ platform_device_register(&rt305x_dwc_otg_device);
+ } else if (soc_is_rt3352() || soc_is_rt5350()) {
+ platform_device_register(&rt3352_ehci_device);
+ platform_device_register(&rt3352_ohci_device);
+ } else {
+ BUG();
+ }
}
projects / openwrt / staging / lynxis / omap.git / blobdiff